Transistor chip package with internal clip interconnect

Abstract

The present disclosure provides a transistor chip package. A semiconductor package includes a transistor chip having a first side and a second side opposite the first side, where the transistor chip includes a first load electrode and a second load electrode on the first side. The semiconductor package includes a carrier facing a second side of the transistor chip, a first terminal post disposed laterally alongside the transistor chip, and a second terminal post disposed laterally alongside the transistor chip on an opposite side. The second terminal post is part of the carrier or is physically connected to the carrier. A first clamp connects the first load electrode to the first terminal post. A second clamp connects the second load electrode to the second terminal post. The upper surface of the first terminal post and the upper surface of the second terminal post are arranged at different height levels measured from the upper surface of the carrier. The first clamp and the second clamp have the same shape.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor packaging technology, and more specifically to transistor chip packaging using fixtures for internal package interconnects. Background Technology

[0002] Semiconductor packages are widely used as electronic switches in various electronic circuits. Higher efficiency, increased power density, lower switching losses, faster switching times, lower device resistance and parasitic effects, and lower cost are key goals for next-generation semiconductor package design.

[0003] A common method to reduce device resistance and parasitic effects, as well as improve thermal behavior, is to use fixtures to connect the load electrodes of a semiconductor transistor chip to the corresponding terminals of a semiconductor package. Fixture attachment, typically performed by fixture attachment machines, significantly increases the overall package cost. Summary of the Invention

[0004] According to a first aspect of this disclosure, a semiconductor package includes a transistor chip having a first side and a second side opposite to the first side. The transistor chip includes a first load electrode and a second load electrode on the first side. The package includes a carrier facing the second side of the transistor chip, a first terminal post laterally disposed next to the transistor chip, and a second terminal post laterally disposed next to the transistor chip on the opposite side of the transistor chip. The second terminal post is part of the carrier or physically connected to the carrier. A first clamp connects the first load electrode to the first terminal post. A second clamp connects the second load electrode to the second terminal post. The upper surfaces of the first terminal post and the second terminal post are disposed at different height levels measured from the upper surface of the carrier. The first clamp and the second clamp have the same shape.

[0005] According to a second aspect of this disclosure, a semiconductor package includes a transistor chip having a first side and a second side opposite to the first side. The transistor chip includes a first load electrode and a second load electrode on the first side. The package includes a carrier facing the second side of the transistor chip, a first terminal post laterally disposed next to the transistor chip, and a second terminal post laterally disposed next to the transistor chip on the opposite side of the transistor chip. The second terminal post is part of the carrier or physically connected to the carrier. A first clamp connects the first load electrode to the first terminal post. A second clamp connects the second load electrode to the second terminal post. The upper surfaces of the first terminal post and the second terminal post are disposed at different height levels measured from the upper surface of the carrier. The first clamp includes a vertical clamp portion extending in a vertical direction and a horizontal clamp portion extending in a horizontal direction, the horizontal clamp portion having a first horizontal segment and a second horizontal segment connected by a vertical stepped segment.

[0006] According to another aspect of this disclosure, a method of manufacturing a semiconductor package according to the first aspect includes providing a first terminal post and providing a second terminal post. The method further includes placing a transistor chip on a carrier. A first fixture is positioned to connect between a first load electrode and the first terminal post. A second fixture is positioned to connect between a second load electrode and the second terminal post. Attached Figure Description

[0007] In the accompanying drawings, the same reference numerals denote corresponding similar parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive, and / or may be selectively omitted unless necessary for description. Embodiments are depicted in the accompanying drawings and are exemplarily detailed in the following description.

[0008] Figure 1 This is a schematic cross-sectional view of an example of a semiconductor package including a transistor chip and first and second fixtures with internal interconnections, according to the first aspect.

[0009] Figure 2 This is a schematic cross-sectional view of an example of a semiconductor package including a transistor chip and first and second fixtures with internal interconnections, according to the second aspect.

[0010] Figure 3 For example Figure 1 or Figure 2 A top view of an example of a semiconductor package shown.

[0011] Figure 4 It is a schematic top view of the fixture attachment frame according to the first aspect.

[0012] Figure 5 It is a schematic top view of the clamp attachment frame according to the second aspect.

[0013] Figure 6A This is a schematic cross-sectional view of a conventional transistor chip package containing two clamps of different shapes.

[0014] Figure 6B yes Figure 6A A schematic cross-sectional view of a conventional transistor chip package during manufacturing, showing the insufficient free length in the fixture frame for fixture bending.

[0015] Figure 7 This is a perspective top view of an example of a second fixture according to this disclosure.

[0016] Figure 8 This is a flowchart illustrating exemplary stages of manufacturing a transistor chip package according to the first aspect.

[0017] Figure 9This is a flowchart illustrating exemplary stages of manufacturing a transistor chip package according to the second aspect. Detailed Implementation

[0018] It should be understood that, unless otherwise specified, the features of the various exemplary embodiments and examples described herein can be combined with each other.

[0019] As used in this specification, the terms "electrically connected" or "electrically coupled" or similar terms do not imply that the elements are in direct contact with each other; intermediate elements may be provided between the "electrically connected" or "electrically coupled" elements, respectively. However, according to this disclosure, the foregoing and similar terms may also optionally have the specific meaning of the elements being in direct contact with each other, i.e., no intermediate element is provided between the "electrically connected" or "electrically coupled" elements, respectively.

[0020] Furthermore, the terms "above" or "below" of a component, element, or layer of material formed, positioned, or arranged "above" or "below" a surface may be used herein to indicate that the component, element, or layer of material is directly positioned (e.g., placed, formed, arranged, deposited, etc.) "above" or "below" the implied surface, such as being in direct contact with the implied surface. However, the terms "above" or "below" of a component, element, or layer of material formed, positioned, or arranged "above" or "below" a surface may be used herein to indicate that the component, element, or layer of material is indirectly positioned (e.g., placed, formed, arranged, deposited, etc.) "above" or "below" the implied surface, wherein one or more additional components, elements, or layers of material are arranged between the implied surface and the component, element, or layer of material.

[0021] Figure 1 A cross-sectional view of an example of a semiconductor package 100 is shown. The semiconductor package 100 includes a carrier 110 and a transistor chip (die) 120 mounted on the carrier 110.

[0022] More specifically, the transistor chip 120 has a first side 120A and a second side 120B opposite to the first side 120A. The second side 120B of the transistor chip 120 faces the carrier 110. For example, the second side 120B of the transistor chip 120 can be attached to the carrier 110 by a bonding material 130 (e.g., solder material, sintering paste, or conductive adhesive).

[0023] The carrier 110 can be, for example, a metal carrier, such as part of a leadframe (e.g., a die pad of a leadframe). The leadframe can be a so-called downset leadframe (a leadframe having a downset portion including the carrier 110). In a downset leadframe, the first terminal post 140_1 (see below) is higher than the carrier 110.

[0024] In other examples, carrier 110 may include, for example, a PCB (printed circuit board), or a ceramic-based carrier, such as a DCB (direct copper bonding) carrier or an AWB substrate.

[0025] The transistor chip 120 includes a first load electrode 122_1 and a second load electrode 122_2. The first load electrode 122_1 and the second load electrode 122_2 are disposed on a first side 120A of the transistor chip 120.

[0026] For example, the first load electrode 122_1 can be the drain (D) electrode of the transistor chip 120, and the second load electrode 122_2 can be the source (S) electrode of the transistor chip 120.

[0027] The transistor chip 120 can be configured as a power semiconductor chip. Power chips are particularly well-suited for switching high currents and / or medium or high voltages (e.g., blocking voltages greater than 50V, 100V, 200V, or 300V). In particular, the exemplary semiconductor package disclosed herein can operate over a medium voltage (MV) range, wherein the blocking voltage is equal to or greater than or less than 200V, 150V, 100V, or 50V.

[0028] The transistor chip 120 can be of different types. The examples described herein specifically relate to HEMT (High Electron Mobility Transistor) devices. More specifically, the transistor chip 120 mentioned herein can be, for example, a III-V compound semiconductor chip having, for example, a high bandgap. The transistor chip 120 can be, for example, a GaN chip. In this case, the GaN chip 120 can be, for example, a GaN-on-substrate device, such as a GaN-on-Si device, a GaN-on-SiC device, or a GaN-on-sapphire device.

[0029] Typically, transistor chip 120 can be, for example, a lateral semiconductor device having load electrodes 122_1, 122_2 only on a first side 120A of transistor chip 120. In a lateral semiconductor device, the load current flows primarily in the lateral (horizontal) direction between the load electrodes 122_1, 122_2.

[0030] The semiconductor package 100 also includes a first terminal post 140_1 arranged laterally next to the transistor chip 120 and a second terminal post 140_2 arranged laterally next to the transistor chip 120 on the opposite side of the transistor chip 120.

[0031] The semiconductor package 100 also includes a first clamp 160_1 and a second clamp 160_2. The first clamp 160_1 connects a first load electrode 122_1 to a first terminal post 140_1. The second clamp 160_2 connects a second load electrode 122_2 to a second terminal post 140_2. For example, the first clamp 160_1 and the second clamp 160_2 may be made of, for example, copper or aluminum, or a copper-based or aluminum-based alloy.

[0032] The first clamp 160_1 and the second clamp 160_2 are configured as load current clamps. In the example shown, the first clamp 160_1 is, for example, a drain clamp, and the second clamp 160_2 is, for example, a source clamp.

[0033] The upper surface 140_1A of the first terminal post 140_1 and the upper surface 140_2A of the second terminal post 140_2 are arranged at different height levels measured from the upper surface 110A of the carrier 110. For example, the height of the upper surface 140_1A of the first terminal post 140_1 is H1. The height of the upper surface 140_2A of the second terminal post 140_2 above the upper surface 110A of the carrier 110 is, for example, zero (if the second terminal post 140_2 is formed, for example, by a region on the upper surface 110A of the carrier 110).

[0034] In other examples (not shown), the upper surface 140_2A of the second terminal post 140_2 (to which the second clamp 160_2 is attached) may, for example, be raised above the upper surface 110A of the carrier 110, which serves as a mounting platform for the transistor chip 120. For example, the carrier 110 may be provided with a protrusion or base having the upper surface 140_2A at a height (not shown) above the upper surface 110A of the carrier 110. Typically, the second terminal post 140_2 is part of or physically attached to the carrier 110.

[0035] In the following text, the distance between the upper surface 140_1A of the first terminal post 140_1 and the upper surface of the transistor chip 120 at its first side 120A is referred to as the SOH (standoff height) of the first clamp 160_1. In other words, the SOH is the free height bridged by the first clamp 160_1. Typically, especially when the lower surface 110B of the carrier 110 remains exposed at the semiconductor package 100, the SOH of the first clamp 160_1 may need to be quite high. For example, the SOH may be equal to or greater than or less than 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm. These rather large values ​​of SOH may be due, for example, to the minimum height H1 required in some examples of packaged transistor chip 120.

[0036] The first load electrode 122_1 and the second load electrode 122_2 of the transistor chip 120 are laterally spaced apart by a gap of width W. Generally, W can be, for example, equal to, less than, or greater than 250 μm, 300 μm, or 350 μm.

[0037] For example, W < SOH. In this case, the bent portions of the jigs 160_1, 160_2 (i.e., the vertical sections 160_1V, 160_2V) are longer than the distance between the electrode 122_1 and the electrode 122_2.

[0038] The first jig 160_1 and the second jig 160_2 can each include a vertical jig portion 160_1V and 160_2V, and a horizontal jig portion 160_1H and 160_2H, respectively. The horizontal jig portion 160_1H of the first jig 160_1 can be attached to the first terminal post 140_1 (e.g., attached to its upper surface 140_1A). The vertical jig portion 160_1V of the first jig 160_1 can be attached to the first load electrode 122_1. Similarly, the horizontal jig portion 160_2H of the second jig 160_2 can be attached to the second load electrode 122_2, and the vertical jig portion 160_2V of the second jig 160_2 can be attached to, for example, the second terminal post 140_2 (e.g., attached to its upper surface 140_2A).

[0039] For each of the jigs 160_1, 160_2, the vertical jig portions 160_1V, 160_2V can be one end of the jigs 160_1, 160_2, and the horizontal jig portions 160_1H, 160_2H can be the other end of the jigs 160_1, 160_2. The vertical jig portions 160_1V, 160_2V can be connected to the horizontal jig portions 160_1H, 160_2H via a jig bend having a bend angle of, for example, approximately 90°. For example, each of the jigs 160_1, 160_2 can have only one jig bend, i.e., each of the jigs 160_1, 160_2 can, for example, include the vertical jig portions 160_1V, 160_2V, the jig bend, and the horizontal jig portions 160_1H, 160_2H, or consist of the vertical jig portions 160_1V, 160_2V, the jig bend, and the horizontal jig portions 160_1H, 160_2H.

[0040] The vertical jig portions 160_1V and 160_2V are the jig portions that need to be bent downward during the manufacture of the jigs 160_1 and 160_2, respectively. The lengths of the downward-bent vertical jig portions 160_1V and 160_2V define the free height H of the first and second jigs 160_1, 160_2.

[0041] According to a first aspect of this disclosure, the first fixture 160_1 and the second fixture 160_2 have the same shape. "Same shape" can actually mean the same shape in the 3D dimension, i.e., the same shape. This also means that only one fixture must be used for the internal interconnects of the semiconductor package 100.

[0042] In other words, universal fixtures 160_1 and 160_2 can be used to contact the load electrodes 122_1 and 122_2 (e.g., drain and source) of the transistor chip 120. The availability of universal fixtures reduces the cost of fixtures 160_1 and 160_2 because traditionally, two different fixtures—one drain fixture and one source fixture—are not required. Purchasing two different fixtures is more expensive than purchasing the same fixture with twice the volume.

[0043] Fixture attachment is typically performed through pick-and-place operations. Thanks to the universal fixtures 160_1 and 160_2, the pick-and-place process does not require consideration of different fixtures for picking up the source or drain terminals, saving operating space and / or increasing UPH (units per hour) manufacturing rate.

[0044] Specifically, the first clamp 160_1 and the second clamp 160_2 (which have the same shape according to the first aspect of this disclosure) must have the same free height H. In a specific example, SOH = H can be chosen.

[0045] Furthermore, the first clamp 160_1 and the second clamp 160_2 may include stepped abutment surfaces AS at the end sections of the horizontal clamp portions 160_1H and 160_2H. The abutment surfaces AS may include a higher abutment surface portion AS1 and a lower abutment surface portion AS2.

[0046] For example, the higher adjacent surface portion AS1 of the first clamp 160_1 is placed on the first terminal post 140_1 (e.g., on its upper surface 140_1A), and the lower adjacent surface portion AS2 of the second clamp 160_2 is placed on the second load electrode 122_2.

[0047] The height difference between the higher adjacent surface portion AS1 and the lower adjacent surface portion AS2 can be appropriately set to allow the first clamp 160_1 and the second clamp 160_2 to have the same shape. In other words, the height of the upper surface of the transistor chip 120 at the first side 120A, measured from the upper surface 110A of the carrier 110 (which may be the height to be bridged by the second clamp 160_2) and the height of the upper surface 140_1A of the first terminal post 140_1, measured from the upper surface of the first side 120A of the transistor chip 120 (which may be the height to be bridged by the first clamp 160_1) can differ by, for example, by an offset OS. This offset OS can be compensated by the stepped adjacent surface AS (e.g., the step height, i.e., the height difference between AS1 and AS2, is set to OS). Then, due to the stepped adjacent surface AS, this offset OS will not prevent the first clamp 160_1 and the second clamp 160_2 from having the same shape.

[0048] like Figure 1 As shown, the semiconductor package 100 may include an encapsulation 180. For example, a molding process may be performed to encapsulate the transistor chip 120 mounted on the carrier 110 with a molding material. The molded encapsulation 180 may, for example, form a package body.

[0049] The carrier 110 can remain exposed at the bottom of the encapsulation 180. For example, the first clamp 160_1 and the second clamp 160_2 can be completely covered by the encapsulation 180.

[0050] In some examples, semiconductor package 100 is a leaded package. Semiconductor package 100 may include, for example, leads to form a first package terminal 190_1 and / or a second package terminal 190_2. The leads may, for example, protrude from the peripheral side of the encapsulation 180.

[0051] For example, the leads forming the first package terminal 190_1 (e.g., D) and / or the second package terminal 190_2 (e.g., S) can be formed as follows: Figure 6A , Figure 6B The gull-wing lead wire shown.

[0052] In some examples, semiconductor package 100 may be a partially leaded package (not shown). Such a semiconductor package may, for example, include one or more leads to form a first package terminal 190_1. The second package terminal 190_2 may, for example, be leadless, i.e., no leads protrude from the (right) peripheral side of the enclosure 180. For example, such a package may be, for example, a TOLL (TO - leadless) package or a TOLG (TO - leaded with gull wings) package, such as a BSC (basic size) package. In these packages, the second package terminal 190_2 may, for example, be formed by the exposed lower surface 110B of the carrier 110.

[0053] Figure 2 Shows an example of a semiconductor package 200 according to a second aspect of the present disclosure. The semiconductor package 200 is mainly designed according to the features described for the semiconductor package 100. Therefore, to avoid repetition, reference is made to the above description.

[0054] The semiconductor package 200 is different from the semiconductor package 100 in terms of fixture design. The first fixture 160_1 includes a vertical fixture portion 160_1V extending in the vertical direction and a horizontal fixture portion 160_1H extending in the horizontal direction. The horizontal fixture portion 160_1H of the first fixture 160_1 has a first section A and a second section B. The first section A and the second section B are connected by a vertical stepped section ST. The vertical stepped section ST allows the horizontal fixture portion 160_1H to bridge a height difference, i.e., a vertical distance Dv.

[0055] The stepped section ST can be used to reduce the free height H of the vertical fixture portion 160_1V. For example, compared with Figure 1 the semiconductor package 100 shown, the free height H of the vertical fixture portion 160_1V is reduced by Dv, i.e., H(package 200) = H(package 100) - Dv. In particular, since H(package 100) can be equal to SOH, the free height H of the semiconductor package 200 can, for example, be read as H = SOH - Dv.

[0056] In this way, the dimension H can be smaller than the width W of the gap between the first load electrode 122_1 and the second load electrode 122_2. This allows the first fixture 160_1 and the second fixture 160_2 to be formed within the same fixture frame, as will be described in further detail below. Therefore, the first fixture 160_1 and the second fixture 160_2 can, for example, be placed together on the transistor chip 120 and the terminal posts 140_1, 140_2 by a single placement process. This reduces the cost of the fixture attachment process because each semiconductor package 200 only requires one fixture attachment operation.

[0057] In the semiconductor package 200, SOH can, for example, be equal to or greater than or less than 250 μm, 300 μm, 350 μm, 400 μm, 450 μm or 500 μm (i.e., the same values as in the semiconductor package 100 can be adopted). For example, Dv can, for example, be equal to or greater than or less than 300 μm, 250 μm, 200 μm, 150 μm or 100 μm. Similar ranges apply to H, which can, for example, be equal to or greater than or less than 300 μm, 250 μm, 200 μm, 150 μm or 100 μm (e.g., H < W to allow the in-frame fixture to bend, see the explanation Figure 6B ).

[0058] The "lower" second segment B of the horizontal clamping portion 160_1H of the first clamp 160_1 may have a length represented as a horizontal distance Dh. The horizontal distance Dh is the end of the first clamp 160_1 at the vertical clamping portion 160_1V (i.e., Figure 2 The distance between the first clamp 160_1 at the right end and the vertical stepped section ST.

[0059] In the semiconductor package 200, Dh can be equal to or greater than 0.5 mm, 0.75 mm, or 1.0 mm, for example. This allows the use of the upper flat surface of the second segment B to provide sufficient space for the pick-up head (not shown) of the pick-up placement assembly unit used to place the first fixture 160_1 on the transistor chip 120.

[0060] More specifically, the pickup head for picking up and placing the assembly unit may be provided with a suction area that has a minimum-sized flat surface area on the fixture for processing by the pickup and placement assembly unit. This area may be provided by the upper flat surface of the second segment B of the first fixture 160_1 (and similarly the second fixture 160_2).

[0061] The "higher" second section A of the horizontal clamping portion 160_1H of the first clamp 160_1 may have an opposite end to the first clamp 160_1 (in Figure 2 The length measured between the left side of the section and the vertical stepped segment ST. This length can be equal to, greater than, or less than 0.5 mm, 0.75 mm, or 1.0 mm (e.g., similar to length Dh).

[0062] According to a second aspect of this disclosure, the first clamp 160_1 and the second clamp 160_2 may, for example, have the same shape, such as Figure 2 As shown. However, the first clamp 160_1 and the second clamp 160_2 can also have different shapes. The first clamp 160_1 is shaped to include a stepped section ST, while the second clamp 160_2 can be shaped, for example, as shown. Figure 1 The semiconductor packaging 100 is shown in the figure.

[0063] Figure 3 Semiconductor packages (e.g., in...) are shown. Figure 1 and Figure 2 The diagram shows a top view of an example of a semiconductor package (100, 200). For illustrative purposes, the encapsulation 180 is omitted.

[0064] For example, the first package terminal 190_1 includes a plurality of leads extending from the first terminal post 140_1. The second package terminal 190_2 may also include a plurality of leads extending from the second terminal post 140_2. As previously described, the second terminal post 140_2 may be connected to or located on the carrier 110. For example, the second terminal post 140_2 may be formed from a region on the upper surface 110A of the carrier 110 where the second clamp 160_2 is placed.

[0065] The first package terminal 190_1 may extend along most or all of the length on one side of the semiconductor packages 100 and 200. The second package terminal 190_2 may also extend along most or all of the length on the opposite side of the semiconductor packages 100 and 200.

[0066] Semiconductor packages 100 and 200 may further include package terminals 390_1 and / or package terminals 390_2. Package terminals 390_1 and / or package terminals 390_2 may be connected to, for example, control electrodes (e.g., gates) and / or sensing electrodes on a first side 120A of a transistor chip 120.

[0067] like Figure 3 As shown, the first load electrode 122_1 and / or the second load electrode 122_2 can be formed as parallel strips extending along the longitudinal dimension of the transistor chip 120. The distance between these strips is a gap of width W.

[0068] Figure 4 A clamp attachment frame 400 according to a first aspect of this disclosure is shown. The clamp attachment frame 400 includes a frame 410 and a first clamp 160_1 connected to the frame 410 via a rod 420. The clamp attachment frame 400 is part of a clamp attachment reel, which is in... Figure 4 Extending from left to right and including repeating clamp attachment frames 400, as shown... Figure 4 As shown.

[0069] According to a first aspect of this disclosure, a first clamp attachment frame 400 for providing a first clamp 160_1 for a plurality of semiconductor packages 110 and a second clamp attachment frame 400 (which is identical to the clamp attachment frame 400 shown) for providing a second clamp 160_2 can be used to clamp the plurality of semiconductor packages 100. That is, one clamp attachment frame 400 is used to provide drain clamps for the plurality of semiconductor packages 100, and another clamp attachment frame 400 (which is identical to the clamp attachment frame 400) is used to provide source clamps for the semiconductor packages 100.

[0070] In subsequent pick-and-place operations of each semiconductor package, a first fixture 160_1 (e.g., a drain fixture) and a second fixture 160_2 (e.g., a source fixture) are placed. However, cost reduction is achieved by using a fixture attachment frame 400 of the same shape for attaching the first and second fixtures.

[0071] In other words, two identically shaped clamp attachment reels, each containing a series of clamp attachment frames 400, are used to sequentially apply drain and source clamps to each semiconductor package 100. Compared to conventional clamp attachments, these two clamp reels (drain clamp reel and source clamp reel) no longer have different shapes.

[0072] Figure 5 A clamp attachment frame 500 according to a second aspect of this disclosure is shown. The clamp attachment frame 500 is similar to the clamp attachment frame 400, and reference is made to the above description to avoid repetition. However, the clamp attachment frame 500 differs from the clamp attachment frame 400 in that the first clamp 160_1 and the second clamp 160_2 are implemented in the same frame 510. More specifically, the clamp attachment frame 500 includes a frame 510 and a first clamp 160_1 and a second clamp 160_2 connected to the frame 510 via a rod 520.

[0073] Only one clamping attachment process is needed to attach the first clamp 160_1 and the second clamp 160_2 (which can have the same shape or different shapes) together to the transistor chip 120 of each semiconductor package 200. Therefore, cost reduction is achieved by requiring only one clamping attachment process to simultaneously attach the first clamp 160_1 and the second clamp 160_2. In this case, Figure 5 The clamp attachment reel extending from left to right and including repeating clamp attachment frames 500 includes both clamps 160_1 and 160_2. Only a single clamp attachment reel is required to provide the first clamp 160_1 and the second clamp 160_2 for one or more semiconductor packages 200.

[0074] Figure 6A and Figure 6B Conventional chip packages 600_1 and 600_2 are schematically shown respectively. Regarding the first aspect of this disclosure, in Figure 6A In this configuration, the first clamp 160_1' and the second clamp 160_2' have different shapes. Therefore, two clamp attachment frames 400 (clamp attachment reels) of different designs are required to apply the (different-shaped) first clamp 160_1' and second clamp 160_2'.

[0075] Regarding the second aspect of this disclosure, and Figure 5 compared to, Figure 6BThe narrow gap (of width W) between the first load electrode 122_1 and the second load electrode 122_2 prevents the first clamp 160_1' and the second clamp 160_2' from being assembled within the same clamp attachment frame 500 (clamp attachment reel). This is impossible because the SOH is large, and therefore the length required for the clamp to bend within the frame (i.e., bending the end of the clamp 160_1' downwards to create the vertical clamp portion 160_1V, which requires a length similar to the SOH) is longer than the width W of the gap between the first load electrode 122_1 and the second load electrode 122_2 (i.e., SOH > W). Therefore, the conventional first clamp 160_1' and second clamp 160_2' without the stepped segment ST according to the second aspect of this disclosure need to be supplied in two separate clamp attachment frames (clamp reels) and need to be placed by separate pick-and-place attachment processes.

[0076] refer to Figure 7 In some examples, the vertical clamping portion 160_1V of the first clamp 160_1 and / or the vertical clamping portion 160_2V of the second clamp 160_2 may include, or be made of, one or more bent segments BS. The bent segments may be U-shaped. The U-shaped bent segments BS allow for a large contact area between the first clamp 160_1 and the first load electrode 122_1 and / or between the second clamp 160_2 and the second terminal post 140_2.

[0077] Each bent segment BS may include, or be formed from, an integral contact element 701, 702 protruding from, the lateral sidewalls SW1, SW2 of the first clamp 160_1 and / or the second clamp 160_2. The sidewall SW1 is arranged opposite the first sidewall SW2. The contact elements 701, 702 are bent downwards in a direction toward the transistor chip 120 or the carrier 110 to electrically contact the first load electrode 122_1 or the second terminal post 140_2. The bending axis is in the longitudinal direction of the first clamp 160_1 and / or the second clamp 160_2. For example, the contact elements 701, 702 forming the U-shaped bent segment BS may each be bent more than 90°, particularly about 180°. The contact elements 701 and 702 on both sides of the respective fixtures 160_1 and 160_2 facilitate the fixture attachment process and improve the mechanical stability of the respective fixtures 160_1 and 160_2 mounted on the transistor chip 120.

[0078] Due to the U-shaped bending section BS, the contact surfaces of the contact elements 701 and 702 facing the transistor chip 120 (first clamp 160_1) or the carrier 110 (second clamp 160_2) are the bent portions of the upper surfaces of the corresponding clamps 160_1 or 160_2 that are away from the transistor chip 120 or the carrier 110.

[0079] The U-shaped bend section BS allows for the formation of the vertical clamping portion 160_1V without creating sharp cutting edges that could contact the sensitive surface of the first load electrode 122_1. Therefore, the risk of damage to the transistor chip 120 during clamping is reduced. Conversely, if the vertical clamping portion 160_1V were formed by bending around the transverse axis of the corresponding clamp 160_1, sharp cutting edges at the ends of the vertical clamping portion 160_1V could potentially damage the first load electrode 122_1.

[0080] Furthermore, simulations have verified that the longitudinal bending of contact elements 701 and 702 provides the same effect as the transverse bending using clamps 160_1 and 160_2 (e.g., Figure 1 and Figure 2 The resulting electrical package resistance is comparable to that of a standard electrical package. These package resistances are significantly lower than any package resistance that can be obtained by using bonding wires instead of clamps.

[0081] Furthermore, since the bending axis is in the longitudinal direction of the first clamp 160_1 or the second clamp 160_2 rather than in the transverse direction, the bending process performed at the first clamp 160_1 will not interfere with the position of the second clamp 160_2 if, for example, they are arranged in the same clamp reel. Therefore, the two clamps 160_1 and 160_2 can be integrated onto the same clamp attachment frame 500, such as... Figure 7 As shown.

[0082] In other words, compared to using a curved axis in the lateral direction, there is always sufficient space and material to complete two clamps 160_1 and 160_2 in the same clamp attachment frame. This is due to the following facts: Figure 6B The dimensional constraints shown exist in the longitudinal direction, while when using fixtures 160_1 and 160_2 with the curved section BS, the bend is repositioned in the transverse direction.

[0083] refer to Figure 8 A method of manufacturing a semiconductor package 100 according to the first aspect of this disclosure includes providing a first terminal post and providing a second terminal post at S1.

[0084] At point S2, the transistor chip is placed on the carrier.

[0085] At S3, the first clamp is positioned to connect between the first load electrode and the first terminal post.

[0086] At S4_1, the second clamp is positioned to connect between the second load electrode and the second terminal post. Here, for example, the placement of the first clamp (at S3) and the placement of the second clamp (at S4_1) are performed sequentially.

[0087] refer to Figure 9 The method of manufacturing the semiconductor package 200 according to the second aspect of this disclosure may include the same stages S1 to S3 as described above. Furthermore, at S4_2, a second clamp is placed to connect between the second load electrode and the second terminal post, wherein, for example, the placement of the first clamp (at S3) and the placement of the second clamp (at S4_2) are performed together. Therefore, one pick-and-place operation per semiconductor package 200 may be sufficient.

[0088] If the vertical clamp portions 160_1V and 160_2V include a curved section BS that allows clamps 160_1 and 160_2 to be integrated within the same clamp attachment frame 500, then the manufacturing method may also be used in the first aspect of this disclosure.

[0089] Example

[0090] The following examples relate to other aspects of this disclosure:

[0091] Example 1 is a semiconductor package including a transistor chip having a first side and a second side opposite to the first side. The transistor chip includes a first load electrode and a second load electrode on the first side. The package includes a carrier facing the second side of the transistor chip, a first terminal post laterally disposed next to the transistor chip, and a second terminal post laterally disposed next to the transistor chip on the opposite side of the transistor chip. The second terminal post is part of the carrier or physically connected to the carrier. A first clamp connects the first load electrode to the first terminal post. A second clamp connects the second load electrode to the second terminal post. The upper surfaces of the first and second terminal posts are disposed at different height levels measured from the upper surface of the carrier. The first and second clamps have the same shape.

[0092] In Example 2, the subject matter of Example 1 may optionally include: wherein the first clamp and the second clamp include a vertical clamp portion extending in a vertical direction and a horizontal clamp portion extending in a horizontal direction, and wherein the horizontal clamp portion of the first clamp is attached to the first terminal post, and the vertical clamp portion of the first clamp is attached to the first load electrode.

[0093] In Example 3, the subject matter of Example 2 may optionally include, wherein the horizontal clamping portion of the second clamp is attached to the second load electrode, and the vertical clamping portion of the second clamp is attached to the second terminal post.

[0094] In Example 4, the subject matter of Example 3 or 4 may optionally include, wherein the horizontal clamp portion has an end section comprising a stepped abutment surface, the stepped abutment surface comprising a lower abutment surface portion and a higher abutment surface portion.

[0095] In Example 5, the subject matter of Example 4 may optionally include, wherein the higher adjacent surface portion of the first clamp is placed on the first terminal post, and the lower adjacent surface portion of the second clamp is placed on the second load electrode.

[0096] In Example 6, the subject of any of the preceding examples may optionally include: wherein the first clamp and the second clamp are identical in the 3D dimension.

[0097] In Example 7, the subject matter of any of the preceding examples may optionally include, wherein the first load electrode and the second load electrode are laterally spaced apart by a gap of width W, the free height of the vertical clamp portion is SOH, and W <SOH。

[0098] In Example 8, the subject of any of the preceding examples may optionally include, wherein the carrier is part of the lead frame.

[0099] In Example 9, the subject matter of any of the preceding examples may optionally include, wherein the package is a leaded package, the leads extending from the sidewalls of the package to form a first terminal of the package, and the first terminal post is a lead post.

[0100] In Example 10, the subject matter of any of the preceding examples may optionally include, wherein the transistor chip is a lateral power chip, particularly a GaN chip.

[0101] In Example 11, the subject matter of any of the preceding examples may optionally include: wherein the first load electrode and the second load electrode are the drain electrode and the source electrode, respectively.

[0102] In Example 12, the subject matter of any of the foregoing examples may optionally include, wherein the first clamp and the second clamp each include a first contact element that protrudes from a first sidewall of the first clamp or the second clamp and bends downward, with the bending axis in the longitudinal direction of the first clamp or the second clamp.

[0103] In Example 13, the subject matter of Example 12 may optionally include, wherein the first clamp and the second clamp each include a second contact element, the second contact element protruding from a second sidewall of the first clamp or the second clamp and bending downward, the bending axis being in the longitudinal direction of the first clamp or the second clamp, wherein the second sidewall is arranged opposite to the first sidewall.

[0104] In Example 14, the subject matter of Example 12 or 13 may optionally include, wherein the first contact element and / or the second contact element is U-shaped.

[0105] Example 15 is a method of manufacturing a semiconductor package according to any of the foregoing examples. The method includes providing a first terminal post and providing a second terminal post. The method also includes placing a transistor chip on a carrier. A first clamp is positioned between a first load electrode and the first terminal post. A second clamp is positioned between a second load electrode and the second terminal post.

[0106] In Example 16, the subject of Example 15 may optionally include, wherein placing the first fixture and placing the second fixture are performed sequentially.

[0107] Example 17 is a semiconductor package including a transistor chip having a first side and a second side opposite to the first side. The transistor chip includes a first load electrode and a second load electrode on the first side. The package includes a carrier facing the second side of the transistor chip, a first terminal post laterally disposed next to the transistor chip, and a second terminal post laterally disposed next to the transistor chip on the opposite side of the transistor chip. The second terminal post is part of the carrier or physically connected to the carrier. A first clamp connects the first load electrode to the first terminal post. A second clamp connects the second load electrode to the second terminal post. The upper surfaces of the first and second terminal posts are disposed at different height levels measured from the upper surface of the carrier. The first clamp includes a vertical clamp portion extending in a vertical direction and a horizontal clamp portion extending in a horizontal direction, the horizontal clamp portion having a first horizontal segment and a second horizontal segment connected by a vertical stepped segment.

[0108] In Example 18, the subject matter of Example 17 may optionally include, wherein the first load electrode and the second load electrode are laterally spaced apart by a gap of width W, the free height of the vertical clamping portion of the first clamp is SOH, and W>SOH.

[0109] In Example 19, the subject matter of Example 17 or 18 may optionally include, wherein a horizontal clamping portion of the first clamp is attached to a first terminal post, and a vertical clamping portion of the first clamp is attached to a first load electrode.

[0110] In Example 20, the subject matter of any one of Examples 17 to 19 may optionally include: wherein the second clamp includes a vertical clamp portion extending in the vertical direction and a horizontal clamp portion extending in the horizontal direction.

[0111] In Example 21, the subject matter of Example 20 may optionally include, wherein a horizontal clamping portion of the second clamp is attached to the second load electrode, and a vertical clamping portion of the second clamp is attached to the second terminal post.

[0112] In Example 22, the subject of any of Examples 17 to 21 may optionally include: wherein the first clamp and the second clamp have the same shape.

[0113] In Example 23, the subject of any of Examples 17 to 22 may optionally include, wherein the second terminal post is part of the carrier.

[0114] Example 24 is a method of manufacturing a semiconductor package according to any one of Examples 17 to 23. The method includes providing a first terminal post and providing a second terminal post. The method also includes placing a transistor chip on a carrier. A first jig is positioned between a first load electrode and the first terminal post. A second jig is positioned between a second load electrode and the second terminal post.

[0115] In Example 25, the subject of Example 24 may optionally include, wherein placing the first fixture and placing the second fixture are performed together.

[0116] Although specific embodiments have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations can be used instead of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor package, comprising: A transistor chip having a first side and a second side opposite to the first side, wherein the transistor chip includes a first load electrode and a second load electrode on the first side; A carrier facing the second side of the transistor chip; The first terminal post is arranged laterally next to the transistor chip; The second terminal post is laterally arranged next to the transistor chip on the opposite side of the transistor chip, wherein the second terminal post is part of the carrier or physically connected to the carrier; A first clamp, the first clamp connecting the first load electrode to the first terminal post; and A second clamp connects the second load electrode to the second terminal post; The upper surfaces of the first terminal post and the second terminal post are arranged at different height levels measured from the upper surface of the carrier. The first clamp and the second clamp have the same shape. Its features are: The first terminal post and the second terminal post are located at different heights.

2. The semiconductor package according to claim 1, wherein, The first clamp and the second clamp include a vertical clamp portion extending in a vertical direction and a horizontal clamp portion extending in a horizontal direction, wherein the horizontal clamp portion of the first clamp is attached to the first terminal post, and the vertical clamp portion of the first clamp is attached to the first load electrode.

3. The semiconductor package according to claim 2, wherein, The horizontal clamping portion of the second clamp is attached to the second load electrode, and the vertical clamping portion of the second clamp is attached to the second terminal post.

4. The semiconductor package according to claim 2 or 3, wherein, The horizontal clamp portion has an end section including a stepped abutment surface, the stepped abutment surface including a lower abutment surface portion and a higher abutment surface portion.

5. The semiconductor package according to claim 4, wherein, The higher adjacent surface portion of the first clamp rests on the first terminal post, and the lower adjacent surface portion of the second clamp rests on the second load electrode.

6. The semiconductor package according to any one of the preceding claims, wherein, The first fixture and the second fixture are identical in the 3D dimension.

7. The semiconductor package according to any one of the preceding claims, wherein, The first load electrode and the second load electrode are laterally spaced apart by a gap of width W, and the free height of the vertical clamp portion is SOH, and W <SOH。 8. The semiconductor package according to any one of the preceding claims, wherein, The carrier is part of the lead frame.

9. The semiconductor package according to any one of the preceding claims, wherein, The package is a leaded package, with leads extending from the sidewall of the package to form a first terminal of the package, and the first terminal post being a lead post.

10. The semiconductor package according to any one of the preceding claims, wherein, The transistor chip is a lateral power chip, particularly a GaN chip.

11. The semiconductor package according to any one of the preceding claims, wherein, The first load electrode and the second load electrode are the drain electrode and the source electrode, respectively.

12. The semiconductor package according to any one of the preceding claims, wherein, The first clamp and the second clamp each include a first contact element, which protrudes from a first sidewall of the first clamp or the second clamp and bends downward, with the bending axis in the longitudinal direction of the first clamp or the second clamp.

13. The semiconductor package according to claim 12, wherein, The first clamp and the second clamp each include a second contact element, which protrudes from the second sidewall of the first clamp or the second clamp and bends downward, with the bending axis in the longitudinal direction of the first clamp or the second clamp, wherein the second sidewall is arranged opposite to the first sidewall.

14. The semiconductor package according to claim 12 or 13, wherein, The first contact element and / or the second contact element are U-shaped.

15. A method of manufacturing a semiconductor package, the semiconductor package comprising: A transistor chip having a first side and a second side opposite to the first side, wherein the transistor chip includes a first load electrode and a second load electrode on the first side; a carrier facing the second side of the transistor chip; a first terminal post laterally disposed next to the transistor chip; a second terminal post laterally disposed next to the transistor chip on the opposite side of the transistor chip, wherein the second terminal post is part of the carrier or physically connected to the carrier; a first clamp connecting the first load electrode to the first terminal post; a second clamp connecting the second load electrode to the second terminal post; wherein the upper surfaces of the first terminal post and the upper surfaces of the second terminal post are disposed at different height levels measured from the upper surface of the carrier, and the first clamp and the second clamp have the same shape, the method comprising: The first terminal post is provided and the second terminal post is provided, wherein the first terminal post and the second terminal post are located at different heights; The transistor chip is placed on the carrier; The first clamp is positioned to connect between the first load electrode and the first terminal post; and The second clamp is placed between the second load electrode and the second terminal post.

16. A semiconductor package, comprising: A transistor chip having a first side and a second side opposite to the first side, wherein the transistor chip includes a first load electrode and a second load electrode on the first side; A carrier facing the second side of the transistor chip; The first terminal post is arranged laterally next to the transistor chip; The second terminal post is laterally arranged next to the transistor chip on the opposite side of the transistor chip, wherein the second terminal post is part of the carrier or physically connected to the carrier; A first clamp connects the first load electrode to the first terminal post; A second clamp connects the second load electrode to the second terminal post; The upper surfaces of the first terminal post and the second terminal post are arranged at different height levels measured from the upper surface of the carrier. The first clamp includes a vertical clamp portion extending in a vertical direction and a horizontal clamp portion extending in a horizontal direction. The horizontal clamp portion of the first clamp has a first horizontal section and a second horizontal section, which are connected by a vertical stepped section.

17. The semiconductor package of claim 16, wherein, The first load electrode and the second load electrode are laterally separated by a gap of width W, and the free height of the vertical clamping portion of the first clamp is SOH, where W>SOH.

18. The semiconductor package according to claim 16 or 17, wherein, The horizontal clamping portion of the first clamp is attached to the first terminal post, and the vertical clamping portion of the first clamp is attached to the first load electrode.

19. The semiconductor package according to any one of claims 16 to 18, wherein, The second clamp includes a vertical clamp portion extending in a vertical direction and a horizontal clamp portion extending in a horizontal direction, wherein the horizontal clamp portion of the second clamp is attached to the second load electrode, and the vertical clamp portion of the second clamp is attached to the second terminal post.

20. The semiconductor package according to any one of claims 16 to 19, wherein, The first clamp and the second clamp have the same shape.

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