Liquid ejecting apparatus and capacitive load driving circuit

Abstract

The invention provides a liquid ejecting apparatus and a capacitive load driving circuit, which can improve the frequency of a driving signal. A capacitive load drive circuit that outputs a drive signal for displacing a capacitive load includes: a gate drive circuit that outputs a first gate drive signal corresponding to a modulation signal output by a modulation circuit, and a second gate drive signal corresponding to the modulation signal; an amplifier circuit that outputs an amplified modulation signal by driving a first transistor driven according to the first gate drive signal and a second transistor driven according to the second gate drive signal; and a demodulation circuit that outputs a driving signal obtained by demodulating the amplified and modulated signal, the first transistor and the second transistor include gallium nitride, and the gate driving circuit, the first transistor, and the second transistor are housed in a single package and constitute a semiconductor device.

Description

Technical Field

[0001] This invention relates to a liquid ejection device and a capacitive load drive circuit. Background Technology

[0002] In liquid ejection devices that eject liquid by driving a capacitive load such as a piezoelectric element, the capacitive circuit driving the output driving signal for the capacitive load is known to use a structure called a Class D amplifier circuit: modulating the signal waveform defined by the base driving signal that forms the basis of the driving signal, amplifying the modulated signal, and demodulating the amplified signal to generate the driving signal. Compared to capacitive load driving circuits using Class A, Class B, or Class AB amplifier circuits, this Class D amplifier circuit has the advantage of reducing power consumption.

[0003] For example, Patent Document 1 discloses a liquid ejection device having a drive signal output circuit, wherein the drive signal output circuit is a capacitive load drive circuit that outputs a drive signal to drive a piezoelectric element as a capacitive load, and the drive signal output circuit includes a D-stage amplifier circuit.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2022-117051

[0005] In recent years, in order to meet market demands for increased productivity of liquid ejection devices, there has been a need for shorter liquid ejection cycles and higher frequencies of drive signals that drive capacitive loads to eject liquid.

[0006] However, in the liquid ejection device described in Patent Document 1, when the frequency of the drive signal output by the capacitive load drive circuit (drive signal output circuit) including the D-stage amplifier circuit is increased, it is necessary to increase the drive frequency of the amplifier circuit that amplifies the modulation signal obtained by modulating the signal waveform specified by the base drive signal. When the drive frequency of the amplifier circuit is increased, the loss in the amplifier circuit increases, which may impair one of the advantages of the capacitive load drive circuit using the D-stage amplifier circuit: the ability to reduce power consumption.

[0007] In particular, when a liquid ejection device drives a capacitive load via a drive signal, and controls the position of the meniscus of the ejection section to control the amount of liquid ejected, the waveform accuracy of the drive signal has a significant impact on the ejection accuracy. Therefore, the capacitive negative drive circuit is required to output a drive signal with high waveform accuracy, including a signal waveform with rapidly changing voltage values. Thus, to achieve a high frequency drive signal while maintaining high waveform accuracy, it is necessary to further increase the drive frequency of the amplifier circuit in the capacitive load drive circuit. As a result, the losses of the amplifier circuit and the power consumption of the capacitive load drive circuit further increase.

[0008] That is, from the viewpoint of increasing the frequency of the drive signal output by the capacitive load drive circuit using the D-level amplifier circuit, the technology described in Patent Document 1 alone is insufficient, and there is room for further improvement. Summary of the Invention

[0009] One aspect of the liquid ejection device according to the present invention comprises:

[0010] A capacitive load is displaced by a drive signal.

[0011] The ejector section ejects liquid as the capacitive load displaces; and

[0012] The capacitive load drive circuit outputs the drive signal.

[0013] The capacitive load drive circuit has:

[0014] The modulation circuit outputs a modulated signal obtained by modulating the base drive signal that forms the basis of the drive signal;

[0015] The gate driving circuit outputs a first gate driving signal and a second gate driving signal corresponding to the modulation signal;

[0016] An amplifier circuit includes a first transistor and a second transistor. The first transistor is driven by a first gate drive signal, and the second transistor is driven by a second gate drive signal. The amplifier circuit outputs an amplified and modulated signal by driving the first transistor and the second transistor.

[0017] The demodulation circuit outputs the drive signal after demodulating the amplified modulation signal.

[0018] The first transistor contains gallium nitride.

[0019] The second transistor contains gallium nitride.

[0020] The gate drive circuit, the first transistor, and the second transistor are housed in a package and constitute a semiconductor device.

[0021] One embodiment of the capacitive load driving circuit involved in this invention is as follows:

[0022] The capacitive load driving circuit outputs a driving signal to the capacitive load, which is then displaced by supplying the driving signal to eject liquid from the ejector section.

[0023] The capacitive load drive circuit has:

[0024] The modulation circuit outputs a modulated signal obtained by modulating the base drive signal that forms the basis of the drive signal;

[0025] The gate driving circuit outputs a first gate driving signal and a second gate driving signal corresponding to the modulation signal;

[0026] An amplifier circuit includes a first transistor and a second transistor. The first transistor is driven by a first gate drive signal, and the second transistor is driven by a second gate drive signal. The amplifier circuit outputs an amplified and modulated signal by driving the first transistor and the second transistor.

[0027] The demodulation circuit outputs the drive signal after demodulating the amplified modulation signal.

[0028] The first transistor contains gallium nitride.

[0029] The second transistor contains gallium nitride.

[0030] The gate drive circuit, the first transistor, and the second transistor are housed in a package and constitute a semiconductor device. Attached Figure Description

[0031] Figure 1 This is a diagram illustrating a simplified configuration of a liquid ejection device.

[0032] Figure 2 This is a diagram illustrating an example of the functional configuration of a liquid ejection device.

[0033] Figure 3 This is a diagram showing a simplified structure of one of the ejection sections 600.

[0034] Figure 4 This is a diagram showing an example of the signal waveforms of the drive signals COMA, COMB, and COMC.

[0035] Figure 5This is a diagram illustrating an example of the selection control circuit and the configuration of the selection circuit.

[0036] Figure 6 This is a diagram illustrating an example of the decoded content in the decoder.

[0037] Figure 7 This is a diagram illustrating an example of the configuration of a selection circuit.

[0038] Figure 8 It is a diagram used to illustrate the selection control circuit and the operation of the selection circuit.

[0039] Figure 9 This is a diagram illustrating an example of the configuration of a drive circuit.

[0040] Figure 10 This is a diagram showing an example of the structure of transistor M1.

[0041] Figure 11 This is a diagram showing an example of the configuration of the drive circuit in the second embodiment.

[0042] Figure 12 This is a diagram showing an example of the configuration of the drive circuit in the third embodiment.

[0043] Explanation of reference numerals in the attached figures

[0044] 1…Liquid ejection device, 2…Ink container, 10…Control unit, 20…Head unit, 21…Carriage, 30…Moving unit, 31…Carriage motor, 32…Circular belt, 40…Conveying unit, 41…Conveying motor, 42…Conveying roller, 50, 50a, 50b, 50c…Drive circuit, 52…Reference voltage output circuit, 60…Piezoelectric element, 100…Control circuit, 210…Selection control circuit, 212…Shift register, 214…Latch circuit, 216…Decoder, 230…Selection circuit, 232a, 232b, 232c…Inverter, 234a, 234b, 234c…Transmission gate, 500, 500a, 500b…Integrated circuit device, 510…Modulation circuit, 512, 513…Adder, 514…Comparator, 515…Inverter, 516…Integrator Attenuator, 517…attenuator, 520…gate drive circuit, 521, 522…gate driver, 550…amplifier circuit, 560…demodulation circuit, 570, 572…feedback circuit, 600…ejector, 601…piezoelectric element, 611, 612…electrode, 621…vibrator plate, 631…cavity, 632…nozzle plate, 641…memory, 651…nozzle, 661…supply port, 701~705…layers, 710…semiconductor substrate, 720…buffer layer, 730…electron transport layer, 740…electron supply layer, 750…gate layer, 760…source electrode, 770…gate electrode, 780…drain electrode, 790…secondary electron gas, C1~C5…capacitor, D1…diode, L1…coil, M1, M2…transistor, P…dielectric, R1~R6…resistor. Detailed Implementation

[0045] Hereinafter, preferred embodiments of the present invention will be described using the accompanying drawings. The drawings are used for ease of explanation. It should be noted that the embodiments described below do not unduly limit the scope of the invention as described in the claims. Furthermore, the components described below are not all essential elements of the present invention.

[0046] 1. First Implementation Method

[0047] 1.1 Overview of the Liquid Ejection Device

[0048] Figure 1This diagram illustrates a simplified example of the configuration of the liquid ejection device 1. The liquid ejection device 1 is a serial printing inkjet printer in which a carriage 21, equipped with a head unit 20 that ejects ink (an example of liquid), reciprocates along a scanning axis and ejects ink from a medium P conveyed in the transport direction, thereby forming a desired image on the medium P. The medium P used in this liquid ejection device 1 can be any printing material such as printing paper, resin film, or fabric. It should be noted that the liquid ejection device 1 is not limited to serial printing inkjet printers; it can also be a line printing inkjet printer. Furthermore, the liquid ejection device 1 is not limited to inkjet printers; it can also be a pigment ejection device for manufacturing color filters such as liquid crystal displays, an electrode material ejection device for forming electrodes in organic EL displays, FED (fiber emitting diode) displays, etc., a biological organic matter ejection device for manufacturing biochips, a three-dimensional modeling device, and a printing and dyeing device, etc.

[0049] like Figure 1 As shown, the liquid ejection device 1 includes an ink container 2, a control unit 10, a head unit 20, a moving unit 30, and a conveying unit 40.

[0050] Various types of ink that can be sprayed onto medium P are stored in ink container 2. Examples of ink colors stored in ink container 2 include black, blue-green, magenta, yellow, red, and gray. Ink container 2 for storing such ink can be ink cartridges, pouch-shaped ink bags made of flexible membranes, or ink cans that allow for ink replenishment.

[0051] The control unit 10 includes, for example, a CPU (Central Processing Unit), an FPGA (Field Programmable Gate Array) and other processing circuits, a semiconductor memory and other storage circuits, and controls the various elements of the liquid ejection device 1, including the head unit 20.

[0052] The head unit 20 is mounted on the carriage 21. The carriage 21 is also fixed to the annular belt 32 included in the moving unit 30. It should be noted that, in addition to the head unit 20, an ink container 2 may also be mounted on the carriage 21.

[0053] The control signal Ctrl-H output by the control unit 10 for controlling the head unit 20 is input to the head unit 20 mounted on the carriage 21. Additionally, ink stored in the ink container 2 is supplied to the head unit 20 via a tube (not shown). Then, the head unit 20 ejects the ink supplied from the ink container 2 based on the input control signal Ctrl-H.

[0054] The moving unit 30 includes a carriage motor 31 and an annular belt 32. The carriage motor 31 is driven by a control signal Ctrl-C input from the control unit 10. The annular belt 32 rotates according to the drive of the carriage motor 31. As a result, the carriage 21, which is fixed to the annular belt 32, reciprocates along the scanning axis. That is, the liquid ejection device 1 includes a carriage 21 that reciprocates along the scanning axis, which intersects the transport direction described later for transporting the medium P on which the ink ejected from the head unit 20 lands.

[0055] The conveying unit 40 includes a conveying motor 41 and a conveying roller 42. The conveying motor 41 is driven based on a control signal Ctrl-T input from the control unit 10. The conveying roller 42 rotates according to the drive of the conveying motor 41. As the conveying roller 42 rotates, the medium P is conveyed along the conveying direction.

[0056] In the liquid ejection device 1 configured as described above, the head unit 20 mounted on the carriage 21 ejects ink onto the medium P in conjunction with the transport of the medium P based on the transport unit 40 and the reciprocating movement of the carriage 21 based on the moving unit 30. Thus, the ink ejected from the head unit 20 lands at any position on the surface of the medium P. As a result, a desired image is formed on the medium P.

[0057] A specific example of the functional configuration of the liquid ejection device 1 constructed as described above will be explained. Figure 2 This diagram illustrates an example of the functional configuration of the liquid ejection device 1. Figure 2 As shown, the liquid ejection device 1 has a control unit 10, a head unit 20, a moving unit 30, and a conveying unit 40.

[0058] The control unit 10 has a control circuit 100.

[0059] The control circuit 100 receives image signals from external devices such as a host computer, generates various control signals corresponding to the image signals, and outputs them to the corresponding components.

[0060] Specifically, the control circuit 100 receives an image signal and performs printing processing on the medium P, thereby generating control signals Ctrl-T and Ctrl-C. The control signal Ctrl-T output by the control circuit 100 is input to the transport motor 41 included in the transport unit 40. The transport motor 41 is driven according to the control signal Ctrl-T. Driven by the transport motor 41, the medium P is transported along the transport direction. Additionally, the control signal Ctrl-C output by the control circuit 100 is input to the carriage motor 31 included in the moving unit 30. The carriage motor 31 is driven according to the control signal Ctrl-C. Driven by the carriage motor 31, the carriage 21 carrying the head unit 20 reciprocates along the scanning axis. It should be noted that the transport unit 40 may also include one or more transport rotors in addition to the transport motor 41. Furthermore, the transport unit 40 may also include a transport motor driver circuit for converting the control signal Ctrl-T into a predetermined signal to drive the transport motor 41. Alternatively, the moving unit 30 may also include a carriage motor driver circuit for converting the control signal Ctrl-C into a predetermined signal that drives the carriage motor 31.

[0061] In addition, the control circuit 100 generates a clock signal SCK, a print data signal SI, a latch signal LAT, and digital base drive signals dA, dB, and dC based on the image signal input from an external device, and outputs them as control signal Ctrl-H to the head unit 20.

[0062] The head unit 20 includes drive circuits 50a, 50b, and 50c, a reference voltage output circuit 52, a selection control circuit 210, multiple selection circuits 230, and multiple ejector sections 600. Furthermore, each of the multiple ejector sections 600 is correspondingly arranged with one of the multiple selection circuits 230.

[0063] In other words, the carriage 21 is equipped with a head unit 20 including a piezoelectric element 60, an ejector 600, and drive circuits 50a, 50b, and 50c.

[0064] The base drive signal dA is input to drive circuit 50a. Drive circuit 50a performs digital-to-analog conversion on the input base drive signal dA and amplifies the converted analog signal by stage D, thereby generating and outputting drive signal COMA as drive signal COM. The base drive signal dB is input to drive circuit 50b. Drive circuit 50b performs digital-to-analog conversion on the input base drive signal dB and amplifies the converted analog signal by stage D, thereby generating and outputting drive signal COMB as drive signal COM. The base drive signal dC is input to drive circuit 50c. Drive circuit 50c performs digital-to-analog conversion on the input base drive signal dC and amplifies the converted analog signal by stage D, thereby generating and outputting drive signal COMC as drive signal COM.

[0065] The reference voltage output circuit 52 generates and outputs a constant DC voltage, such as 5.5V or 6V, as a reference voltage signal VBS by boosting or bucking a power supply voltage (not shown). This reference voltage signal VBS functions as a reference potential for driving the piezoelectric element 60 in the ejector section 600, which will be described later. It should be noted that the voltage value of the reference voltage signal VBS is not limited to 5.5V or 6V; it can also be a ground potential.

[0066] The clock signal SCK, the printed data signal SI, and the latch signal LAT are input to the selection control circuit 210. Based on the input clock signal SCK, printed data signal SI, and latch signal LAT, the selection control circuit 210 generates a selection signal S corresponding to each of the multiple selection circuits 230 and outputs it to the corresponding selection circuit 230.

[0067] The drive signals COMA, COMB, COMC and the corresponding selection signal S output by the selection control circuit 210 are input to each selection circuit 230. Based on the input selection signal S, the selection circuit 230 makes each of the drive signals COMA, COMB, COMC selected or unselected, thereby generating a drive signal VOUT corresponding to each of the plurality of ejector sections 600 and supplying it to the corresponding ejector section 600.

[0068] Each of the multiple ejector sections 600 includes a piezoelectric element 60. A drive signal VOUT output from the corresponding selection circuit 230 is supplied to one end of the piezoelectric element 60 included in each of the multiple ejector sections 600. Additionally, a reference voltage signal VBS output from the reference voltage output circuit 52 is commonly supplied to the other end of the piezoelectric element 60 included in each of the multiple ejector sections 600. Furthermore, the piezoelectric element 60 is driven according to the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS supplied to the other end. An amount of ink corresponding to the driving of the piezoelectric element 60 is ejected from the ejector section 600.

[0069] Here, an example of the structure of the ejection section 600 of the head unit 20 will be described. Figure 3 This is a diagram showing a simplified structure of one of the multiple ejector sections 600 of the head unit 20. (See diagram for details.) Figure 3 As shown, the ejection section 600 includes a piezoelectric element 60, a vibrating plate 621, a cavity 631, and a nozzle 651.

[0070] The cavity 631 is filled with ink supplied from the reservoir 641. Additionally, ink is introduced into the reservoir 641 from the ink container 2 via an ink tube (not shown) and a supply port 661. That is, the cavity 631 is filled with ink stored in the corresponding ink container 2.

[0071] Vibrating plate 621 via Figure 3 The piezoelectric element 60 located on the upper surface is displaced by the drive. Furthermore, the internal volume of the ink-filled cavity 631 expands and contracts with the displacement of the vibrating plate 621. That is, the vibrating plate 621 functions as a diaphragm that changes the internal volume of the cavity 631.

[0072] Nozzle 651 is an opening provided on nozzle plate 632 and communicating with cavity 631. Due to the change in the internal volume of cavity 631, an amount of ink corresponding to the change in internal volume is ejected from nozzle 651.

[0073] The piezoelectric element 60 is a structure in which a piezoelectric body 601 is clamped by a pair of electrodes 611 and 612. In such a structure, the central portion of the electrodes 611 and 612 flexes together with the vibrating plate 621 in the up-down direction according to the potential difference of the signal supplied to the electrodes 611 and 612.

[0074] For example, a drive signal VOUT is supplied to one end of the piezoelectric element 60, i.e., one of the electrodes 611 or 612, and a reference voltage signal VBS is supplied to the other end of the piezoelectric element 60, i.e., the other of the electrodes 611 or 612. When the voltage value of the drive signal VOUT increases, the piezoelectric element 60 flexes upward. Then, by flexing the piezoelectric element 60 upward, the vibrating plate 621 is displaced, and the internal volume of the cavity 631 expands. As a result, ink is introduced from the reservoir 641. On the other hand, when the voltage value of the drive signal VOUT decreases, the piezoelectric element 60 flexes downward. Then, by flexing the piezoelectric element 60 downward, the vibrating plate 621 is displaced, and the internal volume of the cavity 631 shrinks. As a result, an amount of ink corresponding to the degree of shrinkage is ejected from the nozzle 651.

[0075] That is, the ejection unit 600 includes a piezoelectric element 60 driven by a drive signal VOUT based on the drive signal COM, and ink is ejected by the piezoelectric element 60. In other words, the head unit 20 ejects ink according to the drive signals COMA, COMB, and COMC.

[0076] In this embodiment of the liquid ejection device 1, from the viewpoint of increasing the speed of image formation on the medium P, i.e., increasing the productivity of the liquid ejection device 1, it is envisioned that the head unit 20 has more than 3000 ejection sections 600, and the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to the more than 3000 ejection sections 600. That is, it is envisioned that the head unit 20 has more than 3000 piezoelectric elements 60, and the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to the more than 3000 piezoelectric elements 60. As a result, the amount of ink that can be ejected at one time, i.e., the number of dots that can be formed at one time on the medium P, increases, thereby increasing the speed of image formation on the medium P, i.e., increasing the productivity of the liquid ejection device 1. That is, the head unit 20 includes more than 3000 piezoelectric elements 60, and the more than 3000 piezoelectric elements 60 are driven by the drive signal COM output by the drive circuit 50.

[0077] It should be noted that the structure of the piezoelectric element 60 is not limited to... Figure 3 The example shown is one where ink can be ejected from the ejection section 600. Therefore, the structure of the piezoelectric element 60 is not limited to the bending vibration structure described above; for example, a longitudinal vibration structure can also be used. Furthermore, the piezoelectric element 60 can also be configured to flex downwards when the voltage value of the drive signal VOUT increases and flex upwards when the voltage value of the drive signal VOUT decreases.

[0078] As described above, the liquid ejection device 1 of this embodiment includes: a piezoelectric element 60, which is displaced by being supplied with a drive signal VOUT based on drive signals COMA, COMB, and COMC; an ejection section 600, which ejects ink as the piezoelectric element 60 is displaced; and drive circuits 50a, 50b, and 50c, wherein drive circuit 50a outputs drive signal COMA, drive circuit 50b outputs drive signal COMB, and drive circuit 50c outputs drive signal COMC.

[0079] 1.2 Signal waveform of the drive signal

[0080] Next, an example of the signal waveforms of the drive signals COMA, COMB, and COMC output by drive circuits 50a, 50b, and 50c will be explained. Figure 4This is a diagram illustrating an example of the signal waveforms for the drive signals COMA, COMB, and COMC. (See diagram for example.) Figure 4 As shown, the drive signals COMA, COMB, and COMC each include drive waveforms Adp, Bdp, and Cdp corresponding to a period tp from the start of the rise of the latch signal LAT to the next rise of the latch signal LAT. Then, the selection control circuit 210 and the selection circuit 230 select any one of the drive signals COMA, COMB, and COMC, i.e., any one of the drive waveforms Adp, Bdp, and Cdp, based on the clock signal SCK and the printed data signal SI for each period tp, and output it as the drive signal VOUT.

[0081] like Figure 4 As shown, the driving waveform Adp drives the corresponding piezoelectric element 60 by varying the voltage value between voltage va1 and voltage va5 within the period tp. Driven by this piezoelectric element 60, a predetermined amount of ink is ejected from the corresponding nozzle 651. That is, the driving waveform Adp included in the driving signal COMA is a signal waveform used to drive the corresponding piezoelectric element 60 in such a way that a predetermined amount of ink is ejected from the ejection section 600. Here, in the following description, voltage va1 is described as 36V, voltage va2 as 15V, voltage va3 as 12V, voltage va4 as 8V, and voltage va5 as 5V, but the values ​​of voltage va1 to voltage va5 are not limited to these.

[0082] Specifically, at the timing of the rise of the latch signal LAT, i.e., the start of period tp, the voltage value of the drive waveform Adp becomes constant at voltage va3. After this, the voltage value of the drive waveform Adp begins to rise at time ta1, and becomes constant at voltage va1 at time ta2. Then, the voltage value of the drive waveform Adp begins to fall at time ta3, becomes constant at voltage va2 at time ta4, begins to fall again at time ta5, and becomes constant at voltage va5 at time ta6. After this, the voltage value of the drive waveform Adp begins to rise at time ta7, becomes constant at voltage va4 at time ta8, begins to rise again at time ta9, and becomes constant at voltage va3 at time ta10. After this, period tp ends due to the rise of the latch signal LAT.

[0083] In the ejection section 600 supplied with the aforementioned drive waveform Adp, at the timing of the rise of the latch signal LAT, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the tip of the ink stored inside the nozzle 651 of the ejection section 600, that is, the position of the meniscus in the nozzle 651, becomes approximately the same as the position of the tip of the nozzle 651. Then, at time ta1, when the voltage value of the drive waveform Adp rises, the piezoelectric element 60 propels the ink into the ejection section 600 supplied with the drive waveform Adp. Figure 3 As shown, the upward flexing increases the internal volume of cavity 631. Consequently, ink stored inside nozzle 651 of the ejection section 600 is introduced into cavity 631, and the position of the meniscus in nozzle 651 is towards... Figure 3 It moves upwards as shown.

[0084] After this, at time ta2, after the voltage value of the driving waveform Adp becomes constant, and the position of the meniscus in the nozzle 651 of the ejection section 600 is maintained, at time ta3, when the voltage value of the driving waveform Adp decreases, the piezoelectric element 60 in the ejection section 600 supplied with the driving waveform Adp... Figure 3 As shown, the downward flexing reduces the internal volume of cavity 631. Consequently, the ink stored in cavity 631 is pressurized and moves towards the corresponding nozzle 651. At this time, the central portion of the meniscus formed by the ink stored inside nozzle 651 is pushed out, forming a... Figure 3 The liquid column extends downwards as shown.

[0085] At time ta4, when the voltage value of the driving waveform Adp becomes constant, the liquid column formed in the center of the meniscus tends to move towards the center due to inertial force. Figure 3 The downward direction is shown. Then, at time ta5, the voltage value of the driving waveform Adp decreases, and the internal volume of cavity 631 decreases, thereby pressurizing the ink stored in cavity 631. As a result, the ink separates from the liquid column and is ejected as droplets.

[0086] After this, at time ta6, the voltage value of the driving waveform Adp becomes constant. From time ta7 to time ta10, the voltage value of the driving waveform Adp rises and becomes constant at voltage va3. Therefore, the displacement of the piezoelectric element 60 in the ejection section 600 supplied with the driving waveform Adp and the internal volume of the cavity 631 are in the rising edge state of the latch signal LAT. At this time, an amount of ink corresponding to the amount of ink ejected is supplied to the cavity 631 from the ink container 2 via the supply port 661 due to capillary action. Therefore, the position of the meniscus in the nozzle 651 of the ejection section 600 at the timing of the rising of the latch signal LAT is approximately the same as the position of the tip of the nozzle 651.

[0087] In addition, such as Figure 4 As shown, the driving waveform Bdp drives the corresponding piezoelectric element 60 by varying the voltage value between voltage vb1 and voltage vb5 within the period tp. Driven by this piezoelectric element 60, a smaller amount of ink than the predetermined amount is ejected from the corresponding nozzle 651. That is, the driving waveform Bdp included in the driving signal COMB is a signal waveform used to drive the corresponding piezoelectric element 60 in a manner that ejects a smaller amount of ink than the predetermined amount from the ejection section 600. Here, in the following description, voltage vb1 is described as 36V, voltage vb2 as 20V, voltage vb3 as 12V, voltage vb4 as 10V, and voltage vb5 as 7V, but the values ​​of voltages vb1 to vb5 are not limited to these.

[0088] Specifically, at the timing of the rise of the latch signal LAT, i.e., the start of period tp, the voltage value of the drive waveform Bdp becomes constant at voltage vb3. After this, the voltage value of the drive waveform Bdp begins to rise at time tb1 and becomes constant at voltage vb1 at time tb2. Then, the voltage value of the drive waveform Bdp begins to fall at time tb3, becomes constant at voltage vb4 at time tb4, begins to rise at time tb5, becomes constant at voltage vb2 at time tb6, then begins to fall at time tb7 and becomes constant at voltage vb5 at time tb8. Then, the voltage value of the drive waveform Bdp begins to rise at time tb9 and becomes constant at voltage vb3 at time tb10. After this, period tp ends due to the rise of the latch signal LAT.

[0089] In the ejector section 600 supplied with the aforementioned drive waveform Bdp, at the timing of the rise of the latch signal LAT, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the tip of the ink stored inside the nozzle 651 of the ejector section 600, i.e., the position of the meniscus in the nozzle 651, becomes approximately the same as the position of the tip of the nozzle 651. Then, at time tb1, when the voltage value of the drive waveform Bdp rises, the piezoelectric element 60 propels the ink into the ejector section 600 supplied with the drive waveform Bdp. Figure 3 As shown, the upward flexing increases the internal volume of cavity 631. Consequently, ink stored inside nozzle 651 of the ejection section 600 is introduced into cavity 631, and the position of the meniscus in nozzle 651 shifts towards... Figure 3 It moves upwards as shown.

[0090] After this, at time tb2, after the voltage value of the driving waveform Bdp becomes constant, thus maintaining the position of the meniscus in the nozzle 651 of the ejection section 600, at time tb3, when the voltage value of the driving waveform Bdp decreases, the piezoelectric element 60 in the ejection section 600 supplied with the driving waveform Bdp... Figure 3 As shown, the downward flexing reduces the internal volume of cavity 631. Consequently, the ink stored in cavity 631 is pressurized and moves towards the corresponding nozzle 651. At this time, the central portion of the meniscus formed by the ink stored inside nozzle 651 is pushed out, forming a... Figure 3 The liquid column extends downwards as shown.

[0091] At time tb4, when the voltage value of the driving waveform Bdp becomes constant, the liquid column formed in the center of the meniscus tends to move towards the center due to inertial force. Figure 3 The downward extension is shown. Then, at time tb5, as the voltage value of the driving waveform Bdp increases and the internal volume of cavity 631 increases, it tends to extend downwards due to inertial force. Figure 3 The downward-extending liquid column shown is introduced. At time tb6, after the voltage value of the driving waveform Bdp becomes constant, at time tb7, the voltage value of the driving waveform Bdp decreases, thereby reducing the internal volume of cavity 631. The ink stored in cavity 631 is pressurized, and the ink separates from the liquid column, being ejected as droplets. At this time, due to inertial force, at time tb5, the liquid column is about to... Figure 3 After the downward-extending liquid column shown is introduced, at time tb7, the ink droplets separated from the liquid column by pressure are ejected. Therefore, the amount of ink ejected from the ejection section 600 of the supplied drive waveform Bdp is less than the amount of ink ejected from the ejection section 600 of the supplied drive waveform Adp.

[0092] After this, at time tb8, the voltage value of the driving waveform Bdp becomes constant, and at times tb9 to tb10, the voltage value of the driving waveform Bdp rises until the voltage vb3 becomes constant. Therefore, the displacement of the piezoelectric element 60 in the ejection section 600 supplied with the driving waveform Bdp and the internal volume of the cavity 631 become the state at the rising edge of the latch signal LAT. At this time, an amount of ink corresponding to the amount of ink ejected is supplied from the ink container 2 to the cavity 631 via the supply port 661 due to capillary action. Therefore, at the timing of the rising edge of the latch signal LAT, the position of the meniscus in the nozzle 651 of the ejection section 600 becomes approximately the same as the position of the tip of the nozzle 651.

[0093] In addition, such as Figure 4As shown, the driving waveform Cdp drives the corresponding piezoelectric element 60 by varying the voltage value between voltage vc1 and voltage vc2 within the period tp. Driven by this piezoelectric element 60, ink is not ejected from the corresponding nozzle 651, and the ink near the opening of the nozzle 651 vibrates. This reduces the likelihood of increased viscosity of the ink near the opening of the nozzle 651. In other words, the driving waveform Cdp included in the driving signal COMC is a signal waveform used to drive the piezoelectric element 60 in such a way that the ink near the opening of the nozzle 651 of the ejection section 600 vibrates even when ink is not ejected from the ejection section 600. Here, in the following description, voltage vc1 is described as 15V and voltage vc2 as 12V, but the values ​​of voltage vc1 and voltage vc2 are not limited to these.

[0094] Specifically, at the timing of the rise of the latch signal LAT, i.e., the beginning of period tp, the voltage value of the drive waveform Cdp becomes constant at voltage vc2. After this, the voltage value of the drive waveform Cdp begins to rise at time tc1 and becomes constant at voltage vc1 at time tc2. Then, the voltage value of the drive waveform Cdp begins to fall at time tc3 and becomes constant at voltage vc1 at time tc4. After this, period tp ends due to the rise of the latch signal LAT.

[0095] In the ejector section 600 supplied with the aforementioned drive waveform Cdp, at the timing of the rise of the latch signal LAT, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the tip of the ink stored inside the nozzle 651 of the ejector section 600, i.e., the position of the meniscus in the nozzle 651, becomes approximately the same as the position of the tip of the nozzle 651. Then, at time tc1, when the voltage value of the drive waveform Cdp rises, the piezoelectric element 60 propels the ink into the ejector section 600 supplied with the drive waveform Cdp. Figure 3 As shown, the upward flexing increases the internal volume of cavity 631. Consequently, ink stored inside nozzle 651 of the ejection section 600 is introduced into cavity 631, and the position of the meniscus in nozzle 651 is towards... Figure 3 The upward movement is shown. After this, at time tc2, when the voltage value of the driving waveform Bdp becomes constant, and thus the position of the meniscus in the nozzle 651 of the ejection section 600 is maintained, at time tc3, when the voltage value of the driving waveform Cdp decreases, the piezoelectric element 60 moves towards the ejection section 600 supplied with the driving waveform Cdp. Figure 3As shown, the downward flexing reduces the internal volume of cavity 631. Consequently, the ink stored in cavity 631 is pressurized and moves towards the corresponding nozzle 651. At this time, the central portion of the meniscus formed by the ink stored inside nozzle 651 is pushed out, forming a... Figure 3 The liquid column extends downwards as shown. After this, at time tc4, the voltage value of the driving waveform Bdp becomes constant. At this time, the change in the voltage value of the driving waveform Cdp is less than the changes in the voltage values ​​of the driving waveform Adp and the driving waveform Bdp; therefore, the ink does not separate from the liquid column. Consequently, the ink only vibrates and is not ejected from nozzle 651.

[0096] Furthermore, at time tc4, the voltage value of the driving waveform Cdp becomes constant with voltage vc2, thereby the displacement of the piezoelectric element 60 in the ejection section 600 of the driving waveform Cdp and the internal volume of the cavity 631 become the rising edge state of the latch signal LAT.

[0097] As described above, drive circuit 50a outputs drive signal COMA including drive waveform Adp, which drives piezoelectric element 60 by ejecting a predetermined amount of ink from ejection section 600. Drive circuit 50b outputs drive signal COMB including drive waveform Bdp, which drives piezoelectric element 60 by ejecting a smaller amount of ink than the predetermined amount from ejection section 600. Drive circuit 50c outputs drive signal COMC including drive waveform Cdp, which drives piezoelectric element 60 by causing ink to vibrate next to the opening of corresponding nozzle 651 without ejecting ink from ejection section 600. In the following description, the amount of ink ejected from corresponding ejection section 600 when drive waveform Adp is supplied to one end of piezoelectric element 60 is sometimes referred to as a large amount, and the amount of ink ejected from corresponding ejection section 600 when drive waveform Bdp is supplied to one end of piezoelectric element 60 is sometimes referred to as a small amount. In addition, when the driving waveform Cdp is supplied to one end of the piezoelectric element 60, the action of causing the ink near the nozzle opening of the ejection section 600 corresponding to the piezoelectric element 60 to vibrate is sometimes referred to as micro-vibration.

[0098] In this embodiment of the liquid ejection apparatus 1, from the viewpoint of increasing the speed of image formation on the medium P, i.e., increasing the productivity of the liquid ejection apparatus 1, it is envisioned that the period tp of ink ejected from the ejection section 600 by the drive signals COMA, COMB, and COMC is 10 μs or less. That is, it is envisioned that the frequency of the drive signals COMA, COMB, and COMC output by the drive circuits 50a, 50b, and 50c, i.e., the frequency of the period tp, is 100 kHz or more. Therefore, in this embodiment of the liquid ejection apparatus 1, the speed of image formation on the medium P can be increased, i.e., the productivity of the liquid ejection apparatus 1 can be increased.

[0099] 1.3 Selection control circuit, its structure, and its operation

[0100] Next, the configuration and operation of the selection control circuit 210 and the selection circuit 230, which generate drive signals VOUT by making the signal waveforms included in the drive signals COMA, COMB, and COMC selectable or non-selectable and output them to the corresponding ejection section 600, will be explained. Figure 5 This is a diagram showing an example of the configuration of the selection control circuit 210 and the selection circuit 230. It should be noted that in the following description, the more than 3,000 piezoelectric elements 60 of the head unit 20 will be described as n piezoelectric elements 60.

[0101] The clock signal SCK, the printed data signal SI, and the latch signal LAT are input to the selection control circuit 210. Furthermore, a group of shift registers (S / R) 212, latch circuits 214, and decoders 216 are correspondingly arranged in the selection control circuit 210 for each of the n piezoelectric elements 60. That is, the selection control circuit 210 includes n shift registers 212, n latch circuits 214, and n decoders 216.

[0102] The print data signal SI is input synchronously to the selection control circuit 210 along with the clock signal SCK. Furthermore, the print data signal SI, corresponding serially to each of the n piezoelectric elements 60, includes 2 bits of print data [SIH, SIL] for selecting any one of "Large Dot LD", "Small Dot SD", "Non-Recording ND", and "Micro Vibration BSD". The print data [SIH, SIL] included in the print data signal SI is held in n shift registers 212 corresponding to the n piezoelectric elements 60. Specifically, the n shift registers 212 corresponding to the piezoelectric elements 60 are cascaded together, and the serially input print data signal SI is sequentially transmitted to the subsequent shift register 212 according to the clock signal SCK. Then, the clock signal SCK stops as the print data [SIH, SIL] is held in the corresponding shift register 212. Thus, the print data [SIH, SIL] included in the print data signal SI is held in the corresponding shift register 212. It should be noted that in Figure 5 In order to distinguish the n shift registers 212, they are sequentially described as level 1, level 2, ..., level n from the upstream side of the input printed data signal SI.

[0103] Each of the n latch circuits 214 latches the printed data [SIH, SIL] held in the corresponding shift register 212 along with the rising edge of the latch signal LAT. Then, the printed data [SIH, SIL] latched by the latch circuits 214 is input to the corresponding decoder 216. Figure 6 This diagram illustrates an example of the decoded content in decoder 216. During period tp, decoder 216 outputs selection signals S1, S2, and S3 as selection signals S at logic levels specified by the input printed data [SIH, SIL]. For example, when printed data [SIH, SIL] = [1, 0] is input to decoder 216, decoder 216 outputs a low-level selection signal S1, a high-level selection signal S2, and a low-level selection signal S3 during period tp.

[0104] The selection signals S1, S2, and S3 output by the decoder 216 are input to the selection circuit 230. The selection circuit 230 is configured to correspond to each of the n ejector sections 600. Figure 7 This is a diagram illustrating an example of the configuration of the selection circuit 230. (As shown...) Figure 7 As shown, the selection circuit 230 includes inverters 232a, 232b, and 232c as NOT circuits, and transmission gates 234a, 234b, and 234c.

[0105] The selection signal S1 is input to the positive control terminal (not marked with a circle) of transmission gate 234a, and after the logic level is inverted by inverter 232a, it is also input to the negative control terminal (marked with a circle) of transmission gate 234a. Additionally, a drive signal COMA is supplied to the input terminal of transmission gate 234a. Then, transmission gate 234a conducts between its input and output terminals when the selection signal S1 is high, and de-conducts between its input and output terminals when the selection signal S1 is low. That is, transmission gate 234a outputs the drive waveform Adp, which includes the drive signal COMA, from its output terminal when the logic level of the selection signal S1 is high, and does not output the drive waveform Adp, which includes the drive signal COMA, from its output terminal when the logic level of the selection signal S1 is low.

[0106] The selection signal S2 is input to the positive control terminal (not marked with a circle) of transmission gate 234b, and after the logic level is inverted by inverter 232b, it is also input to the negative control terminal (marked with a circle) of transmission gate 234b. Additionally, a drive signal COMB is supplied to the input terminal of transmission gate 234b. Then, when a high-level selection signal S2 is input, transmission gate 234b connects its input and output terminals; when a low-level selection signal S2 is input, it disconnects them. That is, when the logic level of the selection signal S2 is high, transmission gate 234b outputs the drive waveform Bdp, which includes the drive signal COMB, from its output terminal; when the logic level of the selection signal S2 is low, it does not output the drive waveform Bdp, which includes the drive signal COMB, from its output terminal.

[0107] The selection signal S3 is input to the positive control terminal (not marked with a circle) of transmission gate 234c, and after the logic level is inverted by inverter 232c, it is also input to the negative control terminal (marked with a circle) of transmission gate 234c. Additionally, a drive signal COMC is supplied to the input terminal of transmission gate 234c. Then, when the selection signal S3 is input at a high level, transmission gate 234c makes the input and output terminals conductive; when the selection signal S3 is input at a low level, it makes the input and output terminals non-conductive. That is, when the logic level of the selection signal S3 is high, transmission gate 234c outputs the drive waveform Cdp included in the drive signal COMC from its output terminal; when the logic level of the selection signal S3 is low, it does not output the drive waveform Cdp included in the drive signal COMC from its output terminal.

[0108] Furthermore, in the selection circuit 230, the output terminals of transmission gates 234a, 234b, and 234c are connected to a common ground. The signal at the connection point where the output terminals of transmission gates 234a, 234b, and 234c are connected to a common ground is output as the drive signal VOUT.

[0109] Here, use Figure 8 The operation of the selection control circuit 210 and the selection circuit 230 will be explained. Figure 8 This diagram illustrates the operation of the selection control circuit 210 and the selection circuit 230. The printing data signal SI is input to the selection control circuit 210 as a serial signal synchronized with the clock signal SCK, and is sequentially transmitted to the n shift registers 212 corresponding to the n piezoelectric elements 60, also synchronized with the clock signal SCK. After this, when the input of the clock signal SCK stops, the shift registers 212 hold the printing data [SIH, SIL] corresponding to each of the n piezoelectric elements 60. It should be noted that the printing data signal SI is input to the nth, ..., 2nd, and 1st stages of the shift registers 212 in a corresponding order.

[0110] Furthermore, when the latch signal LAT rises, each pair of printed data [SIH, SIL] held in the shift register 212 by the latch circuit 214 is latched simultaneously. It should be noted that... Figure 8 The LT1, LT2, ..., LTn shown represent printed data [SIH, SIL] latched by latching circuits 214 corresponding to shift registers 212 of levels 1, 2, ..., n.

[0111] Decoder 216 outputs selection signals S1, S2, and S3 at logic levels specified by the latched printed data [SIH, SIL] for each cycle tp. Then, selection circuit 230 generates drive signal VOUT by making drive signals COMA, COMB, and COMC selected or deselected according to the logic levels of the selection signals S1, S2, and S3 output by decoder 216.

[0112] Specifically, when printing data [SIH, SIL] = [1, 1] is input to decoder 216, decoder 216 sets the logic levels of selection signals S1, S2, and S3 within period tp to H, L, and L levels, respectively. Consequently, selection circuit 230 supplies a drive signal VOUT, including the drive waveform Adp, to the piezoelectric element 60 of the corresponding ejector section 60 within period tp. As a result, a large amount of ink is ejected from the corresponding ejector section 600. This large amount of ink ejected from the ejector section 600 lands on the medium P, forming a large dot LD on the medium P.

[0113] Furthermore, when printing data [SIH, SIL] = [1, 0] is input to decoder 216, decoder 216 sets the logic levels of selection signals S1, S2, and S3 within period tp to L, H, and L levels, respectively. Consequently, selection circuit 230 supplies a drive signal VOUT, including the drive waveform Bdp, to the piezoelectric element 60 of the corresponding ejector section 60 within period tp. As a result, a small amount of ink is ejected from the corresponding ejector section 600. This small amount of ink ejected from the ejector section 600 lands on the medium P, forming small dots SD on the medium P.

[0114] Furthermore, when printing data [SIH, SIL] = [0, 1] is input to decoder 216, decoder 216 sets the logic levels of selection signals S1, S2, and S3 in period tp to L, L, L levels. Consequently, selection circuit 230 does not select drive waveforms Adp, Bdp, and Cdp within period tp. At this time, a signal maintaining a constant voltage value through the capacitance component of the piezoelectric element 60 of the corresponding ejector section 600 is supplied. That is, selection circuit 230 supplies a drive signal VOUT with a constant voltage value to the piezoelectric element 60 of the corresponding ejector section 600 within period tp. As a result, the piezoelectric element 60 of the corresponding ejector section 600 is not driven, and ink is not ejected from the ejector section 600. Therefore, non-recording ND is performed, where ink does not fall onto medium P and no point is formed on medium P.

[0115] Furthermore, when printing data [SIH, SIL] = [0, 0] is input to decoder 216, decoder 216 sets the logic levels of selection signals S1, S2, and S3 in period tp to L, L, and H levels, respectively. Consequently, selection circuit 230 supplies a drive signal VOUT, including the drive waveform Cdp, to the piezoelectric element 60 of the corresponding ejector section 600 within period tp. As a result, micro-vibration BSD is performed, causing ink to vibrate near the opening of the nozzle 651 of the ejector section 600 even when no ink is ejected from the corresponding ejector section 600.

[0116] As described above, the selection control circuit 210 and the selection circuit 230 generate a drive signal VOUT by making the signal waveforms of the drive signals COMA, COMB, and COMC output by the drive circuits 50a, 50b, and 50c select or not select, and output it to the piezoelectric element 60 of the corresponding ejection section 600.

[0117] 1.4 Composition and Operation of the Drive Circuit

[0118] Next, the configuration and operation of the drive circuits 50a, 50b, and 50c included in the liquid ejection device 1 of this embodiment will be described. Here, drive circuits 50a, 50b, and 50c are identical in configuration, differing only in the input and output signals. Therefore, in the following description, drive circuits 50a, 50b, and 50c will be simply referred to as drive circuit 50 without distinction. In this case, it will be described that a base drive signal dO, serving as base drive signals dA, dB, and dC, is input to drive circuit 50, and drive circuit 50 outputs a drive signal COM, serving as drive signals COMA, COMB, and COMC.

[0119] Figure 9 This is a diagram illustrating an example of the configuration of the drive circuit 50. (As shown...) Figure 9 As shown, the driving circuit 50 includes a DAC (Digital to Analog Converter) 511, a modulation circuit 510, a gate driving circuit 520, an amplifier circuit 550, a demodulation circuit 560, feedback circuits 570 and 572, and several other circuit elements.

[0120] A digital signal with a defined waveform of the drive signal COM is input to DAC511, namely the base drive signal dO. DAC511 converts the input base drive signal dO into a base drive signal aO as an analog signal and outputs it to modulation circuit 510. The amplified signal of the base drive signal aO output by DAC511 is equivalent to the drive signal COM. In other words, the base drive signal aO is the target signal before amplification of the drive signal COM, and the base drive signal dO is the target signal before amplification of the drive signal COM, and is a digital signal that defines the waveform shape of the drive signal COM. The voltage amplitude of the base drive signal aO output by DAC511 is set to, for example, 1V to 2V.

[0121] The modulation circuit 510 generates a modulation signal Ms by modulating the base drive signal aO and outputs it to the gate drive circuit 520. The modulation circuit 510 includes adders 512 and 513, comparator 514, inverter 515, integrator attenuator 516, and attenuator 517.

[0122] The integrator attenuator 516 attenuates and integrates the signal corresponding to the voltage value of the drive signal COM input via the feedback circuit 570 (described later), and outputs the integrated signal to the input terminal on the - side of the adder 512. A base drive signal aO is input to the input terminal on the + side of the adder 512. The adder 512 generates a signal by subtracting the voltage value of the signal input to the - side from the voltage value of the signal input to the input terminal on the + side, and then integrates the result, outputting this signal to the input terminal on the + side of the adder 513. Here, the maximum value of the voltage amplitude of the base drive signal aO is approximately 2V, as previously described, while the maximum value of the voltage value of the drive signal COM sometimes exceeds 40V. When calculating the deviation, the integrator attenuator 516 attenuates the drive signal COM input via the feedback circuit 570 (described later) to match the range of the voltage amplitude of the base drive signal aO with the range of the voltage amplitude of the drive signal COM.

[0123] Attenuator 517 supplies a voltage, after attenuating the high-frequency components of the drive signal COM input via feedback circuit 572 (described later), to the input terminal on the - side of adder 513. The signal output by adder 512 is input to the input terminal on the + side of adder 513. A voltage signal As is generated by subtracting the voltage value of the signal input to the - side of the input from the voltage value of the signal input to the + side of adder 513, and is output to comparator 514. That is, the voltage signal As is the signal obtained by subtracting the voltage value of the signal input via feedback circuit 570 (described later) from the voltage value of the base drive signal aO, and further subtracting the voltage value of the signal input via feedback circuit 572 (described later). Therefore, the voltage signal As becomes a signal after correcting for the deviation of the attenuated voltage of the drive signal COM subtracted from the voltage value of the target base drive signal aO using the high-frequency components of the drive signal COM.

[0124] Comparator 514 pulse-modulates the voltage signal As and outputs it as a modulation signal Ms. Specifically, comparator 514 outputs the following modulation signal Ms: during the period when the voltage value of the voltage signal As rises, it becomes a high level when the voltage value of the voltage signal As is above a predetermined threshold Vth1; during the period when the voltage value of the voltage signal As falls, it becomes a low level when the voltage value of the voltage signal As is below a predetermined threshold Vth2. Here, the thresholds Vth1 and Vth2 are set to a relationship where threshold Vth1 > threshold Vth2. The frequency and duty cycle of this modulation signal Ms change in a way that matches the base drive signals dO and aO. That is, by adjusting the modulation gain, which corresponds to the sensitivity of attenuator 517, the amount of change in the frequency and duty cycle of the modulation signal Ms can be adjusted.

[0125] The modulation signal Ms is input to the gate driver 521 included in the gate drive circuit 520. Additionally, after the modulation signal Ms is inverted by the inverter 515, it is also input to the gate driver 522 included in the gate drive circuit 520. That is, the gate driver 521 and the gate driver 522 are input signals with an exclusive relationship to each other at the logic level.

[0126] Here, timing can also be controlled to ensure that the logic levels of the signals input to gate drivers 521 and 522 do not simultaneously reach the H level. That is, the aforementioned "exclusivity of logic levels" means that the logic levels of the signals input to gate driver 521 and the logic levels of the signals input to gate driver 522 do not simultaneously reach the H level, and also includes the case where the logic levels of the signals input to gate driver 521 and the logic levels of the signals input to gate driver 522 simultaneously reach the L level.

[0127] The gate drive circuit 520 includes gate driver 521 and gate driver 522.

[0128] Gate driver 521 levels-shifts the modulation signal Ms output by comparator 514 to generate and output gate signal Hgd. The high-potential side of the power supply voltage of gate driver 521 is electrically connected to one end of capacitor C5 and the cathode of diode D1. The other end of capacitor C5 is electrically connected to the junction of the source terminal of transistor M1 and the drain terminal of transistor M2. A DC voltage, such as a voltage signal Vm, generated by a power supply circuit (not shown), is supplied to the anode of diode D1. This generates a potential difference across capacitor C5 that is approximately equal to the voltage signal Vm. The low-potential side of the power supply voltage of gate driver 521 is electrically connected to the junction of the source terminal of transistor M1 and the drain terminal of transistor M2. Therefore, the gate driver 521 generates and outputs the following gate signal Hgd according to the logic level of the input modulation signal Ms: the voltage value of the H level is greater than the voltage value of the voltage signal Vm at the connection point of the source terminal of transistor M1 and the drain terminal of transistor M2, and the voltage value of the L level becomes the voltage value at the connection point of the source terminal of transistor M1 and the drain terminal of transistor M2.

[0129] Gate driver 522 operates on a lower potential side than gate driver 521. Gate driver 522 levels-shifts the logic level of the modulation signal Ms output by comparator 514 after it has been inverted by inverter 515, thereby generating and outputting a gate signal Lgd. A voltage signal Vm is supplied to the high potential side of the power supply voltage of gate driver 522, and a ground potential is supplied to the low potential side of the power supply voltage of gate driver 522. Then, based on the logic level of the input signal, gate driver 522 generates and outputs a gate signal Lgd with a voltage value of H level equal to the voltage value of voltage signal Vm and a voltage value of L level equal to the ground potential.

[0130] Here, as described above, the gate signal Hgd is a signal obtained by level-shifting the voltage value of the modulation signal Ms, and the gate signal Lgd is a signal obtained by level-shifting the voltage value of the inverted signal after inverting the logic level of the modulation signal Ms. Therefore, the gate signals Hgd and Lgd output by the gate drive circuit 520 are also considered as signals modulated by the base drive signals dO and aO.

[0131] The amplifier circuit 550 includes a transistor pair consisting of transistor M1 and transistor M2.

[0132] A DC voltage, i.e., a voltage signal VHV, is supplied to the drain terminal of transistor M1, for example. It should be noted that the voltage value of the voltage signal VHV only needs to be greater than the maximum voltage value of the drive signal COM output by the drive circuit 50, and is not limited to 42V. The gate terminal of transistor M1 is electrically connected to one end of resistor R1. A gate signal Hgd is input to the other end of resistor R1. That is, a gate signal Hgd is input to the gate terminal of transistor M1 via resistor R1. The source terminal of transistor M1 is electrically connected to the drain terminal of transistor M2. Furthermore, in transistor M1, the conduction state between the drain terminal and the source terminal is controlled by the gate signal Hgd input to the gate terminal.

[0133] The drain terminal of transistor M2 is electrically connected to the source terminal of transistor M1. The gate terminal of transistor M2 is electrically connected to one end of resistor R2. The other end of resistor R2 receives a gate signal Lgd. That is, a gate signal Lgd is input to the gate terminal of transistor M2 via resistor R2. A ground potential is supplied to the source terminal of transistor M2. Furthermore, in transistor M2, the conduction state between the drain and source terminals is controlled by the gate signal Lgd input to the gate terminal.

[0134] In the following description, the state in which the drain and source terminals of transistors M1 and M2 are controlled to be on is sometimes referred to as on, and the state in which the drain and source terminals of transistors M1 and M2 are controlled to be off is sometimes referred to as off.

[0135] In the amplifier circuit 550 configured as described above, when transistor M1 is controlled to be off and transistor M2 is controlled to be on, the voltage at the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2 becomes ground potential. At this time, a voltage signal Vm is supplied to the high potential side of the power supply voltage of the gate driver 521. On the other hand, when transistor M1 is controlled to be on and transistor M2 is controlled to be off, the voltage at the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2 becomes voltage signal VHV. At this time, a signal equal to the sum of the voltage values ​​of voltage signal VHV and voltage signal Vm is supplied to the high potential side of the power supply voltage of the gate driver 521. That is, the gate driver 521 driving transistor M1 uses capacitor C5 as a floating power source. The voltage value at the other end of capacitor C5, that is, the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2, changes to ground potential or voltage signal VHV according to the operation of transistor M1 and transistor M2. Thus, the gate driver 521 generates a gate signal Hgd and supplies it to the gate terminal of transistor M1. The L level of the gate signal Hgd is the voltage value of voltage signal VHV, and the H level is the sum of the voltage values ​​of voltage signal VHV and voltage signal Vm.

[0136] On the other hand, the gate driver 522 that drives transistor M2 generates a gate signal Lgd independently of the operation of transistors M1 and M2 and supplies it to the gate terminal of transistor M2. The L level of the gate signal Lgd is ground potential and the H level is the voltage value of voltage signal Vm.

[0137] As described above, transistors M1 and M2 of amplifier circuit 550 operate according to gate signals Hgd and Lgd, and amplify the modulation signal Ms after the base drive signals dO and aO are modulated based on the voltage signal VHV. Furthermore, amplifier circuit 550 outputs the amplified signal as the amplified modulation signal AMs from the connection point where the source terminals of transistor M1 and the drain terminals of transistor M2 are connected to a common ground.

[0138] The demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing it and generates a drive signal COM. Furthermore, the demodulation circuit 560 outputs the generated drive signal COM from the drive circuit 50.

[0139] The demodulation circuit 560 includes a coil L1 and a capacitor C1. One end of the coil L1 is electrically connected to the source terminal of transistor M1 and the drain terminal of transistor M2. Thus, an amplified modulation signal AMs is input to one end of the coil L1. The other end of the coil L1 is connected to the Out terminal, which is the output of the drive circuit 50. The other end of the coil L1 is also connected to one end of the capacitor C1. Furthermore, a ground potential is supplied to the other end of the capacitor C1. That is, the coil L1 and the capacitor C1 constitute a low-pass filter. Moreover, through the low-pass filter configured in the demodulation circuit 560, the amplified modulation signal AMs is smoothed, thereby generating a drive signal COM.

[0140] The feedback circuit 570 includes resistors R3 and R4. One end of resistor R3 is connected to the Out terminal of the output drive signal COM, and the other end of resistor R3 is connected to the integrating attenuator 516 of the modulation circuit 510 and one end of resistor R4. A voltage signal VHV is supplied to the other end of resistor R4. Thus, the drive signal COM from the feedback circuit 570 is pulled up and fed back to the integrating attenuator 516 of the modulation circuit 510 through the Out terminal.

[0141] The feedback circuit 572 includes capacitors C2, C3, and C4, and resistors R5 and R6. One end of capacitor C2 is connected to the Out terminal of the output drive signal COM, and the other end of capacitor C2 is connected to one end of resistor R5 and one end of resistor R6. A ground potential is supplied to the other end of resistor R5. Thus, capacitor C2 and resistor R5 function as a high-pass filter.

[0142] Additionally, the other end of resistor R6 is connected to one end of capacitor C4 and one end of capacitor C3. Ground potential is supplied to the other end of capacitor C3. Therefore, resistor R6 and capacitor C3 function as a low-pass filter.

[0143] As described above, the feedback circuit 572 is configured with a high-pass filter and a low-pass filter. Therefore, the feedback circuit 572 functions as a band-pass filter that allows the drive signal COM to pass through a predetermined frequency range. Furthermore, the other end of the capacitor C4 included in the feedback circuit 572 is connected to the attenuator 517 of the modulation circuit 510. Thus, the DC component of the high-frequency component of the drive signal COM, after passing through the feedback circuit 572 which functions as a band-pass filter allowing predetermined frequency components to pass, is blocked, and the signal is fed back to the attenuator 517 of the modulation circuit 510.

[0144] Furthermore, the drive signal COM output from terminal Out is a demodulated signal obtained by smoothing the amplified modulation signal AMs based on the base drive signal dO through demodulation circuit 560. Additionally, the drive signal COM output from demodulation circuit 560 is integrated and attenuated via feedback circuit 570 before being fed back to adder 512. Thus, drive circuit 50 oscillates self-excitedly at a frequency determined by the feedback delay and the feedback transfer function. However, sometimes the delay is large due to the feedback path solely via the integrator attenuator 516 of modulation circuit 510, and sometimes the self-excited oscillation frequency cannot be increased to a level sufficient to ensure the accuracy of drive signal COM.

[0145] The drive circuit 50 of this embodiment has a path that feeds back the high-frequency components of the drive signal COM via the feedback circuit 572 and the attenuator 517 of the modulation circuit 510, which is different from the path via the integral attenuator 516 of the modulation circuit 510. As a result, in the drive circuit 50 of this embodiment, the delay is reduced when viewed from the perspective of the circuit constituting the drive circuit 50 as a whole, and the frequency of the voltage signal As can be increased to a level that sufficiently ensures the accuracy of the drive signal COM.

[0146] As described above, the driving circuit 50 of this embodiment includes: a modulation circuit 510 that outputs a modulation signal Ms after modulating the base driving signals dO and aO, which form the basis of the driving signal COM; a gate driving circuit 520, including a gate driver 521 and a gate driver 522, wherein the gate driver 521 outputs a gate signal Hgd corresponding to the modulation signal Ms, and the gate driver 522 outputs a gate signal Lgd corresponding to the modulation signal Ms; an amplifier circuit 550, including a transistor M1 and a transistor M2, wherein the transistor M1 is driven according to the gate signal Hgd, and the transistor M2 is driven according to the gate signal Lgd, and the amplifier circuit 550 outputs an amplified modulation signal AMs by driving the transistors M1 and M2; a demodulation circuit 560 that outputs a driving signal COM after demodulating the amplified modulation signal AMs; and feedback circuits 570 and 572 that feed back the driving signal COM to the modulation circuit 510.

[0147] Here, when the oscillation frequency of the self-excited oscillation of the drive circuit 50, i.e., the drive frequency of transistors M1 and M2, increases, the switching losses generated in transistors M1 and M2 increase, resulting in increased heat generation in transistors M1 and M2. Furthermore, when the heat generation of transistors M1 and M2 increases, the stability of the operation of the drive circuit 50, including transistors M1 and M2, decreases, and the waveform accuracy of the drive signal COM output by the drive circuit 50 decreases. In particular, the turn-on and turn-off times of transistors M1 and M2, and the drain current flowing through transistors M1 and M2, contribute significantly to the switching losses generated in transistors M1 and M2. Therefore, as with the liquid ejection device 1 of this embodiment, when the drive circuit 50 supplies a high-frequency drive signal COM of 100kHz or higher to a large number of piezoelectric elements 60, i.e., more than 3000 piezoelectric elements 60, the current flowing through transistors M1 and M2 sometimes increases, and the drive frequency of transistors M1 and M2 exceeds 8MHz. As a result, the switching losses of transistors M1 and M2 increase significantly. Consequently, the possibility of increased heat generation in transistors M1 and M2 further increases, and the possibility of decreased stability in the operation of the drive circuit 50 further increases.

[0148] To address this problem, by setting the driving frequencies of transistors M1 and M2 to the same frequency as when the frequency of the driving signal COM is below 100kHz, the possibility of increased switching losses and increased heat generation of transistors M1 and M2 can be reduced. However, in the case of a liquid ejection device 1 that controls the position of the curved surface of the ejection section 600 and the amount of ink ejected from the ejection section 60 by driving the piezoelectric element 60 as shown in this embodiment, from the viewpoint of detailed control of the ink ejection amount, it is necessary to finely control the driving of the piezoelectric element 60 within the period tp, and the voltage value of the driving signal COM needs to be such that... Figure 4 As shown, the voltage of the drive signal COM changes drastically in a short period of time. Even at high frequencies above 100kHz, there are instances where the voltage of the drive signal COM changes abruptly by more than 20V per 1μs, and there are also periods when the voltage of the drive signal COM remains constant for less than 0.25μs. Therefore, in the drive circuit 50 for the output drive signal COM, assuming that the drive frequencies of transistors M1 and M2 are set to the same as when the frequency of the drive signal COM is below 100kHz, it is impossible to ensure a sufficient number of samples to maintain the waveform accuracy of the drive signal COM. This could lead to a decrease in the waveform accuracy of the output drive signal COM and a decrease in the ink ejection accuracy.

[0149] In other words, from the viewpoint of improving the productivity of the liquid ejection device 1, when the drive circuit 50 supplies a high-frequency drive signal COM of 100kHz or higher to a large number of piezoelectric elements 60, i.e., more than 3,000 piezoelectric elements 60, in order to maintain the high waveform accuracy of the drive signal COM, it is necessary to further increase the drive frequency of transistors M1 and M2. Therefore, the drive circuit 50 is required to reduce the heat generated in the drive circuit 50 and reduce the possibility of the waveform accuracy of the output drive signal COM, even when the drive frequency of transistors M1 and M2 increases.

[0150] In contrast, conventionally, transistors with low switching losses could be selected from silicon-based transistors used as transistors M1 and M2. However, since switching losses and conduction losses in transistors are inversely related, selecting transistors with low switching losses results in increased conduction losses, making it impossible to reduce heat generation in the drive circuit 50. In other words, to supply a high-frequency drive signal COM of 100kHz or higher to the drive circuit 50 of the liquid ejection device 1, which contains more than 3000 piezoelectric elements 60, a transistor with reduced conduction and switching losses is required. Therefore, a transistor with a Baliga performance index exceeding that of silicon-based transistors is required.

[0151] Therefore, in the drive circuit 50 of this embodiment, the characteristic structures of transistors M1 and M2 reduce losses generated in transistors M1 and M2 even when they are driven at high frequencies. Consequently, even when the drive circuit 50 supplies high-frequency drive signals COMA, COMB, and COMC of 100kHz or higher to numerous piezoelectric elements 60 (i.e., more than 3000 piezoelectric elements 60), the heat generated in the drive circuit 50 can be reduced, and the possibility of a decrease in the waveform accuracy of the output drive signal COM can be decreased.

[0152] An example of the structure of such transistors M1 and M2 will be described. Here, transistors M1 and M2 have the same structure. Therefore, in the following description, only the structure of transistor M1 will be described, and the illustrations and descriptions of the structure of transistor M2 will be simplified or omitted.

[0153] Figure 10 This is a diagram illustrating an example of the structure of transistor M1. When describing the structure of transistor M1, orthogonal X-axis and Y-axis are used. Furthermore, in the following description, the starting side of the arrow on the X-axis is sometimes referred to as the -X side, and the leading side as the +X side; similarly, the starting side of the arrow on the Y-axis is referred to as the -Y side, and the leading side as the +Y side.

[0154] like Figure 10 As shown, transistor M1 has layers 701-705, a source electrode 760, a gate electrode 770, and a drain electrode 780.

[0155] Layer 701 is located at the -Y side of transistor M1 and includes a semiconductor substrate 710. Such a semiconductor substrate 710 can be, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a sapphire substrate.

[0156] Layer 702 is located above layer 701, on the +Y side, and includes a buffer layer 720. The buffer layer 720 is configured to include one or more nitride semiconductors. This buffer layer 720 reduces the possibility of warping of the semiconductor substrate 710 and cracking in the transistor M1 due to the difference in thermal expansion coefficients between the semiconductor substrate 710 and the electron transport layer 730 (described later). For example, the buffer layer 720 can be configured as a graded AlGaN with different compositions including aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and aluminum (Al).

[0157] Layer 703 is located above layer 702, on the +Y side, and includes an electron transport layer 730. This electron transport layer 730 is configured to include a nitride semiconductor such as GaN. Alternatively, to reduce leakage current, the electron transport layer 730 may be partially insulated by introducing impurities into a portion of it, making the area outside the surface region on the +Y side semi-insulating.

[0158] Layer 704 is located above layer 703, on the +Y side, and includes an electron supply layer 740. This electron supply layer 740 is configured to include a nitride semiconductor, such as AlGaN, having a band gap larger than that of the electron transport layer 730.

[0159] Here, the electron transport layer 730 and the electron supply layer 740 are constructed using nitride semiconductors with different lattice constants. Therefore, a lattice-mismatched heterojunction is formed between GaN, the nitride semiconductor constituting the electron transport layer 730, and AlGaN, the nitride semiconductor constituting the electron supply layer 740. At this time, due to the spontaneous polarization of the electron transport layer 730 and the electron supply layer 740, and the piezoelectric polarization caused by crystal distortion near the heterojunction boundary, the energy level of the transport body of the electron transport layer 730 near the heterojunction boundary is lower than the Fermi level. Consequently, a two-dimensional electron gas 790 diffuses into the electron transport layer 730 near the heterojunction boundary between the electron transport layer 730 and the electron supply layer 740.

[0160] Layer 705 is located above layer 704, on the +Y side, and includes gate layer 750. This gate layer 750 is configured to include a nitride semiconductor containing acceptor impurities, such as gallium nitride (p-type GaN) doped with acceptor impurities. Here, zinc (Zn), magnesium (Mg), carbon (C), etc., can be used as the doped acceptor impurities.

[0161] The gate electrode 770 is located above the gate layer 750 included in layer 705, i.e., on the +Y side, and is electrically connected to the gate terminal of transistor M1. This gate electrode 770 is configured to include one or more metal layers, such as titanium nitride (TiN), and forms a Schottky junction with the gate layer 750. It should be noted that the gate electrode 770 may also be configured, for example, to include a first metal layer made of titanium (Ti) and a second metal layer made of TiN disposed above the first metal layer.

[0162] The source electrode 760 is located above layer 704 on the +Y side, at the -X side of gate layer 750 and gate electrode 770, and is electrically connected to the source terminal of transistor M1. Similarly, the drain electrode 780 is located above layer 704 on the +Y side, at the +X side of gate layer 750 and gate electrode 770, and is electrically connected to the drain terminal of transistor M1. Such source electrode 760 and drain electrode 780 can be constructed from any combination of one or more metal layers, such as Ti, TiN, and Al. It should be noted that the source electrode 760 and drain electrode 780 can also be constructed from alloys including aluminum-silicon-copper alloy (Al-Si-Cu) and aluminum-copper alloy (AlCu).

[0163] That is, each of transistors M1 and M2 includes: a layer 703 including an electron transport layer 730 configured to include a nitride semiconductor such as GaN; a layer 704 including a nitride semiconductor such as AlGaN with a band gap larger than that of the electron transport layer 730; a source electrode 760 electrically connected to the source terminal of transistor M1; a drain electrode 780 electrically connected to the drain terminal of transistor M1; and a gate electrode 770 electrically connected to the gate terminal of transistor M1. A layer 704 is disposed above layer 703, and a source electrode 760, a gate electrode 770, and a gate electrode 780 are disposed above layer 704. When viewed along the Y-axis, at least a portion of the gate electrode 770 is located between the source electrode 760 and the drain electrode 780.

[0164] Next, the operation of transistors M1 and M2 configured as described above will be explained. When a 0V signal is supplied to the gate electrode 770, that is, when the potential of the gate electrode 770 is the same as that of the source electrode 760, the gate layer 750 raises the potential of the heterojunction boundary between the electron transport layer 730 and the electron supply layer 740, which forms the channel. As a result, the conduction band on the -Y side of the gate electrode 770 in the conduction band of the heterojunction boundary between the electron transport layer 730 and the electron supply layer 740 becomes higher than the Fermi level. Therefore, the heterojunction boundary between the electron transport layer 730 and the electron supply layer 740, which forms the channel, is depleted. That is, when a 0V signal is supplied to the gate electrode 770, that is, when the gate electrode 770 and the source electrode 760 are at the same potential, the source electrode 760 and drain electrode 780 of each transistor M1 and M2, that is, the drain terminal and source terminal of each transistor M1 and M2, become non-conductive.

[0165] On the other hand, when a positive voltage signal is supplied to the gate electrode 770, and the voltage value of the signal is higher than a predetermined threshold voltage, the potential at the heterojunction boundary between the electron transport layer 730 and the electron supply layer 740, which forms the channel, decreases. At this time, electrons are generated at the heterojunction boundary between the electron transport layer 730 and the electron supply layer 740, and transistors M1 and M2 operate in the same way as conventional FETs (Field Effect Transistors).

[0166] Furthermore, when the voltage value of the signal supplied to the gate electrode 770 increases, and this voltage value is higher than the positive turn-on voltage of the pn junction, holes begin to be injected from the gate electrode 770 towards the heterojunction boundary between the electron transport layer 730 and the electron supply layer 740, which forms the channel. At this time, due to the potential barrier of the heterojunction, electrons hardly flow into the gate electrode 770. Therefore, in order to satisfy the charge neutrality condition, an equal amount of electrons as the holes injected from the gate electrode 770 are attracted from the source electrode 760 to the heterojunction boundary between the electron transport layer 730 and the electron supply layer 740, which forms the channel. The electrons attracted from the source electrode 760 move at high speed toward the drain electrode 780 due to the voltage supplied to the drain electrode 780. On the other hand, since the mobility of holes is smaller than that of electrons, a large number of holes remain next to the gate electrode 770. Therefore, in order to satisfy the charge neutrality condition, an equal amount of electrons as holes are also generated. Therefore, the ratio of the number of injected holes to the number of generated electrons is roughly equal to the ratio of electron mobility to hole mobility, so even if the gate current hardly flows, the drain current increases.

[0167] As described above, transistors M1 and M2 are made of GaN and have Figure 10The structure shown is a GaN transistor utilizing conductivity modulation based on hole injection from the gate electrode 770. It exhibits normally-off characteristics and is a low-on-resistance HEMT (High Electron Mobility Transistor) structure capable of high-current drive. Here, transistors M1 and M2 are simply HEMT-structured GaN transistors, and their normally-off characteristics are not required; they are not limited to this type. Figure 10 The configuration shown could, for example, be a configuration with cascaded MOS-FETs instead of the gate layer 750 included in layer 705.

[0168] Here, GaN transistors are compound semiconductors using GaN as the semiconductor material. GaN, as the semiconductor material, has a higher band gap, dielectric breakdown electric field strength, electron mobility, and saturation electron velocity than Si, the mainstream semiconductor material. Therefore, the Baliga performance index of GaN, determined by a comprehensive evaluation of multiple physical properties such as dielectric breakdown electric field strength and electron mobility, reaches 900 when Si is set to "1" as the semiconductor material. In GaN transistors using GaN as the semiconductor material, high-speed switching with low on-resistance can be achieved compared to Si transistors using Si as the semiconductor material. Furthermore, by structuring GaN transistors as HEMTs, high-speed electron movement is possible, and the possibility of high-speed switching being hindered by parasitic capacitance is reduced, enabling even faster switching.

[0169] By using GaN transistors with such a HEMT structure as transistors M1 and M2 in the amplifier circuit 550 included in the drive circuit 50 of the liquid ejection device 1 of this embodiment, losses generated in transistors M1 and M2 can be reduced even when transistors M1 and M2 are driven at high frequencies. That is, even when the drive circuit 50 outputs a drive signal of 100 kHz or higher, and transistors M1 and M2 are driven at, for example, a high frequency of 8 MHz or higher, the heat generated in transistors M1 and M2 is reduced, and the possibility of decreased stability in the operation of the drive circuit 50 is also reduced. Therefore, from the viewpoint of improving productivity in the liquid ejection device 1, even when the drive circuit 50 supplies a high-frequency drive signal COM of 100 kHz or higher to a large number of piezoelectric elements 60, i.e., more than 3000 piezoelectric elements 60, the possibility of decreased waveform accuracy of the output drive signal COM is also reduced.

[0170] Furthermore, by using GaN transistors with a HEMT structure as transistors M1 and M2, the losses generated in transistors M1 and M2 are reduced even when they are driven at high frequencies. As a result, the power consumption of the drive circuit 50 can be reduced. Moreover, since transistors M1 and M2 can be driven at high frequencies, the frequency of the feedback signal fed back to the modulation circuit 510 via the feedback circuit 572 can be increased. Consequently, the waveform accuracy of the drive signal COM output by the drive circuit 50 is further improved.

[0171] Furthermore, since transistors M1 and M2 can be driven at high frequencies, the frequency of the amplified modulation signal AMs output by transistors M1 and M2 also increases. This allows for miniaturization of the coil L1 in the demodulation circuit 560, miniaturization of the drive circuit 50, and reduction of the product of the coil L1 and capacitor C1 in the demodulation circuit 560. Consequently, the output bandwidth of the drive circuit 50 can be expanded, enabling the output of a drive signal COM with high waveform accuracy even when the voltage value of the drive signal COM changes drastically.

[0172] That is, in the driving circuit 50 of this embodiment, transistors M1 and M2 have Figure 10 The characteristic structure shown reduces losses in transistors M1 and M2 even when they are driven at high frequencies. Therefore, even when the drive circuit 50 supplies high-frequency drive signals COMA, COMB, and COMC at frequencies above 100kHz to numerous piezoelectric elements 60 (i.e., more than 3000 piezoelectric elements 60), it can reduce heat generation in the drive circuit 50 and decrease the possibility of a decrease in the waveform accuracy of the output drive signal COM. Therefore, in the drive circuit 50 of this embodiment, when the drive frequency of transistor M1 is set such that the shortest period of the drive cycle of transistor M1 is shorter than the shortest period of the voltage change of the drive signal COM and shorter than the shortest period of the constant voltage value of the drive signal COM, and when the drive frequency of transistors M1 and M2 is set such that the shortest period of the drive cycle of transistor M2 is shorter than the shortest period of the voltage change of the drive signal COM and shorter than the shortest period of the constant voltage value of the drive signal COM, and when the drive frequencies of transistors M1 and M2 exceed 8MHz during the period when transistors M1 and M2 output the amplified modulation signal AMs, the losses generated in transistors M1 and M2 can also be reduced. As a result, the heat generated in the drive circuit 50 can be reduced, and the possibility of a decrease in the waveform accuracy of the output drive signal COM can also be reduced.

[0173] Here, among the semiconductor materials constituting transistors M1 and M2, considering only the Baliga performance index, SiC and gallium oxide (Ga2O3) have a larger Baliga performance index than Si. However, SiC and Ga2O3 are semiconductor materials envisioned for use at high voltages of several hundred V to several kV, and their switching performance at high frequencies is worse than GaN. Therefore, they are not suitable semiconductor materials for transistors M1 and M2 in the drive circuit 50 of the liquid ejection device 1, which is envisioned for use at voltages below 100V and high frequencies of several MHz. Furthermore, when using GaN as the semiconductor material and employing a vertical structure instead of a HEMT structure, parasitic capacitances generated between the gate and source will hinder operation at high frequencies of several MHz. Therefore, for the transistors M1 and M2 of the driving circuit 50 of the liquid ejection device 1, which is intended to be used at voltage values ​​below 100V and high frequencies of several MHz, the use of GaN transistors with HEMT structure is the most suitable option, considering not only the Baliga performance index of the semiconductor material but also other physical properties and structures.

[0174] Here, the drive signal COM is an example of a drive signal, the piezoelectric element 60 is an example of a capacitive load, the drive circuit 50 is an example of a capacitive load drive circuit, the gate signal Hgd is an example of a first gate drive signal, the gate drive circuit 520 is an example of a gate drive circuit, the transistor M1 is an example of a first transistor, the transistor M2 is an example of a second transistor, the period tp is an example of an ejection period, and the reciprocal of the drive frequency of transistors M1 and M2 is an example of a drive period.

[0175] 1.5 Effect

[0176] In the liquid ejection device 1 configured as described above, the drive circuit 50 includes: a modulation circuit 510 that outputs a modulation signal Ms after modulating the base drive signals dO and aO, which form the basis of the drive signal COM; a gate drive circuit 520 including a gate driver 521 and a gate driver 522, wherein the gate driver 521 outputs a gate signal Hgd corresponding to the modulation signal Ms, and the gate driver 522 outputs a gate signal Lgd corresponding to the modulation signal Ms; an amplifier circuit 550 including a transistor M1 and a transistor M2, wherein the transistor M1 is driven according to the gate signal Hgd, and the transistor M2 is driven according to the gate signal Lgd, and the amplifier circuit 550 outputs an amplified modulation signal AMs by driving the transistors M1 and M2; and a demodulation circuit 560 that outputs a drive signal COM after demodulating the amplified modulation signal AMs. The transistors M1 and M2, at least one and preferably both, are configured to include: a layer 703 including an electron transport layer 730, the electron transport layer 730 being configured to include a nitride semiconductor such as GaN; a layer 704 including a nitride semiconductor such as AlGaN with a band gap larger than that of the electron transport layer 730; a source electrode 760 electrically connected to the source terminal of transistor M1; a drain electrode 780 electrically connected to the drain terminal of transistor M1; and a gate electrode 770 electrically connected to the gate terminal of transistor M1. A layer 704 is disposed above layer 703, and a source electrode 760, a gate electrode 770, and a gate electrode 770 are disposed above layer 704. When viewed along the Y-axis, at least a portion of the gate electrode 770 is located between the source electrode 760 and the drain electrode 780, thereby reducing the losses generated in transistors M1 and M2 even when transistors M1 and M2 are driven at high frequencies. Therefore, even when the frequency of the drive signal COM output by the drive circuit 50 using the D-level amplifier circuit is high, for example, even when the drive circuit 50 supplies high-frequency drive signals COMA, COMB, and COMC of more than 100kHz to numerous piezoelectric elements 60, i.e., more than 3,000 piezoelectric elements 60, to meet market demands for increasing productivity in the liquid ejection device 1, it is possible to reduce the heat generated in the drive circuit 50 and reduce the possibility of a decrease in the waveform accuracy of the output drive signal COM.

[0177] That is, by setting at least one, and preferably both, of the transistors M1 and M2 in the amplifier circuit 550 as GaN transistors with a HEMT structure, even when the transistors M1 and M2 are driven at a high frequency, the losses generated in the transistors M1 and M2 can be reduced. Therefore, even when the drive circuit 50 supplies high-frequency drive signals COMA, COMB, and COMC of 100kHz or higher to a large number of piezoelectric elements 60, i.e., more than 3,000 piezoelectric elements 60, in order to meet market demands for increasing productivity in the liquid ejection device 1, the heat generated in the drive circuit 50 can be reduced while the possibility of a decrease in the waveform accuracy of the output drive signal COM can be reduced.

[0178] Furthermore, since the liquid ejection device 1 has a drive circuit 50 that feeds back the drive signal COM to the modulation circuit 510, the transistors M1 and M2 are driven at a high frequency. Therefore, from the perspective of the overall system of the drive circuit 50, the response speed of the drive circuit 50 can be improved. As a result, the waveform accuracy of the drive signal COM output by the drive circuit 50 can be improved.

[0179] Furthermore, in the liquid ejection device 1 of this embodiment, even when transistors M1 and M2 are driven at high frequencies, the losses generated in transistors M1 and M2 can be reduced, thus reducing the heat generation of the drive circuit 50 including transistors M1 and M2. Therefore, even when the drive circuit 50 and the ejection section 600 are mounted together on the carriage 21, the possibility of changes in the physical properties of the ejected ink due to the heat generation of the drive circuit 50 including transistors M1 and M2 is reduced. In addition, by mounting the drive circuit 50 and the ejection section 600 together on the carriage 21, the transmission path from the drive signal COM output by the drive circuit 50 to the ejection section 600 can be shortened, improving the waveform accuracy of the drive signal COM supplied to the ejection section 600 and improving the ejection accuracy of the ink from the ejection section 600.

[0180] 2. Second Implementation Method

[0181] Next, the liquid ejection device 1 of the second embodiment will be described. When describing the liquid ejection device 1 of the second embodiment, the same reference numerals will be used for the same components as those in the liquid ejection device 1 of the first embodiment, and detailed descriptions will be simplified or omitted.

[0182] Figure 11This is a diagram showing an example of the configuration of the drive circuit 50 in the second embodiment. In the liquid ejection device 1 of the second embodiment, the gate drive circuit 520 that outputs gate signals Hgd and Lgd, as well as transistors M1 and M2, are mounted in an integrated circuit device 500 in the drive circuit 50, which is different from the liquid ejection device 1 of the first embodiment.

[0183] like Figure 11 As shown, the integrated circuit device 500 includes terminals Tvm, Tsi, Td, Ts, Tout, Tbt, gate drive circuit 520, amplifier circuit 550, diode D1, and inverter 515.

[0184] The modulation signal Ms output by the modulation circuit 510 is input to terminal Tsi. A voltage signal Vm is supplied to terminal Tvm. A voltage signal VHV is supplied to terminal Td. A ground potential is supplied to terminal Ts. One end of capacitor C5 is electrically connected to terminal Tbt. The other end of capacitor C5 is electrically connected to terminal Tout. Terminal Tout is electrically connected to one end of coil L1 of the demodulation circuit 560.

[0185] The modulation signal Ms is input to the gate driver 521 included in the gate drive circuit 520 via the terminal Tsi. Additionally, after being input to the inverter 515 via the terminal Tsi, the modulation signal Ms is inverted by the inverter 515 and also input to the gate driver 522 included in the gate drive circuit 520. That is, the input logic levels to the gate driver 521 and the gate driver 522 are mutually exclusive.

[0186] Gate driver 521 generates and outputs gate signal Hgd by level-shifting the modulation signal Ms. The high-potential side of the power supply voltage of gate driver 521 is electrically connected to the cathode of diode D1 and also electrically connected to one end of capacitor C5 via terminal Tbt. The other end of capacitor C5 is electrically connected to terminal Tout, which is also electrically connected to the junction of the source terminal of transistor M1 and the drain terminal of transistor M2. A voltage signal Vm is supplied to the anode of diode D1 via terminal Tvm. This generates a potential difference across capacitor C5 that is almost equal to the voltage value of the voltage signal Vm. The low-potential side of the power supply voltage of gate driver 521 is electrically connected to the junction of the source terminal of transistor M1 and the drain terminal of transistor M2, i.e., terminal Tout. Therefore, the gate driver 521 generates and outputs the following gate signal Hgd according to the logic level of the input modulation signal Ms: the voltage value of the H level is greater than the voltage value of the terminal Tout by the voltage value of the voltage signal Vm, and the voltage value of the L level becomes the voltage value of the terminal Tout.

[0187] Gate driver 522 operates at a lower potential than gate driver 521. Gate driver 522 generates and outputs a gate signal Lgd by level-shifting the signal after the logic level of the modulation signal Ms input via terminal Tsi is inverted by inverter 515. A voltage signal Vm is supplied to the high potential side of the power supply voltage of gate driver 522 via terminal Tvm, and a ground potential is supplied to the low potential side of the power supply voltage of gate driver 522 via terminal Ts. Furthermore, gate driver 522 generates and outputs the following gate signal Lgd based on the logic level of the input signal: the voltage value of the H level is the voltage value of the voltage signal Vm, and the voltage value of the L level is the ground level.

[0188] The amplifier circuit 550 includes a transistor pair consisting of transistor M1 and transistor M2.

[0189] A voltage signal VHV is supplied to the drain terminal of transistor M1 via terminal Td. A gate signal Hgd is input to the gate terminal of transistor M1. The source terminal of transistor M1 is electrically connected to terminal Tout and the drain terminal of transistor M2. Furthermore, in transistor M1, the conduction state between the drain and source terminals is controlled by the gate signal Hgd input to the gate terminal.

[0190] The drain terminal of transistor M2 is electrically connected to terminal Tout and the source terminal of transistor M1. A gate signal Lgd is input to the gate terminal of transistor M2. A ground potential is supplied to the source terminal of transistor M2 via terminal Ts. Furthermore, in transistor M2, the conduction state between the drain and source terminals is controlled by the gate signal Lgd input to the gate terminal.

[0191] In the amplifier circuit 550 configured as described above, when transistor M1 is controlled to be off and transistor M2 is controlled to be on, the voltage value of terminal Tout becomes ground potential. At this time, a voltage signal Vm is supplied to the high potential side of the power supply voltage of gate driver 521. On the other hand, when transistor M1 is controlled to be on and transistor M2 is controlled to be off, the voltage value of terminal Tout becomes voltage signal VHV. At this time, a signal equal to the sum of the voltage values ​​of voltage signal VHV and voltage signal Vm is supplied to the high potential side of the power supply voltage of gate driver 521. That is, the gate driver 521 driving transistor M1 uses capacitor C5 as a floating power source. The voltage value of the other end of capacitor C5, i.e. terminal Tout, changes to ground potential or voltage signal VHV according to the operation of transistor M1 and transistor M2. This generates gate signal Hgd and supplies it to the gate terminal of transistor M1. The L level of the gate signal Hgd is the voltage value of voltage signal VHV, and the H level is the sum of the voltage value of voltage signal VHV and voltage value of voltage signal Vm.

[0192] On the other hand, the gate driver 522 that drives transistor M2 generates a gate signal Lgd independently of the operation of transistors M1 and M2, and supplies it to the gate terminal of transistor M2. The L level of the gate signal Lgd is ground potential, and the H level is the voltage value of voltage signal Vm.

[0193] As described above, the amplifier circuit 550 operates via transistors M1 and M2 according to gate signals Hgd and Lgd, and amplifies the modulation signal Ms after the base drive signals dO and aO are modulated based on the voltage signal VHV. Furthermore, the amplifier circuit 550 outputs the amplified signal from terminal Tout as the amplified modulation signal AMs.

[0194] Then, the demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing it and generates a drive signal COM. Furthermore, the demodulation circuit 560 outputs the generated drive signal COM from the drive circuit 50.

[0195] Even the drive circuit 50 of the second embodiment configured as described above, through transistors M1 and M2, has Figure 10 The structure shown also serves the same function as the liquid ejection device 1 in the first embodiment.

[0196] At this time, in the liquid ejection device 1 of the second embodiment, the gate drive circuit 520 that outputs gate signals Hgd and Lgd, and transistors M1 and M2 constitute an integrated circuit device 500 housed in a single package. This shortens the transmission path for each of the gate signals Hgd and Lgd, and improves the waveform accuracy of the gate signal Hgd input to transistor M1 and the gate signal Lgd input to transistor M2.

[0197] If used Figure 10 As described, transistors M1 and M2 are GaN transistors with a HEMT structure, comprising: a layer 703 including an electron transport layer 730, which is composed of a nitride semiconductor such as GaN; a layer 704 including a nitride semiconductor such as AlGaN with a bandgap larger than that of the electron transport layer 730; a source electrode 760 electrically connected to the source terminal of transistor M1; a drain electrode 780 electrically connected to the drain terminal of transistor M1; and a gate electrode 770 electrically connected to the gate terminal of transistor M1. Furthermore, a layer 704 is disposed above layer 703, and a source electrode 760, a gate electrode 770, and a gate electrode 770 are disposed above layer 704. When viewed along the Y-axis, at least a portion of the gate electrode 770 is located between the source electrode 760 and the drain electrode 780. With this configuration, high-frequency driving can be achieved with high-speed switching.

[0198] However, when the wiring for transmitting the gate signals Hgd and Lgd is long, there is a possibility that distortion may occur in the waveform of the gate signals Hgd and Lgd due to the impedance component of the wiring. Therefore, when the wiring for transmitting the gate signals Hgd and Lgd is long, there is a possibility that the driving frequency of transistors M1 and M2 may be limited by the waveform distortion of the gate signals Hgd and Lgd. In particular, this problem becomes significant in GaN transistors with HEMT structure, such as transistors M1 and M2 in the drive circuit 50 shown in this embodiment, since high-speed switching is possible.

[0199] In contrast, in the liquid ejection device 1 of the second embodiment, since the wiring for transmitting each of the gate signals Hgd and Lgd can be shortened, the possibility of distortion in the signal waveforms of each of the gate signals Hgd input to transistor M1 and Lgd input to transistor M2 is reduced. Therefore, the driving frequencies of transistors M1 and M2 can be further increased, and the waveform accuracy of the driving signal COM output by the driving circuit 50 can be further improved.

[0200] Here, the integrated circuit device 500 is an example of a semiconductor device.

[0201] 3. Third Implementation Method

[0202] Next, the liquid ejection device 1 of the third embodiment will be described. When describing the liquid ejection device 1 of the third embodiment, the same reference numerals will be used for the same components as those in the first embodiment and the second embodiment, and detailed descriptions will be simplified or omitted.

[0203] Figure 12 This is a diagram showing an example of the configuration of the drive circuit 50 in the third embodiment. The difference between the liquid ejection device 1 in the third embodiment and the liquid ejection devices 1 in the first and second embodiments is that, in the drive circuit 50, the gate driver 521 for outputting the gate signal Hgd and the transistor M1 are mounted in an integrated circuit device 500a, and the gate driver 522 for outputting the gate signal Lgd and the transistor M2 are mounted in an integrated circuit device 500b.

[0204] like Figure 12 As shown, integrated circuit device 500a includes terminals Tvma, Tsia, Tda, Tsa, gate driver 521, and transistor M1, and integrated circuit device 500b includes terminals Tvmb, Tsib, Tdb, Tsb, gate driver 522, and transistor M2.

[0205] The modulation signal Ms output by modulation circuit 510 is input to terminal Tsia. Terminal Tvma is electrically connected to the cathode of diode D1 and one end of capacitor C5. A voltage signal VHV is supplied to terminal Tda. Terminal Tsa is electrically connected to terminal Tdb of integrated circuit device 500b. Additionally, the modulation signal Ms output by modulation circuit 510 is input to terminal Tsib via inverter 515. A voltage signal Vm is input to terminal Tvmb. Terminal Tdb is electrically connected to terminal Tsa of integrated circuit device 500a. A ground potential is supplied to terminal Tsb.

[0206] The modulation signal Ms is input to the gate driver 521 via terminal Tsia. Additionally, after the logic level of the modulation signal Ms is inverted by the inverter 515, it is input to the gate driver 522 via terminal Tsib. That is, the gate driver 521 and gate driver 522 are input signals with an exclusive relationship to each other in terms of logic level.

[0207] Gate driver 521 generates and outputs gate signal Hgd by level shifting the modulation signal Ms. The high-potential side of the power supply voltage of gate driver 521 is electrically connected to the cathode of diode D1 and one end of capacitor C5 via terminal Tvma. The other end of capacitor C5 is electrically connected to terminal Tsa, which is electrically connected to the source terminal of transistor M1. A voltage signal Vm is supplied to the anode of diode D1. This generates a potential difference across capacitor C5 that is approximately equal to the voltage value of the voltage signal Vm. The low-potential side of the power supply voltage of gate driver 521 is electrically connected to the source terminal of transistor M1, i.e., terminal Tsa. Therefore, gate driver 521 generates and outputs the following gate signal Hgd based on the logic level of the input modulation signal Ms: the voltage value of the H level is greater than the voltage value of the voltage signal Vm, and the voltage value of the L level becomes the voltage value of terminal Tsa.

[0208] Gate driver 522 performs a level shift on the signal after the logic level of the modulation signal Ms input via terminal Tsib is inverted by inverter 515, thereby generating and outputting a gate signal Lgd. A voltage signal Vm is supplied to the high-potential side of the power supply voltage of gate driver 522 via terminal Tvmb, and a ground potential is supplied to the low-potential side of the power supply voltage of gate driver 522 via terminal Tsb. Then, gate driver 522 generates and outputs a gate signal Lgd with a voltage value of H level equal to the voltage value of voltage signal Vm and a voltage value of L level equal to the ground potential, based on the logic level of the input signal.

[0209] A voltage signal VHV is supplied to the drain terminal of transistor M1 via terminal Tda. A gate signal Hgd is input to the gate terminal of transistor M1. The source terminal of transistor M1 is electrically connected to terminal Tsa. Furthermore, in transistor M1, the conduction state between the drain and source terminals is controlled by the gate signal Hgd input to the gate terminal.

[0210] The drain terminal of transistor M2 is electrically connected to terminal Tdb. Additionally, terminal Tdb is electrically connected to terminal Tsa. That is, the source terminal of transistor M1 and the drain terminal of transistor M2 are electrically connected via terminals Tsa and Tdb. A gate signal Lgd is input to the gate terminal of transistor M2. A ground potential is supplied to the source terminal of transistor M2 via terminal Tsb. Furthermore, in transistor M2, the conduction state between the drain and source terminals is controlled by the gate signal Lgd input to the gate terminal.

[0211] Furthermore, when transistor M1 is controlled to be off and transistor M2 is controlled to be on, the voltage at the connection point of terminals Tsa and Tdb becomes ground potential. At this time, a voltage signal Vm is supplied to the high-potential side of the power supply voltage of the gate driver 521. On the other hand, when transistor M1 is controlled to be on and transistor M2 is controlled to be off, the voltage at the connection point of terminals Tsa and Tdb becomes voltage signal VHV. At this time, a signal equal to the sum of the voltage values ​​of voltage signals VHV and Vm is supplied to the high-potential side of the power supply voltage of the gate driver 521. That is, the gate driver 521 driving transistor M1 uses capacitor C5 as a floating power source. The voltage value at the other end of capacitor C5, that is, the connection point of terminals Tsa and Tdb, changes to ground potential or voltage signal VHV according to the operation of transistors M1 and M2, thereby generating gate signal Hgd and supplying it to the gate terminal of transistor M1. The L level of the gate signal Hgd is the voltage value of voltage signal VHV, and the H level is the sum of the voltage values ​​of voltage signal VHV and voltage signal Vm.

[0212] On the other hand, the gate driver 522 that drives transistor M2 generates a gate signal Lgd independently of the operation of transistors M1 and M2, and supplies it to the gate terminal of transistor M2. The L level of the gate signal Lgd is ground potential, and the H level is the voltage value of voltage signal Vm.

[0213] As described above, transistors M1 and M2 operate according to gate signals Hgd and Lgd, amplifying the modulated signal Ms after the base drive signals dO and aO are modulated based on the voltage signal VHV. Furthermore, the signal amplified by transistors M1 and M2 is output as the amplified modulated signal AMs from the connection point between terminals Tsa and Tdb.

[0214] Then, the demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing it and generates a drive signal COM. Furthermore, the demodulation circuit 560 outputs the generated drive signal COM from the drive circuit 50.

[0215] Even the drive circuit 50 of the third embodiment configured as described above, through transistors M1 and M2, has Figure 10 The structure shown also serves the same function as the liquid ejection device 1 in the first and second embodiments.

[0216] In this case, in the liquid ejection device 1 of the third embodiment, the gate driver 521 for outputting the gate signal Hgd and the transistor M1 constitute an integrated circuit device 500a housed in a single package, and the gate driver 522 for outputting the gate signal Lgd and the transistor M2 constitute an integrated circuit device 500b housed in a single package. This shortens the transmission path for each of the gate signals Hgd and Lgd, and improves the waveform accuracy of the gate signal Hgd input to the transistor M1 and the waveform accuracy of the gate signal Lgd input to the transistor M2.

[0217] If used Figure 10 As described, transistors M1 and M2 are GaN transistors with a HEMT structure, comprising: a layer 703 including an electron transport layer 730, which is composed of a nitride semiconductor such as GaN; a layer 704 including a nitride semiconductor such as AlGaN with a bandgap larger than that of the electron transport layer 730; a source electrode 760 electrically connected to the source terminal of transistor M1; a drain electrode 780 electrically connected to the drain terminal of transistor M1; and a gate electrode 770 electrically connected to the gate terminal of transistor M1. Furthermore, a layer 704 is disposed above layer 703, and a source electrode 760, a gate electrode 770, and a gate electrode 770 are disposed above layer 704. When viewed along the Y-axis, at least a portion of the gate electrode 770 is located between the source electrode 760 and the drain electrode 780. With this configuration, high-frequency driving can be achieved with high-speed switching.

[0218] However, when the wiring for transmitting the gate signals Hgd and Lgd is long, there is a possibility that distortion may occur in the waveforms of the gate signals Hgd and Lgd due to the impedance component of the wiring. Therefore, when the wiring for transmitting the gate signals Hgd and Lgd is long, there is a possibility that the driving frequency of transistors M1 and M2 may be limited by the waveform distortion of the gate signals Hgd and Lgd. In particular, in GaN transistors with HEMT structures such as transistors M1 and M2 in the drive circuit 50 shown in this embodiment, since high-speed switching is possible, the aforementioned problems become significant.

[0219] In contrast, in the liquid ejection device 1 of the third embodiment, similarly to the liquid ejection device 1 of the second embodiment, since the wiring for transmitting each of the gate signals Hgd and Lgd can be shortened, the possibility of distortion in the signal waveforms of each of the gate signals Hgd input to transistor M1 and Lgd input to transistor M2 is reduced. Therefore, the driving frequencies of transistors M1 and M2 can be further increased, and the waveform accuracy of the driving signal COM output by the driving circuit 50 can be further improved.

[0220] The embodiments and variations have been described above, but the present invention is not limited to these embodiments and can be implemented in various ways without departing from its spirit. For example, the above embodiments can also be appropriately combined.

[0221] This invention includes configurations that are substantially the same as those described in the embodiments (e.g., configurations with the same function, method, and result, or configurations with the same purpose and effect). Additionally, this invention includes configurations that replace non-essential parts of the configurations described in the embodiments. Furthermore, this invention includes configurations that have the same effect as those described in the embodiments or that can achieve the same purpose. Additionally, this invention includes configurations that incorporate known techniques into the configurations described in the embodiments.

[0222] The following content can be derived based on the above implementation method.

[0223] One method of liquid ejection device includes:

[0224] A capacitive load is displaced by a drive signal.

[0225] The ejector section ejects liquid as the capacitive load displaces; and

[0226] The capacitive load drive circuit outputs the drive signal.

[0227] The capacitive load drive circuit has:

[0228] The modulation circuit outputs a modulated signal obtained by modulating the base drive signal that forms the basis of the drive signal;

[0229] The gate driving circuit outputs a first gate driving signal and a second gate driving signal corresponding to the modulation signal;

[0230] An amplifier circuit includes a first transistor and a second transistor. The first transistor is driven by a first gate drive signal, and the second transistor is driven by a second gate drive signal. The amplifier circuit outputs an amplified and modulated signal by driving the first transistor and the second transistor.

[0231] The demodulation circuit outputs the drive signal after demodulating the amplified modulation signal.

[0232] The first transistor contains gallium nitride.

[0233] The second transistor contains gallium nitride.

[0234] The gate drive circuit, the first transistor, and the second transistor are housed in a package and constitute a semiconductor device.

[0235] In this liquid ejection device, by incorporating gallium nitride with a high Baliga performance index into both the first and second transistors, the losses caused by the drive are reduced even when at least one of the first and second transistors is driven at high speed with an increasingly higher frequency of the output drive signal. This reduces the heat generation of the amplifier circuit. Consequently, the possibility of decreased stability in the operation of the capacitive load drive circuit due to heat generation from the amplifier circuit is reduced, and the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0236] In this liquid ejection device, the gate drive circuit, the first transistor, and the second transistor are configured within a single packaged semiconductor device, thereby shortening the wiring length for transmitting the first gate signal and the second gate signal. Therefore, the likelihood of waveform distortion in the first and second gate signals input to the first and second transistors is reduced, the driving accuracy of the first and second transistors is improved, and the possibility of the driving frequency of the first and second transistors being limited by waveform distortion in the first and second gate signals is reduced, enabling further high-speed driving of the first and second transistors.

[0237] That is, even when the driving frequencies of the first transistor and the second transistor increase with the increase of the frequency of the output driving signal in the liquid ejection device, the first transistor and the second transistor can still be driven stably with low loss. Therefore, the possibility of the stability of the operation of the capacitive load driving circuit decreases, and the possibility of the waveform accuracy of the driving signal output by the capacitive load driving circuit decreases.

[0238] According to one method of the liquid ejection device, it can also be that...

[0239] The ejection cycle of the liquid ejected from the ejection section is less than 10 μs.

[0240] In this liquid ejection device, the ejection period of the liquid ejected from the ejection section is less than 10μs. Therefore, even when the drive signal output by the capacitive load drive circuit becomes high frequency, the first transistor and the second transistor can be driven with low loss and stability. As a result, the possibility of the stability of the operation of the capacitive load drive circuit decreases, and the possibility of the waveform accuracy of the drive signal output by the capacitive load drive circuit decreases.

[0241] According to one method of the liquid ejection device, it can also be that...

[0242] During the period when the amplifier circuit outputs the amplified modulation signal, the first transistor is driven at a frequency of 8 MHz or higher, and the second transistor is driven at a frequency of 8 MHz or higher.

[0243] In this liquid ejection device, even if the driving frequency of the first transistor and the second transistor is a high frequency of 8MHz or higher, the first transistor and the second transistor can be driven with low loss and stability. Therefore, the possibility of the stability of the operation of the capacitive load drive circuit decreases, and the possibility of the waveform accuracy of the drive signal output by the capacitive load drive circuit decreases.

[0244] According to one method of the liquid ejection device, it can also be that...

[0245] The shortest period in the driving cycle of the first transistor is shorter than the shortest period in which the voltage value of the driving signal changes, and shorter than the shortest period in which the voltage value of the driving signal is constant.

[0246] The shortest period of the driving cycle of the second transistor is shorter than the shortest period of the voltage value change of the driving signal, and shorter than the shortest period of the voltage value of the driving signal being constant.

[0247] In this liquid ejection device, since the shortest period in the driving cycle of the first transistor is shorter than the shortest period in the period of voltage change of the driving signal and shorter than the shortest period in the period when the voltage of the driving signal is constant, and the shortest period in the driving cycle of the second transistor is shorter than the shortest period in the period of voltage change of the driving signal and shorter than the shortest period in the period when the voltage of the driving signal is constant, the first transistor and the second transistor can be driven stably with low loss even when the driving frequency of the first transistor and the second transistor becomes high frequency. Therefore, the possibility of the stability of the operation of the capacitive load driving circuit decreasing is reduced, and the possibility of the waveform accuracy of the driving signal output by the capacitive load driving circuit decreasing is reduced.

[0248] According to one method of the liquid ejection device, it can also be that...

[0249] The capacitive load drive circuit has a feedback circuit that feeds the drive signal back to the modulation circuit.

[0250] In this liquid ejection device, even when the driving frequencies of the first and second transistors are set to high frequencies, the possibility of decreased stability in the operation of the capacitive load drive circuit is reduced, thus improving the responsiveness via the feedback circuit in the capacitive load drive circuit. Consequently, the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0251] According to one method of the liquid ejection device, it can also be that...

[0252] The liquid ejection device includes a carriage that moves along a main sweeping shaft, which intersects the conveying direction for transporting the medium onto which the liquid ejected from the ejection section lands.

[0253] The capacitive load, the ejector, and the capacitive load drive circuit are mounted on the carriage.

[0254] In this liquid ejection device, since the driving loss of at least one of the first transistor and the second transistor is reduced, the heat generation in the amplifier circuit is reduced. Therefore, even when the capacitive load drive circuit is mounted on the carriage, the possibility of changes in the liquid characteristics due to the heat generation in the amplifier circuit contributing to the liquid is also reduced.

[0255] One method for driving a capacitive load is as follows:

[0256] The capacitive load driving circuit outputs a driving signal to the capacitive load, which is then displaced by supplying the driving signal to eject liquid from the ejector section.

[0257] The capacitive load drive circuit has:

[0258] The modulation circuit outputs a modulated signal obtained by modulating the base drive signal that forms the basis of the drive signal;

[0259] The gate driving circuit outputs a first gate driving signal and a second gate driving signal corresponding to the modulation signal;

[0260] An amplifier circuit includes a first transistor and a second transistor. The first transistor is driven by a first gate drive signal, and the second transistor is driven by a second gate drive signal. The amplifier circuit outputs an amplified and modulated signal by driving the first transistor and the second transistor.

[0261] The demodulation circuit outputs the drive signal after demodulating the amplified modulation signal.

[0262] The first transistor contains gallium nitride.

[0263] The second transistor contains gallium nitride.

[0264] The gate drive circuit, the first transistor, and the second transistor are housed in a package and constitute a semiconductor device.

[0265] In this capacitive load drive circuit, by incorporating gallium nitride (GaN) with a high Baliga performance index into both the first and second transistors, the drive-related losses are reduced even when at least one of the first and second transistors is driven at high speed with an increasingly higher frequency of the output drive signal. This reduces the heat generated by the amplifier circuit. Consequently, the possibility of decreased stability in the operation of the capacitive load drive circuit due to heat generation from the amplifier circuit is reduced, and the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0266] In this liquid ejection device, the gate drive circuit, the first transistor, and the second transistor are configured within a single packaged semiconductor device, thereby shortening the wiring length for transmitting the first gate signal and the second gate signal. Therefore, the likelihood of waveform distortion in the first and second gate signals input to the first and second transistors is reduced, the driving accuracy of the first and second transistors is improved, and the possibility of the driving frequency of the first and second transistors being limited by waveform distortion in the first and second gate signals is reduced, enabling further high-speed driving of the first and second transistors.

[0267] That is, in this capacitive load drive circuit, even when the driving frequencies of the first transistor and the second transistor increase with the frequency of the output driving signal, the first transistor and the second transistor can still be driven stably with low loss. Therefore, the possibility of the stability of the operation of the capacitive load drive circuit decreases, and the possibility of the waveform accuracy of the driving signal output by the capacitive load drive circuit decreases.

[0268] According to one method of the capacitive load drive circuit, it can also be that...

[0269] Liquid is ejected from the ejector section with an ejection cycle of less than 10 μs.

[0270] In this liquid ejection device, the ejection period of the liquid ejected from the ejection section is less than 10μs. Therefore, even when the drive signal output by the capacitive load drive circuit becomes high frequency, the first transistor and the second transistor can be driven with low loss and stability. As a result, the possibility of the stability of the operation of the capacitive load drive circuit decreases, and the possibility of the waveform accuracy of the drive signal output by the capacitive load drive circuit decreases.

[0271] According to one method of the capacitive load drive circuit, it can also be that...

[0272] During the period when the amplifier circuit outputs the amplified modulation signal, the first transistor is driven at a frequency of 8 MHz or higher, and the second transistor is driven at a frequency of 8 MHz or higher.

[0273] In this liquid ejection device, even if the driving frequency of the first transistor and the second transistor is a high frequency of 8MHz or higher, the first transistor and the second transistor can be driven with low loss and stability. Therefore, the possibility of the stability of the operation of the capacitive load drive circuit decreases, and the possibility of the waveform accuracy of the drive signal output by the capacitive load drive circuit decreases.

[0274] According to one method of the capacitive load drive circuit, it can also be that...

[0275] The shortest period in the driving cycle of the first transistor is shorter than the shortest period in which the voltage value of the driving signal changes, and shorter than the shortest period in which the voltage value of the driving signal is constant.

[0276] The shortest period of the driving cycle of the second transistor is shorter than the shortest period of the voltage value change of the driving signal, and shorter than the shortest period of the voltage value of the driving signal being constant.

[0277] In this capacitive load drive circuit, since the shortest period in the drive cycle of the first transistor is shorter than the shortest period in the period of voltage change of the drive signal and shorter than the shortest period in the period when the voltage value of the drive signal is constant, and the shortest period in the drive cycle of the second transistor is shorter than the shortest period in the period of voltage change of the drive signal and shorter than the shortest period in the period when the voltage value of the drive signal is constant, even if the drive frequency of the first transistor and the second transistor increases, the first transistor and the second transistor can be driven stably with low loss. Therefore, the possibility of the stability of the operation of the capacitive load drive circuit decreasing is reduced, and the possibility of the waveform accuracy of the drive signal output by the capacitive load drive circuit decreasing is reduced.

[0278] According to one method of the capacitive load drive circuit, it can also be that...

[0279] The capacitive load drive circuit has a feedback circuit that feeds the drive signal back to the modulation circuit.

[0280] In this capacitive load drive circuit, even when the driving frequencies of the first and second transistors are set to high frequencies, the possibility of decreased stability in the operation of the capacitive load drive circuit is reduced, thus improving the responsiveness via the feedback circuit. Consequently, the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0281] According to one method of the capacitive load drive circuit, it can also be that...

[0282] The capacitive load drive circuit is mounted on a carriage that moves along a main sweeping axis that intersects with the conveying direction for transporting the medium onto which the liquid ejected from the ejection section lands.

[0283] In this capacitive load drive circuit, since the driving loss of at least one of the first transistor and the second transistor is reduced, the heat generation in the amplifier circuit is reduced. Therefore, even when the capacitive load drive circuit is mounted on the carriage, the possibility of changes in the liquid's properties due to the heat generation in the amplifier circuit contributing to the liquid is also reduced.

Claims

1. A liquid ejection device, characterized in that, have: A capacitive load is displaced by a drive signal. The ejector section ejects liquid as the capacitive load displaces; and The capacitive load drive circuit outputs the drive signal. The capacitive load drive circuit has: The modulation circuit outputs a modulated signal obtained by modulating the base drive signal that forms the basis of the drive signal; The gate driving circuit outputs a first gate driving signal and a second gate driving signal corresponding to the modulation signal; An amplifier circuit includes a first transistor and a second transistor. The first transistor is driven according to a first gate drive signal, and the second transistor is driven according to a second gate drive signal. The amplifier circuit outputs an amplified modulation signal by driving the first transistor and the second transistor. as well as The demodulation circuit outputs the drive signal after demodulating the amplified modulation signal. The first transistor contains gallium nitride. The second transistor contains gallium nitride. The gate drive circuit, the first transistor, and the second transistor are housed in a package and constitute a semiconductor device.

2. The liquid ejection device according to claim 1, characterized in that, The ejection cycle of the liquid ejected from the ejection section is less than 10 μs.

3. The liquid ejection device according to claim 1, characterized in that, During the period when the amplifier circuit outputs the amplified modulation signal, the first transistor is driven at a frequency of 8 MHz or higher, and the second transistor is driven at a frequency of 8 MHz or higher.

4. The liquid ejection device according to claim 1, characterized in that, The shortest period in the driving cycle of the first transistor is shorter than the shortest period in which the voltage value of the driving signal changes, and shorter than the shortest period in which the voltage value of the driving signal is constant. The shortest period of the driving cycle of the second transistor is shorter than the shortest period of the voltage value change of the driving signal, and shorter than the shortest period of the voltage value of the driving signal being constant.

5. The liquid ejection device according to claim 1, characterized in that, The capacitive load drive circuit has a feedback circuit that feeds the drive signal back to the modulation circuit.

6. The liquid ejection device according to claim 1, characterized in that, The liquid ejection device includes a carriage that moves along a main sweeping shaft, which intersects the conveying direction for transporting the medium onto which the liquid ejected from the ejection section lands. The capacitive load, the ejector, and the capacitive load drive circuit are mounted on the carriage.

7. A capacitive load driving circuit, characterized in that, The capacitive load driving circuit outputs a driving signal to the capacitive load, which is then displaced by supplying the driving signal to eject liquid from the ejector section. The capacitive load drive circuit has: The modulation circuit outputs a modulated signal obtained by modulating the base drive signal that forms the basis of the drive signal; The gate driving circuit outputs a first gate driving signal and a second gate driving signal corresponding to the modulation signal; An amplifier circuit includes a first transistor and a second transistor. The first transistor is driven according to a first gate drive signal, and the second transistor is driven according to a second gate drive signal. The amplifier circuit outputs an amplified modulation signal by driving the first transistor and the second transistor. as well as The demodulation circuit outputs the drive signal after demodulating the amplified modulation signal. The first transistor contains gallium nitride. The second transistor contains gallium nitride. The gate drive circuit, the first transistor, and the second transistor are housed in a package and constitute a semiconductor device.

8. The capacitive load driving circuit according to claim 7, characterized in that, Liquid is ejected from the ejector section with an ejection cycle of less than 10 μs.

9. The capacitive load driving circuit according to claim 7, characterized in that, During the period when the amplifier circuit outputs the amplified modulation signal, the first transistor is driven at a frequency of 8 MHz or higher, and the second transistor is driven at a frequency of 8 MHz or higher.

10. The capacitive load driving circuit according to claim 7, characterized in that, The shortest period in the driving cycle of the first transistor is shorter than the shortest period in which the voltage value of the driving signal changes, and shorter than the shortest period in which the voltage value of the driving signal is constant. The shortest period of the driving cycle of the second transistor is shorter than the shortest period of the voltage value change of the driving signal, and shorter than the shortest period of the voltage value of the driving signal being constant.

11. The capacitive load driving circuit according to claim 7, characterized in that, The capacitive load drive circuit has a feedback circuit that feeds the drive signal back to the modulation circuit.

12. The capacitive load driving circuit according to claim 7, characterized in that, The capacitive load drive circuit is mounted on a carriage that moves along a main sweeping axis that intersects with the conveying direction for transporting the medium onto which the liquid ejected from the ejection section lands.

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