Wafer bearing platform, testing machine and wafer testing device

Abstract

The invention provides a wafer bearing platform, a testing machine and a wafer testing device. The wafer bearing platform comprises a probe station, a fixing frame, a probe card and a light source. The probe station comprises a first test surface and is provided with an accommodating cavity, and the accommodating cavity is recessed from the first test surface. The fixing frame is connected to the first testing surface, and a mounting groove is concavely formed in the surface, facing the accommodating cavity, of the fixing frame. The probe card comprises a first connecting surface and a second connecting surface, the first connecting surface and the second connecting surface are oppositely arranged, the first connecting surface comprises a first area and a second area, the first area is connected with the fixing frame, the second area is used for being electrically connected with the testing machine, and the second connecting surface is used for being electrically connected with the wafer. The light source is connected to the groove wall of the installation groove and can emit light towards the first area so that the light can penetrate through the probe card and irradiate the surface of the wafer. According to the embodiment of the invention, the wafer can be directly connected with the testing machine through the probe card, so that the signal transmission rate between the testing machine and the wafer is improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, specifically to a wafer carrier platform, a testing machine, and a wafer testing device. Background Technology

[0002] Currently, in chip testing, a light source is generally required between the testing machine and the chip. For example, in image sensor testing, a light beam needs to be provided to illuminate the test area of ​​the image sensor to convert it into electrical and digital signals for identification. The presence of the light source results in a significant distance between the testing machine and the chip, necessitating additional electrical connections. However, these additional connections limit the signal transmission rate, ultimately leading to inaccurate chip testing. Summary of the Invention

[0003] Based on this, this application provides a wafer carrier platform, a tester, and a wafer testing device, which enables the wafer and the tester to be directly connected via a probe card, thereby improving the signal transmission rate between the tester and the wafer and increasing the accuracy of wafer testing.

[0004] In a first aspect, this application provides a wafer carrier platform, comprising:

[0005] The probe station includes a first test surface for docking with a test machine. The probe station is provided with a receiving cavity, which is recessed from the first test surface and is used to accommodate a wafer.

[0006] A mounting bracket is connected to the first test surface, and the surface of the mounting bracket facing the receiving cavity is recessed with a mounting groove;

[0007] The probe card includes a first connecting surface and a second connecting surface. Along the thickness direction of the probe card, the first connecting surface and the second connecting surface are arranged opposite to each other. The first connecting surface includes a first region and a second region. The first region is connected to the fixture, the second region is used for electrical connection with the test equipment, and the second connecting surface is used for electrical connection with the wafer.

[0008] The light source is connected to the wall of the mounting slot and can emit light toward the first area so that the light passes through the probe card and illuminates the surface of the wafer.

[0009] Currently, in wafer inspection, a light source is typically required between the tester and the wafer. For example, in the wafer testing of CIS chips, a light beam needs to be provided to illuminate the test area of ​​the wafer to convert it into electrical and digital signals for identification. The presence of the light source results in a significant distance between the tester and the wafer, necessitating additional electrical connections. However, these additional connections limit the signal transmission rate, ultimately leading to inaccurate wafer inspection.

[0010] In this embodiment, the wafer testing apparatus directly integrates the light source and the mounting bracket, allowing the light source to be embedded within the test machine's clearance slot. Therefore, after the test machine docks with the wafer inspection platform, the light source will not obstruct the docking between the test machine and the wafer. The wafer can directly dock with the test machine via a probe card, thereby avoiding signal transmission between the test machine and the wafer through connecting cables or adapter boards, thus improving the signal quality of transmission between the test machine and the wafer. This enables the test machine to effectively detect high-speed signals from the wafer.

[0011] The light source can simulate various lighting environments that CIS chips may encounter in practical applications, such as sunlight, indoor lighting, and low light. By adjusting parameters such as the intensity and spectral distribution of the light source, the performance of the CIS chip under different lighting conditions can be evaluated, including sensitivity, signal-to-noise ratio, and color reproduction capability.

[0012] The mounting bracket serves as a reinforcement structure for the probe station. It is installed on the first test surface of the probe station. The bracket enhances the structural stability of the entire wafer carrier platform.

[0013] In one possible implementation, the light-emitting surface of the light source is flush with the surface of the mounting bracket facing the first connecting surface.

[0014] In this embodiment, the light source can be flush with the surface of the mounting bracket facing the first connection surface, thereby allowing the light source to adhere to the first connection surface and avoiding a gap between the light source and the probe card. When the light source emits light, the light can directly pass through the lens structure of the probe card and illuminate the wafer surface, preventing light from escaping from the gap between the probe card and the light source.

[0015] In one possible implementation, the first connecting surface is flush with the first test surface.

[0016] In this embodiment, when the first connecting surface is flush with the first test surface, the probe card will not protrude relative to the probe station, thereby avoiding the probe card from being subjected to external impacts due to a protruding position.

[0017] Furthermore, when the first connecting surface is flush with the first test surface, the probe card will not be recessed relative to the probe station, thereby preventing the first connecting surface from failing to be tightly aligned and connected with the test machine.

[0018] In one possible implementation, the mounting groove extends through the mounting frame along its width, and the light source protrudes from both sides of the mounting frame relative to its width.

[0019] In this embodiment, the size of the light source can exceed the mounting frame to increase the light-emitting area. A larger light source area means that more areas of the wafer surface can be illuminated simultaneously, thereby accelerating the inspection speed. For large wafers, such as 10-inch or 12-inch wafers, a large-area light source can significantly reduce the inspection time. At the same inspection accuracy, a larger light source area can reduce the number of scans on the wafer surface, further improving inspection efficiency.

[0020] A large-area light source can reduce blind spots during the inspection process, ensuring that every tiny area on the wafer surface can be fully illuminated and inspected, thereby improving the comprehensiveness and accuracy of the inspection.

[0021] In one possible implementation, there are two second regions, located on opposite sides of the first region.

[0022] In one possible implementation, the mounting bracket is provided with a connection hole that penetrates the bottom wall of the mounting groove and the surface of the mounting bracket facing away from the first test surface.

[0023] The wafer carrier platform also includes connectors that pass through connection holes and are connected to the light source.

[0024] Secondly, this application provides a testing machine for interfacing with the wafer carrier platform described above to test the wafer. The testing machine includes:

[0025] The housing has a second test surface, which is set opposite to the first test surface. The housing also has a relief groove, which is recessed from the second test surface.

[0026] The first connector is connected to the housing and is located within the range of the second test surface;

[0027] Image acquisition card, which is plugged into the first connector.

[0028] In this embodiment, the image acquisition card in the test machine can be directly replaced. When wafers are upgraded, the image acquisition card can also be replaced simultaneously, while remaining compatible with all CIS chips in the testing industry, ensuring that the evolution of the test machine is unrestricted and its testing compatibility is unlimited.

[0029] The image acquisition card is integrated with the test machine via a first connector. The image acquisition card is located close to the wafer and is directly electrically connected to it via a probe card. This avoids signal transmission between the image acquisition card and the wafer through connecting cables or adapter boards, thus improving the signal quality between them and enabling the test machine to inspect the wafer.

[0030] In one possible implementation, the tester further includes a power board and / or a digital board, and also includes a second connector connected to the housing and located within the range of the second test surface. The power board and / or digital board are electrically connected to the second connector.

[0031] In this embodiment, the test machine directly integrates the high-speed image acquisition card, power supply board, and digital board via the first and second connectors. The test machine can directly connect to the wafer carrier platform via the first and second connectors, eliminating the need for connecting cables or adapter boards. This allows for better compatibility with the test platform hardware systems of testing manufacturers, and broadens the application scenarios in the current market.

[0032] The power board can precisely control the output voltage and current to ensure that the wafer receives a stable and compliant power supply during testing.

[0033] Digital circuit boards can generate various digital signals, such as clock signals and data signals. These signals are used to stimulate the wafer, simulating various digital input situations that the chip may encounter in actual operation. At the same time, digital circuit boards also have high-precision signal acquisition capabilities, enabling them to capture the wafer's response to the stimulation signals in real time for subsequent data analysis and processing.

[0034] Thirdly, this application provides a wafer testing apparatus, including the wafer carrier platform and the testing machine as described above.

[0035] When the wafer testing equipment is in operation, the wafer is connected to the second connection surface of the probe card, the second test surface of the tester is positioned opposite to the first test surface of the wafer carrier platform, and the first connector is electrically connected to the second area of ​​the probe card.

[0036] It is known that currently, because there is generally a light source device between the test machine and the wafer carrier platform, the test machine and the wafer carrier platform cannot be directly connected. They are typically connected via connecting cables and adapter boards to enable electrical conduction between the test machine and the wafer. However, because the structure of connecting cables and adapter boards can affect the signal transmission quality and speed, current test machines have difficulty detecting the transmission of high-speed signals within the wafer.

[0037] In this embodiment, after inspecting the wafers, substandard wafers can be prevented from entering subsequent chip fabrication processes. Chips manufactured from substandard wafers often have a high defect rate, meaning manufacturers need to invest more resources in handling these defective products, such as recycling, remanufacturing, or destruction. These measures also increase manufacturing costs.

[0038] The light source and mounting bracket of the wafer testing device provided in this application embodiment are embedded in the clearance slot of the testing machine. Therefore, after the testing machine is docked with the wafer inspection platform, the light source will not block the docking of the testing machine and the wafer, and the light source can still emit light to the wafer.

[0039] Because the tester directly integrates an image acquisition card and a power supply / digital board, it can automatically align itself with the wafer carrier platform during the wafer testing process and start testing, thus improving the overall automation level of the wafer testing equipment.

[0040] In one possible implementation, the height of the mounting bracket is less than or equal to the depth of the clearance groove in the housing. Attached Figure Description

[0041] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the structure of a wafer testing device provided in an embodiment of this application;

[0043] Figure 2 yes Figure 1 The diagram shows the structure of the wafer carrier platform.

[0044] Figure 3 yes Figure 2 The diagram shows the assembly of the probe station, fixture, and light source of the wafer carrier platform.

[0045] Figure 4 yes Figure 3 The diagram shows the structural arrangement of the mounting bracket and the light source.

[0046] Figure 5 yes Figure 4 A cross-sectional schematic diagram of the mounting bracket and the light source shown;

[0047] Figure 6 yes Figure 2 The diagram shows the structure of the probe card.

[0048] Figure 7 yes Figure 1 The diagram shows the structure of the testing machine.

[0049] Figure 8 yes Figure 7 The first connector shown is connected to the image acquisition card and has a clamping structure inside. Detailed Implementation

[0050] The specific embodiments of this application will now be described in more detail with reference to the accompanying drawings. Although exemplary embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in other ways different from those described herein, and therefore, this application is not limited to these embodiments.

[0051] For ease of understanding, the terminology used in the embodiments of this application will be explained first.

[0052] Multiple: refers to two or more.

[0053] Connection: should be interpreted broadly. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through an intermediary.

[0054] The specific embodiments of this application will now be clearly described in conjunction with the accompanying drawings.

[0055] Please see Figure 1 , Figure 1 This is a schematic diagram of a wafer testing apparatus 100 provided in an embodiment of this application. The wafer testing apparatus 100 provided in this embodiment can be used to inspect wafers of CMOS image sensor (CIS) chips. The wafer is an integrated circuit comprising a silicon substrate. The wafer testing apparatus 100 includes a wafer carrier platform 10, a testing machine 20, and an external controller 30. The wafer carrier platform 10 provides a placement space for the wafer so that the testing machine 20 can test the wafer. The external controller 30 can identify the test results of the wafer through signals from the testing machine 20.

[0056] Among them, a CIS chip is an integrated circuit that generates images through photoelectric conversion. The wafer testing device 100 can detect the electrical performance of the wafer, including key parameters such as resistance, capacitance, and current, ensuring that the wafer meets design requirements at the electrical level. During the testing process, defective areas of the wafer are marked. Timely removal of defective dies through wafer testing avoids the need for subsequent packaging and testing of defective products, thereby reducing unnecessary material waste and manufacturing costs. This ensures the quality and reliability of the final product.

[0057] It should be noted that, Figure 1 The purpose of this illustration is merely to depict the connection relationship between the wafer carrier platform 10, the test machine 20, and the external controller 30, and is not to specifically limit the connection positions, specific structures, or quantities of each device. Furthermore, the structures illustrated in the embodiments of this application do not constitute a specific limitation on the wafer testing apparatus 100. In other embodiments of this application, the wafer testing apparatus 100 may include... Figure 1This may involve more or fewer components, or combining certain components, or splitting certain components, or different component arrangements.

[0058] Currently, in wafer inspection, a light source is typically required between the tester and the wafer. For example, in the wafer testing of CIS chips, a light beam needs to be provided to illuminate the test area of ​​the wafer to convert it into electrical and digital signals for identification. The presence of the light source results in a significant distance between the tester and the wafer, necessitating additional electrical connections. However, these additional connections limit the signal transmission rate, ultimately leading to inaccurate wafer inspection.

[0059] Based on this, please refer to Figure 2 , Figure 2 yes Figure 1 The diagram shows the structure of the wafer carrier platform 10. The wafer carrier platform 10 can integrate the light source 14.

[0060] The wafer carrier platform 10 includes a probe station 11, a mounting bracket 12, a probe card 13, and a light source 14. The mounting bracket 12 is connected to the probe station 11. The probe card 13 and the light source 14 are mounted on the mounting bracket 12.

[0061] Please see Figure 3 , Figure 3 yes Figure 2 The diagram shows an assembly of the probe station 11, the mounting bracket 12, and the light source 14 of the wafer carrier platform 10. The probe station 11 includes a first test surface 111. The first test surface 111 is oriented towards the testing machine 20. The probe station 11 has a receiving cavity 1101. The receiving cavity 1101 is recessed from the first test surface 111. That is, the receiving cavity 1101 has an opening in the first test surface 111.

[0062] In this embodiment, the probe station 11 can provide a space for the probe card 13 and the wafer 40 to perform precise measurements on the wafer 40.

[0063] Please refer to the following: Figure 3 and Figure 4 , Figure 4 yes Figure 3 The diagram shows a structural schematic of the mounting bracket 12 and the light source 14 assembled together. The mounting bracket 12 includes a first surface 121 and a second surface 122. The first surface 121 and the second surface 122 are arranged opposite to each other. The mounting bracket 12 is provided with a mounting groove 1201. The mounting groove 1201 is recessed from the first surface 121. The bottom wall of the mounting groove 1201 is spaced apart from the second surface 122 of the mounting bracket 12. The mounting groove 1201 can penetrate the mounting bracket 12 along its width direction.

[0064] The first surface 121 of the mounting bracket 12 is connected to the first test surface 111 of the probe station 11. Both ends of the mounting bracket 12 along its length can be connected to the first test surface 111. Along the height direction of the wafer carrier platform 10, the middle region of the mounting bracket 12 can be located above the receiving cavity 1101 of the probe station 11. The area above the receiving cavity 1101 is the side of the receiving cavity 1101 facing the first test surface 111. The middle region of the mounting bracket 12 is opposite to the opening of the receiving cavity 1101.

[0065] In this embodiment, the mounting bracket 12 serves as a reinforcement structure for the probe station 11. The mounting bracket 12 is mounted on the first test surface 111 of the probe station 11. The mounting bracket 12 can enhance the structural stability of the entire wafer carrier platform 10.

[0066] The light source 14 is connected to the wall of the mounting groove 1201. The surface of the light source 14 facing away from the mounting groove 1201 is the light-emitting surface. The light source 14 can protrude from both sides of the mounting bracket 12 in the width direction. The light-emitting surface of the light source 14 can be flush with the first surface 121 of the mounting bracket 12. Alternatively, the light-emitting surface of the light source 14 can be recessed relative to the first surface 121 of the mounting bracket 12.

[0067] In one possible implementation, please refer to [the relevant documentation]. Figure 4 and Figure 5 , Figure 5 yes Figure 4 The diagram shows a cross-sectional view of the mounting bracket 12 and the light source 14. The mounting bracket 12 is provided with a connection hole 1202, which penetrates the bottom wall of the mounting groove 1201 and the surface of the mounting bracket 12 facing away from the first test surface 111.

[0068] A connecting groove 1401 is provided on the side of the light source 14 facing the bottom wall of the groove. The inner wall of the connecting groove 1401 may be threaded. At least part of the groove structure of the connecting groove 1401 may be located within the connecting hole 1202 of the fixing bracket 12.

[0069] The wafer carrier platform 10 also includes a connector 15, which passes through the connection hole 1202 and is connected to the light source 14.

[0070] Specifically, the connector 15 can be a screw. The head of the connector 15 can abut against the second surface 122 of the fixing bracket 12. The periphery of the rod of the connector 15 can be provided with threads. The rod of the connector 15 is threadedly connected to the connecting groove 1401 of the light source 14.

[0071] Please refer to the following: Figure 2The probe card 13 includes a first connecting surface 131 and a second connecting surface 132. Along the thickness direction of the probe card 13, the first connecting surface 131 and the second connecting surface 132 are arranged opposite to each other. The first connecting surface 131 is used for electrical connection with the test machine 20. The second connecting surface 132 is used for electrical connection with the wafer 40.

[0072] Please see Figure 6 , Figure 6 yes Figure 2 The diagram shows the structure of the probe card 13. The first connecting surface 131 includes a first region 1311 and a second region 1312. There can be two second regions 1312, located on opposite sides of the first region 1311. The first region 1311 is used for fixed connection with the mounting bracket 12. The second region 1312 is used for electrical connection with the testing machine 20.

[0073] The first region 1311 is connected to both ends of the mounting bracket 12 along its length. A light-transmitting hole 1313 may be provided in the middle portion of the first region 1311. The light-transmitting hole 1313 penetrates the probe card 13 along its thickness direction. A lens structure (not shown) may be provided within the light-transmitting hole 1313.

[0074] In this embodiment, the light source 14 can emit light toward the first region 1311. The light source 14 can contact the first region 1311 of the first connection surface 131. The light can be irradiated onto the surface of the wafer 40 through the lens structure of the light-transmitting hole 1313 of the probe card 13.

[0075] When wafer 40 is being tested, wafer 40 can be electrically connected to the second connection surface 132 of probe card 13. The test area of ​​wafer 40 can be opposite to the area of ​​probe card 13 where the light-transmitting hole 1313 is provided.

[0076] Please see Figure 7 , Figure 7 yes Figure 1 The diagram shows the structure of the testing machine 20. The testing machine 20 includes a housing 21, a first connector 22, a second connector 23, an image acquisition card 24, a power supply board 25, and a digital board 26. The first connector 22, the second connector 23, the image acquisition card 24, the power supply board 25, and the digital board 26 are all connected to the housing 21.

[0077] In this embodiment, the test machine 20 can be electrically connected to the probe card 13 of the wafer carrier platform 10 to receive signals from the wafer 40. The test machine 20 is also electrically connected to an external controller 30 to perform high-speed image processing. The external controller 30 can use the target data obtained from the image processing information to identify the effects of interference.

[0078] The housing 21 includes a second test surface 211. The housing 21 is provided with a clearance groove 2101, a first connecting hole 2102, and a second connecting hole 2103. The clearance groove 2101 is recessed within the second test surface 211. For example, the clearance groove 2101 may be located in the middle region of the second test surface 211. The depth of the clearance groove 2101 may be greater than or equal to the height of the mounting bracket 12.

[0079] There can be multiple first connection holes 2102, and these multiple first connection holes 2102 can penetrate the second test surface 211 of the housing 21. The first connection holes 2102 can connect the internal space of the housing 21 with the external space. For example, the opening of the first connection hole 2102 can be located in the edge region of the second test surface 211.

[0080] There can be multiple second connecting holes 2103, and each second connecting hole 2103 can penetrate the second test surface 211 of the housing 21. Multiple second connecting holes 2103 can be arranged around the clearance groove 2101. The second connecting holes 2103 can be spaced apart from the first connecting holes 2102. The second connecting holes 2103 can communicate between the internal space and the external space of the housing 21. For example, the opening of the second connecting hole 2103 can be located in the edge region of the second test surface 211, and the second connecting holes 2103 can be arranged around the clearance groove 2101.

[0081] The first connector 22 is connected to the first connection hole 2102. The first connector 22 is located within the area of ​​the second test surface 211. The surface of the first connector 22 located outside the housing 21 may be flush with the second test surface 211 of the housing 21. Alternatively, the surface of the first connector 22 located outside the housing 21 may protrude relative to the second test surface 211. For example, the first connector 22 may be a pogo pin.

[0082] The second connector 23 is connected to the second connection hole 2103. The second connector 23 is located within the area of ​​the second test surface 211. The surface of the second connector 23 located outside the housing 21 may be flush with the second test surface 211 of the housing 21. Alternatively, the surface of the second connector 23 located outside the housing 21 may protrude relative to the second test surface 211. For example, the second connector 23 may be a pogo pin.

[0083] Image acquisition card 24 is installed inside housing 21. Image acquisition card 24 is connected to the first connector 22 located on one side inside housing 21. For example, gold finger contacts (not shown) may be provided on the bottom of image acquisition card 24. For example, image acquisition card 24 may be a high-speed image acquisition card.

[0084] In this embodiment, to support high-speed data transmission, the image acquisition card 24 can employ a high-speed interface, such as a PCIe (Peripheral Component Interconnect Express) interface, whose transmission rate is far higher than that of the traditional PCI interface. The image acquisition card 24 may employ parallel processing technology, enabling it to process multiple image data channels simultaneously, thereby improving overall processing speed. Through built-in hardware acceleration algorithms or customizable FPGA (Field-Programmable Gate Array) logic, the high-speed image acquisition card 24 can optimize the image processing flow, reduce computation time, and improve processing efficiency. The high-speed image acquisition card 24 offers high speed and efficiency in data acquisition, processing, and transmission, resulting in improved real-time performance and accuracy.

[0085] For one possible implementation, please refer to Figure 8 , Figure 8 yes Figure 7 The first connector 22 shown connects to the image acquisition card 24. Inside the first connector 22 is a clamping structure 221. After the image acquisition card 24 is inserted into the first connector 22, the image acquisition card 24 can be fixedly connected to the clamping structure 221 of the first connector 22, causing the gold finger contacts of the image acquisition card 24 to contact the first connector 22, thereby electrically connecting the image acquisition card 24 to the first connector 22.

[0086] Please refer to the following: Figure 7 The power board 25 and / or the digital board 26 are connected inside the housing 21. The power board 25 and / or the digital board 26 are electrically connected to the second connector 23.

[0087] In this embodiment, the power board 25 can precisely control the output voltage and current to ensure that the wafer 40 receives a stable and compliant power supply during testing.

[0088] Digital board 26 can generate various digital signals, such as clock signals and data signals. These signals are used to stimulate wafer 40, simulating various digital input situations that the chip may encounter in actual operation. At the same time, digital board 26 also has high-precision signal acquisition capabilities, which can capture the response output of wafer 40 to the stimulation signals in real time for subsequent data analysis and processing.

[0089] In one possible implementation, the test machine 20 includes at least one power board 25 and at least one digital board 26. One power board 25 is electrically connected to a second connector 23. One digital board 26 is electrically connected to a second connector 23.

[0090] In this embodiment, the test machine 20 directly integrates the high-speed image acquisition card 24, power supply board 25, and digital board 26 via the first connector 22 and the second connector 23. The test machine 20 can be directly electrically connected to the wafer carrier platform 10 via the first connector 22 and the second connector 23, without the need for connecting cables or adapter boards. This allows the test machine 20 to be more compatible with the test platform hardware systems of testing manufacturers, and gives it a wider range of applications in the current market.

[0091] The image acquisition card 24 in the test machine 20 can be directly replaced. When the wafer 40 is upgraded, the image acquisition card 24 can also be replaced synchronously. At the same time, it is compatible with all CIS chips in the testing industry, so that the evolution space of the test machine 20 is not limited and the testing compatibility is not limited.

[0092] When the wafer testing apparatus 100 is in operation, the wafer 40 is located within the receiving cavity 1101 of the wafer carrier platform 10. The wafer 40 is connected to the second connection surface 132 of the probe card 13. The second test surface 211 of the tester 20 is opposite to the first test surface 111 of the wafer carrier platform 10. The second test surface 211 can contact the first test surface 111. The mounting bracket 12 of the wafer carrier platform 10 can be embedded in the clearance slot 2101 of the tester 20. The first connector 22 and the second connector 23 of the tester 20 can connect to the second area 1312 of the first connection surface 131 of the probe card 13.

[0093] The first connector 22 can be plugged into the probe card 13 via a pogo pin. The first connector 22, projected onto the probe card 13, can be located in the second region 1312 of the first connection surface 131 of the probe card 13. The first connector 22 can electrically connect the image acquisition card 24 to the probe card 13, thereby electrically connecting the image acquisition card 24 to the wafer 40. The image acquisition card 24 can be electrically connected to the external controller 30 via a connection cable 60.

[0094] It is known that currently, because there is generally a light source device between the test machine and the wafer carrier platform, the test machine and the wafer carrier platform cannot be directly connected. They are typically connected via connecting cables and adapter boards to enable electrical conduction between the test machine and the wafer. However, because the structure of connecting cables and adapter boards can affect the signal transmission quality and speed, current test machines have difficulty detecting the transmission of high-speed signals within the wafer.

[0095] In this embodiment, the image acquisition card 24 is integrated with the test machine 20 via the first connector 22. The image acquisition card 24 is located close to the wafer 40 and is directly electrically connected to the wafer 40 via the probe card 13. This avoids signal transmission between the image acquisition card 24 and the wafer 40 through connecting cables or adapter boards, thereby improving the signal quality of transmission between the image acquisition card 24 and the wafer 40. This allows the test machine 20 to perform testing on the wafer 40.

[0096] Since wafer 40 is generally the basic material for chip manufacturing, inspecting wafer 40 can prevent substandard wafer 40 from entering subsequent chip fabrication processes. Chips made from substandard wafer 40 often have a high defect rate, meaning manufacturers need to invest more resources in handling these defective products, such as recycling, remanufacturing, or destruction. These handling measures also increase manufacturing costs.

[0097] Reducing the transmission length of the test signal link between the test machine 20 and the wafer 40 can increase the signal transmission rate between them, thereby enabling more accurate verification of the proper functioning of the wafer 40, including image acquisition, signal processing, and data transmission. Furthermore, it allows for testing of the wafer 40's performance under different operating conditions, such as sensitivity, signal-to-noise ratio, and dynamic range, to ensure it meets design requirements and application needs.

[0098] The light source 14 and the mounting bracket 12 of the wafer testing device 100 are embedded in the clearance slot 2101 of the testing machine 20. Therefore, after the testing machine 20 is docked with the wafer 40 testing platform, the light source 14 will not obstruct the docking between the testing machine 20 and the wafer 40, and the light source 14 can still emit light to the wafer 40. The light source 14 can simulate various lighting environments that CIS chips may encounter in practical applications, such as sunlight, indoor lighting, and low light. By adjusting parameters such as the intensity and spectral distribution of the light source 14, the performance of the CIS chip under different lighting conditions can be evaluated, including sensitivity, signal-to-noise ratio, and color reproduction capability.

[0099] Since the tester 20 directly integrates the image acquisition card 24 and the power board 25 / digital board 26, it can automatically align the tester 20 with the wafer carrier platform 10 during the wafer testing process of the wafer testing device 100, and enable the tester 20 to start testing, thereby improving the overall automation level of the wafer testing device 100.

[0100] The second connector 23 can be plugged into the probe card 13 via a pogo pin. The orthographic projection of the second connector 23 toward the probe card 13 can be located in the second region 1312 of the first connection surface 131 of the probe card 13.

[0101] The above are exemplary embodiments of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A wafer carrier platform, characterized in that, include: A probe station includes a first test surface for docking with a testing machine. The probe station is provided with a receiving cavity, which is recessed from the first test surface and is used to accommodate a wafer. A mounting bracket is connected to the first test surface, and the surface of the mounting bracket facing the receiving cavity is recessed with a mounting groove. The probe card includes a first connecting surface and a second connecting surface. Along the thickness direction of the probe card, the first connecting surface and the second connecting surface are arranged opposite to each other. The first connecting surface includes a first region and a second region. The first region is connected to the fixture, the second region is used for electrical connection with the test equipment, and the second connecting surface is used for electrical connection with the wafer. A light source is connected to the wall of the mounting slot, and the light source is able to emit light toward the first area so that the light passes through the probe card and illuminates the surface of the wafer.

2. The wafer carrier platform according to claim 1, characterized in that, The light-emitting surface of the light source is flush with the surface of the fixing frame facing the first connecting surface.

3. The wafer carrier platform according to claim 2, characterized in that, The first connecting surface is flush with the first test surface.

4. The wafer carrier platform according to any one of claims 1-3, characterized in that, The mounting groove extends through the fixing frame along the width direction, and the light source protrudes from both sides of the fixing frame relative to the width direction.

5. The wafer carrier platform according to any one of claims 1-3, characterized in that, There are two second regions, located on opposite sides of the first region.

6. The wafer carrier platform according to any one of claims 1-3, characterized in that, The fixing frame is provided with a connecting hole, which penetrates the bottom wall of the mounting groove and the surface of the fixing frame away from the first test surface; The wafer carrier platform also includes a connector, which passes through the connection hole and is connected to the light source.

7. A testing machine, characterized in that, For docking with the wafer carrier platform according to any one of claims 1-6 to test the wafer, the testing machine includes: The housing has a second test surface, which is arranged opposite to the first test surface. The housing also has a clearance groove, which is recessed from the second test surface. A first connector is connected to the housing and is located within the area of ​​the second test surface; An image acquisition card, which is plugged into the first connector.

8. The testing machine according to claim 7, characterized in that, The testing machine also includes a power board and / or a digital board, and a second connector connected to the housing. The second connector is located within the range of the second testing surface, and the power board and / or digital board are electrically connected to the second connector.

9. A wafer testing device, characterized in that, Includes the wafer carrier platform as described in any one of claims 1-6, and the test machine as described in claim 7 or 8; When the wafer testing device is in operation, the wafer is connected to the second connection surface of the probe card, the second test surface of the test machine is disposed opposite to the first test surface of the wafer carrier platform, and the first connector is electrically connected to the second area of ​​the probe card.

10. The wafer testing apparatus according to claim 9, characterized in that, The height of the fixing frame is less than or equal to the depth of the clearance groove of the housing.

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