Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a substrate, a circuit layer, a filter layer and a dielectric layer, the circuit layer is arranged on the substrate, and the circuit layer comprises a signal line. The filter layer is disposed on the circuit layer, and the filter layer includes a plurality of filter patterns. One of the plurality of filter patterns includes a first arc angle and a second arc angle, and the first arc angle and the second arc angle are adjacent to the signal line. The filter layer is arranged between the circuit layer and the dielectric layer. Wherein the curvature radius of the first arc angle is different from that of the second arc angle.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to an electronic device including a filter layer disposed on a circuit layer. Background Technology

[0002] With technological advancements, electronic devices have become indispensable in modern life. In electronic devices such as virtual reality (VR) devices and liquid crystal displays, the small pixel size places higher demands on the alignment accuracy and patterning design of the color filter layer. Therefore, the architectural design of color filter layers in electronic devices remains one of the important research topics today. Summary of the Invention

[0003] The purpose of this invention is to provide an electronic device that, by using a filter pattern with different curvatures and arc angles on a filter layer disposed on a circuit layer, can reduce light leakage and improve color saturation, thereby improving the display quality of the electronic device.

[0004] This invention provides an electronic device comprising a substrate, a circuit layer, a filter layer, and a dielectric layer. The circuit layer is disposed on the substrate and includes signal lines. The filter layer is disposed on the circuit layer and includes multiple filter patterns. One of the multiple filter patterns includes a first arc angle and a second arc angle, the first arc angle and the second arc angle being adjacent to the signal lines. The filter layer is disposed between the circuit layer and the dielectric layer. The radius of curvature of the first arc angle is different from the radius of curvature of the second arc angle. Attached Figure Description

[0005] Figure 1 This is a partial top view of the electronic device according to the first embodiment of the present invention.

[0006] Figure 2A and Figure 2B This is an enlarged top view schematic diagram of some variations of the filter pattern in the first embodiment of the present invention.

[0007] Figure 3 This is a partial top view of the electronic device according to the second embodiment of the present invention.

[0008] Figure 4 This is a partial top view of the electronic device according to the third embodiment of the present invention.

[0009] Figure 5 This is an enlarged top view of a variation of the filter pattern in the third embodiment of the present invention.

[0010] Figure 6 This is a partial top view of the electronic device according to the fourth embodiment of the present invention.

[0011] Figure 7 This is a partial top view of the electronic device according to the fifth embodiment of the present invention.

[0012] Figure 8 This is a partial cross-sectional schematic diagram of the electronic device according to the fifth embodiment of the present invention.

[0013] Figure 9 This is a magnified top view of the holes in the filter layer according to the fifth embodiment of the present invention.

[0014] Figure 10 This is a partial cross-sectional schematic diagram of a variation of the electronic device according to the fifth embodiment of the present invention.

[0015] Figure 11 This is a partial top view of the electronic device according to the sixth embodiment of the present invention.

[0016] Figure 12 This is a partial cross-sectional schematic diagram of the electronic device according to the sixth embodiment of the present invention.

[0017] Explanation of reference numerals: 100, OSB - substrate; 200 - circuit layer; 210 - signal line; 300 - filter layer; 310 - filter pattern; 311 - first filter pattern; 312 - second filter pattern; 313 - third filter pattern; 400 - dielectric layer; 100, OSB - substrate; A1 - first included angle; A2 - second included angle; BF - buffer layer; C1 - first arc angle; C2 - second arc angle; C3, C4, C5, C6, C7, C8 - arc angle; CH1, CH2 - channel area; CL - center line; CT1, CT2 - contact; D1, D2 - diagonal; DE1, DE2 - drain; DL - data line; E1, E2 - extension line; ED - electronic device; EPa, EPb - end; GE1, GE2 - gate; GL - scan line; IN, IN1, IN2, I N3, IN4, IN5, IN6, IN7, IN8 - Insulating layer; LS, BM - Light-shielding layer; ME1, M1, M2, M3, M4, M5, M6, ME2, M7 - Conductive layer; OC, PL - Protective layer; OPS - Second spacer; PR - Peripheral area; PS - First spacer; R1, R2, RV - Radius of curvature; RE - Rectangle; REF - Reference pattern; RR - Radius; RS - Recess; S1 - First edge; S2 - Second edge; S3 - Third edge; S4 - Fourth edge; SE1, SE2 - Source; SM1, SM2 - Semiconductor layer; TFT - Thin film transistor; TFT1 - First thin film transistor; TFT2 - Second thin film transistor; V1, V0 - Hole; W - Maximum width; W1, W2 - Width; WR - Working area; X, Y, Z - Direction. Detailed Implementation

[0018] The present invention will be described in detail below with reference to specific embodiments and accompanying drawings. It should be noted that, for ease of understanding and to keep the drawings concise, many of the accompanying drawings only depict a portion of the device or structure, and specific elements in the drawings are not drawn to scale. Furthermore, the number and dimensions of each element in the drawings are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0019] Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This invention is not intended to distinguish between elements that have the same function but different names. In this specification and claims, words such as "comprising," "including," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". When the terms "comprising," "including," and / or "having" are used in this specification, they specify the presence of the stated feature, area, step, operation, and / or element, but do not exclude the presence or addition of one or more other features, areas, steps, operations, elements, and / or combinations thereof.

[0020] When an element or membrane is referred to as being "on" or "connected" to another element or membrane, it can be directly on or directly connected to the other element or membrane, or there can be an inserted element or membrane between the two. Conversely, when an element is referred to as being "directly" on or "directly connected" to another element or membrane, there can be no inserted element or membrane between the two.

[0021] The directional terms used in this invention, such as "up," "down," "front," "back," "left," and "right," are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the invention.

[0022] The ordinal numbers used in the specification and claims of this invention, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number of that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing methods. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0023] The terms “equal to,” “same as,” “substantially,” or “approximately” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0024] According to embodiments of the present invention, the length, width, and / or distance between elements can be measured using an optical microscope (OM), a scanning electron microscope (SEM), or other suitable methods. For example, the length, width, and / or distance between elements can be measured from images obtained by a scanning electron microscope, but this is not a limitation.

[0025] The electronic device described in this invention can be applied to display devices, virtual reality devices, augmented reality (AR) devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or splicing devices, but is not limited thereto. The electronic device can be bendable or flexible. The electronic device may include, for example, liquid crystal, light-emitting diode, fluorescence, phosphorescence, other suitable display media, or combinations thereof, but is not limited thereto. The display device can be a non-self-emissive display device or a self-emissive display device. The antenna device can be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device can be a sensing device for capacitance, light, heat, or ultrasound, but is not limited thereto. The electronic device may include, for example, passive and active electronic components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. Light-emitting diodes (LEDs) may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited thereto. Splicing devices may be, for example, display splicing devices or antenna splicing devices, but are not limited thereto. It should be noted that electronic devices may be any combination of the foregoing, but are not limited thereto. Electronic devices may have peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, wearable devices (e.g., augmented reality or virtual reality devices), automotive devices (e.g., automotive windshields), or splicing devices.

[0026] It should be understood that, without departing from the spirit of the present invention, features in several different embodiments can be replaced, recombined, or mixed to complete other embodiments.

[0027] Please refer to Figure 1 This is a partial top view schematic diagram of the electronic device according to the first embodiment of the present invention. For the sake of simplicity, the figures are shown below. Figure 1The image shows only a top view of some components of the electronic device ED, in which... Figure 1 The stacking of the electronic device ED along direction Z on the substrate 100 can be, for example (but not limited to), referenced to Figure 8 The cross-sectional structure shown. (As shown) Figure 1 As shown, and in conjunction with Figure 8 The electronic device ED may include a substrate 100 and a circuit layer 200 (shown in...). Figure 8 ), filter layer 300 and dielectric layer 400 (shown in Figure 8 A circuit layer 200 is disposed on the substrate 100, and the circuit layer 200 includes signal lines 210. Signal lines 210 may include scan lines GL and data lines DL. Scan lines GL may extend along direction X, and data lines DL may extend along direction Y, wherein direction X is not parallel to direction Y; for example, direction X may be perpendicular to direction Y, but is not limited thereto. Direction Z may be the normal direction of the electronic device ED and parallel to the top view direction of the electronic device ED and the normal direction of the surface of the substrate 100. That is, direction Z may be perpendicular to the upper or lower surface of the substrate 100, and directions X and Y may be perpendicular to direction Z, respectively. The substrate 100 may include rigid or flexible materials, such as glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or combinations thereof, but is not limited thereto.

[0028] The filter layer 300 is disposed on the circuit layer 200, and the filter layer 300 is disposed between the circuit layer 200 and the dielectric layer 400 in the Z direction (e.g., Figure 8 (As shown). By placing the filter layer 300 and the circuit layer 200 on the same side of the dielectric layer 400, the alignment accuracy of the film layers can be improved. The filter layer 300 includes a plurality of filter patterns 310, wherein one or more filter patterns 310 include a first arc angle C1 and a second arc angle C2, and the first arc angle C1 and the second arc angle C2 are adjacent to the signal line 210. The radius of curvature R1 of the first arc angle C1 is different from the radius of curvature R2 of the second arc angle C2; ​​that is, the curvature of the first arc angle C1 is different from the curvature of the second arc angle C2. According to... Figure 1 In the illustrated embodiment, the first arc angle C1 and the second arc angle C2 of the filter pattern 310 may be adjacent to the scan line GL, and the radius of curvature R2 of the second arc angle C2 is smaller than the radius of curvature R1 of the first arc angle C1. The second arc angle C2 may be formed, for example (but not limited to), by means of optical proximity correction (OPC) technology.

[0029] In some embodiments, a plurality of scan lines GL and a plurality of data lines DL may be formed on the substrate 100, intersecting to define regions of a plurality of pixels (or sub-pixels), and the electronic device ED may have the function of displaying an image, but is not limited thereto. The plurality of filter patterns 310 may include a first filter pattern 311, a second filter pattern 312, and a third filter pattern 313, which can filter light of specific wavelengths to allow different colors of light to pass through and correspond to sub-pixels of different colors. For example, the first filter pattern 311 allows red light to pass through and corresponds to a red sub-pixel, the second filter pattern 312 allows green light to pass through and corresponds to a green sub-pixel, and the third filter pattern 313 allows blue light to pass through and corresponds to a blue sub-pixel, but is not limited thereto. A sub-pixel corresponding to the first filter pattern 311, another sub-pixel corresponding to the second filter pattern 312, and yet another sub-pixel corresponding to the third filter pattern 313 can constitute a pixel, and the electronic device ED may include a plurality of pixels arranged in a pixel array along directions X and Y, but is not limited thereto. Each filter pattern 310 may include a red color resist, a green color resist, a blue color resist, other suitable filter elements, or any combination thereof. In some embodiments, multiple filter patterns 310 may also be coupled with light-emitting elements that emit different colors of light to make the sub-pixels present different colors, but this is not a limitation.

[0030] like Figure 1 As shown, the electronic device ED may also include an elongated aperture V1 extending along the X direction, and the conductive layers located above and below the filter layer 300 can be electrically connected through the aperture V1, for example, see reference. Figure 8 The stacked structure shown will be described in further detail later. In some embodiments, the electronic device ED may also include at least one insulating layer, at least one conductive layer, and / or a thin-film transistor (e.g., a thin-film transistor) disposed on the substrate 100. Figure 8 The thin-film transistors (TFTs) and other film layers and components shown herein can be connected to and control the pixels or sub-pixels corresponding to each filter pattern 310, serving as switching or driving elements. The thin-film transistors located below the filter layer 300 can be electrically connected to the conductive layer located above the filter layer 300 through the aperture V1.

[0031] according to Figure 1In the illustrated embodiment, the multiple filter patterns 310 can be island-shaped patterns, that is, the upper and lower horizontally arranged filter patterns 310 can be separated from each other to reduce the area occupied by the filter layer 300, thereby allowing sufficient space for electrical connection between the conductive layers above and below the filter layer 300, thus reducing the impact on the electrical connection area. In some embodiments, the design can be carried out using sub-pixel rendering (SPR) technology, so that filter patterns 310 of different colors are included in the same vertical row. For example, the first filter pattern 311, the second filter pattern 312, and the third filter pattern 313 can be configured as follows: Figure 1 The arrangement shown is not limited to the above; however, the present invention is not limited thereto. In other embodiments, the same row may include only one color filter pattern 310, such as... Figure 4 As shown.

[0032] Please refer to Figure 2A and Figure 2B and cooperate Figure 1 . Figure 2A and Figure 2B This is a top view schematic diagram illustrating some variations of the filter pattern in the first embodiment of the present invention. The following will use... Figure 2A and Figure 2B The filter pattern 310 shown is for illustrative purposes only. It should be noted that... Figure 1 One or more of the filter patterns 310 shown may also conform to the following detailed structural features. For example... Figure 2A and Figure 2B As shown, the filter pattern 310 may include a first edge S1, a second edge S2, and a third edge S3. A first arc angle C1 connects the first edge S1 and the second edge S2, and a second arc angle C2 connects the second edge S2 and the third edge S3. The first edge S1 and the third edge S3 are opposite each other, and the second edge S2 connects the first edge S1 and the third edge S3. The radius of curvature R2 of the second arc angle C2 may be smaller than the radius of curvature R1 of the first arc angle C1. A first included angle A1 corresponding to the first arc angle C1 exists between the extension line E1 of the first edge S1 and the extension line E2 of the second edge S2. A second included angle A2 corresponding to the second arc angle C2 exists between the extension line E2 of the second edge S2 and the extension line E3 of the third edge S3. Both the first included angle A1 and the second included angle A2 are less than 180 degrees, where the first included angle A1 is greater than 90 degrees and the second included angle A2 is less than 90 degrees. That is, the first included angle A1 is an obtuse angle, and the second included angle A2 is an acute angle. In some embodiments, the edge of the filter pattern 310 connecting the second arc angle C2 may also include a recess RS, for example, the third edge S3 may include a recess RS, but is not limited thereto.

[0033] according to Figure 2A and Figure 2BIn the illustrated embodiment, the filter pattern 310 has a maximum width W in the direction X. For example, the longest distance between the first edge S1 and the second edge S2 in the direction X can be defined as the maximum width W. One end EPa of the second edge S2 is connected to the second arc angle C2, and a center line CL can be defined where the filter pattern 310 has the maximum width W. The center line CL is perpendicular to the direction X, and the length L1 of the second edge S2 between the end EPa and the center line CL is greater than or equal to 1 / 6 times the maximum width W (i.e., L1≥W*1 / 6). The second edge S2 also has another end EPb relative to the end EPa, and the other end EPb is connected to the first arc angle C1, where the length L2 of the second edge S2 between the other end EPb and the center line CL is less than 1 / 6 times the maximum width W (i.e., L2<W*1 / 6). In other words, when the end of the second edge S2 is at a distance greater than or equal to W*1 / 6 from the center line CL, the arc angle connected to this end is defined as the second arc angle C2; when the end of the second edge S2 is at a distance less than W*1 / 6 from the center line CL, the arc angle connected to this end is defined as the first arc angle C1.

[0034] According to the foregoing Figure 1 、 Figure 2A and Figure 2B In the illustrated embodiment, the filter pattern 310 of the filter layer 300 provided on the circuit layer 200 has a specific pattern design, which includes the first arc angle C1 and the second arc angle C2 with different radii of curvature, can reduce light leakage and improve color saturation, and thus improve the display quality of the electronic device ED.

[0035] Such as Figure 1 、 Figure 2A and Figure 2BAs shown, in some embodiments, the filter pattern 310 may further include another arc angle C3 (which may be referred to as a third arc angle), which is located on opposite sides of a diagonal D1 of the filter pattern 310, wherein the radius of curvature of arc angle C3 is smaller than the radius of curvature R1 of the first arc angle C1. Arc angle C3 may be formed, for example (but not limited to), by means of optical approximation correction techniques. The filter pattern 310 may also have another diagonal D2, the length of which is different from the length of diagonal D1. For example, the length of diagonal D1 may be greater than the length of diagonal D2. In some embodiments, the filter pattern 310 may further include yet another arc angle C4, which is located on opposite sides of diagonal D2, and the radius of curvature of arc angle C4 is greater than the radii of curvature of the second arc angle C2 and arc angle C3. Specifically, the filter pattern 310 may include a fourth edge S4 opposite to the second edge S2, with an arc angle C3 connecting the first edge S1 and the fourth edge S4, and the arc angle C4 connecting the fourth edge S4 and the third edge S3. The extension line E4 of the fourth edge S4, together with extension lines E1, E2, and E3, forms the smallest quadrilateral surrounding the filter pattern 310. Referring to the aforementioned positional relationship between the second arc angle C2, the first arc angle C1, and their corresponding edges, the arc angle C3 may have similar detailed structural features to the second arc angle C2, and the arc angle C4 may have similar detailed structural features to the first arc angle C1; these details will not be elaborated further here.

[0036] according to Figure 1 , Figure 2A and Figure 2B The structural design of the filter pattern 310 shown allows adjacent filter patterns 310 (e.g., adjacent first filter pattern 311 and second filter pattern 312) to have arc angles with smaller radii of curvature on both sides of diagonal D1 (i.e., second arc angle C2 and arc angle C3), and arc angles with larger radii of curvature on both sides of diagonal D2 (i.e., first arc angle C1 and arc angle C4). This reduces the risk of adjacent filter patterns 310 overlapping at corners, where overlapping patterns may result in an excessively thick film layer, affecting the insulating layer (e.g., on the filter layer 300). Figure 8 The filling capacity of PLN shown.

[0037] Please refer to Figure 3 This is a partial top view of the electronic device according to the second embodiment of the present invention. Figure 3 The electronic device ED of the second embodiment shown is Figure 1The difference in the first embodiment shown is that, in a diagonal direction other than the diagonal with a second arc angle C2 on one side, one corner of the filter pattern 310 that allows light of the same color to pass through can be connected to each other. Furthermore, the electronic device ED can include a plurality of mutually spaced apertures V1, and the conductive layers located above and below the filter layer 300 can be electrically connected through the plurality of apertures V1. Specifically, as... Figure 3 As shown, the corners of two adjacent first filter patterns 311 can be connected to each other, wherein the connected corners are located on one side of a diagonal. Similarly, multiple second filter patterns 312 can be connected to each other, and multiple third filter patterns 313 can be connected to each other, but are not limited thereto.

[0038] Please refer to Figure 4 and Figure 5 . Figure 4 This is a partial top view of the electronic device according to the third embodiment of the present invention. Figure 5 This is an enlarged top view of a variation of the filter pattern in the third embodiment of the present invention, wherein... Figure 5 The filter pattern 310 shown can be applied to Figure 4 The electronic device ED is shown. According to... Figure 4 and Figure 5 In the illustrated embodiment, the first arc angle C1 and the second arc angle C2 of the filter pattern 310 may be adjacent to the data line DL, wherein the radius of curvature R2 of the second arc angle C2 is smaller than the radius of curvature R1 of the first arc angle C1. The second arc angle C2 may be formed, for example (but not limited to), by optical approximation correction techniques. The filter pattern 310 includes the first arc angle C1 and the second arc angle C2 with different radii of curvature, which can reduce light leakage and improve color saturation, thereby improving the display quality of the electronic device ED. In some embodiments, the filter pattern 310 may also include another arc angle C5, the second arc angle C2 and the arc angle C5 are located on the same side of the filter pattern 310, wherein the radius of curvature of the arc angle C5 is smaller than the radius of curvature R1 of the first arc angle C1. The arc angle C5 may be formed, for example (but not limited to), by optical approximation correction techniques. In some embodiments, the filter pattern 310 may further include another arc angle C6 (which may be referred to as the fourth arc angle), wherein the first arc angle C1 and the arc angle C6 are located on the same side of the filter pattern 310, and the radius of curvature of the arc angle C6 is greater than the radius of curvature R2 of the second arc angle C2.

[0039] like Figure 5As shown, the width W1 of one side of the filter pattern 310 is different from the width W2 of the other side. For example, the longest distance between the first arc angle C1 and arc angle C6 in the direction X can be defined as the width W1, and the longest distance between the second arc angle C2 and arc angle C5 in the direction X can be defined as the width W2, and the width W1 can be smaller than the width W2. The filter pattern 310 may include a first edge S1, a second edge S2, a third edge S3, and a fourth edge S4. The first arc angle C1 connects the first edge S1 and the second edge S2, the second arc angle C2 connects the second edge S2 and the third edge S3, the arc angle C5 connects the third edge S1 and the fourth edge S4, and the arc angle C6 connects the fourth edge S4 and the first edge S1. The detailed structural features of the extension lines of each arc angle and corresponding edge in the filter pattern 310 can be referred to the aforementioned first embodiment, and will not be repeated here.

[0040] like Figure 4 As shown, the electronic device ED may include an elongated hole V1 extending along the X direction, and a thin-film transistor (e.g., Figure 8 The thin-film transistor (TFT) shown can be connected to and control the sub-pixels corresponding to each filter pattern 310 through the hole V1. For example, the sub-pixel corresponding to the first filter pattern 311 can be connected to the TFT through the hole V1 on its lower side for signal transmission. Figure 4 and Figure 5 The structural design of the filter pattern 310 shown allows for a smaller radius of curvature on one side (i.e., the second arc angle C2 and arc angle C5) opposite to the position where the sub-pixel connects to the thin-film transistor, and a larger radius of curvature on the other side (i.e., the first arc angle C1 and arc angle C6) adjacent to the position where the corresponding sub-pixel connects to the thin-film transistor. In other words, the filter pattern 310 has a smaller area on the side where the sub-pixel connects to the thin-film transistor for signal transmission, thus allowing the insulating layer (e.g., [insulator name missing]) covering the filter layer 300 to [expand / enlarge / enlarge] more space. Figure 8 The insulating layer IN shown has good filling ability and can reduce the risk of line breakage caused by the conductive layer above the filter layer 300.

[0041] according to Figure 4 In the illustrated embodiment, the plurality of filter patterns 310 can be island-shaped patterns, that is, the upper and lower horizontally arranged filter patterns 310 can be separated from each other to reduce the area occupied by the filter layer 300. In some embodiments, such as Figure 4 As shown, a single row may include only one color filter pattern 310. That is, one row may include multiple first filter patterns 311, another row may include multiple second filter patterns 312, and yet another row may include multiple third filter patterns 313, but this is not a limitation.

[0042] Please refer to Figure 6This is a partial top view of the electronic device according to the fourth embodiment of the present invention. Figure 6 The electronic device ED of the fourth embodiment shown is Figure 5 The difference in the third embodiment shown is that the electronic device ED may include a plurality of holes V1 that are separated from each other, and the conductive layers located above and below the filter layer 300 may be electrically connected through the plurality of holes V1. For example, the sub-pixels corresponding to the first filter pattern 311, the second filter pattern 312 and the third filter pattern 313 may be connected to the thin-film transistor through the holes V1 on their lower sides for signal transmission.

[0043] Please refer to Figure 7 and Figure 8 . Figure 7 This is a partial top view of the electronic device according to the fifth embodiment of the present invention. Figure 8 This is a partial cross-sectional schematic diagram of an electronic device according to a fifth embodiment of the present invention. Figure 7 Only shown in Figure 8 A top view of some components of the electronic device ED shown. Figure 7 The partial cross-sectional structure of the electronic device ED corresponding to sections A-A' and B-B' can be referenced. Figure 8 .like Figure 7 and Figure 8 As shown, the electronic device ED may include a substrate 100 and a circuit layer 200, a filter layer 300, an insulating layer IN, a conductive layer ME1, and a dielectric layer 400 disposed on the substrate 100 along the Z direction. The circuit layer 200 includes signal lines 210 and thin-film transistors (TFTs), and the signal lines 210 may include scan lines GL extending along the X direction and data lines DL extending along the Y direction. The filter layer 300 may include a plurality of filter patterns 310, such as a first filter pattern 311, a second filter pattern 312, and a third filter pattern 313 extending along the Y direction, and the filter layer 300 has a hole V0, wherein the hole V0 includes one or more arc angles C7. The arc angles C7 may be formed, for example (but not limited to), by means of optical approximation correction techniques. The insulating layer IN has a hole V1, which may at least partially overlap the hole V0 in the Z direction, and the conductive layer ME1 may be electrically connected to the thin-film transistors (TFTs) through the holes V1 and V2. For example, the conductive layer ME1 can be electrically connected to the thin-film transistor (TFT) via a conductive layer M6 that partially fills and bridges the holes V1 and V0. The conductive layer ME1 can serve as a pixel electrode. The insulating layer IN can serve as a planarization layer to facilitate the placement of other components or films thereon. According to the above structural design, the holes V0 of the filter layer 300 have an arc angle C7, which can improve the adhesion of the filter layer 300 and increase the area of ​​the electrical transfer layer.

[0044] Please refer to Figure 9This is a magnified top view of the apertures in the filter layer according to the fifth embodiment of the present invention. Figure 9 As shown, taking the top view pattern of the aperture V0 of the filter layer 300 as the center, extending in directions parallel to direction X and parallel to direction Y, a minimum rectangle RE surrounding the aperture V0 can be obtained. Furthermore, using the four sides of rectangle RE as boundaries, a minimum circle or ellipse can be obtained within it as a reference pattern REF. From a top view, the area of ​​the aperture V0 is larger than the area of ​​the reference pattern REF. When the reference pattern REF is circular, the radius of curvature RV of the arc angle C7 of the aperture V0 can be smaller than the radius RR of the reference pattern REF; when the reference pattern REF is elliptical, the radius of curvature RV of the arc angle C7 of the aperture V0 can be smaller than half of the minor axis of the reference pattern REF. In some embodiments, such as... Figure 9 As shown, the hole V0 may include four arc angles C7 on its two diagonals; however, the invention is not limited thereto, and in other embodiments the hole V0 may include two arc angles C7 on the same side (e.g., the upper or lower side).

[0045] according to Figure 7 and Figure 8 In the illustrated embodiment, the circuit layer 200 may include a semiconductor layer SM1, an insulating layer IN1, a conductive layer M1, an insulating layer IN2, a semiconductor layer SM2, an insulating layer IN3, a conductive layer M2, an insulating layer IN4, a conductive layer M3, an insulating layer IN5, a conductive layer M4, an insulating layer IN6, and a conductive layer M5, sequentially disposed along the Z direction on the substrate 100. A portion of the conductive layer M2 may constitute a scan line GL in the signal line 210, and a portion of the conductive layer M3 may constitute a data line DL in the signal line 210. The circuit layer 200 may include a plurality of thin-film transistors (TFTs), which may include a first thin-film transistor TFT1 disposed in the peripheral region PR of the electronic device ED and a second thin-film transistor TFT2 disposed in the working region WR of the electronic device ED. When the electronic device ED is a display device with display function, the working region WR may be a display area and include multiple pixels (or sub-pixels), and the peripheral region PR may be a non-display area. In some embodiments, the electronic device ED may also selectively include a buffer layer BF disposed between the substrate 100 and the circuit layer 200. It should be noted that... Figure 8 The structure of circuit layer 200 shown is merely exemplary and is not intended to be limiting.

[0046] The first thin-film transistor (TFT) 1 may include a semiconductor layer SM1, a gate GE1, a source SE1, and a drain DE1. The semiconductor layer SM1 may include a channel region CH1. The gate GE1 is disposed above the semiconductor layer SM1 and overlaps with the channel region CH1. The source SE1 and drain DE1 are electrically connected to opposite sides of the channel region CH1, respectively. The gate GE1 may be formed by a conductive layer M1, while the source SE1 and drain DE1 may be formed by a conductive layer M2. An insulating layer IN1 may serve as the gate insulating layer of the first TFT 1. The semiconductor layer SM1 may, for example (but not limited to), include low-temperature polycrystalline silicon (LTPS). In some embodiments, the circuit layer 200 may further include a contact CT1 formed by a conductive layer M3, wherein the contact CT1 is electrically connected to the source SE1 and drain DE1 of the first TFT 1, so that the first TFT 1 can be electrically connected to external electronic components through the contact CT1.

[0047] The second thin-film transistor (TFT2) may include a semiconductor layer SM2, a gate GE2, a source SE2, and a drain DE2. The semiconductor layer SM2 may include a channel region CH2. The gate GE2 is disposed above the semiconductor layer SM2 and overlaps with the channel region CH2. The source SE2 and drain DE2 are electrically connected to opposite sides of the channel region CH2. The gate GE2 may be formed by a conductive layer M2, the source SE2 may be formed by a conductive layer M3, and the drain DE2 may be formed by a conductive layer M4. An insulating layer IN3 may serve as the gate insulating layer of the second thin-film transistor TFT2. The semiconductor layer SM2 may include a metal oxide, such as (but not limited to) indium gallium zinc oxide (IGZO). In some embodiments, the circuit layer 200 may further include a light-shielding layer LS formed by a conductive layer M1, wherein the light-shielding layer LS may be disposed corresponding to the channel region CH2 of the semiconductor layer SM2. In some embodiments, the light-shielding layer LS may serve as another gate GE2 of the second thin-film transistor TFT2, i.e., the second thin-film transistor TFT2 may be a dual-gate thin-film transistor. In some embodiments, the circuit layer 200 may further include a contact CT2 formed by a conductive layer M5, wherein the contact CT2 is electrically connected to the drain DE2 of the second thin-film transistor TFT2.

[0048] like Figure 7 and Figure 8As shown, the electronic device ED may further include a filter layer 300, an insulating layer IN, a conductive layer M6, an insulating layer IN7, a conductive layer ME1, an insulating layer IN8, and a conductive layer ME2 sequentially disposed along direction Z on the circuit layer 200. The conductive layer M6 can fill the holes V1 of the insulating layer IN and the holes V0 of the filter layer 300 and contact the contact CT2, thereby electrically connecting the conductive layer M6 to the second thin-film transistor TFT2 (or the drain DE2 of the second thin-film transistor TFT2) through the contact CT2. The insulating layer IN7 can fill the holes V1 and V0 and cover the conductive layer M6. The insulating layer IN7 can serve as a planarization layer to facilitate the deposition of other film layers (e.g., the conductive layer ME1). The conductive layer ME1 can contact and be electrically connected to the conductive layer M6, thereby electrically connecting the conductive layer ME1 to the drain DE2 of the second thin-film transistor TFT2 through the conductive layer M6 and the contact CT2. The conductive layer ME1 can serve as a pixel electrode, and the conductive layer ME2 can serve as a common electrode. In some embodiments, such as Figure 8 As shown, the electronic device ED may further include a conductive layer M7 disposed between the insulating layer IN8 and the conductive layer ME2, and the conductive layer M7 may partially overlap with the data line DL and / or the data line GL in the Z direction. The conductive layer M7 can reduce the resistance of the conductive layer ME2, which serves as a common electrode, and improve its voltage uniformity. It can also provide a light-shielding function to reduce color mixing between adjacent pixels of different colors at oblique viewing angles.

[0049] according to Figure 8 In the illustrated embodiment, conductive layers M1, M2, M3, M5, and M7 may comprise any suitable conductive material, such as (but not limited to) metallic materials. In some embodiments, conductive layer M7 may also be replaced by a non-conductive layer with a light-shielding effect, for example, it may comprise a black photoresist material or other materials with better light absorption, but is not limited thereto. Conductive layers M4, M6, ME1, and ME2 may comprise transparent conductive materials, such as (but not limited to) indium tin oxide (ITO). Insulating layers IN1, IN2, IN3, IN4, IN5, IN6, IN7, and IN9 may comprise any suitable organic or inorganic insulating material.

[0050] like Figure 8As shown, the electronic device ED may further include another substrate OSB, disposed opposite to the substrate 100, and a dielectric layer 400 may be disposed between the conductive layer ME2 and the substrate OSB. The material of the substrate OSB may refer to the material of the substrate 100 described above. The dielectric layer 400 may include, for example, a liquid crystal material as a display dielectric layer, but is not limited thereto. In some embodiments, the dielectric layer 400 may be provided with a plurality of spacers to maintain the gap between film layers. Specifically, the electronic device ED may include a plurality of first spacers PS disposed on the conductive layer ME2 and a plurality of second spacers OPS disposed opposite to the first spacers PS. For example, in the manufacturing process, a light-shielding layer BM may be first disposed on the substrate OSB, and then a protective layer OC may be disposed on the substrate OSB, and a plurality of second spacers OPS may be disposed on the protective layer OC, wherein the pattern of the light-shielding layer BM may correspond to the second spacers OPS. Next, the substrate OSB and the substrate 100 may be assembled such that the plurality of second spacers OPS are respectively superimposed on the plurality of first spacers PS in the Z direction. The second spacers OPS may or may not contact the first spacers PS to which they correspond.

[0051] according to Figure 7 and Figure 8 The electronic device ED shown, the method for manufacturing the aperture V0 of the filter layer 300 and the aperture V1 of the insulating layer IN may include the following steps. In some embodiments, the filter layer 300 may be patterned first to form a plurality of filter patterns 310 and a plurality of apertures V0 with an arc angle C7, and then the insulating layer IN may be formed and patterned to form a plurality of apertures V1, each aperture V1 may overlap an aperture V0 in the Z direction. Both the filter layer 300 and the insulating layer IN include photoresist material and can be directly patterned using a photolithography process. In other embodiments, protective photoresist may be formed on the filter layer 300 and the insulating layer IN respectively, the pattern may be defined by a photolithography process of the protective photoresist, and the filter layer 300 and the insulating layer IN may be patterned (e.g., including an etching process) respectively to form apertures V0 and V1 with an arc angle C7. In other embodiments, the filter layer 300 may be patterned first to form a plurality of filter patterns 310, then an insulating layer IN may be formed and patterned to form a plurality of holes V1, then a protective photoresist may be formed on the insulating layer IN, then the filter layer 300 may be patterned (e.g., including an etching process) to form a plurality of holes V0 with an arc angle C7, and then the protective photoresist may be removed. In other embodiments, the step of forming the protective photoresist may also be omitted.

[0052] Please refer to Figure 10 This is a partial cross-sectional schematic diagram of a variation of the electronic device according to the fifth embodiment of the present invention, wherein... Figure 10 A top view diagram of the electronic device ED corresponding to the cross-sectional structures along section lines A-A' and B-B' can be referenced. Figure 7 . Figure 10 The electronic device ED shown Figure 8 The difference in the fifth embodiment shown is that the electronic device ED may further include a protective layer PL disposed on the insulating layer IN, wherein the protective layer PL includes, for example (but not limited to), silicon nitride (SiNx). Figure 10 The electronic device ED shown includes a method for manufacturing holes V0 in the filter layer 300 and holes V1 in the insulating layer IN, which may include the following steps. First, a plurality of filter patterns 310 may be formed in the filter layer 300. Then, the insulating layer IN may be formed and patterned to form a plurality of holes V1. Next, a protective layer PL may be formed on the insulating layer IN. Then, a protective photoresist may be formed on the protective layer PL. Then, the protective layer PL and the filter layer 300 may be patterned (e.g., including an etching process) to form a plurality of holes V0 with an arc angle C7. In this embodiment, the conductive layer M6 partially covers the holes V1. In other embodiments, the conductive layer M6 may completely cover the holes V1, and the invention is not limited thereto.

[0053] Please refer to Figure 11 and Figure 12 . Figure 11 This is a partial top view of the electronic device according to the sixth embodiment of the present invention. Figure 12 This is a partial cross-sectional schematic diagram of an electronic device according to a sixth embodiment of the present invention. Figure 11 Only shown in Figure 12 A top view of some components of the electronic device ED shown. Figure 11 The partial cross-sectional structure of the electronic device ED corresponding to sections A-A' and B-B' can be referenced. Figure 12 . Figure 11 and Figure 12 The sixth embodiment shown is the same as Figure 7 and Figure 8 The difference in the fifth embodiment shown is that the insulating layer IN and the filter layer 300 have a hole V1. That is, the sidewall of the hole V1 can pass through the insulating layer IN and the filter layer 300, and the conductive layer ME1 (or conductive layer M6) can be electrically connected to the thin-film transistor TFT through the hole V1 in the insulating layer IN and the filter layer 300. The hole V1 may include one or more arc angles C8, thereby improving the adhesion of the filter layer 300 and increasing the electrical transfer area. The arc angle C8 can be formed, for example (but not limited to), by optical approximation correction techniques. A corresponding minimum rectangle and reference pattern, as well as the radius of curvature of its arc angle C8, can be obtained based on V1, as detailed above. Figure 9 The method shown will not be repeated here.

[0054] according to Figure 11 and Figure 12The electronic device ED shown, a method for manufacturing the aperture V1 of the filter layer 300 and the insulating layer IN may include the following steps. In some embodiments, the filter layer 300 may be patterned first to form a plurality of filter patterns 310, and then the insulating layer IN may be formed and the insulating layer IN and the filter layer 300 may be patterned to form a plurality of apertures V1 having an arc angle C8. In other embodiments, the filter layer 300 may be patterned first to form a plurality of filter patterns 310, and then the insulating layer IN and a protective layer (e.g., Figure 9 The protective layer PL is shown. A protective photoresist can then be formed on the protective layer PL. The protective layer PL, the insulating layer IN, and the filter layer 300 can then be patterned (e.g., including an etching process) to form a plurality of holes V1 with arc angles C8. In some other embodiments, the filter layer 300 can be patterned first to form a plurality of filter patterns 310, followed by the sequential formation of the insulating layer IN and the protective photoresist. Then, the insulating layer IN and the filter layer 300 can be patterned (e.g., including an etching process) to form a plurality of holes V1 with arc angles C8, and the protective photoresist can then be removed.

[0055] In summary, the electronic device according to embodiments of the present invention, by designing the filter pattern of the filter layer disposed on the circuit layer with arc angles of different curvatures, can reduce light leakage and improve color saturation, thereby improving the display quality of the electronic device. Furthermore, the pattern design of the filter pattern according to different embodiments can reduce the risk of film layer overlap, reduce the impact on the electrical transfer area, and / or reduce the risk of circuit breakage. In addition, by designing the holes in the filter layer and / or insulating layer with arc angles, the adhesion of the filter layer can be improved, and the electrical transfer area can be increased.

[0056] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An electronic device, characterized by comprising: Comprising: a substrate; a circuit layer disposed on the substrate, the circuit layer comprising a signal line; a filter layer disposed on the circuit layer, the filter layer comprising a plurality of filter patterns, wherein one of the plurality of filter patterns comprises a first arc angle and a second arc angle, the first arc angle and the second arc angle being adjacent to the signal line; and a dielectric layer, the filter layer being disposed between the circuit layer and the dielectric layer; wherein a radius of curvature of the first arc angle is different from a radius of curvature of the second arc angle. 2.The electronic device of claim 1, wherein, The one of the plurality of filter patterns further comprises a first edge, a second edge, and a third edge, the first arc angle being connected between the first edge and the second edge, the second arc angle being connected between the second edge and the third edge; wherein a first included angle between an extension line of the first edge and an extension line of the second edge corresponds to the first arc angle, a second included angle between the extension line of the second edge and an extension line of the third edge corresponds to the second arc angle, and the first included angle and the second included angle are both less than 180 degrees. 3.The electronic device of claim 2, wherein, The first included angle is greater than 90 degrees, and the second included angle is less than 90 degrees. 4.The electronic device of claim 1, wherein, The one of the plurality of filter patterns further comprises an edge connected to the second arc angle, and the edge comprises a recess. 5.The electronic device of claim 1, wherein, A width of one side of the one of the plurality of filter patterns is different from a width of another side thereof. 6.The electronic device of claim 1, wherein, The one of the plurality of filter patterns has a maximum width W in a direction and further comprises an edge having one end connected to the second arc angle, and a center line is defined at a location where the one of the plurality of filter patterns has the maximum width W, the center line being perpendicular to the direction, wherein a length of the edge between the one end and the center line is greater than or equal to W*1 / 6. 7.The electronic device of claim 6, wherein, The edge further has another end opposite to the one end, the other end being connected to the first arc angle, wherein a length of the edge between the other end and the center line is less than W*1 / 6. 8.The electronic device of claim 1, wherein, The one of the plurality of filter patterns further comprises a third arc angle, the third arc angle and the second arc angle being located on opposite sides of a diagonal line of the filter pattern, wherein a radius of curvature of the second arc angle is less than a radius of curvature of the first arc angle, and a radius of curvature of the third arc angle is less than the radius of curvature of the first arc angle. 9.The electronic device of claim 8, wherein, The one of the plurality of filter patterns further has another diagonal line, a length of the other diagonal line being different from a length of the diagonal line. 10.The electronic device of claim 1, wherein, The one of the plurality of filter patterns further comprises a fourth arc angle, the first arc angle and the fourth arc angle being located on a same side of the filter pattern, wherein a radius of curvature of the first arc angle is greater than a radius of curvature of the second arc angle, and a radius of curvature of the fourth arc angle is greater than the radius of curvature of the second arc angle.

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