Test method and system on chip

Abstract

The embodiment of the invention provides a test method and a system on chip, and the test method comprises the steps: responding to a test instruction, and constructing a scan chain; at least one target clock control module is determined in the clock control modules, and the target clock control module comprises delay selection information and at least one delay unit; determining at least one target delay unit according to the delay selection information corresponding to each target clock control module, determining a delay link corresponding to each target clock control module, and generating a corresponding delay shift clock signal based on each delay link; and controlling the scan chain to process test data corresponding to the test instruction in response to each delay shift clock signal. Through the test method provided by the embodiment of the invention, the power consumption of the system-on-chip during the test is reduced, and the reliability of the system-on-chip test is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present specification relate to the field of testing, and in particular, to a testing method and a system on a chip. BACKGROUND

[0002] With the evolution of semiconductor technology and the rise of multi-scenario intelligent applications, higher requirements are put forward for the performance, energy efficiency and reliability of a system on a chip (SOC). In order to meet the requirements of high parallel computing and low power control of the SOC put forward by various intelligent scenarios, the integration scale and architecture complexity of the SOC are continuously improved.

[0003] Before the SOC is put into application, in order to ensure product quality and functional reliability, comprehensive functional verification and fault detection are usually required after manufacturing. However, with the increasing scale and complexity of the SOC, the power consumption of the testing process is significantly increased, which becomes an important factor leading to the failure of the testing link. Therefore, the power consumption problem of the SOC testing becomes an important factor restricting the testability and yield improvement of the SOC. Therefore, an SOC testing method that can reduce the power consumption of the SOC testing is urgently needed to improve the reliability of the testing. SUMMARY

[0004] Therefore, the embodiments of the present specification provide a testing method. One or more embodiments of the present specification also relate to a system on a chip, a computing device, a computer readable storage medium and a computer program product to solve the technical defects in the prior art.

[0005] According to a first aspect of the embodiments of the present specification, a testing method is provided, applied to a system on a chip, wherein the system on a chip includes at least one functional module, each functional module includes at least one clock output module set and a clock control module corresponding to each clock output module set, and the testing method includes: constructing a scan chain in response to a test instruction; determining at least one target clock control module in each clock control module, wherein the target clock control module includes delay selection information and at least one delay unit; determining at least one target delay unit according to the delay selection information corresponding to each target clock control module, determining a delay link corresponding to each target clock control module, and generating a corresponding delay shift clock signal based on each delay link; controlling the scan chain to process test data corresponding to the test instruction in response to each delay shift clock signal.

[0006] According to a second aspect of the embodiments of the present specification, a test method is provided, applied to a system on chip, wherein the system on chip comprises at least one functional module, each functional module comprising at least one integrated clock gating, and the method comprises: in response to a test instruction, constructing a scan chain and at least one capture clock control unit corresponding to the scan chain, wherein the capture clock control unit comprises a gating unit; obtaining configuration information of at least one integrated clock gating; determining the number of clock output switches according to the gating unit, grouping each integrated clock gating according to the number of clock output switches and the configuration information of each integrated clock gating, obtaining at least one integrated clock gating group, and each clock output switch corresponds to each integrated clock gating; determining an integrated clock gating group outputting a capture clock signal according to the clock output switch, and outputting the capture clock signal; controlling the scan chain to process test data corresponding to the test instruction in response to each capture clock signal, obtaining response data, and determining a test result of the system on chip according to the response data and preset response data.

[0007] According to a third aspect of the embodiments of the present specification, a system on chip is provided, comprising at least one functional module, each functional module comprising at least one clock output module set and a clock control module corresponding to each clock output module set, and the system on chip comprises: a response module configured to construct a scan chain in response to a test instruction; a determination module configured to determine at least one target clock control module in each clock control module, wherein the target clock control module comprises delay selection information and at least one delay unit; a delay module configured to determine at least one target delay unit according to the delay selection information corresponding to each target clock control module, determine a delay link corresponding to each target clock control module, and generate a corresponding delay shift clock signal based on each delay link; a control module configured to control the scan chain to process test data corresponding to the test instruction in response to each delay shift clock signal.

[0008] According to a fourth aspect of the embodiments of the present specification, a system on chip is provided, comprising at least one functional module, each functional module comprising at least one integrated clock gating, comprising: a construction module configured to construct a scan chain and at least one capture clock control unit corresponding to the scan chain in response to a test instruction, wherein the capture clock control unit comprises a gating unit; The acquisition module is configured to acquire configuration information of at least one integrated clock gating, and determine the number of clock output switches according to the gating unit; The grouping module is configured to group the integrated clock gate according to the number of clock output switches and the configuration information of each integrated clock gate, obtain at least one integrated clock gate group, and each clock output switch corresponds to each integrated clock gate; The output module is configured to determine the integrated clock gate group outputting the capture clock signal according to the clock output switch, and output the capture clock signal. The control module is configured to control the scan chain to process the test data corresponding to the test instruction in response to each capture clock signal, obtain response data, and determine the test result of the system on chip according to the response data and preset response data.

[0009] According to a fifth aspect of an embodiment of the present specification, a data processing system is provided, which includes a processor core and a system on chip, and the system is executed by the host device to implement the steps of the above method.

[0010] According to a sixth aspect of an embodiment of the present specification, a computer readable storage medium is provided, which stores a computer program / instruction, and the computer program / instruction is executed by a processor to implement the steps of the above method.

[0011] According to a seventh aspect of an embodiment of the present specification, a computer program product is provided, which includes a computer program / instruction, and the computer program / instruction is executed by a processor to implement the steps of the above method.

[0012] One embodiment of the present specification implements a system on chip test method, constructs a scan chain in response to a test instruction, determines at least one target clock control module in each clock control module, wherein the target clock control module includes delay selection information and at least one delay unit, and through the target clock control module, the time of the clock output by each clock output module can be adjusted, so that the response time of the scan chain to the clock output module is more flexible. At least one target delay unit is determined according to the delay selection information corresponding to each target clock control module, a delay link corresponding to each target clock control module is determined, and a corresponding delay shift clock signal is generated based on each delay link. By determining the number of delay units in the delay link, the time of the clock output by each clock output module can be different, the simultaneous flip of the clock edge is avoided, the response time of the scan chain to the clock output module is further flexibly controlled, and the power consumption problem in the system on chip test process is solved. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is the overall structure diagram of the present system on chip in the scan test provided by one embodiment of the present specification; Figure 2 is a timing diagram of clock signals output by each clock output module of a system on chip during a scan test, according to an embodiment of the present specification; Figure 3 is a flowchart of a test method, according to an embodiment of the present specification; Figure 4 is a circuit structure diagram of a delay unit, according to an embodiment of the present specification; Figure 5 is a circuit structure diagram of a delay link, according to an embodiment of the present specification; Figure 6 is a whole circuit structure diagram of a scan test shift stage, according to an embodiment of the present specification; Figure 7 is a timing diagram of clock signals output by each clock output module of a system on chip after the clock output modules are delayed by a delay control module during a scan test, according to an embodiment of the present specification; Figure 8 is a flowchart of another test method, according to an embodiment of the present specification; Figure 9 is a circuit structure diagram of a capture clock control unit corresponding to a clock output module, according to an embodiment of the present specification; Figure 10 is a diagram of a capture clock signal output by a capture clock control unit, according to an embodiment of the present specification; Figure 11 is a test structure diagram of multiple capture clock control units in a test environment, according to an embodiment of the present specification; Figure 12 is a structure diagram of a system on chip, according to an embodiment of the present specification; Figure 13 is a structure diagram of a system on chip, according to an embodiment of the present specification.

[0014] Figures 1 to 13 Corresponding relationships of physical meanings of each circuit structure and port involved in the present specification are as follows: D: data input port, used for receiving an input signal; Q: data output port, used for outputting a signal stored in a register; SI: scan input port, used for receiving external shift input data; SE: scan enable signal receiving port, used for determining a scan test phase; CK: clock input port, used for receiving a scan clock signal to drive a flip-flop to flip; RST: reset signal input port, used to restore the initial state of the circuit; reg0~reg3: gated register, used to generate the gate control signal for ICG during scan test process; ICG0~ICG15: clock output switch, used to control the opening or closing of the corresponding ICG group; iCK: input terminal of ICG0~ICG15, used to receive the main clock signal; oCK: output terminal of ICG0~ICG15, output the gated clock signal; E: enable signal receiving terminal of clock output switch, used to control whether the clock output switch is enabled; TE: start-stop signal receiving terminal of clock output switch, used to start or stop the clock output switch.

[0015] Figures 1 to 13 The corresponding relationship between the signals in each circuit involved and their physical meanings is as follows: icg_te_on: signal to open all ICGs globally, so that all registers receive the capture clock signal; icg_te_off: signal to close all ICGs, masking the capture clock signal; icg_te_1 / 16_on: signal to make 1 / 16 of the ICG group in the OCC domain in the open state; icg_te_1 / 8_on: signal to make 1 / 8 of the ICG group in the open state; icg_te_1 / 4_on: signal to make 1 / 4 of the ICG group in the open state; icg_te_1 / 2_on: signal to make 1 / 2 of the ICG group in the open state; icg_te_[4:1]: output signal of each gate unit, which generates control signal for clock output switch by combination; icg_te_mux[15:0]: multiplexing control signal, which collects icg_te_[4:1] signals through multiplexing logic to control the start-stop state of each integrated clock gate group; icg_te_out[15:0]: control signal indicating the opening or closing state of 16 ICG groups; scan_in: scan input signal, used to input test data to the scan chain input port; scan_en: scan enable signal, used to control the working mode of the scan chain, high level for shift stage, low level for capture stage; scan_clk: scan clock signal, used to drive the register in the scan chain to flip data in the shift phase or capture phase; scan_reset: scan reset signal, used to initialize and reset the register in the scan chain before testing. DETAILED DESCRIPTION

[0016] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present description. However, the present description can be practiced without the specific details, other than those described in this specification, and it is understood that the scope of the present description is not limited to the details of the description.

[0017] The terminology used in this description of one or more embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of one or more embodiments of the present description. As used in this description of one or more embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0018] It will be understood that, although the terms first, second, etc. can be used herein to describe various information, these terms are not intended to denote a temporal or chronological order. Rather, these terms are used solely to distinguish one from another only. For example, without departing from the scope of one or more embodiments, first can be termed second, and similarly, second can be termed first. The term "if can be interpreted as meaning "when" or "upon" or "in response to determining," depending on the context.

[0019] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present description are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards in relevant regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0020] First, the terms involved in one or more embodiments of the present description are explained.

[0021] Design for testability: Design for testability (DFT) is an integrated circuit design technique. It is a method of implanting special structures in the design phase of the circuit to ensure that the electronic components are free of functional or manufacturing defects after testing. Circuit testing is not always easy, and many internal node signals of the circuit are difficult to control and observe externally.

[0022] Scan test: In the DFT system, scan test is the most basic and widely used one. By inserting scan chains in the design, a shift register is formed by connecting flip-flops in series to realize the loading and reading of test data, which is used to verify the correctness of the internal logic function of the system on a chip.

[0023] Scan chain: Scan chain is a shift register chain formed by connecting multiple flip-flops with scan function in series. It is used to move in or out test data in testing. It allows testers to control and observe the signal values of internal flip-flops from the outside by implanting shift registers.

[0024] Voltage drop: Voltage drop (IR drop) is the phenomenon of voltage deviation from the normal value in the power supply network of integrated circuits due to the resistance of interconnection lines. It is mainly caused by the voltage loss when current flows through metal wires, which may cause timing errors or test failures.

[0025] Test coverage: The proportion of potential faults that can be detected by the test process, used to measure the sufficiency of the test.

[0026] Test vector: The input signal sequence generated by the automatic test generation tool, used to stimulate the circuit and detect the correctness of the logic function.

[0027] On-chip clocking (OCC): A module used to control the output of the clock during DFT testing. Its main function is to generate shift clock and capture clock inside the system on a chip according to external test instructions, and distribute the corresponding clock to each clock domain to realize the synchronous control of scan chain registers. Each OCC corresponds to an independent clock domain, and in the capture phase, it is responsible for distributing the capture clock to each integrated clock gating unit in the clock domain.

[0028] Integrated clock gating unit (ICG): It controls the transmission of clock signals through an enable signal to reduce dynamic power consumption or realize time-sharing control of test clock.

[0029] With the continuous evolution of semiconductor technology and the rapid development of multi-scenario intelligent applications, higher requirements are put forward for the performance, energy efficiency and reliability of system on chip (SoC). To meet the needs of high parallel computing and low power control in multiple scenarios, the integration scale and architecture complexity of SoC are continuously increasing. Before SoC is put into application, DFT is usually used to improve the testability and reliability of SoC.

[0030] In the DFT system, the commonly used structured test method is scan test, which realizes the loading and reading of test data through the construction of scan chain structure to verify the logic function of SoC. To realize the distribution and control of test clock, on-chip clocking (OCC) and integrated clock gating unit (ICG) are usually set in SoC.

[0031] In the scan test process, there are usually two main stages: (1) Shift stage: the test control module sequentially shifts the test vectors into the scan chain registers through the clock signal, and outputs the response data in the shift-out stage. In this stage, the OCC output clock is usually driven by an external test clock source, and its rising edge and falling edge are completely aligned, which causes the scan chain registers in each clock domain to flip almost simultaneously. Although physical delay may cause slight misalignment, the misalignment time is very short, which still produces high dynamic power consumption.

[0032] (2) Capture stage: after the data loading is completed, the circuit captures the logic response results through single or small pulse clock. This stage requires the phase alignment of each clock domain to ensure test accuracy. Tools generally automatically phase misalign different OCC outputs, so that the overall power consumption in the capture stage is lower than that in the shift stage, but a large number of registers in a single OCC domain may still flip simultaneously, causing IR drop and other problems.

[0033] To solve the above problems, there are currently a variety of scan power optimization schemes: In the Shift stage, common methods include: (1) test vector splitting, which can reduce power consumption by reducing the coverage range of a single test vector, but significantly increases test time; (2) reducing test frequency, which can reduce power consumption, but increases test time; (3) reducing flip rate, which can reduce power consumption, but the flip rate has a lower limit, and increases test time.

[0034] In the Capture phase, common methods include: (1) All clock gating is closed at the beginning of test vector generation, and the gating is reopened to continue generating test vectors after the number of generated test vectors and the coverage are stable. This method needs to generate test vectors twice, the process is cumbersome and the overall efficiency is low; (2) All clock gating is opened at the beginning of the test to generate main test vectors, and then the gating is closed to generate supplementary test vectors to cover the logic paths when the gating is closed. This method has high power consumption in the initial stage, which can easily cause peak power consumption and power supply voltage drop problems; (3) Randomly control the on-off state of each clock gating during test vector generation, so that the generated test vectors can cover both the gating on and off cases. This method has strong randomness, unstable optimization effect, and may still have a problem of instantaneous high power consumption.

[0035] Referring to Figure 1 , Figure 1 The overall structure diagram of the current system on chip in scan testing is shown. The top layer of the system on chip includes a plurality of functional modules. Taking one of the functional modules as an example, at least one clock output module and its corresponding scan chain are arranged in the functional module.

[0036] The clock output module is used to output a clock signal in the scan testing process to drive the scan registers inside the scan chain, so as to realize the loading and reading of test data. A plurality of clock output modules can constitute a clock output module set for unified control and distribution under multiple clock domains.

[0037] The scan chain is composed of a plurality of flip-flops with scanning function. In the scan testing process, the test clock signal output by the clock output module drives the scan chain, so that each flip-flop sequentially shifts in the test data and outputs the response data in the capture phase. By comparing the response data with the preset response data, the logic correctness of the functional module can be verified.

[0038] Referring to Figure 2 , Figure 2A timing diagram of the clock signals output by the clock output modules of a current SoC during a scan test is shown. The diagram shows the clock output waveforms of the clock output modules 2020, 2022, and 2024 during a scan test. The entire test process includes three stages: a power-on preparation stage 202, a shift stage 204 (Shift), and a capture stage 206 (Capture). In the power-on preparation stage 202, each clock output module is in an initial standby state, and the output port is maintained at a low level or a static state. In the shift stage 204, the shift clock signals output by each OCC module are all driven by an external test clock source, and the rising and falling edges are completely aligned. Due to the synchronous flipping of the OCC output clocks of multiple clock domains, the scan chain registers under each clock domain are almost switched at the same time, resulting in high instantaneous dynamic power consumption of the SoC during this stage. Although there is a slight physical delay between different OCCs, the overall phase difference is very small and cannot effectively disperse the current peak at the moment of flipping. In the capture stage 206, the capture clock signals output by the OCCs are usually automatically staggered by the test control tool to ensure the test synchronization between the clock domains. The number of clock pulses in this stage is small (usually a single or small number of pulses), and the overall power consumption is significantly lower than that in the shift stage.

[0039] In summary, the existing solutions can usually only optimize one of the test power consumption, IR drop, test time, or coverage, and it is difficult to meet multiple requirements. Therefore, for a large-scale and complex SoC, how to effectively reduce the Scan test power consumption while ensuring the test coverage and test time is still a technical problem to be solved in the field.

[0040] Based on this, in the present specification, a test method is provided, and the present specification also relates to a SoC, a computing device, a computer readable storage medium, and a computer program product, which are described in detail one by one in the following embodiments. Referring to Figure 3 , Figure 3 A flowchart of a test method provided by an embodiment of the present specification is shown, which is applied to a SoC including at least one functional module, each functional module including at least one clock output module set and a clock control module corresponding to each clock output module set, and the method specifically includes the following steps.

[0041] Step 302: In response to a test instruction, a scan chain is constructed.

[0042] The system on chip can be understood as an integrated circuit system integrated with multiple functional modules, each functional module is usually implemented in the form of a physical block, and the functional module can be understood as a logical unit that separately divides a processor, a storage module, etc. into independent regions for layout and wiring in the back-end implementation stage of the system on chip, for simplifying the implementation process of the system on chip, and each functional module can include a processing unit, a storage unit, a clock management unit, or an input / output interface unit, etc.

[0043] Based on this, in the specific embodiments provided in the specification, the test instruction can be understood as an instruction for controlling the system on chip to enter a scan test state, for triggering a test control module in the system on chip, and starting a test process, and the test instruction can be issued by an external test device (such as an automated test equipment and a JTAG controller, etc.). The scan chain can be understood as a shift register chain formed by a plurality of flip-flops with scanning function, for sequentially shifting in or out test data in the test process. By implanting the scan chain, the tester can control and observe the signal value of the internal flip-flop of the circuit from the outside.

[0044] In the DFT of the system on chip, the scan test enables the test device to control and observe the logic state of the internal flip-flop from the outside by inserting the scan chain structure in the circuit, so as to verify the internal logic function. When the test control module in the system on chip receives the test instruction, the scan chain construction logic is activated, and each scannable flip-flop is cascaded to form a complete shift path according to the preset connection relationship. Through the scan chain, test data can be sequentially shifted in and output results can be collected in the subsequent steps, to realize controllable testing of the logic nodes of the system on chip.

[0045] In a specific embodiment provided in the specification, the system on chip receives the test instruction sent by the external test device, determines the register set that needs to participate in scanning according to the test configuration file or the preset test mode, connects the flip-flops in the register set according to the logical order, forms one or more scan chains, sets a test data input end at the head of the scan chain, and sets a test data output end at the tail, to realize the shifting in and out of the test data, and after confirming the connectivity and clock control relationship of the scan chain, enters the shift stage preparation state.

[0046] For example, in a system on chip including four functional modules, a plurality of scannable flip-flops are arranged in each module. When the system on chip receives the test instruction, a local scan chain is constructed in each module, and the local scan chains are connected end to end according to the logical relationship between the modules to form a complete global scan chain. The test device can input a test vector through the head of the scan chain, and read the response data at the tail, to realize the functional verification of the entire system on chip.

[0047] By constructing the scan chain in response to the test instruction, the automatic generation and activation of the internal test path of the system on chip can be realized, so that the test equipment can accurately control and observe the internal logic unit from the outside. The basic path is provided for the subsequent shift phase and capture phase, so as to ensure that the test signal can be stably transmitted in the system.

[0048] In an embodiment provided in the specification, the test instruction includes mode control information and scan structure information. In response to the test instruction, the scan chain is constructed, including: receiving the test instruction; parsing the test instruction to obtain mode control information and scan structure information; entering the test mode according to the mode control information, and determining the topology structure and input and output ports of the scan chain according to the scan structure information; constructing the scan chain according to the topology structure and input and output ports of the scan chain.

[0049] Based on this, in an embodiment provided in the specification, the test instruction includes mode control information and scan structure information. The mode control information can be understood as information for indicating the system on chip to enter the test state, which is carried by the test instruction and triggered to control the system on chip to enter the shift mode, the capture mode or other preset test modes.

[0050] The scan structure information can be understood as information recording specific test parameters, which is used to describe the structure configuration of the scan chain. The scan structure information can include but is not limited to the number of scan chains, the clock grouping mode, the test clock frequency and the gating state, etc. The scan structure information can be obtained from the test configuration file, which can be stored in the external test equipment or the internal register of the system on chip, and can be triggered and loaded by the test instruction. The topology structure of the scan chain can be understood as the connection relationship and order between the scan flip-flops in the scan chain, including the number of scan chains, the starting position and the termination position of each scan chain, the serial order between the flip-flops, and the distribution mode of each scan chain in different clock domains. The input and output ports of the scan chain can be understood as the interface ports for realizing the loading and reading of the test data.

[0051] In the DFT of the system on chip, the test coverage is one of the indexes for measuring the effect of scan test, and is an important index for measuring the effectiveness of the manufacturing test of the system on chip. The influencing factors of the test coverage mainly include the scan chain insertion ratio and topology structure in the structure level, the test vector generation quality and fault model selection in the algorithm level, and the clock control and test execution condition in the system level. After designing a reasonable testability structure and cooperating with a high-quality test vector generation strategy, the test coverage and fault detection capability of the system on chip can be significantly improved.

[0052] The scan chain is one of the factors affecting the test coverage of the system on chip. The scan chain topology structure can ensure the propagation of the test signal between different clock domains, avoid the logic nodes that are not excited or observed, and improve the test coverage and fault detection capability. Meanwhile, by optimizing the number, distribution and input / output port configuration of the scan chain, the test power consumption and time can be considered on the premise of ensuring the coverage, and the overall test efficiency and reliability can be improved.

[0053] In a specific embodiment provided in the specification, a test instruction is received from an external test device. After receiving the test instruction, the system on chip parses the test instruction to obtain mode control information and scan structure information. According to the mode control information, the system on chip enters a test mode. According to the scan structure information, the topology structure and input / output port of the scan chain of the system on chip are determined. According to the topology structure and input / output port of the scan chain, the scan chain is constructed.

[0054] For example, in a system on chip including four functional modules, the four functional modules correspond to four clock output modules OCC_1~OCC_4 respectively, and a plurality of scan flip-flops are arranged in each functional module. After the external test device sends a test instruction, the test control module in the system on chip can parse the mode control information and scan structure information included in the test instruction to determine to construct four scan chains. According to the clock domain to which each OCC belongs, the system on chip connects the scan flip-flops in each functional module in series to construct a local scan chain, and determines the connection order between the local scan chains according to the scan structure information, so as to connect the output port of OCC_1 and the input port of OCC_2 to form a global scan chain.

[0055] By constructing the scan chain, the sequential transmission of the test data between the scan flip-flops is realized, so as to realize the logic function verification and fault detection. Through the process, the test system can sequentially access the internal registers of the system on chip in the test mode, and realize the comprehensive test and verification of the logic function.

[0056] Step 304: determining at least one target clock control module in each clock control module, wherein the target clock control module includes delay selection information and at least one delay unit.

[0057] Each clock control module can be understood as a circuit structure for adjusting the clock signal output by the corresponding clock output module, and each clock control module corresponds to a clock output module. The target clock control module can be understood as a circuit structure that needs to adjust the delay of the clock output by the corresponding clock output module. By adjusting the delay of the target clock control module, the phase of different clock domains can be offset during the test process, so as to reduce the simultaneous flip rate of the shift stage and optimize the test power consumption.

[0058] The delay selection information can be understood as information for determining the delay duration of the target clock control module, which can be issued by a test data register (TDR). The test data register is a component for storing test instructions and test data, which is composed of multiple shift registers and supports serial input and output of data. After receiving the test data, the test data register loads the delay selection information into the target clock control module to control the working state of the internal delay unit.

[0059] The delay unit can be understood as a programmable delay unit for introducing a controllable delay amount on the clock signal path to realize phase adjustment of the test clock.

[0060] Referring to Figure 4 , Figure 4 A circuit structure schematic diagram of a delay unit provided by one embodiment of the present specification is shown. The delay unit includes a data input port and a data output port for inputting and outputting clock signals, respectively; a control signal port for setting the delay gear of the delay unit, and the delay gear of each delay unit can be fixed as a constant value; a power input port and a ground port for power supply and ground signals. By taking the value of the control signal input through the control signal port, the delay amount of the clock signal can be controlled.

[0061] Since the system on chip usually includes multiple clock output modules and corresponding clock control modules, the number of registers, switching frequency and dynamic power consumption of the clock domains of different modules are quite different. Therefore, not all clock control modules need to be adjusted in the test stage. Therefore, it is necessary to select the target control module for subsequent clock phase adjustment.

[0062] In the specific embodiment provided in the present specification, by selecting part of the clock control modules that need to adjust the clock phase as target clock control modules in the plurality of clock control modules, and by delaying the output clock of the target clock control module, the overall power consumption of the system on chip in the scan test process can be maintained below the preset threshold. It can be understood that the specific embodiment of the present specification does not require all clock control modules to simultaneously perform delay adjustment, but achieves system-level power consumption constraint through selective adjustment, thereby effectively reducing the peak power consumption of the shift stage without affecting the test coverage and test time.

[0063] For example, in a system on chip including four functional modules, the four functional modules correspond to four clock output modules OCC_1-OCC_4 and clock control modules CTRL_1-CTRL_4 corresponding thereto, respectively. Each clock control module is used to adjust the test clock signal output by the corresponding clock output module. During the test process, the test control module can select part of the clock control modules as target clock control modules according to the preset delay configuration scheme, for example, select CTRL_1 and CTRL_3 as target modules, and load delay selection information into them.

[0064] After receiving the delay selection information, CTRL_1 and CTRL_3 set the time delay gear of the internal delay unit according to the information, so that the clock signals output by OCC_1 and OCC_3 are phase-shifted relative to other modules. In this way, the registers under different clock domains can be flipped in time during the shift stage of the scan test, thereby reducing the instantaneous power consumption peak and ensuring the test synchronization and timing stability of each module.

[0065] The determination of the target clock control module can be based on the power consumption estimation result or the register flip rate statistical information. The test control module can dynamically select the clock control module with larger power consumption contribution and apply delay control, thereby realizing targeted power optimization and flexible clock phase management. By selecting and determining at least one target clock control module from a plurality of clock control modules, the module that needs to adjust the clock can be flexibly determined, and on-demand delay and system-level low-power test control can be realized.

[0066] In the specific embodiment provided in the present specification, determining at least one target clock control module in each clock control module includes: obtaining the predicted power consumption of each functional module of the system on chip in the test process, and calculating the overall predicted power consumption according to each predicted power consumption; In the case where the overall predicted power consumption is greater than the preset power consumption threshold, sorting each predicted power consumption to obtain a sorting result; According to the sorting result, a clock control module corresponding to a functional module satisfying a preset power consumption condition is determined as a target clock control module.

[0067] The predicted power consumption can be understood as a theoretical power consumption value of each functional module in the scan test process, and can be obtained through various quantifiable test-related parameters, including test simulation analysis, register flip rate statistics, historical test data, or on-chip power consumption monitoring results, and the like, and is used to reflect the dynamic power consumption level of each functional module in the test phase. The total predicted power consumption can be understood as a total power consumption prediction result of the system on chip under the current test configuration, which is a weighted sum or statistical accumulation of the predicted power consumption of each functional module, and is used to evaluate whether the power consumption of the entire system exceeds a preset threshold. The sorting result can be understood as the sorting information of each functional module according to the size of the predicted power consumption of each functional module, and is used to represent the order of the modules to be adjusted in the power consumption optimization process.

[0068] By evaluating the predicted power consumption of each functional module of the system on chip in the test process, the test power consumption can be estimated in advance. When the total predicted power consumption exceeds the preset threshold, the system selects the clock control module corresponding to the module with higher power consumption as the target clock control module according to the sorting result of the power consumption of each module, and adjusts the delay of the clock output by the target clock control module.

[0069] In a specific embodiment provided in the present specification, first, the predicted power consumption values of each functional module are obtained through quantifiable tests, and then the total power consumption prediction result of the system on chip is obtained by summation. In the case where the total power consumption prediction result exceeds the preset threshold, the predicted power consumptions of each functional module are sorted to obtain the sorting result. The clock control module corresponding to the functional module with higher predicted power consumption is selected as the target clock control module from the sorting result, and the target clock control module is controlled subsequently.

[0070] For example, for a system on chip including four functional modules, the four functional modules correspond to four clock output modules OCC_1 to OCC_4 and clock control modules CTRL_1 to CTRL_4 corresponding thereto. Before testing, the test control module can calculate the predicted power consumption of each functional module based on simulation analysis or historical test data, and compare the result with the preset power consumption threshold. Assuming that among the four functional modules, the total predicted power consumption of the system exceeds the preset threshold and the predicted power consumptions of module 1 and module 3 are higher, the test control module determines the clock control modules CTRL_1 and CTRL_3 corresponding thereto as the target clock control modules according to the power consumption sorting result.

[0071] The prediction power consumption sorting of each clock control module determines at least one target clock control module, realizes a dynamic screening mechanism based on a power consumption threshold, and enables the system to clearly determine the operation object for subsequent more targeted and flexible reduction of test peak power consumption without affecting the test coverage and test time, thereby improving the energy efficiency and stability of scan testing.

[0072] Step 306: determining at least one target delay unit according to the delay selection information corresponding to each target clock control module, determining the delay link corresponding to each target clock control module, and generating the corresponding delay shift clock signal based on each delay link.

[0073] The target delay unit can be understood as a basic unit for determining the delay duration of the target clock control module, and is the basic structure of the delay link. The delay performance (such as the delay duration) of each delay unit can be determined by the production process parameters and device model. The delay link can be understood as a signal transmission path formed by sequentially connecting a plurality of delay units. By increasing or decreasing the number of delay units in the delay link, the adjustment of the delay amount of the output clock signal of the target clock control module can be realized. The delay shift clock signal can be understood as a clock signal generated by adjusting the delay of the original shift clock signal, and the delay duration can be determined according to the delay selection information in the delay link.

[0074] Referring to Figure 5 , Figure 5 The circuit structure schematic diagram of the delay link provided by one embodiment of the present specification is shown, the delay link includes a delay unit set composed of delay units, receives the shift clock signal and the delay selection information sent by the test data register, and outputs the delay shift clock signal. The delay selection information sent by the test data register is used to determine the number of delay units through which the shift clock signal passes, thereby realizing delay of different gears.

[0075] In scan testing, each shift clock signal will flip, and since the clock source of each shift clock signal comes from the source clock of the system on chip, the rising edge and the falling edge of each shift clock signal are completely aligned with each other, which causes the scan registers under different clock domains to flip at almost the same time, thereby causing high instantaneous power consumption. Therefore, by setting the delay link in each target clock control module, the shift clock signal is controlled to have different delay durations, and the number of series-connected delay units in the delay link is adjusted to realize programmable setting of the delay amount. Therefore, the register flip time under different clock domains can be staggered, the number of registers that flip at the same time can be reduced, and the peak power consumption in the shift stage can be effectively reduced.

[0076] In an embodiment provided in the specification, at least one target delay unit is determined according to delay selection information corresponding to each target clock control module. The delay selection information can be sent by a TDR, which can dynamically control the delay parameters of the delay link corresponding to each target clock control module and generate a corresponding delay shift clock signal based on the delay link.

[0077] Referring to Figure 6 , Figure 6 An overall circuit structure schematic diagram of a scan test shift phase provided in an embodiment of the specification is shown. A plurality of functional modules are included in the top layer of the system on chip. Taking one of the functional modules as an example, a source clock sends a shift clock signal, a test register 1 determines whether the shift clock signal is delayed, and in the case of delay, the shift clock signal passes through a delay link, a test register 2 sends delay selection information for determining the delay duration of the shift clock signal passing through the delay link, a clock output module outputs a corresponding delay shift clock signal according to the delay duration, and a scan chain receives the delay shift clock signal. The scan chain is composed of a plurality of flip-flops with scan function connected in series.

[0078] Taking CTRL_1 as an example for further description in the above example. CTRL_1 includes a configurable delay link, which is composed of a plurality of delay units connected in series. A test data register TDR can configure the number of delay units of the delay link in CTRL_1 according to the current test requirement and output corresponding delay selection information. According to the number of delay units configured by the TDR, CTRL_1 adjusts the total delay duration of its delay link, so that a specific delay amount is generated when the corresponding clock output module OCC_1 outputs the shift clock signal.

[0079] By configuring the number of delay units in the delay link through the TDR, different delay duration controls can be flexibly realized, so as to output corresponding delay shift clock signals. The number of delay units can be flexibly set according to actual test requirements to realize different delay control schemes. The structure makes the delay control of each clock module have high programmability and flexibility, which can be dynamically adjusted according to the test phase, the power threshold or the test scene, so as to further improve the energy efficiency and timing controllability of the scan test.

[0080] In an embodiment provided in the specification, at least one target delay unit is determined according to delay selection information corresponding to each target clock control module, the delay link corresponding to each target clock control module is determined, and a corresponding delay shift clock signal is generated based on each delay link, including: determining the delay duration of each target clock control module according to the delay selection information; acquire a unit delay duration of the target delay unit, and determine a target delay unit quantity corresponding to each target clock control module according to the delay duration of each target clock control module and the unit delay duration; construct a delay link according to the target delay unit quantity corresponding to each target clock control module, and generate a corresponding delay shift clock signal based on each delay link.

[0081] The delay duration of each target clock control module can be understood as the amount of time delay that the target clock control module needs to apply to its output clock signal to achieve timing misalignment between different clock domains. The delay duration can be dynamically configured by the TDR according to the test mode or test phase. The unit delay duration of the target delay unit can be understood as the fixed delay time that a single delay unit can provide under certain process conditions, which is the basic measurement unit of the delay link. The unit delay duration can be determined by simulation modeling or process testing during the circuit design phase, and is usually 10ps-100ps. The target delay unit quantity can be understood as the number of delay units that need to be connected in series when constructing the delay link, and its value can be determined according to the ratio of the delay duration to the unit delay duration.

[0082] In the process of constructing the delay link, the test control module can dynamically select a corresponding number of delay units according to the delay duration of each target clock control module and establish a delay link, and then output a corresponding delay shift clock signal through the delay link. The clock signal is used to drive the corresponding scan chain register, thereby forming timing misalignment between different clock domains, reducing the number of simultaneously flipped registers, and reducing the peak power consumption in the shift phase.

[0083] In a specific embodiment provided in the present specification, the delay duration of the target clock control module is determined according to the delay selection information issued by the TDR; the unit delay duration of the target delay unit is acquired, and the target delay unit quantity corresponding to each target clock control module is determined according to the ratio of the delay duration of each target clock control module to the unit delay duration; and a delay link is constructed according to the target delay unit quantity corresponding to each target clock control module, and a corresponding delay shift clock signal is generated based on each delay link.

[0084] In the above example, the TDR issues delay selection information to determine that the delay duration of CTRL_1 is 20ps, and the unit delay duration of the delay unit is 10ps. Then, the ratio of the delay duration of CTRL_1 to the unit delay duration of the delay unit is taken to obtain the target delay unit quantity, which is 2. Then, it is determined that a delay link is constructed by two delay units, and a delay shift clock signal with a delay of 20ps is generated based on the delay link.

[0085] By the embodiment, programmable generation of the delay-shift clock signal can be realized while maintaining test accuracy and test coverage, reducing test power consumption, and improving power controllability and timing flexibility of the test.

[0086] In a specific embodiment provided in the specification, the delay selection information includes a period parameter of the shift clock. Determining the delay duration of each target clock control module according to the delay selection information includes: Determining a delay threshold according to the period parameter of the shift clock. According to the delay threshold, the delay duration of each target clock control module is determined, wherein each delay duration is less than the delay threshold.

[0087] The period parameter of the shift clock can be understood as the period information of the test clock in the scan test shift phase, which reflects the length of time between clock pulses. This parameter can be carried by an external test device when issuing a test instruction, or can be read and loaded from a test configuration file by an on-chip test control module in the test initialization phase, which is a preset clock parameter. The delay threshold can be understood as the maximum delay duration allowed under the premise that no timing violation occurs in the clock output module.

[0088] In scan testing, the shift phase is driven by the slow clock of the system-on-chip to load test data into each scan chain register in turn. To reduce the instantaneous power consumption in the shift phase, the embodiment introduces a phase offset to the shift clock signals of different clock domains through the delay link, thereby reducing the number of registers that flip at the same time.

[0089] However, when the total delay duration configured by the delay link is too large, it may cause some registers to not complete data setup or hold within the valid sampling window, thereby causing timing violations or logic competition phenomena. To avoid the above problems, it is necessary to control the delay amount while ensuring the offset effect, so that the delay range is within the safe timing margin, ensuring timing safety.

[0090] The factors affecting timing safety can include: (1) setup time: the time during which the input data needs to be stable before the clock edge arrives; (2) hold time: the time during which the input data needs to be stable after the clock edge arrives. If the phase offset between the clock signals of adjacent clock domains is too large, it may cause the data of some registers to not be established or to be held too early, thereby causing timing violations.

[0091] In practical applications, in order to maintain sufficient sampling margin between clock domains and achieve the power optimization effect caused by clock staggering, the clock phase offset is usually controlled within 1 / 4 of the clock period. When the total delay time generated by the delay chain exceeds 1 / 4 of the shift clock period, the register may not complete data setup or hold within the valid sampling window, thereby causing data race or sampling error. Therefore, the delay threshold is set to 1 / 4 of the shift clock period in the embodiment to ensure that the delay is controlled within the safe timing range, while taking into account power optimization and timing stability.

[0092] Therefore, in scan testing, the maximum delay time of the delay chain configuration is usually less than 1 / 4 of the shift clock period to ensure that the phase difference between the output clock signals of each clock domain is within a safe range, thereby avoiding cross-clock-domain sampling errors and timing violation risks. Based on this, in a specific embodiment provided by the present specification, the delay threshold is determined according to the period parameter of the shift clock, and the delay time of each target clock control module is constrained to be less than the delay threshold, achieving a balance between power optimization and timing stability.

[0093] In a specific embodiment provided by the present specification, the delay threshold is determined according to the period parameter of the shift clock, and the delay threshold is a value less than 1 / 4 of the shift clock period; and the delay time of each target clock control module is determined according to the delay threshold, so that each delay time is less than the delay threshold, thereby ensuring that the test process does not occur timing violation while adjusting the delay.

[0094] Continuing with the above example, if the period parameter of the shift clock is 20 ns, the delay threshold is 5 ns, that is, the delay time of each target clock control module needs to be less than 5 ns. Therefore, the delay time of CTRL_1 is 20 ps, which is much less than the delay threshold 5 ns, so that safe delay can be achieved under the condition of ensuring timing stability.

[0095] Through the embodiment, while adjusting the delay of the shift clock signal, timing violation can be effectively avoided, thereby achieving safe and reliable low-power test control under the premise of ensuring test accuracy and stability.

[0096] Step 308: Control the scan chain to process test data corresponding to the test instruction in response to each delay shift clock signal.

[0097] The test data can be understood as a test vector used to drive the logic of the circuit and verify the correctness of the function in the scan test process. The test vector can be generated by an external automatic test equipment (ATE) or an automatic test pattern generation (ATPG) tool, and is used to cover each logic node in the circuit under test. The generation of the test vector is usually based on the design netlist and the fault model to ensure that the test coverage reaches the predetermined requirement.

[0098] In the scan test, the test data is sequentially moved into each register node through the scan chain, so that the circuit runs in a controlled input state, and the response data is output in the moving-out stage to determine whether the logic function is correct. The test control module drives each scan chain using the aforementioned delay shift clock signal to achieve the ordered loading and moving-out of the test data.

[0099] In one specific embodiment provided in the specification, the test control module controls the scan chain registers to sequentially load the test data according to the delay shift clock signals, and moves out the response data to the test interface after the loading is completed, for the external test equipment to perform result comparison and fault analysis. This process realizes the complete transmission of the test data and the acquisition of the response, and provides a stable initial state for the subsequent capture stage.

[0100] In the above example, the OCC_1 outputs the delay shift clock signal adjusted through the delay link, and the scan chain sequentially moves in the test vector under the corresponding clock signal. The test vector generated by the external test equipment is V_1, and the test control module moves V_1 into the corresponding scan chain according to the phase difference of each delay shift clock signal. Since there is a 20ps phase offset in the shift clock signal, the registers in different clock domains will not flip at the same time, thereby effectively suppressing the instantaneous current peak value.

[0101] Through the above embodiment, the clock phase offset based on the delay link is introduced in the process of controlling the shift of the scan chain, so that the scan registers in different clock domains are time-shared to flip, which significantly reduces the instantaneous peak power consumption in the shift stage. At the same time, through the programmable configuration of the delay selection information, flexible delay adjustment of the shift clock is realized, which has higher power controllability and timing stability on the premise of ensuring test accuracy and test coverage, thereby effectively improving the energy efficiency and reliability of the scan test of the system on chip.

[0102] In one specific embodiment provided in the specification, the control of the scan chain to process the test data corresponding to the test instruction in response to each delay shift clock signal includes: loading the test data into the scan chain using the delay shift clock signal; The scan chains perform data test processing on the test data.

[0103] The test data can be understood as a test vector used to drive the logic of the circuit and verify the correctness of the function in the scan test phase. The test data is usually generated by ATE or ATPG to cover the paths of the logic unit under test.

[0104] Referring to Figure 7 , Figure 7 The timing diagram of the clock signals output by the clock output modules after the delay control module delays the clock output modules in the scan test process of the system on chip provided by an embodiment of the present specification is shown.

[0105] As Figure 7 shown, the figure shows the clock output waveforms of the clock output modules 7020, 7022 and 7024 in the scan test process. The entire test process includes three phases: power-on preparation phase 702, shift phase 704 and capture phase 706.

[0106] In the power-on preparation phase 702, each clock output module is in an initial standby state, and the output port maintains a low level or a static state. In the shift phase 704, the shift clock signals output by the clock output modules 7020, 7022 and 7024 are delayed through different delay links, and at this time the rising edges and falling edges of each shift clock signal are not completely aligned. The synchronous flip-flop of the clock output by multiple clock output modules is avoided, thereby avoiding the generation of high instantaneous dynamic power consumption of the system on chip in this phase. There is a certain phase difference between the clock output modules 7020, 7022 and 7024. The delay effectively disperses the current peak value at the moment of flip-flop. In the capture phase 706, the clock output modules 7020, 7022 and 7024 output capture clock signals.

[0107] In the shift phase of the scan test, the test control module drives each scan chain register through the delayed shift clock signal, so that the test data is loaded into the flip-flop nodes inside the circuit in the intended order. Subsequently, according to the running of the loaded test data, the corresponding response data is output for verifying whether the internal logic meets the expected design function. Since the shift clock signal used in the present embodiment is phase-shifted through the delay link, the scan chain registers of different clock domains are flipped at different times, thereby significantly reducing the instantaneous power consumption while ensuring the accuracy of the test.

[0108] In a specific embodiment provided by the present specification, the test control module receives the delayed shift clock signal, and according to the trigger order of the delayed shift clock signal, the external test data is sequentially loaded into each scan chain register, and the scan chain is controlled to process the test data after the shift is completed.

[0109] For example, in a system-on-chip containing four scan chains, OCC_1 and OCC_3 output the delay-shifted clock signals adjusted by the delay links respectively. The test control module drives the corresponding scan chains to load test data V_1 and V_3 according to the phase difference of the clock signals.

[0110] By introducing the clock phase control mechanism based on the delay link in the process of loading and processing test data, the power consumption of the shift stage is effectively suppressed. This scheme can realize flexible and programmable low-power test control while ensuring test accuracy and timing stability, further improving the test energy efficiency and reliability of the system-on-chip.

[0111] In a specific embodiment provided in the specification, it also includes: Obtaining the capture clock signals output by the clock output module set; Controlling the scan chains to process the test data corresponding to the test instructions in response to the capture clock signals to obtain response data; Determining the test result of the system-on-chip by judging whether the response data is consistent with the preset response data.

[0112] The response data can be understood as the test result output by the scan chain in the capture stage, which is used to reflect the actual logic response of the circuit under test conditions. The preset response data can be understood as the expected output result obtained in advance according to the circuit design logic, which is used as the benchmark for test comparison. The test result is used to characterize whether the circuit logic is correct. When the response data is consistent with the preset response data, it means that the logic structure of the circuit under test is consistent with the design expectation. When they are inconsistent, it means that the circuit has functional abnormalities or logic faults.

[0113] By comparing the response data output by the scan chain in the capture stage with the preset response data, it is determined whether the actual logic behavior of the circuit is consistent with the design logic, thereby realizing the verification of the functional correctness of the system-on-chip. This process belongs to the standard test verification stage in scan testing.

[0114] In a specific embodiment provided in the specification, the test control module receives and distributes the capture clock signals, the scan chains output the response data under the driving of the capture clock, and the test equipment or the test control module compares the response data with the preset response data. If they are consistent, it is determined that the system-on-chip is functionally correct. If they are inconsistent, it is determined that there is a logic error or a timing fault.

[0115] For example, during the test process, the test vector loaded by the external test equipment is [1, 0, 1, 1], and the preset response data expected by the circuit design logic is [0, 1, 0, 0]. When the response data output by the scan chain in the capture stage is completely consistent with the preset response data, it indicates that the circuit logic function is correct; if the output is [0, 0, 0, 0] or there is any bit inconsistency, it indicates that there is a logic abnormality or timing problem on the path.

[0116] In addition, it should be noted that, since the delay link is arranged at the slow clock input end of the OCC, the clock signal in the capture stage will also be affected by the delay except in the shift stage. In order to ensure the timing requirements of the capture stage, when generating the test vector, the setup time and the hold time of the scan enable signal before and after the capture clock can be appropriately extended to ensure that the signal sampling is stable and the timing is correct.

[0117] In addition, the introduction of the delay link will cause the clock path length of the Shift and Capture paths to be not completely consistent, which brings certain challenges to the backend timing convergence. The following two methods are usually used to solve this problem: (1) During the timing convergence stage, the delay link path is not considered for the time being, and the clock main path timing is ensured to be converged first, and then the delay link is enabled, and the delay position without timing violation is recorded as the scan test vector configuration reference; (2) During the timing convergence stage, some positions of the delay link are enabled, and the backend engineering is targeted to converge, so as to balance the power consumption optimization effect of the delay link and the timing constraints.

[0118] Through the above method, the safe use of the delay link in the capture stage can be realized without increasing the difficulty of the backend implementation, and the accuracy of the test result and the timing stability of the system as a whole are ensured.

[0119] By comparing the response data and the preset response data, the automatic verification of the logic function of the system on chip is realized, which belongs to the standard scan test verification process. At the same time, combined with the delay shift clock, the test reaches a balance between power consumption optimization and timing safety, which ensures the test accuracy and maintains the system stability.

[0120] Reference Figure 8 , Figure 8 A flowchart of another test method provided according to one embodiment of the present specification is shown, which is applied to a system on chip including at least one functional module, each functional module including at least one clock output module set and a capture clock control unit corresponding to each clock output module set, and the method specifically includes the following steps.

[0121] Step 802: in response to the test instruction, constructing a scan chain and at least one capture clock control unit corresponding to the scan chain, wherein the capture clock control unit comprises a gating unit; The capture clock control unit can be understood as a control module that controls whether the clock signal reaches the module under test in the capture phase. The capture clock control unit can control the capture clock signal, thereby determining whether the corresponding register in the scan chain receives the capture clock pulse. The gating unit can be understood as a circuit structure that controls the ICG, and is used to control the on-off state of the enable end of the ICG according to the preset logic or test signal, thereby controlling whether the clock pulse passes.

[0122] Referring to Figure 9 , Figure 9 The circuit structure of the capture clock control unit corresponding to the clock output module provided by one embodiment of the present specification is shown. The capture clock control unit comprises a gating unit and a timing remodeling unit. The test register controls the on-off state of the ICG enable end, thereby controlling whether the clock pulse passes. In the gating unit, reg0-reg3 are gating registers, which are used to generate the gating control signal for the ICG in the scan test process.

[0123] In the test register, icg te on indicates that all global ICGs are turned on, and all registers receive the capture clock signal. Icg te off indicates that all ICGs are turned off, and the capture clock signal is shielded. Icg te 1 / 16 on makes 1 / 16 of the ICG groups in the OCC domain in an open state. Icg te 1 / 8 on makes 1 / 8 of the ICG groups in an open state. Icg te 1 / 4 on makes 1 / 4 of the ICG groups in an open state. Icg te 1 / 2 on makes 1 / 2 of the ICG groups in an open state. These signals are finally summarized into the icg te mux[15:0] signal through the multiplexing logic, which is used to control the start-stop state of each ICG group. Icg te out[15:0] is the gating output control signal corresponding to the 16 ICG groups in the OCC domain. The signal is generated by the combination of the gating unit and the test register, and is used to determine whether the ICG unit allows the capture clock pulse to pass in the current test clock cycle.

[0124] In the scan test process, the test vector usually includes two stages of shift and capture. In the case of multiple OCCs, the capture stage is automatically processed by the tool to make the flip-flop clock of different OCCs staggered, but in a single OCC clock domain, the situation of all registers being triggered by the capture clock at the same time still occurs, resulting in instantaneous current peak and IR drop problems. Therefore, by introducing a capture clock control unit in the capture clock path corresponding to each OCC, some registers are not triggered at the capture time, thereby reducing the proportion of registers that flip at the same time, balancing the power consumption distribution and suppressing the IR drop risk while reducing the power consumption of the capture stage.

[0125] In the specific implementation provided in the specification, the system can identify the current scan test stage through the test control module. When it is detected that the shift stage ends and the capture stage starts, the capture clock control unit is automatically enabled, and each ICG gate signal is loaded and enabled, thereby realizing fine control of the capture clock.

[0126] For example, in a system on chip containing four OCCs, each OCC corresponds to a capture clock control unit. The system controls the gating state of different ICGs in the capture stage, so that the capture clock pulse of some OCCs is shielded, thereby reducing the number of registers triggered in a single cycle and reducing the instantaneous power consumption.

[0127] By constructing the capture clock control unit and introducing the gating control mechanism, the triggering proportion of each clock domain can be flexibly controlled in the capture stage, the instantaneous current peak in a single clock domain is reduced, and the IR drop phenomenon is effectively suppressed. This scheme can balance low power consumption and high stability in the test stage without changing the circuit logic function.

[0128] In a specific implementation provided in the specification, a capture clock control unit is constructed, wherein the capture clock control unit includes a gating unit, which includes: determining the number of gated registers; According to the number of gated registers, a corresponding number of gated registers are determined, and the gating unit is constructed according to the gated registers; According to the gating unit and the timing remodeling unit, a capture clock control unit is constructed.

[0129] The gating register is used to output a gating control signal, and the output logic value is used to generate a switch combination of the integrated clock gating unit. The number of gating registers can be determined according to design requirements or power consumption control strategies. The timing remodeling unit can be understood as a circuit structure for timing reorganization of the gating signal before capturing the clock signal input, and generally includes a negative edge triggered retiming register for optimizing the performance of a sequential circuit, such as shortening the clock period, reducing the number of registers, or reducing power consumption. It balances the combination logic path by moving the register forward or backward to meet the performance requirements.

[0130] In the capture phase of the scan test, if all registers in the same clock domain simultaneously receive the capture clock signal, it will cause large-scale flipping of the registers, resulting in instantaneous peak current and IR drop problems. To reduce this risk, the embodiment introduces a capture clock control unit in the capture clock path to gate control whether the capture clock signal arrives. The capture clock control unit is composed of a gating unit and a timing remodeling unit, wherein the gating unit outputs a gating control signal through a plurality of gating registers, which is used to control the opening or closing of the ICG, and the timing remodeling unit is used to optimize the performance of the circuit to ensure the stability of the gating signal.

[0131] In a specific embodiment provided in the present specification, the number of gating registers is determined, a gating unit is constructed based on the corresponding number of gating registers, and a capture clock control unit is further constructed according to the gating unit and the timing remodeling unit.

[0132] For example, if the number of gating registers is 4, 4 gating registers are selected to construct a gating unit, and then a capture clock control unit is constructed according to the gating unit and the timing remodeling unit, and the timing remodeling unit can be a retiming register.

[0133] By constructing the capture clock control unit, it can be flexibly determined whether each module receives the capture clock pulse in the capture phase, thereby realizing on-demand triggering and time-sharing capture, effectively suppressing the instantaneous power consumption rise caused by simultaneous flipping of the registers, and reducing the risk of instantaneous current peak and IR drop.

[0134] Step 804: Obtain configuration information of at least one integrated clock gating, and determine the number of clock output switches according to the gating unit; The configuration information can be understood as configuration information for constructing the capture clock control unit, which is used to describe the gating configuration mode of each ICG. The configuration information can be loaded by an external test control module, or can be predefined by a DFT configuration file in the design stage, and is used as a configuration basis for the gating of the capture clock control unit. The clock output switch can be understood as an ICG switch structure controlled by the gating register, which is used to control whether the corresponding clock signal is output.

[0135] By acquiring the configuration information of the integrated clock gating, the number and distribution of the ICGs in the system are determined, and in combination with the number of the gating registers in the gating unit, the number of the independently controllable clock output switches is calculated. This method can realize the mapping of the correspondence between the gating unit and the ICG, so that the clock control unit has multiple programmable gating combinations.

[0136] In an embodiment provided in the specification, the configuration information of the integrated clock gating is acquired, and the number of the clock output switches is determined according to the number of the gating registers in the gating unit.

[0137] In the above example, the gating unit includes 4 gating registers, and the number of the clock output switches is 16.

[0138] By determining the number of the clock output switches according to the gating unit, the number of the clock output switches can be automatically determined according to the configuration information of the integrated clock gating, and multiple gating control combination modes are supported, so that more flexible clock management and power consumption control are realized in the capture stage, and the flexibility of the configuration in the test stage is improved.

[0139] In an embodiment provided in the specification, the gating unit includes at least one gating register; Determining the number of the clock output switches according to the gating unit includes: According to the number of the registers of the gating registers, the number of the types of the output types of the gating unit is determined; According to the number of the types, the number of the clock output switches is determined.

[0140] The output type of the gating unit can be understood as a control type formed by the logical output state combination of the gating registers. Since each gating register can output logic "0" or "1", when the number of the gating registers is n, 2n different output types can be formed. By counting the number of these output types, the number of the independently controllable clock output switches of the system can be determined. n

[0141] In the capture stage, different gating register combinations correspond to different ICG switch states, and each output type can control the opening or closing of a group of clock output switches, so that the on-demand management of the multi-channel capture clock is realized. By increasing the number of the gating registers, the number of the output types of the gating unit can be expanded, so that the system can support more independent clock output paths and realize higher granularity clock control.

[0142] ​In the specific embodiment provided in the specification, the number of gated registers is first determined, the number of output types of the gating unit is calculated according to the number of gated registers, and the number of clock output switches required is determined according to the number of output types.

[0143] In the above example, when the gating unit contains 4 gated registers, each register can output logic "0" or "1", and 16 different output types can be formed. The system determines that 16 clock output switches need to be set according to the number of output types, and establishes the corresponding control mapping relationship to realize the control of the 16 ICG gating units.

[0144] By determining the number of output types according to the number of gated registers, and determining the number of clock output switches according to the number of output types, the capture clock control unit can flexibly adjust the number of control paths according to the test scale, improve the scalability and flexibility of gating control, and thus realize the fine management and power optimization of the clock output in the capture phase.

[0145] Step 806: Grouping each integrated clock gate according to the number of clock output switches and the configuration information of each integrated clock gate, obtaining at least one integrated clock gate group, each clock output switch corresponding to each integrated clock gate; The integrated clock gate group can be understood as a set of ICGs divided according to the clock domain to which each ICG belongs and its position in the physical layout, which is used to realize the grouping gating control in the capture phase. Each group corresponds to a group of clock output switches, which is driven by the control signal output by the gating unit, and is used to control the opening or closing state of the group of ICGs.

[0146] In the synthesis environment of the system on chip, the tool will automatically insert the ICG unit under different OCC clock domains to optimize the dynamic power consumption. After obtaining the ICG configuration information, the embodiment groups the ICGs. Through this grouping method, only about 1 / N of the ICGs in the corresponding group will be activated by the capture pulse each time, so that only about 1 / N of the registers will flip at the same time, which significantly reduces the instantaneous power consumption and IR drop risk.

[0147] In the specific embodiment provided in the specification, the system obtains the ICG configuration information under each OCC clock domain, and divides the ICGs into several groups according to the configuration information. Finally, the TE end of each group is connected with the corresponding clock output switch signal to form the ICG grouping control in the capture phase.

[0148] In the above example, the configuration information of each ICG in the system on chip is obtained, the ICGs are grouped according to the configuration information, and each group is connected with the corresponding clock output switch.

[0149] By grouping the ICs according to the configuration information of the ICGs, the embodiment can realize distributed gating in the capture phase, so that the registers in different clock domains and the same clock domain respond to the capture clock at different times. While reducing the peak power consumption and IR drop, the extreme cases of full closing or full opening are avoided, which not only shortens the test time, but also improves the test coverage and system stability.

[0150] In a specific embodiment provided in the specification, the configuration information of the integrated clock gate includes attribute information and location information. According to the number of clock output switches and the configuration information of each integrated clock gate, each integrated clock gate is grouped to obtain at least one integrated clock gate group, including: According to the attribute information of each integrated clock gate, each integrated clock gate is grouped to obtain at least one first clock group. According to the location information of each integrated clock gate and the number of clock output switches, the first clock group is grouped to obtain at least two second clock groups, wherein the number of second clock groups is consistent with the number of clock output switches.

[0151] The attribute information can be understood as information representing the clock domain (OCC) to which each ICG belongs, which is used to distinguish the logical attribution relationship of the ICG. The location information can be understood as the position coordinates or area information of the ICG in the physical layout of the system on chip, which is used to realize physical balance during grouping. The first clock group can be understood as a preliminary group formed after dividing according to the clock domain to which the ICG belongs. The second clock group can be understood as a sub-group further subdivided according to the physical location of the ICG on the basis of the first clock group, and each group corresponds to a clock output switch.

[0152] In the scan test of the system on chip, the capture phase is triggered by the capture clock signal output by the OCC to flip multiple registers at the same time, which is easy to cause local current surge and power consumption peak. Since the ICG is a key node for controlling the transmission of the capture clock pulse, the number and distribution of ICs under different OCCs are quite different, and if there is no reasonable grouping, it may lead to concentrated load in some areas and uneven power consumption. Therefore, first, according to the attribute information, the ICs under the same OCC domain are grouped into a group to ensure the independence of the logical clock domain; then, according to the location information, the ICs in each group are evenly distributed to several sub-groups in the physical space, so that the TE end of each sub-group corresponds to a different clock output switch.

[0153] In one specific embodiment provided in the present specification, the ICs are grouped according to the number of clock output switches and the ICG configuration information, including: grouping according to the attribute information of the ICs to obtain at least one first clock group. The first clock group is further divided according to the position information of the ICs and the number of clock output switches to obtain a plurality of second clock groups. The number of second clock groups is ensured to be consistent with the number of clock output switches to realize one-to-one mapping relationship between grouping and gated signal output.

[0154] In the above example, it is assumed that there are 4 OCC clock domains in the system on chip, and each OCC contains 64 ICs. First, according to the attribute information, the 4 OCCs are respectively formed into 4 first clock groups; then, according to the position information and the number of clock output switches of the system (such as 16), the 64 ICs in each first clock group are further divided and evenly distributed into 16 second clock groups. The TE port of each second clock group corresponds to 16 clock output switches one-to-one. When the gated register output signal flips, only one corresponding group is activated, so that only about 1 / 16 of the ICs are turned on at any time.

[0155] Through the double-layer ICG grouping method based on attribute information and position information, the clock consistency within the same OCC domain can be guaranteed at the logic level, the ICG distribution can be balanced at the physical level, the local register flip is avoided, the peak power consumption and IR drop risk in the capture stage are significantly reduced, the test coverage and stable timing performance are maintained, and the low power consumption and high reliability are balanced.

[0156] In addition, for a system on chip with a multi-OCC architecture, an independent ICG control unit can be configured for each OCC, and the scan units in each ICG control unit are connected in series to form an independent test chain, so that the consistency of power consumption control and test coverage is maintained, and the vector generation efficiency of the test tool and the system expansion capability are further improved.

[0157] Step 808: determining the integrated clock gating group outputting the capture clock signal according to the clock output switch, and outputting the capture clock signal; The capture clock signal can be understood as a clock pulse signal output by the OCC in the capture phase of the scan test, which is used to trigger the registers under each clock domain to capture the logic response result. Each integrated clock gating group is established in the foregoing steps to control whether the capture clock signal is transmitted to the corresponding register group.

[0158] In this embodiment, only part of the ICG groups are turned on in the capture phase, and only the ICG groups connected to the clock output switches in the on state are activated, and the rest of the groups remain in the off state, so that only part of the registers receive the capture clock pulse. The capture clock signal only acts on the selected group, thereby realizing the time-sharing flip of the register and reducing the overall power consumption.

[0159] In one specific embodiment provided in the specification, the ICG group outputting the capture clock signal is determined according to the state of the clock output switch, and the capture clock signal is outputted.

[0160] In the above example, it is assumed that the ICG under each OCC domain is divided into 16 groups and corresponds to 16 clock output switches.

[0161] When the gate register output control signal flips, only one clock output switch is in the on state, and the corresponding one ICG group receives the capture clock signal.

[0162] Therefore, about 1 / 16 of the registers in this clock domain are triggered for capture operation, and the rest of the registers remain static, significantly reducing the number of simultaneous flips.

[0163] Referring to Figure 10 , Figure 10 The figure shows the schematic diagram of the capture clock control unit outputting the capture clock signal provided in one embodiment of the specification.

[0164] Each clock output switch corresponds to an integrated clock gate group, and each integrated clock gate group corresponds to a connected scan chain. The input end iCK of each ICG is used to receive the capture clock signal, and the output end oCK outputs the gated capture clock signal. The output clock of each integrated clock gate group drives the corresponding scan chain, realizing independent clock control of different register groups.

[0165] The right side waveform shows the capture clock signals outputted by different integrated clock gate groups under the control of the clock output switch. Since the capture clock control unit controls the integrated clock gate, part of the clock output switches are set to the on state, so only part of the scan chains output the capture clock signal. This realizes the shielding of the capture clock signal by part of the scan chains and the response of the capture clock signal by another part of the scan chains at the same time and in the same OCC. By flexibly adjusting the number of clock switches in the test phase, the number of registers that flip at the same time is reduced, effectively reducing the power consumption in the capture phase and reducing the risk of IR drop.

[0166] In one specific embodiment provided in the specification, the ICG group outputting the capture clock signal is determined according to the state of the clock output switch, and the capture clock signal is outputted. According to the clock output switch, the start-stop state of each integrated clock gating group is determined; In the case that the start-stop state is on, the corresponding integrated clock gating group outputs a capture clock signal; In the case that the start-stop state is off, the corresponding integrated clock gating group is turned off.

[0167] The start-stop state can be understood as the on-off control state of each integrated clock gating group, which is used to indicate whether the capture clock signal is transmitted to the corresponding register group. When the start-stop state is on, the capture clock signal is transmitted to the downstream register via the ICG of the group; when the start-stop state is off, the ICG of the group blocks the capture clock signal, and the register remains static.

[0168] In the capture phase, by selectively turning on part of the ICG groups based on the start-stop state of the clock output switch, only part of the registers receive the capture clock signal, so that the logic response capture is completed in time. The control principle is based on the configurable gating ratio design, that is, the system can flexibly adjust the number of open groups according to the power consumption and test coverage requirements, and realize configurable gear control.

[0169] In a specific embodiment provided in the present specification, according to the start-stop control signal output by the gated register, the number of currently opened ICG groups is determined, and the corresponding capture clock signal is output. The system can set different opening ratios under different test configurations, such as 1 / 16, 1 / 8, 1 / 4 or 1 / 2, to adapt to the power consumption constraints and test time requirements of different designs.

[0170] In the above example, in a certain system on a chip, the total number of ICGs under an OCC is 256, and the system divides them into 16 groups. In the first configuration, only 1 / 16 of the groups (i.e. 16 ICGs) are turned on, at this time only about 1 / 16 of the registers are activated, and the power consumption is the lowest; in the second configuration, 1 / 8 or 1 / 4 of the groups can be turned on to balance the power consumption and test time. The start-stop state of all ICGs is controlled by the gated register, and when the gated register flips, the corresponding group automatically enters the on state and completes the capture operation.

[0171] By introducing a configurable start-stop control strategy, the embodiment can flexibly adjust the proportion of the opened ICG according to the test target. In a design with strict power consumption constraints, only a small number of ICG groups (such as 1 / 16) are opened, which significantly reduces the peak power consumption and IR drop risk; in a design with test efficiency as the priority, more ICG groups (such as 1 / 4 or 1 / 2) can be opened to shorten the test time; compared with the full-on or full-off situation, the embodiment realizes a dynamic balance between power consumption, IR drop, test time and test coverage; at the same time, it supports the extreme mode of opening or closing all ICGs, maintaining the universality and compatibility of the test structure.

[0172] Step 810: controlling the scan chain to process the test data corresponding to the test instruction in response to each capture clock signal, obtaining response data, and determining the test result of the system on a chip according to the response data and preset response data.

[0173] The response data can be understood as the test result output by the scan chain in the capture phase, which is used to reflect the actual logic response of the circuit under test conditions. The preset response data can be understood as the expected output result obtained in advance according to the circuit design logic, which is used as a reference for test comparison. The test result is used to characterize whether the circuit logic is correct. When the response data is consistent with the preset response data, it means that the logic structure of the circuit under test is consistent with the design expectation; when they are inconsistent, it means that the circuit has functional abnormalities or logic faults.

[0174] By comparing the response data output by the scan chain in the capture phase with the preset response data, it is determined whether the actual logic behavior of the circuit is consistent with the design logic, thereby verifying the correctness of the function of the system on a chip. This process belongs to the standard test verification phase in scan testing.

[0175] In a specific embodiment provided in the present specification, the test control module receives and distributes the capture clock signal, and the scan chain outputs the response data under the driving of the capture clock. The test equipment or test control module compares the response data with the preset response data. If they are consistent, it is determined that the function of the system on a chip is correct; if they are inconsistent, it is determined that there is a logic error or a timing fault.

[0176] For example, in the test process, the test vector loaded by the external test equipment is [1, 0, 1, 1], and the preset response data expected to be output according to the circuit design logic is [0, 1, 0, 0]. When the response data output by the scan chain in the capture phase is completely consistent with the preset response data, it means that the circuit logic function is correct; if the output is [0, 0, 0, 0] or there is any bit inconsistency, it means that there is a logic abnormality or a timing problem on the path.

[0177] By comparing the response data captured from the scan chain output with the preset response data, whether the logic function of the system on chip is correctly designed and implemented can be effectively verified.

[0178] In an embodiment provided in the specification, the test result of the system on chip is determined according to the response data and the preset response data, including: In the case that the response data and the preset response data are consistent, the test result is success; In the case that the response data and the preset response data are inconsistent, the test result is failure; In the case that the test result is failure, the difference between the response data and the preset response data is recorded, and the functional module of the system on chip is adjusted; The adjusted system on chip is retested.

[0179] In the scan test, by comparing the response data with the preset response data, whether the system on chip to be tested has logic abnormality or structural failure can be determined. When the two are consistent, it indicates that the logic function of the system is consistent with the design expectation; when the two are inconsistent, it indicates that there is an error in part of the logic path or the register, and fault positioning and function adjustment need to be performed according to the difference. The process constitutes a closed-loop feedback mechanism between the test and the design, which can improve the reliability and yield of the system in repeated testing and correction.

[0180] In an embodiment provided in the specification, the test result is determined according to the response data and the preset response data, including: comparing the response data with the preset response data; when the two are consistent, determining that the test result is success; when the two are inconsistent, determining that the test result is failure and recording the difference; modifying or optimizing the functional module of the system on chip according to the difference; and re-executing the test on the adjusted system on chip to verify the correction effect.

[0181] For example, in the test process, the preset response data is [1, 0, 1, 0, 1, 1], and the response data output by the scan chain is [1, 0, 1, 1, 1, 1]. By comparing, it is found that the 4th data is different, and it is determined that the corresponding logic path of the register has an abnormality. The system is positioned to the corresponding functional module according to the difference, and the scan test is performed again after adjusting the logic unit. After retesting, the two sets of data are completely consistent, and the test result is determined to be success, indicating that the system function returns to normal.

[0182] Through the result judgment mechanism based on the response data and the preset response data, the embodiment realizes the closed-loop test process from test detection, fault positioning, design correction and retest verification, which can significantly improve the accuracy of the test and the reliability of the system, and reduce the debugging cost in the production stage.

[0183] The above are all descriptions of a single clock output module and registers under the clock domain thereof. For the case of multiple clock output modules, a corresponding capture clock control unit is constructed for each clock output module for control, and all capture clock control units are connected in series to obtain a single scan chain.

[0184] Referring to Figure 11 , Figure 11 A test structure diagram of multiple capture clock control units in a test environment provided by an embodiment of the present specification is shown. The test clock control structure of the embodiment includes a scan chain 1102 and multiple capture clock control units 1104. The scan chain 1102 is formed by multiple registers connected in series, and is used to realize the moving in and out of test data in the test process. The multiple capture clock control units 1104 are respectively set corresponding to each OCC clock domain, and are used to independently control the capture clock of the uplink register in different OCC clock domains. Specifically, each OCC clock domain is provided with a corresponding ICG controller, which is used to receive a test enable signal and a clock enable signal, generate a gated capture clock, and distribute the gated capture clock to the uplink register in the clock domain.

[0185] In addition, in order to improve the efficiency of the test tool generation vector, the scan units inside each ICG controller can be connected in series in structure to form an independent scan chain and be connected to the test environment, so as to realize unified scan control and test configuration. Through this way, the independent clock management of different OCC clock domains can be ensured, and the vector derivation efficiency and clock power consumption distribution of the scan test can be optimized as a whole.

[0186] Corresponding to the above method embodiment, the present specification also provides a system on chip embodiment, Figure 12 A structure diagram of a system on chip provided by an embodiment of the present specification is shown. The system on chip includes at least one functional module, each functional module includes at least one clock output module set and a clock control module corresponding to each clock output module set, and the system on chip includes: A response module 1202 configured to construct a scan chain in response to a test instruction; A determination module 1204 configured to determine at least one target clock control module in each clock control module, wherein the target clock control module includes delay selection information and at least one delay unit; A delay module 1206 configured to determine at least one target delay unit according to the delay selection information corresponding to each target clock control module, determine the delay link corresponding to each target clock control module, and generate a corresponding delay shift clock signal based on each delay link; The control module 1208 is configured to control the scan chain to process test data corresponding to the test instruction in response to each delay shift clock signal.

[0187] Optionally, the test instruction comprises mode control information and scan structure information. The response module 1202 is further configured to: receive a test instruction; parse the test instruction to obtain mode control information and scan structure information; enter a test mode according to the mode control information, and determine a topology and input / output ports of the scan chain according to the scan structure information; construct a scan chain according to the topology and input / output ports of the scan chain.

[0188] Optionally, the determination module 1204 is further configured to: obtain predicted power consumptions of each functional module of the system on chip in a test process, and calculate an overall predicted power consumption according to each predicted power consumption; sort each predicted power consumption to obtain a sorting result in a case where the overall predicted power consumption is greater than a preset power consumption threshold; determine a clock control module corresponding to a functional module satisfying a preset power consumption condition as a target clock control module according to the sorting result.

[0189] Optionally, the delay module 1206 is further configured to: determine a delay duration of each target clock control module according to the delay selection information; obtain a unit delay duration of a target delay unit, and determine a quantity of target delay units corresponding to each target clock control module according to the delay duration of each target clock control module and the unit delay duration; construct a delay link according to the quantity of target delay units corresponding to each target clock control module, and generate a corresponding delay shift clock signal based on each delay link.

[0190] Optionally, the delay selection information comprises a period parameter of a shift clock. The delay module 1206 is further configured to: determine a delay threshold according to the period parameter of the shift clock; determine a delay duration of each target clock control module according to the delay threshold, wherein each delay duration is less than the delay threshold.

[0191] Optionally, the control module 1208 is further configured to: load test data to the scan chain by using the delay shift clock signal. The scan chain performs data test processing on the test data.

[0192] Optionally, the control module 1208 is further configured to: acquire the capture clock signals output by the clock output module set; control the scan chain to process the test data corresponding to the test instruction in response to each capture clock signal to obtain response data; determine whether the response data is consistent with preset response data to determine the test result of the system on chip.

[0193] Optionally, the response module 1202 is further configured to: construct a capture clock control unit, wherein the capture clock control unit includes a gating unit; acquire configuration information of at least one integrated clock gating, and determine the number of clock output switches according to the gating unit; group the integrated clock gate according to the number of clock output switches and the configuration information of each integrated clock gate to obtain at least one integrated clock gate group, each clock output switch corresponding to each integrated clock gate; determine the integrated clock gate group outputting the capture clock signal according to the clock output switch, and output the capture clock signal; control the scan chain to process the test data corresponding to the test instruction in response to each capture clock signal to obtain response data, and determine the test result of the system on chip according to the response data and preset response data.

[0194] Corresponding to the method embodiments described above, the present specification also provides system on chip embodiments, Figure 13 An embodiment of the present specification shows a structural schematic diagram of a system on chip. The system on chip includes at least one functional module, each functional module including at least one integrated clock gating, and the system on chip includes: The construction module 1302 is configured to construct a scan chain and at least one capture clock control unit corresponding to the scan chain in response to a test instruction, wherein the capture clock control unit includes a gating unit; The acquisition module 1304 is configured to acquire configuration information of at least one integrated clock gating; The grouping module 1306 is configured to determine the number of clock output switches according to the gating unit, group the integrated clock gate according to the number of clock output switches and the configuration information of each integrated clock gate to obtain at least one integrated clock gate group, and each clock output switch corresponding to each integrated clock gate; The output module 1308 is configured to output the integrated clock gating group of the capture clock signal according to the clock output switch. The control module 1310 is configured to control the scan chain to process the test data corresponding to the test instruction in response to each capture clock signal, obtain response data, and determine a test result of the system on chip according to the response data and preset response data.

[0195] Optionally, the capture clock control unit includes a gating unit. The construction module 1302 is further configured to: determine the number of gating registers; determine a corresponding number of gating registers according to the number of gating registers, and construct the gating unit according to the gating registers; construct the capture clock control unit according to the gating unit and the timing remodeling unit.

[0196] Optionally, the gating unit includes at least one gating register. The acquisition module 1304 is further configured to: determine the number of clock output switches according to the gating unit, including: determine the number of types of output types of the gating unit according to the number of registers of the gating registers; determine the number of clock output switches according to the number of types.

[0197] Optionally, the configuration information of the integrated clock gating includes attribute information and position information. The grouping module 1306 is further configured to: group each integrated clock gating according to the attribute information of each integrated clock gating to obtain at least one first clock group; group the first clock group according to the position information of each integrated clock gating and the number of clock output switches to obtain at least two second clock groups, wherein the number of second clock groups is consistent with the number of clock output switches.

[0198] Optionally, the output module 1308 is further configured to: determine the start-stop state of each integrated clock gating group according to the clock output switch; in the case that the start-stop state is on, the corresponding integrated clock gating group outputs the capture clock signal; in the case that the start-stop state is off, the corresponding integrated clock gating group is turned off.

[0199] Optionally, the control module 1310 is further configured to: in a case where the response data is consistent with the preset response data, the test result is success; in a case where the response data is inconsistent with the preset response data, the test result is failure; in a case where the test result is failure, recording a difference point of the response data and the preset response data, and adjusting a function module of the system on chip; retesting the adjusted system on chip.

[0200] The above is a schematic scheme of the system on chip of the embodiment. It should be noted that the technical scheme of the system on chip and the technical scheme of the test method described above belong to the same concept, and the details of the technical scheme of the system on chip that are not described in detail can be referred to the description of the technical scheme of the test method.

[0201] An embodiment of the present specification further provides a data processing system, comprising: a processor core; a system on chip, wherein the system on chip comprises at least one function module, the function module comprises at least one clock output module set, a clock control module corresponding to each clock output module set, and at least one integrated clock gating, and each integrated clock gating corresponds to a clock control unit, and the system on chip executes the steps of the method according to any one of claims 1-14.

[0202] The processor core is responsible for logical control, task scheduling and serial computation, and its functions can include generating a calculation task instruction, allocating tasks to calculation nodes of the system on chip, etc., and its design focus is on low latency and complex instruction processing. The system on chip is responsible for executing a test task, and is used for verifying the logical function of the system on chip.

[0203] The processor core and the system on chip can interact with each other, the processor core issues a task to the system on chip, the system on chip executes the task in parallel in each calculation node, and returns the result to the processor core.

[0204] The above is a schematic scheme of the system on chip of the embodiment. It should be noted that the technical scheme of the system on chip and the technical scheme of the test method described above belong to the same concept, and the details of the technical scheme of the system on chip that are not described in detail can be referred to the description of the technical scheme of the test method.

[0205] An embodiment of the present specification further provides a computer readable storage medium, which stores a computer program / instruction, and the computer program / instruction is executed by a processor to implement the steps of the test method.

[0206] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, the computer readable storage medium embodiment is described simply because it is basically similar to the test method embodiment, and the relevant part can be referred to the description of the test method embodiment.

[0207] An embodiment of the specification also provides a computer program product, including computer programs / instructions, which, when executed by a processor, implement the steps of the above test method.

[0208] The above is a schematic scheme of a computer program product of the embodiment. It should be noted that the technical scheme of the computer program product and the technical scheme of the test method described above belong to the same concept. The technical scheme of the computer program product which is not described in detail can be referred to the description of the technical scheme of the test method.

[0209] The above describes a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than the order in which they are recited in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order in order to achieve the desired results. In some implementations, multitasking and parallel processing can be advantageous or possible.

[0210] The computer instructions include computer program codes, which can be in the form of source code, object code, executable files, or some intermediate forms, etc. The computer readable medium can include any entity or device capable of carrying the computer program codes, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer readable medium can be appropriately increased or decreased according to the requirements of patent practice. For example, in some regions, according to the patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

[0211] It is noted that the foregoing describes a number of implementations of various embodiments of the present specification. Other embodiments, however, are within the scope of the following claims. In some cases, actions or steps recited in the claims can be performed in a different order and still accomplish the desired results. Additionally, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous. Further, one skilled in the art will readily recognize that the embodiments described in the specification can be practiced with steps in a different order, and / or utilizing other structures, components, and / or processes than those described in the specification without departing from the spirit and scope of the present specification.

[0212] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0213] The preferred embodiments of the present specification disclosed above are only used to help explain the present specification. The alternative embodiments do not describe all the details and do not limit the present invention to the specific embodiments described. Obviously, according to the content of the embodiments of the present specification, many modifications and changes can be made. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of the present specification, so that those skilled in the art can well understand and use the present specification. The present specification is limited only by the claims and their full scope and equivalents.

Claims

1. A testing method applied to an on-chip system, wherein, The on-chip system includes at least one functional module, each functional module including at least one set of clock output modules and a clock control module corresponding to each set of clock output modules, and the test method includes: In response to test commands, construct a scan chain; At least one target clock control module is determined in each clock control module, wherein the target clock control module includes delay selection information and at least one delay unit; At least one target delay unit is determined based on the delay selection information corresponding to each target clock control module, the delay link corresponding to each target clock control module is determined, and a corresponding delay shift clock signal is generated based on each delay link. The scan chain is controlled to process the test data corresponding to the test command in response to each delayed shift clock signal.

2. The method as described in claim 1, wherein the test instruction includes mode control information and scan structure information; In response to test commands, construct a scan chain, including: Receive test instructions; The test instructions are parsed to obtain mode control information and scan structure information; The test mode is entered according to the mode control information, and the topology and input / output ports of the scan chain are determined according to the scan structure information. The scan chain is constructed based on its topology and input / output ports.

3. The method of claim 1, wherein determining at least one target clock control module among the clock control modules includes: The predicted power consumption of each functional module of the on-chip system during the testing process is obtained, and the overall predicted power consumption is calculated based on each predicted power consumption. If the total predicted power consumption is greater than a preset power consumption threshold, the predicted power consumption is sorted to obtain the sorting result; Based on the sorting results, the clock control module corresponding to the functional module that meets the preset power consumption conditions is determined as the target clock control module.

4. The method as described in claim 1, comprising determining at least one target delay unit based on delay selection information corresponding to each target clock control module, determining the delay link corresponding to each target clock control module, and generating a corresponding delay shift clock signal based on each delay link, including: The delay duration of each target clock control module is determined based on the delay selection information; Obtain the unit delay duration of the target delay unit, and determine the number of target delay units corresponding to each target clock control module based on the delay duration and unit delay duration of each target clock control module; Delay links are constructed based on the number of target delay units corresponding to each target clock control module, and corresponding delay shift clock signals are generated based on each delay link.

5. The method of claim 4, wherein the delay selection information includes the period parameter of the shift clock; The delay duration of each target clock control module is determined based on the delay selection information, including: The delay threshold is determined based on the period parameter of the shift clock; Based on the delay threshold, the delay duration of each target clock control module is determined, wherein each delay duration is less than the delay threshold.

6. The method of claim 1, wherein controlling the scan chain to process the test data corresponding to the test command in response to each delayed shift clock signal, includes: The test data is loaded into the scan chain using the delayed shift clock signal; The scanning chain performs data testing processing on the test data.

7. The method of claim 1, further comprising: Obtain the captured clock signals output by each clock output module set; The scan chain is controlled to process the test data corresponding to the test command in response to each capture clock signal, and the response data is obtained. Determine whether the response data is consistent with the preset response data to determine the test result of the on-chip system.

8. The method of claim 1, further comprising constructing a scan chain in response to a test instruction: Construct a capture clock control unit, wherein the capture clock control unit includes a gating unit; Obtain configuration information for at least one integrated clock gating unit, and determine the number of clock output switches based on the gating unit; Based on the number of clock output switches and the configuration information of each integrated clock gate, each integrated clock gate is grouped to obtain at least one integrated clock gate group, with each clock output switch corresponding to each integrated clock gate. The integrated clock gating group for outputting the captured clock signal is determined based on the clock output switch, and the captured clock signal is output. The scan chain is controlled to process the test data corresponding to the test command in response to each capture clock signal, obtain response data, and determine the test result of the on-chip system based on the response data and preset response data.

9. The method of claim 8, wherein, The capture clock control unit includes a gating unit, comprising: Determine the number of gate registers; Based on the number of gate registers, determine the corresponding number of gate registers, and construct the gate control unit based on the gate registers; The capture clock control unit is constructed based on the gating unit and the timing reshaping unit.

10. The method of claim 8, wherein the gating unit comprises at least one gating register; The number of clock output switches is determined based on the gating unit, including: The number of output types of the gate unit is determined based on the number of registers in the gate register; The number of clock output switches is determined based on the number of types mentioned.

11. The method of claim 8, wherein the configuration information for integrated clock gating includes: Attribute information and location information; Based on the number of clock output switches and the configuration information of each integrated clock gate, the integrated clock gates are grouped to obtain at least one integrated clock gate group, including: Based on the attribute information of each integrated clock gate, the integrated clock gates are grouped to obtain at least one first clock group; The first clock group is grouped according to the position information of each integrated clock gating and the number of clock output switches to obtain at least two second clock groups, wherein the number of second clock groups is the same as the number of clock output switches.

12. The method of claim 8, wherein determining the integrated clock gating group of the output capture clock signal based on the clock output switch, and outputting the capture clock signal, includes: The start / stop status of each integrated clock gating group is determined based on the clock output switch. When the start / stop state is enabled, the corresponding integrated clock gating group outputs the captured clock signal; When the start / stop state is off, the corresponding integrated clock gating group is turned off.

13. The method of claim 8, wherein determining the test result of the on-chip system based on the response data and preset response data includes: If the response data and the preset response data are consistent, the test result is successful; If the response data and the preset response data are inconsistent, the test result is a failure; If the test result is a failure, the differences between the response data and the preset response data are recorded, and the functional modules of the system-on-a-chip are adjusted accordingly. Retest the adjusted on-chip system.

14. A test method applied to an on-chip system, wherein, The system-on-a-chip includes at least one functional module, and each functional module includes at least one integrated clock gating. The method includes: In response to a test command, a scan chain is constructed, and at least one capture clock control unit corresponding to the scan chain is constructed, wherein the capture clock control unit includes a gating unit; Obtain configuration information for at least one integrated clock gating unit, and determine the number of clock output switches based on the gating unit; Based on the number of clock output switches and the configuration information of each integrated clock gate, each integrated clock gate is grouped to obtain at least one integrated clock gate group, with each clock output switch corresponding to each integrated clock gate. The integrated clock gating group for outputting the captured clock signal is determined based on the clock output switch, and the captured clock signal is output. The scan chain is controlled to process the test data corresponding to the test command in response to each capture clock signal, obtain response data, and determine the test result of the on-chip system based on the response data and preset response data.

15. A system-on-a-chip, the system-on-a-chip comprising at least one functional module, each functional module comprising at least one set of clock output modules and a clock control module corresponding to each set of clock output modules, comprising: The response module is configured to build a scan chain in response to test commands; The determining module is configured to determine at least one target clock control module among the clock control modules, wherein the target clock control module includes delay selection information and at least one delay unit; The delay module is configured to determine at least one target delay unit based on the delay selection information corresponding to each target clock control module, determine the delay link corresponding to each target clock control module, and generate a corresponding delay shift clock signal based on each delay link. The control module is configured to control the scan chain to process the test data corresponding to the test command in response to each delayed shift clock signal.

16. A system-on-a-chip, the system-on-a-chip comprising at least one functional module, each functional module comprising at least one integrated clock gating, including: A construction module is configured to construct a scan chain and at least one capture clock control unit corresponding to the scan chain in response to a test command, wherein the capture clock control unit includes a gating unit; The acquisition module is configured to acquire configuration information of at least one integrated clock gating unit and determine the number of clock output switches based on the gating unit. The grouping module is configured to group each integrated clock gate according to the number of clock output switches and the configuration information of each integrated clock gate, to obtain at least one integrated clock gate group, with each clock output switch corresponding to each integrated clock gate; The output module is configured to determine the integrated clock gating group of the output capture clock signal based on the clock output switch, and output the capture clock signal. The control module is configured to control the scan chain to process the test data corresponding to the test command in response to each capture clock signal, obtain response data, and determine the test result of the on-chip system based on the response data and preset response data.

17. A data processing system, comprising: Processor core; A system-on-a-chip (SoC) includes at least one functional module, which includes at least one set of clock output modules, a clock control module corresponding to each set of clock output modules, at least one integrated clock gating, and a capture clock control unit corresponding to each integrated clock gating. When the SoC is executed, it implements the steps of the method according to any one of claims 1-14.

18. A computer-readable storage medium storing a computer program / instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1 to 14.

19. A computer program product comprising a computer program / instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1 to 14.

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