Chip power consumption model solving method based on multi-diagonal-block matrix decomposition

Abstract

The invention relates to a chip power consumption model solving method based on multi-diagonal-block matrix decomposition, and the method comprises the steps: carrying out the multi-diagonal-block arrow-shaped permutation sorting of an input original super-large-scale complex symmetric block matrix, and generating a global permutation vector; based on a target node index and a global permutation vector specified at a simulation moment, dynamically recombining the matrix to accurately extract a to-be-eliminated sub-matrix; a three-level parallel collaborative architecture is adopted, and diagonal sub-block inverse matrix calculation, in-block coupling item solving and cross-block result aggregation are sequentially executed in parallel; and a diagonal sub-block inverse matrix caching mechanism is introduced to avoid repeated calculation. Through the core design of one-time sorting permanent multiplexing, dynamic accurate extraction and multi-level parallel caching, the calculation complexity and storage overhead of super-large-scale matrix Schur complement are remarkably reduced, the technical bottlenecks that an existing method is low in efficiency and poor in parallelism, and historical results cannot be multiplexed are effectively solved, and the method is suitable for large-scale matrix Schur complement. And the real-time performance and the expandability of chip power consumption simulation are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit computer-aided design, and particularly relates to a chip power consumption model solving method based on multi-diagonal block matrix decomposition. BACKGROUND

[0002] With the continuous evolution of modern very large scale integrated circuits (VLSI) towards nanometer technology and three-dimensional integration, the number of on-chip and inter-chip coupling nodes grows geometrically, which poses unprecedentedly severe challenges to the performance of matrix solving for power consumption simulation. For high-dimensional complex symmetric block matrices with dimensions up to , it has become a core technical problem to be urgently broken through in the field of circuit power consumption model solving to efficiently and reusably complete Schur complement calculation while ensuring simulation accuracy.

[0003] In the field of chip power consumption model solving, Schur complement calculation of super large scale complex symmetric matrices directly determines the accuracy and efficiency of dynamic power consumption analysis. The current mainstream technical solutions have fundamental limitations when dealing with matrices with dimensions up to , which can be mainly summarized as the following two methods:

[0004] The first type is the Schur complement method based on explicit inversion. This type of method takes the Schur complement formula as the core, and when the block size is large or the block structure needs to be frequently updated, it will face significant performance bottlenecks in the super large scale scenario. Especially when the matrix dimension exceeds , even if only the sub-block is inverted, the cumulative calculation overhead will still cause the overall simulation efficiency to drop sharply. More critically, each time the block is restructured, the matrix rearrangement and factorization process needs to be repeated, and the inherent sparsity or non-zero structure of the matrix cannot be reused, which further limits its scalability in large-scale scenarios.

[0005] The second type is the arrow sorting method. This method rearranges the matrix into an arrow structure to simplify Schur complement calculation, but due to the use of fixed block mechanism, it easily leads to a serious imbalance between the center block and the peripheral block, which in turn causes a sharp fluctuation in the computational load within and between blocks. More prominently, this structure fails to effectively exploit the parallel computing potential of multi-diagonal blocks, making it difficult to fully schedule fine-grained computing resources such as multi-core CPUs or GPU threads, and the parallel acceleration effect is extremely limited. Affected by the uneven structure load, even when dealing with tens of thousands of dimensional matrices, the solving time is still as high as thousands of seconds, which is difficult to meet the actual needs of high-time dynamic power consumption analysis.

[0006] The two types of prior art have advantages and disadvantages, and cannot meet the core requirements of sorting reuse, parallel computing and block load balancing in the dynamic solving of super large scale matrix. The specific performance is as follows: first, the calculation complexity is high. The time complexity of the traditional full matrix inversion or Cholesky decomposition method is When the matrix size N reaches and above, the operation amount increases by a cubic level, and the time consumption of single calculation often breaks through thousands of seconds, which cannot meet the strict real-time requirement of dynamic power simulation. Secondly, the storage crisis caused by the destruction of sparsity. The traditional decomposition process will seriously destroy the inherent sparsity of the matrix, and the number of filled elements will increase exponentially. The storage demand will increase sharply with the matrix size, often exceeding the upper limit of hardware memory bearing, greatly restricting the scalability of the algorithm in the super large scale circuit scenario. Thirdly, the parallel computing efficiency is insufficient. The existing methods mostly use single-layer or overall parallel strategy, and cannot design multi-level parallel coordination mechanism according to the structural characteristics of the block matrix. When executed in a multi-core or distributed environment, the frequent global synchronization operation and inter-node communication overhead make the actual speedup ratio much lower than the theoretical value, which is difficult to fully release the hardware computing power. More prominent is the repeated calculation problem. When the node set to be preserved is updated over time, the existing method needs to re-execute the nested partitioning and matrix rearrangement process, which cannot reuse the historical sorting results and decomposition intermediate data, resulting in a large amount of redundant calculation, which significantly reduces the overall solving efficiency. SUMMARY

[0007] The purpose of the present application is to provide a chip power consumption model solving method based on multi-diagonal block matrix decomposition, to realize efficient, reusable and parallelized calculation of super large scale complex symmetric block matrix Schur complement.

[0008] To achieve the above purpose, the technical scheme adopted by the present application is as follows: a chip power consumption model solving method based on multi-diagonal block matrix decomposition, comprising the following steps:

[0009] Step S1, inputting a super large scale complex symmetric block matrix A, the matrix A has original sparsity characteristics;

[0010] Step S2, sorting and block processing each diagonal block A i of the matrix A respectively, to obtain a single-layer arrow matrix;

[0011] Step S3, performing secondary processing on each sub-matrix on the diagonal line of the single-layer arrow matrix, to convert the single-layer arrow matrix into a double-layer arrow matrix;

[0012] Step S4, integrating the coupling edges corresponding to each diagonal line sub-matrix in the double-layer arrow matrix into the coupling edges of the initial single-layer arrow matrix, to restore it to a single-layer arrow matrix;

[0013] Step S5: Repeat steps S3-S4 to continuously optimize the matrix structure until the number of diagonal blocks reaches the preset target value, and output the global permutation vector and the position information of each block.

[0014] Step S6: Based on the node index set specified at time t and the global permutation vector, locate the position of each node index in the sorted matrix, move the corresponding row and column to the end of the matrix, and obtain the rearranged matrix;

[0015] Step S7: Perform Cholesky decomposition on the s diagonal blocks in the rearranged matrix in parallel to obtain the corresponding lower triangular factors and form the overall lower triangular matrix L;

[0016] Step S8: Based on the lower triangular factor, solve the inverse matrix of each diagonal block in parallel, and use a caching mechanism to store the calculation results;

[0017] Step S9: Based on the inverse matrix of each diagonal block, calculate the coupling terms within each block in parallel;

[0018] Step S10: Calculate the Schur complement of matrix A with respect to the submatrices.

[0019] Furthermore, in step S1, the input ultra-large-scale complex symmetric block matrix A is represented as:

[0020]

[0021] Each diagonal block It is a real symmetric or complex symmetric matrix. , For the i-th diagonal block The dimension; the total size of the ultra-large-scale complex symmetric block matrix A is The ultra-large-scale complex symmetric block matrix A retains its original sparse properties, with non-zero elements concentrated near the diagonal.

[0022] Further, in step S2, for each diagonal block A of matrix A... i The nested partitioning method is used for sorting, and the block processing is performed based on the arrow structure principle to obtain a single-layer arrow matrix.

[0023] Furthermore, in step S3, for the single-layer arrow matrix obtained in step S2, the nested partitioning method and the principle of diagonal edge addition are applied again to the submatrices on its diagonal to perform secondary processing, transforming the single-layer arrow matrix into a double-layer arrow matrix.

[0024] Furthermore, in step S5, the matrix structure is continuously optimized until the number of diagonal blocks reaches a preset target value, wherein each diagonal block The structure is represented as:

[0025]

[0026] in, For the i-th diagonal block The first diagonal matrix, , These are the i-th diagonal blocks. The Middle The first and second matrices of the row.

[0027] Further, in step S6, the set of node indices specified by input time t is... ,in Based on the global permutation vector output in step S5, locate the index of each node. In the sorted matrix, the corresponding row and column are moved to the end of the matrix. Action and Columns, to obtain the rearranged matrix:

[0028]

[0029] in, , , , Each is a matrix submatrix, for transpose, ; among them, each diagonal pieces The submatrix is ​​now complete after removing the specified node indices. and Dynamic extraction.

[0030] Furthermore, in step S7, the s diagonal blocks with balanced sizes in the rearrangement matrix obtained in step S6 are... Perform the Cholesky decomposition of the arrow matrix in parallel, for each diagonal block. , The calculation satisfies lower triangular factor This yields the global lower triangular matrix L:

[0031]

[0032] Among them, each lower triangular factor The structure of the lower triangular matrix with arrowhead shape and side edges is as follows:

[0033]

[0034] in, The i-th lower triangular factor The first diagonal matrix, The i-th lower triangular factor The Middle The first matrix in the row.

[0035] Furthermore, in step S8, the lower triangular factor is... The diagonal blocks and their coupled blocks are recombined into an extended submatrix. The inverse matrix is ​​solved step by step using a recursive method to realize the multi-diagonal block matrix. Inverse of the middle diagonal block matrix Parallel solution is achieved, and the computation results are stored using a caching mechanism.

[0036] Furthermore, in step S9, based on the diagonal block inverse matrix obtained in step S8, the coupling terms within each block are calculated in parallel. :

[0037]

[0038] in, For corresponding sub-blocks and The coupling matrix between them, all Improve processing efficiency through parallel computing using multi-core resources.

[0039] Furthermore, in step S10, the matrix The new matrix is ​​obtained after sorting in step S6. ,in Let be a permutation matrix, its The solution process is as follows:

[0040]

[0041] Combining the parallel computation results from step S9, the final result is achieved through... The solution is complete.

[0042] Compared with existing technologies, this invention has the following beneficial effects: It achieves significant performance improvement in solving Schur complement problems of ultra-large-scale complex symmetric block matrices. Its core technological advantages are mainly reflected in the following three aspects, specifically overcoming the key bottlenecks of current mainstream methods: First, for Schur complement methods based on explicit inversion, existing technologies generally suffer from high computational complexity and severe sparsity violation. Whether it's the traditional direct inversion method or the Cholesky decomposition method, their time complexity is as high as... When processing matrices of 10,000 dimensions or larger, single computations often take thousands of seconds, making it difficult to meet real-time requirements. Simultaneously, the decomposition process triggers a severe filling effect, leading to a rapid degradation of the sparse structure and an exponential increase in storage overhead, easily exceeding the hardware memory limit and severely restricting its applicability in ultra-large-scale scenarios. Secondly, the existing arrow sorting method suffers from uneven structural load and low parallel efficiency. Fixed block partitioning strategies often result in an imbalance between the size of the central and peripheral blocks, causing drastic fluctuations in computational load. Furthermore, the method does not fully exploit the parallel potential between multiple diagonal blocks, resulting in low utilization of fine-grained computational resources and an actual parallel speedup ratio far below theoretical expectations, making it difficult to adapt to modern multi-core or distributed hardware environments.

[0043] To address the aforementioned core bottlenecks, this invention achieves a systemic performance leap through three innovative designs: First, it proposes a "one-time sorting, permanent reuse" mechanism. Only one "multi-diagonal block arrow" permutation operation is performed on the original ultra-large-scale complex symmetric block matrix, generating a global permutation vector and storing it persistently. In subsequent dynamic node extraction at any time step, only row and column rearrangement based on this permutation vector is needed, eliminating the need to repeatedly execute nested partitioning and matrix rearrangement processes. This fundamentally eliminates the redundant sorting overhead of traditional methods, significantly improving data processing efficiency in dynamic scenarios. Second, it constructs a three-level parallel collaborative architecture, sequentially implementing: parallel computation of the inverse matrix of the smallest diagonal sub-block, parallel solution of coupling terms within the sub-block, and parallel aggregation of cross-block coupling results. Through refined task decomposition and collaborative scheduling, the potential of multi-core and distributed computing resources is fully released, significantly improving hardware computing power utilization and effectively solving the pain point of insufficient parallel speedup in existing methods. Third, it introduces a diagonal sub-block inverse caching mechanism. The system efficiently stores and reuses the smallest sub-block inverse matrix obtained from historical calculations, avoiding the high computational cost of repeated inversions. At the same time, it only needs to maintain three types of core data—global permutation vector, block position information, and sub-block inverse cache. Combined with sparse structure optimization and lightweight storage design, it precisely controls memory and storage overhead, achieving a high balance between real-time performance, scalability, and resource utilization, and fully meeting the multiple stringent requirements of ultra-large-scale chip power consumption simulation for performance and resources. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the method implementation process according to an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the original sparse matrix structure in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the sparse structure of the sorted arrow matrix in an embodiment of the present invention;

[0047] Figure 4This is a schematic diagram of the chip power consumption model block matrix in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram comparing the time consumption of block-based chip power consumption model decomposition and Schur elimination in an embodiment of the present invention. Detailed Implementation

[0049] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0050] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0051] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0052] This invention proposes a chip power consumption model solution method based on multi-diagonal block matrix decomposition. The core design revolves around four dimensions: reuse, accuracy, parallelism, and caching. First, only one "arrow-shaped" multi-diagonal block permutation operation is performed on the original block diagonal matrix to generate a global permutation vector, which is persistently stored and can be directly reused during subsequent updates at any time step, eliminating the additional overhead caused by repeated sorting. Second, for dynamically given target node indices, a secondary permutation vector is constructed to accurately extract the corresponding rows and columns of the target node to form submatrices C and P, without re-performing the full matrix decomposition process, significantly reducing the data processing scope. Third, an innovative three-level parallel architecture is designed to achieve the coordinated linkage of parallel computation of the smallest sub-block inverse matrix within a block, parallel solution of coupling terms within a block, and parallel scheduling of tasks between blocks, maximizing the utilization of multi-core and distributed computing resources. Fourth, a diagonal sub-block inverse result caching mechanism is established to store and reuse the diagonal sub-block inverse matrix obtained from historical calculations, avoiding repeated execution of inversion operations. The above design achieves efficient acceleration of Schur complement calculation for ultra-large-scale block matrices, significantly improving computational efficiency and resource utilization, while meeting the dual core requirements of real-time performance and scalability in chip power consumption simulation.

[0053] like Figure 1 As shown, the chip power consumption model solution method based on multi-diagonal block matrix decomposition proposed in this embodiment specifically includes the following steps:

[0054] Step S1: Input a very large-scale complex symmetric block matrix A, expressed as:

[0055]

[0056] Each diagonal block It is a real symmetric or complex symmetric matrix. , For the i-th diagonal block The dimension; the total size of the ultra-large-scale complex symmetric block matrix A is achievable Level; A large-scale complex symmetric block matrix A retains its original sparsity properties, with non-zero elements concentrated near the diagonal, and its structure is as follows: Figure 2 As shown.

[0057] Step S2: For each diagonal block A of matrix A i The nested dissect method is used for sorting, and the blocks are processed based on the principle of arrow structure to obtain a single-layer arrow matrix.

[0058] Step S3: For the single-layer arrow matrix obtained in step S2, apply the nested partitioning method and the diagonal edge-adding block principle to each submatrix on its diagonal for secondary processing to transform the single-layer arrow matrix into a double-layer arrow matrix.

[0059] Step S4: For the double-layer arrow matrix obtained in step S3, integrate the coupling edges corresponding to each diagonal submatrix into the coupling edges of the initial single-layer arrow matrix to achieve the reverse transformation of the matrix structure and restore it to a single-layer arrow matrix.

[0060] Step S5: Repeat steps S3-S4 to continuously optimize the matrix structure until the number of diagonal blocks reaches the preset target value (e.g., ...). Figure 3 (as shown); where each diagonal block The structure is represented as:

[0061]

[0062] in, For the i-th diagonal block The first diagonal matrix, , These are the i-th diagonal blocks. The Middle The first and second matrices of the row.

[0063] The final output includes the global permutation vector and the position information of each block, providing basic data for subsequent steps.

[0064] Step S6: Input the set of node indices specified at time t. (in Based on the global permutation vector output in step S5, locate the index of each node. In the sorted matrix, the corresponding row and column are moved to the end of the matrix. Action and Columns, to obtain the rearranged matrix:

[0065]

[0066] in, , , , Each is a matrix submatrix, for transpose, ; among them, each diagonal pieces The submatrix remaining after removing the specified node index (e.g.) Figure 4 As shown), the submatrix is ​​now complete. and Dynamic extraction.

[0067] Step S7: Arrange the s diagonal blocks of balanced size in the rearrangement matrix obtained in step S6. Perform the Cholesky decomposition of the arrow matrix in parallel, for each diagonal block. , The calculation satisfies lower triangular factor This yields the global lower triangular matrix L:

[0068]

[0069] Among them, each lower triangular factor The structure of the lower triangular matrix with arrowhead shape and side edges is as follows:

[0070]

[0071] in, The i-th lower triangular factor The first diagonal matrix, The i-th lower triangular factor The Middle The first matrix in the row.

[0072] Step S8: Adjust the lower triangular factor The diagonal blocks and their coupled blocks are recombined into an extended submatrix. The inverse matrix is ​​solved step by step using a recursive method to realize the multi-diagonal block matrix. Inverse of the middle diagonal block matrix Parallel solution is achieved, and the computation results are stored using a caching mechanism.

[0073] Step S9: Based on the diagonal block inverse matrix obtained in step S8, calculate the coupling terms within each block in parallel. :

[0074]

[0075] in, For corresponding sub-blocks and The coupling matrix between them, all Improve processing efficiency through parallel computing using multi-core resources.

[0076] Step S10: Calculate the Schur complement of matrix A with respect to submatrix P.

[0077] Step S10, Matrix The new matrix is ​​obtained after sorting in step S6. ,in Let be a permutation matrix, its The solution process is as follows:

[0078]

[0079] Combining the parallel computation results from step S9, the final result is achieved through... The solution is completed, and the Schur complement of matrix A with respect to submatrix P is calculated.

[0080] Through the above steps, this invention achieves efficient solution of the Schur complement of ultra-large-scale complex symmetric block matrix, and has three core advantages: permutation reuse, dynamic node extraction and three-level parallel computing, which significantly improves the real-time performance and scalability of power consumption simulation.

[0081] Figure 5 This is a schematic diagram comparing the time consumption of block-based chip power consumption model decomposition and Schur elimination in this embodiment.

[0082] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0084] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0085] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for solving chip power consumption models based on multi-diagonal block matrix decomposition, characterized in that, Includes the following steps: Step S1: Input a very large-scale complex symmetric block matrix A, where matrix A has the original sparsity property; Step S2: For each diagonal block A of matrix A i Sorting and block processing are performed separately to obtain a single-layer arrow matrix; Step S3: Perform secondary processing on each submatrix on the diagonal of the single-layer arrow matrix to transform the single-layer arrow matrix into a double-layer arrow matrix. Step S4: Integrate the coupling edges corresponding to each diagonal submatrix in the double-layer arrow matrix into the coupling edges of the initial single-layer arrow matrix, and restore it to a single-layer arrow matrix; Step S5: Repeat steps S3-S4 to continuously optimize the matrix structure until the number of diagonal blocks reaches the preset target value, and output the global permutation vector and the position information of each block. Step S6: Based on the node index set specified at time t and the global permutation vector, locate the position of each node index in the sorted matrix, move the corresponding row and column to the end of the matrix, and obtain the rearranged matrix; Step S7: Perform Cholesky decomposition on the s diagonal blocks in the rearranged matrix in parallel to obtain the corresponding lower triangular factors and form the overall lower triangular matrix L; Step S8: Based on the lower triangular factor, solve the inverse matrix of each diagonal block in parallel, and use a caching mechanism to store the calculation results; Step S9: Based on the inverse matrix of each diagonal block, calculate the coupling terms within each block in parallel; Step S10: Calculate the Schur complement of matrix A with respect to the submatrices.

2. The chip power consumption model solution method based on multi-diagonal block matrix decomposition according to claim 1, characterized in that, In step S1, the input ultra-large-scale complex symmetric block matrix A is represented as: Each diagonal block It is a real symmetric or complex symmetric matrix. , For the i-th diagonal block The dimension; the total size of the ultra-large-scale complex symmetric block matrix A is The ultra-large-scale complex symmetric block matrix A retains its original sparse properties, with non-zero elements concentrated near the diagonal.

3. The chip power consumption model solution method based on multi-diagonal block matrix decomposition according to claim 1, characterized in that, In step S2, for each diagonal block A of matrix A... i The nested partitioning method is used for sorting, and the block processing is performed based on the arrow structure principle to obtain a single-layer arrow matrix.

4. The chip power consumption model solution method based on multi-diagonal block matrix decomposition according to claim 1, characterized in that, In step S3, for the single-layer arrow matrix obtained in step S2, the nested partitioning method and the principle of diagonal edge addition are applied again to the submatrices on its diagonal to perform secondary processing, transforming the single-layer arrow matrix into a double-layer arrow matrix.

5. The chip power consumption model solution method based on multi-diagonal block matrix decomposition according to claim 1, characterized in that, In step S5, the matrix structure is continuously optimized until the number of diagonal blocks reaches a preset target value, where each diagonal block... The structure is represented as: in, For the i-th diagonal block The first diagonal matrix, , These are the i-th diagonal blocks. The Middle The first and second matrices of the row.

6. The chip power consumption model solution method based on multi-diagonal block matrix decomposition according to claim 1, characterized in that, In step S6, the set of node indices specified by input time t is used. ,in Based on the global permutation vector output in step S5, locate the index of each node. In the sorted matrix, the corresponding row and column are moved to the end of the matrix. Action and Columns, to obtain the rearranged matrix: in, , , , Each is a matrix submatrix, for transpose, ; among them, each diagonal pieces The submatrix is ​​now complete after removing the specified node indices. and Dynamic extraction.

7. The chip power consumption model solution method based on multi-diagonal block matrix decomposition according to claim 1, characterized in that, In step S7, the s diagonal blocks with balanced sizes in the rearrangement matrix obtained in step S6 are... Perform the Cholesky decomposition of the arrow matrix in parallel, for each diagonal block. , The calculation satisfies lower triangular factor This yields the global lower triangular matrix L: Among them, each lower triangular factor The structure of the lower triangular matrix with arrowhead shape and side edges is as follows: in, The i-th lower triangular factor The first diagonal matrix, The i-th lower triangular factor The Middle The first matrix in the row.

8. The chip power consumption model solution method based on multi-diagonal block matrix decomposition according to claim 1, characterized in that, In step S8, the lower triangular factor is... The diagonal blocks and their coupled blocks are recombined into an extended submatrix. The inverse matrix is ​​solved step by step using a recursive method to realize the multi-diagonal block matrix. Inverse of the middle diagonal block matrix Parallel solution is achieved, and the computation results are stored using a caching mechanism.

9. The chip power consumption model solution method based on multi-diagonal block matrix decomposition according to claim 1, characterized in that, In step S9, based on the diagonal block inverse matrix obtained in step S8, the coupling terms within each block are calculated in parallel. : in, For corresponding sub-blocks and The coupling matrix between them, all Improve processing efficiency through parallel computing using multi-core resources.

10. The chip power consumption model solution method based on multi-diagonal block matrix decomposition according to claim 1, characterized in that, In step S10, the matrix The new matrix is ​​obtained after sorting in step S6. ,in Let be a permutation matrix, its The solution process is as follows: Combining the parallel computation results from step S9, the final result is achieved through... The solution is complete.

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