Voltage sensing fault detection

Abstract

Sensing for fault detection at a memory controller is described herein. An example memory system includes a memory device, a memory system controller, and an edge connector. The memory system controller may be configured to detect an input voltage or an input current at a pin on the memory system controller, wherein the pin on the memory system controller is coupled to a circuit including a light emitting diode (LED). The memory controller may be configured to detect an output voltage or an output current at a pin on a memory system edge connector, wherein the pin on the memory system edge connector is coupled to the circuit. An error in the circuit may be detected based on an input voltage or input current detected at the pin on the memory system controller and an output voltage or output current detected at the pin on the memory system edge connector.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more specifically, to systems, apparatus, and methods associated with sensing for fault detection. Background Technology

[0002] Memory devices are typically provided as internal, semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides persistent data by retaining the stored data even without power and can include NAND flash memory, NOR flash memory, read-only memory (ROM), and resistive variable memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, among others.

[0003] Memory devices can be used as volatile and non-volatile memory for a wide range of electronic applications that require high memory density, high reliability, and low power consumption. For example, non-volatile memory can be used in personal computers, Memory Sticks, solid-state drives (SSDs), digital cameras, cellular phones, portable music players such as MP3 players and movie players, and other electronic devices.

[0004] Various computing systems may include processing resources coupled to memory (e.g., a memory system) associated with executing a set of instructions (e.g., a program, an application program, etc.). Summary of the Invention

[0005] One embodiment of this disclosure provides a method. The method includes: detecting an input voltage or input current at a pin on a memory system controller, wherein the pin on the memory system controller is coupled to circuitry including a light-emitting diode (LED); detecting an output voltage or output current at a pin on a memory system edge connector, wherein the pin on the memory system edge connector is coupled to the circuitry; and detecting whether an error exists in the circuitry based on the input voltage or input current detected at the pin on the memory system controller and the output voltage or output current detected at the pin on the memory system edge connector.

[0006] Another embodiment of this disclosure provides an apparatus. The apparatus includes a memory system comprising a memory device, a memory system controller, and an edge connector. The memory system controller is configured to: detect an input voltage or input current at a pin on the memory system controller, wherein the pin on the memory system controller is coupled to circuitry including a light-emitting diode (LED); detect an output voltage or output current at a pin on the memory system edge connector, wherein the pin on the memory system edge connector is coupled to the circuitry; and detect the presence of an error in the circuitry based on the input voltage or input current detected at the pin on the memory system controller and the output voltage or output current detected at the pin on the memory system edge connector.

[0007] Another embodiment of this disclosure provides an apparatus. The apparatus includes a memory system comprising a memory device, a memory system controller, and an edge connector, wherein a light-emitting diode (LED) circuit is coupled to the edge connector and the memory controller. The memory system controller is configured to: detect the absence of an error in the LED circuit in response to an input voltage or current at a pin on the memory system controller being at a different level than an output voltage or output current at a pin on the memory system edge connector; and detect the presence of an error in the LED circuit in response to the input voltage or current at the pin on the memory system controller being at the same level as the output voltage or output current at the pin on the memory system edge connector. Attached Figure Description

[0008] Figure 1 A block diagram of a computing system including a memory system according to several embodiments of the present disclosure is shown.

[0009] Figure 2 A block diagram of a memory system including an edge connector and light-emitting diode (LED) circuitry according to several embodiments of the present disclosure is shown.

[0010] Figure 3 A schematic diagram of a light-emitting diode (LED) circuit according to several embodiments of the present disclosure is shown.

[0011] Figure 4 The following are logic tables showing the inputs and outputs of a light-emitting diode (LED) circuit according to several embodiments of the present disclosure. Detailed Implementation

[0012] This disclosure includes systems, apparatus, and methods associated with sensing for fault detection. A memory system may include a memory device, a memory system controller, and an edge connector. The memory system controller may be configured to detect an input voltage or input current at pins on the memory system controller, wherein the pins on the memory system controller are coupled to circuitry including light-emitting diodes (LEDs) (e.g., LED circuitry). The memory system controller may be configured to detect an output voltage or output current at pins on the memory system edge connector, wherein the pins on the memory system edge connector are coupled to circuitry. Based on the input voltage or input current detected at the pins on the memory system controller and the output voltage or output current detected at the pins on the memory system edge connector, errors in the circuitry can be detected.

[0013] The LED circuit can be coupled to a general purpose input / output (GPIO) pin on the edge connector. The LED in the LED circuit can be used to monitor signals from the host: the LED is activated when a signal from the host is received; the LED is deactivated when no signal from the host is received. Errors or faults may occur in the LED circuit, causing the LED to fail to activate even when a signal from the host is received. If the LED circuit is not connected to the memory controller, the memory controller cannot determine whether the LED circuit has received a signal from the host. Furthermore, if the LED circuit is not connected to the memory system controller, errors or faults in the LED circuit may go undetected, and the LED circuit may incorrectly indicate that the edge connector and / or the LED circuit itself have not received a signal from the host.

[0014] In several embodiments of this disclosure, the LED circuitry can be coupled to pins on an edge connector (e.g., GPIO pins) and to pins on a memory system controller (e.g., GPIO pins). Errors or faults in the LED circuitry can be detected by the memory system controller based on signals detected at the pins on the edge connector and the pins on the memory controller. When a high-level signal (e.g., voltage or current corresponding to a signal from the host) is detected at a pin on the edge connector and a low-level signal (e.g., voltage or current corresponding to the absence of a signal from a voltage source) is detected at a pin on the memory controller, the memory system controller can determine (e.g., detect) that no error or fault exists in the LED circuitry. Conversely, when a low-level signal (e.g., voltage or current corresponding to the absence of a signal from the host) is detected at a pin on the edge connector and a high-level signal (e.g., voltage or current corresponding to a voltage source) is detected at a pin on the memory controller, the memory system controller can determine (e.g., detect) that no error or fault exists in the LED circuitry.

[0015] When a high-level signal (e.g., voltage or current corresponding to a signal from the host) is detected at a pin on the edge connector and a high-level signal (e.g., voltage or current corresponding to a signal from a voltage source) is detected at a pin on the memory controller, the memory system controller can determine (e.g., detect) that an error or fault exists in the LED circuit. Conversely, when a low-level signal (e.g., voltage or current corresponding to the absence of a signal from the host) is detected at a pin on the edge connector and a low-level signal (e.g., voltage or current corresponding to the absence of a signal from a voltage source) is detected at a pin on the memory controller, the memory system controller can determine (e.g., detect) that an error or fault exists in the LED circuit.

[0016] In several embodiments, the LED circuitry can be used to send commands from the host to the memory system controller via pulse codes. The LED circuitry can also be used for asynchronous serial input from the host to the memory system controller. The host can send signal pulses corresponding to the binary input of the command, which can be received, stored, and executed by the memory system controller.

[0017] As used herein, “one” or “several” can refer to one or more of a certain thing, and “multiple” can refer to two or more of such things. For example, a memory device can refer to one or more memory devices, and multiple memory devices can refer to two or more memory devices.

[0018] As used herein, “device” can refer to, but is not limited to, various structures or combinations thereof, such as circuits or circuit systems, one or more dies, one or more modules, one or more devices, or one or more systems. For example, memory system 108, memory system controller 110, and memory components 116-N can be referred to individually or collectively as “device”.

[0019] The figures in this document follow a numbering convention, where the first one or more numbers correspond to the figure number, and the remaining numbers identify elements or components in the figures. Hyphens and additional numbers or letters may be used to denote similar elements within the figures. Such similar elements may generally be represented without hyphens and additional numbers or letters. For example, elements 112-00, 112-10, ..., 112-N0 may be collectively represented as 112. As used herein, the designations “N” and “X”, particularly relative to the figure reference numerals, indicate the number of specific features that may be included as specified. As will be understood, elements shown in various embodiments herein may be added, interchanged, and / or removed to provide several additional embodiments of this disclosure. Furthermore, as will be understood, the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the invention and should not be construed as limiting.

[0020] Figure 1 This is a block diagram of a computing system 100 capable of implementing several embodiments of the present disclosure, comprising a memory system 108, a memory system controller 110, and a plurality of memory components 116-00, 116-10, 116-N0, 116-01, 116-11, and 116-N1, collectively referred to as memory components 116. The memory system controller 110 includes a plurality of memory channel controllers (e.g., MCs) 112-00, 112-10, 112-N0, 112-01, 112-11, and 112-N1, collectively referred to as memory channel controllers 112, for interfacing with memory components 116 corresponding to respective memory channels 114-0 and 114-N. The computing system 100 includes a host 102 and a processor 104. The computing system 100 may be a laptop computer, personal computer, digital camera, digital recording technology and playback device, mobile phone, PDA, memory card reader, interface hub, sensor, Internet of Things (IoT) enabled device (e.g., thermostat, light bulb, lock, security system, toothbrush, pet feeder, etc.), and other systems, and the host 102 may include several processing resources 104 (e.g., one or more processors) capable of accessing the memory system 108 (e.g., via memory system controller 110). The host 102 may be responsible for executing an operating system (OS) and / or various applications that can be loaded onto it (e.g., loaded from memory system 108 via memory system controller 110).

[0021] although Figure 1 As not shown, the memory system controller may include a physical layer (PHY) for interfacing with the host 102 via an interface 106 that may include several input / output (I / O) lines. The interface 106 may include various combinations of data, address, and control buses, which may be separate buses or one or more combined buses. In at least one embodiment, the interface 106 between the memory system controller 110 and the host 102 may be a Peripheral Component Interconnect High Speed ​​(PCIe) physical and electrical interface operating according to the Computing High Speed ​​Link (CXL) protocol. In embodiments where the interface 106 operates according to the CXL protocol, the memory system controller 110 is configured to receive, (e.g., from the host) a memory access request directed to the memory device 116 according to the CXL protocol, and (e.g., to the host) provide a memory access response corresponding to the memory access request. As a non-limiting example, the interface 106 may be a PCIe 5.0 interface operating according to the CXL 2.0 specification or a PCIe 6.0 interface operating according to the CXL 3.0 specification.

[0022] CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to accelerate the performance of next-generation data centers. CXL technology maintains memory coherence between the CPU memory space and the memory on attached devices such as accelerators, memory buffers, and intelligent I / O devices. This allows resource sharing, thereby improving performance, reducing software stack complexity, and lowering total system cost. With the increasing use of accelerators to supplement CPUs to support emerging applications such as artificial intelligence and machine learning, CXL is designed as an industry-open standard interface for high-speed communication. Built on the PCIe infrastructure, CXL technology leverages PCIe physical and electrical interfaces to provide high-level protocols in areas such as input / output (I / O) protocols, memory protocols (e.g., initially allowing hosts to share memory with accelerators), and coherence interfaces. CXL provides protocols with PCIe-like I / O semantics (e.g., CXL.io), caching protocol semantics (e.g., CXL.cache), and memory access semantics (CXL.mem). CXL can support different CXL device types (e.g., Type 1, Type 2, and Type 3), thus supporting different CXL protocols. The embodiments disclosed herein are not limited to a specific CXL device type.

[0023] The memory system controller 110 may receive memory requests from the host 102 (e.g., in the form of read and / or write commands, which may be referred to as load and store commands, respectively). The memory system controller 110 may transmit commands and / or data between the host 102 and the memory system 108 through several interfaces, which may include physical interfaces, such as buses, and may employ suitable protocols. Such protocols may be custom or proprietary, or the interfaces may employ standardized protocols, such as Peripheral Component Interconnect Fast (PCIe), Gen-Z, CCIX, etc. The memory system controller 110 may include control circuitry in the form of hardware, firmware, or software, or any combination of these. For example, the memory system controller 110 may include a state machine, a sequencer, and / or some other type of control circuitry, which may be implemented as an application-specific integrated circuit (ASIC) coupled to a printed circuit board. In several embodiments, the memory system controller 110 may be co-located with the host 102 (e.g., in a system-on-a-chip (SOC) configuration). Furthermore, the memory system controller 110 may be co-located with the memory system 108.

[0024] The memory system 108 may include several physical memory "chips" or dies, each of which may contain several memory cell arrays (e.g., groups) and corresponding supporting circuitry (e.g., address circuitry, I / O circuitry, control circuitry, read / write circuitry, etc.) associated with accessing the arrays (e.g., reading data from the array and writing data to the array). For example, the memory system 108 may include several DRAM devices, SRAM devices, PCRAM devices, RRAM devices, FeRAM phase-change memory, 3DXpoint, and / or flash memory devices. In several embodiments, the memory system 108 may be used as the main memory of the computing system 100.

[0025] The memory system controller 110 can be responsible for controlling and executing various operations associated with memory access requests (e.g., read commands and write commands) from the host 102. For example, although Figure 1 Not shown, but the memory system controller 110 may include a cache and various error circuitry (e.g., error detection and / or error correction circuitry) capable of generating error detection and / or error correction data to provide data reliability, as well as other functions associated with writing data to and / or reading data from the memory component 116, which may also be referred to as memory device 116.

[0026] As described above, the memory system controller may include several memory channel controllers (e.g., media controllers) and a physical (PHY) layer that couples the memory system controller 110 to the memory device 116. As used herein, the term "PHY layer" generally refers to the physical layer in the Open Systems Interconnection (OSI) model of a computing system. The PHY layer may be the first (e.g., lowest) layer of the OSI model and may be used to transfer data via a physical data transmission medium. In various embodiments, the physical data transmission medium includes memory channels 118-00, 118-10, 118-N0, 118-01, 118-11, and 118-N1, collectively referred to as memory channel 118. For example, memory channel 118 may be a 16-bit channel coupled to a 16-bit (e.g., x16) device and two 8-bit (x8) devices, respectively; however, embodiments are not limited to a particular interface. As another example, channel 118 may also each include two pin data mask inversion (DMI) buses, and other possible bus configurations. The memory system controller 110 can exchange data (e.g., user data and error detection and / or correction data) with the memory device 116 via physical pins corresponding to the respective memory channels 118. As further described herein, in several embodiments, the memory channels 118 can be organized into several channel groups, wherein the memory channels in each group are accessed together in association with performing various memory access operations and / or error detection and / or correction operations.

[0027] like Figure 1 As shown, the memory system controller 110 includes a plurality of memory channel controllers 112 for interfacing with memory components 116 corresponding to respective memory channels 114. In this example, the memory channels 114 are organized into several channel groups 114-0, ..., 114-N. Each channel group 114 includes "N" memory channels 118. For example, channel group 114-1 includes memory channels 118-00, 118-10, ..., 118-N0, and channel group 114-N includes memory channels 118-01, 118-11, ..., 118-N1. Although each channel group is shown to include the same number of memory channels 118, the embodiment is not limited thereto.

[0028] In this example, memory channel controllers 112-00, 112-10, ..., 112-N0 corresponding to channel group 114-1 are coupled to corresponding memory components 116-00, 116-10, ..., 116-N0 via corresponding memory channels 118-00, 118-10, ..., 118-N0. In another example, memory channel controllers 112-00, 112-10, ..., 112-N0 can be implemented as a single memory channel controller driving "N" memory channels. Although Figure 1 As not shown, the memory system controller may include a PHY memory interface for coupling to memory component 116. Channel groups 114-0…114-N can be operated independently by the memory system controller 110, such that memory access requests and / or error operations can be performed separately (and simultaneously) on the memory component 116 corresponding to the respective channel group 114.

[0029] In several embodiments, memory component 116 may be a DRAM memory device, as described above. Memory components 116 may be arranged in rows such that multiple memory components 116 are coupled to the same memory channel controller 112. For example, a memory row may consist of a group of DRAM chips sharing the same chip select signal or activation signal. When the memory controller activates the chip select line, all DRAM chips in the row respond to the command simultaneously. The memory system may be arranged in one, two, or more rows. In this example, memory components 116 are arranged in rows of four, but the embodiments are not limited to this.

[0030] The memory device 116 may include multiple memory arrays, which may be grouped into one or more groups. Each memory group may contain individual rows of memory cells that can store data associated with the memory device 116 or have data write capabilities thereon.

[0031] Although not shown, a data bus, including an address bus and / or a command bus, may couple memory component 116 to memory system controller 110. The data bus may be configured to transfer data from memory component 116 to memory system controller 110, and / or transfer data from memory system controller 110 to memory component 116. The command bus may be configured to provide commands from controller 110 to memory component 116. For example, commands may include read commands and / or write commands, as well as other possible commands that may be provided to memory component 116. The address bus may contain address information associated with the commands. For example, the address associated with a read command may be provided via an address bus connected to memory device 116 and memory system controller 110. Memory device 116 may provide data in response to receiving and / or processing a read command.

[0032] Figure 2 A block diagram of a memory system 208 including an edge connector 220 and light-emitting diode (LED) circuitry 230 according to several embodiments of the present disclosure is shown. The memory system 208 includes a memory system controller 210 and a plurality of memory components 216-00, 216-10, 216-N0, 216-01, 216-11, and 216-N1, collectively referred to as memory component 116 (as per [reference]). Figure 1As described, several embodiments of the present disclosure can be implemented. The memory system controller 210 includes a plurality of memory channel controllers (e.g., MCs) 212-00, 112-10, 112-N0, 212-01, 212-11, 212-N1, collectively referred to as memory channel controllers 212, for interfacing with memory components 216 corresponding to the respective memory channels 214-0, 214-N (as described above). Figure 1 (As described).

[0033] Edge connector 220 can be configured (via Figure 1 The interface 106 shown receives signals from the host. Signals from the host can be transmitted to the memory system controller 210 via edge connector 220. LED circuitry 230 can be coupled to edge connector 220 and memory system controller 210. LED circuitry 230 can be coupled to pins (e.g., GPIO pins) on edge connector 220 and pins (e.g., GPIO pins) on memory system controller 220. LED circuitry 230 may include components such that the output on a pin of memory system controller 210 coupled to LED circuitry 230 depends on the input on a pin of edge connector 220 coupled to LED circuitry 230. The output on a pin of memory system controller 210 coupled to LED circuitry 230 and the input on a pin of edge connector 220 coupled to LED circuitry 230 can be used to determine (e.g., detect) whether an error or fault exists in the LED circuitry.

[0034] In several embodiments, LED circuitry 230 can be used to send commands from a host to memory system controller 210 via pulse codes. LED circuitry 230 can be used for asynchronous serial input from the host to memory system controller 210. The host can send signal pulses corresponding to binary input commands, which can be received, stored, and executed by memory system controller 210.

[0035] In several embodiments, a plurality of LED circuits 230 may be coupled to the memory system controller 210. The plurality of LED circuits may have pins coupled to the edge connector 220, the memory system controller 210, and / or other components on the memory system 208 configured to detect errors or faults according to embodiments of the LED circuits 230 described herein.

[0036] Figure 3 A schematic diagram of a light-emitting diode (LED) circuit 330 according to several embodiments of the present disclosure is shown. The LED circuit 330 can be coupled to an edge connector (e.g., Figure 2 Pin 332 (e.g., GPIO pin) on the edge connector 220 shown. The LED circuit 330 can be coupled to a memory system controller (e.g., ...). Figure 1 and 2 Pin 334 (e.g., a GPIO pin) on the memory system controller 110 / 210 shown. Pin 322 can be coupled to resistor 346, and resistor 346 can be coupled to the gate of transistor 342. Voltage source 336 can be coupled to resistor 338, and resistor 338 can be coupled to the input of LED 340. The output of LED 340 can be coupled to the drain of transistor 342, and coupled to resistor 348. Resistor 348 can be coupled to pin 334 on the memory system controller. The source of transistor 342 can be coupled to ground 344.

[0037] The input detected at pin 332 and the output at pin 334 can be used to detect errors or faults in LED circuit 330. Errors or faults in the LED circuit system can occur at several locations within the LED circuit. These locations may include: location A 350 between voltage source 336 and resistor 338; location B 352 between resistor 338 and LED 340; location C 354 between diode 340 and transistor 342; location D 356 between resistor 348 and pin 334; location E 358 between LED 340 and resistor 348; location F 360 between pin 332 and resistor 346; location G 362 between resistor 346 and transistor 342; location H 364 between resistor 348 and transistor 342; and / or location I 366 between transistor 342 and ground 344.

[0038] When the LED circuit is free from errors or faults, an input signal from the host can be placed on pin 332, thereby turning on transistor 342 and causing transistor 342 to provide low resistance to ground, drawing current from voltage source 336 through resistor 338 and LED 340 to ground 344. When current from voltage source 336 is drawn to ground 344 through resistor 338, LED 340, and transistor 342, pin 334 detects a low-level signal (e.g., a voltage or current corresponding to the absence of a signal from the voltage source).

[0039] When there is no signal from the host on pin 332, transistor 342 is turned off, and the current from voltage source 336 is not absorbed to ground, but is received by pin 334, causing pin 334 to detect a high-level signal (e.g., voltage or current corresponding to the signal from the voltage source).

[0040] Figure 4Logic tables associated with the inputs and outputs of a light-emitting diode (LED) circuit are shown according to several embodiments of the present disclosure. A memory system controller can determine (e.g., detect) whether an error or fault exists in the LED circuit.

[0041] When a low-level signal (e.g., voltage or current corresponding to a signal from the host) is detected at a pin on edge connector 432 and a high-level signal (e.g., voltage or current corresponding to the absence of a signal from a voltage source) is detected at a pin on memory controller 434, the error or fault determination result 470 is good, and the memory system controller can determine (e.g., detect) that there is no error or fault in the LED circuit. Conversely, when a high-level signal (e.g., voltage or current corresponding to the absence of a signal from the host) is detected at a pin on edge connector 432 and a low-level signal (e.g., voltage or current corresponding to a voltage source) is detected at a pin on memory controller 434, the error or fault determination result 470 is good, and the memory system controller can determine (e.g., detect) that there is no error or fault in the LED circuit.

[0042] When a low-level signal (e.g., voltage or current corresponding to the absence of a signal from the host) is detected at a pin on edge connector 432 and a low-level signal (e.g., voltage or current corresponding to the absence of a signal from a voltage source) is detected at a pin on memory controller 434, the error or fault determination result 470 indicates an error, and the memory system controller can determine (e.g., detect) that an error or fault exists in the LED circuit. In response to the error determination based on the low-level signal at a pin on edge connector 432 and the low-level signal at a pin on memory controller 434, the error description 472 can be location A, B, C, D, and / or E in the LED circuit (e.g., ...). Figure 3 (as shown in the image).

[0043] When a high-level signal (e.g., voltage or current corresponding to a signal from the host) is detected at a pin on edge connector 432 and a high-level signal (e.g., voltage or current corresponding to a signal from a voltage source) is detected at a pin on memory controller 434, the result 470 of the error or fault determination indicates an error, and the memory system controller can determine (e.g., detect) that an error or fault exists in the LED circuit. In response to the error determination based on the high-level signal at a pin on edge connector 432 and the high-level signal at a pin on memory controller 434, the error description 472 can be a location F, G, H, and / or I (e.g., ...) in the LED circuit. Figure 3 (as shown in the image).

[0044] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of several embodiments of this disclosure. It should be understood that the above description is illustrative rather than limiting. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of several embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of several embodiments of this disclosure should be determined by reference to the full scope of the appended claims together with the equivalents claimed by such claims.

[0045] In the foregoing detailed description, some features have been grouped together in a single embodiment for the purpose of simplification. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than are expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is, in itself, a separate embodiment.

Claims

1. A method comprising: detecting an input voltage or an input current at a pin on a memory system controller, wherein the pin on the memory system controller is coupled to a circuit including a light emitting diode (LED); detecting an output voltage or an output current at a pin on a memory system edge connector, wherein the pin on the memory system edge connector is coupled to the circuit; and detecting whether an error exists in the circuit based on the input voltage or the input current detected at the pin on the memory system controller and the output voltage or the output current detected at the pin on the memory system edge connector.

2. The method of claim 1, further comprising: detecting that no error exists in the circuit in response to determining that the input voltage or the input current detected at the pin on the memory system controller is at a high level and the output voltage or the output current detected at the pin on the memory system edge connector is at a low level.

3. The method of claim 1, further comprising: detecting that no error exists in the circuit in response to determining that the input voltage or the input current detected at the pin on the memory system controller is at a low level and the output voltage or the output current detected at the pin on the memory system edge connector is at a high level.

4. The method of claim 1, further comprising: detecting that an error exists in the circuit in response to determining that the input voltage or the input current detected at the pin on the memory system controller is at a low level and the output voltage or the output current detected at the pin on the memory system edge connector is at a low level.

5. The method of claim 4, wherein the detected error is on a path between a voltage source and the pin on the memory system controller.

6. The method of claim 1, further comprising: detecting that an error exists in the circuit in response to determining that the input voltage or the input current detected at the pin on the memory system controller is at a high level and the output voltage or the output current detected at the pin on the memory system edge connector is at a high level.

7. The method of claim 6, wherein the detected error is on a path between a drain of a transistor in the circuit and the pin on the memory system edge connector or at a source of the transistor coupled to ground.

8. An apparatus comprising: a memory system including a memory device, a memory system controller, and an edge connector, wherein the memory system controller is configured to: detect an input voltage or an input current at a pin on a memory system controller, wherein the pin on the memory system controller is coupled to a circuit including a light emitting diode (LED); detect an output voltage or an output current at a pin on a memory system edge connector, wherein the pin on the memory system edge connector is coupled to the circuit; and detect whether an error exists in the circuit based on an input voltage or input current detected at the pin on the memory system controller and an output voltage or output current detected at the pin on the memory system edge connector.

9. The apparatus of claim 8, wherein the memory controller is configured to detect that no error exists in the circuit in response to the input voltage or input current detected at the pin on the memory system controller being at a high level and the output voltage or output current detected at the pin on the memory system edge connector being at a low level.

10. The apparatus of claim 8, wherein the memory controller is configured to detect that no error exists in the circuit in response to the input voltage or input current detected at the pin on the memory system controller being at a low level and the output voltage or output current detected at the pin on the memory system edge connector being at a high level.

11. The apparatus of claim 8, wherein the memory controller is configured to detect that an error exists in the circuit in response to the input voltage or input current detected at the pin on the memory system controller being at a low level and the output voltage or output current detected at the pin on the memory system edge connector being at a low level.

12. The apparatus of claim 8, wherein the memory controller is configured to detect that an error exists in the circuit in response to the input voltage or input current detected at the pin on the memory system controller being at a high level and the output voltage or output current detected at the pin on the memory system edge connector being at a high level.

13. The apparatus of any one of claims 8-12, wherein the memory controller is configured to receive a command at a pin on a memory system controller based on a pulse code controlled by a voltage or output current at a pin on a memory system edge connector.

14. The apparatus of claim 13, wherein the apparatus includes another circuit including another LED therein, and wherein the other circuit includes an input / output pin on the memory controller configured to supply an input voltage or input current to the other circuit.

15. An apparatus comprising: a memory system including a memory device, a memory system controller, and an edge connector, wherein a light emitting diode (LED) circuit is coupled to the edge connector and the memory controller, and wherein the memory system controller is configured to: detect that no error exists in the LED circuit in response to an input voltage or input current at a pin on the memory system controller and an output voltage or output current of a pin on the memory system edge connector being at different levels; and An error is detected in the LED circuit in response to the input voltage or input current at the pin on the memory system controller being at the same level as the output voltage or the output current of the pin on the memory system edge connector.

16. The apparatus of claim 15, wherein an error is present when the input voltage or input current at the pin on the memory system controller and the output voltage or the output current of the pin on the memory system edge connector are both at a high level or both at a low level.

17. The apparatus of claim 15, wherein no error is present when the input voltage or input current at the pin on the memory system controller is at a high level and the output voltage or the output current of the pin on the memory system edge connector is at a low level.

18. The apparatus of claim 15, wherein no error is present when the input voltage or input current at the pin on the memory system controller is at a low level and the output voltage or the output current of the pin on the memory system edge connector is at a high level.

19. The apparatus of any one of claims 15-18, wherein the LED circuit includes an LED coupled to a power source, and the LED coupled to a drain of a transistor.

20. The apparatus of claim 19, wherein the pin on the memory system edge connector is coupled to a first resistor, and the first resistor is coupled to a gate of a transistor, and wherein the pin on the memory system controller is coupled to a resistor, and the resistor is coupled to an output of the LED.

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