Chip resistor and manufacturing method thereof

Abstract

The invention provides a chip resistor and a manufacturing method thereof. The chip resistor comprises a substrate, a resistive layer arranged on the substrate, two electrodes, a barrier layer and a protective layer, the resistive layer has a first surface and a second surface opposite to each other, and the substrate is located on the first surface of the resistive layer. The two electrodes are arranged at two opposite ends of the second surface of the resistive layer at intervals. The barrier layer is disposed between the electrodes and covers the second surface of the resistive layer. The protective layer is disposed on the barrier layer and covers the top surface of each electrode and the barrier layer, and the barrier layer is located between the protective layer and the second surface of the resistive layer. Therefore, the possibility that external water vapor passes through the barrier layer can be reduced, so that the influence of the water vapor on the resistance of the chip resistor is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a chip resistor, in particular to an alloy chip resistor and a manufacturing method thereof. BACKGROUND

[0002] The existing chip resistor is mainly composed of a resistor sheet (e.g., an alloy resistor sheet) attached to a substrate carrier (e.g., a FR4 glass fiber plate), and a pair of electrodes disposed on both ends of the resistor sheet by electroplating. In addition, the outer surface of the resistor sheet also includes a resin protective layer to isolate the surface of the resistor sheet from the external environment. Generally speaking, alloy chip resistors are usually used in low-voltage and high-power electronic products. When these electronic products are in operation, the temperature rises due to operation, making it difficult for water vapor to adhere to the surface of the chip resistor. However, once the electronic product stops operating, the temperature of the chip resistor also decreases. The surface of the resin protective layer is prone to water vapor condensation due to temperature differences, increasing the risk of water vapor from the resin protective layer invading the resistor sheet, thereby causing the resistor sheet to oxidize and affecting the stability of the resistance value. SUMMARY

[0003] Therefore, the present disclosure provides a chip resistor to help improve the effectiveness of the chip resistor in resisting water and moisture.

[0004] The present disclosure also provides a manufacturing method of the chip resistor.

[0005] At least one embodiment of the present disclosure provides a chip resistor, which includes a substrate, a resistor layer disposed on the substrate, two first electrodes, a barrier layer, and a protective layer. The resistor layer has a first surface and a second surface opposite to the first surface, and the substrate is located at the first surface of the resistor layer. The two first electrodes are spaced apart and disposed at opposite ends of the second surface of the resistor layer. The barrier layer is disposed between the first electrodes and covers the second surface of the resistor layer. The protective layer is disposed on the barrier layer and covers the top surface of each first electrode and the barrier layer. The barrier layer is located between the protective layer and the second surface of the resistor layer.

[0006] In at least one embodiment of the present disclosure, the resistance temperature coefficient of the barrier layer is less than the resistance temperature coefficient of the resistor layer.

[0007] In at least one embodiment of the present disclosure, the barrier layer extends between the side surface of each first electrode and the protective layer.

[0008] In at least one embodiment of the present disclosure, the wafer resistor further includes two second electrodes and two solder layers. The second electrodes are disposed on the first electrodes, respectively, and electrically connected with the first electrodes. The second electrodes cover the exposed blocks of the first electrodes by the protective layer, and a portion of the protective layer is located between the second electrodes and the first electrodes. The solder layers are disposed on the second electrodes, respectively, and the second electrodes are located between the first electrodes and the solder layers.

[0009] In at least one embodiment of the present disclosure, the thickness of the barrier layer is less than 0.003 times the thickness of the resistive layer.

[0010] In at least one embodiment of the present disclosure, the thickness of the barrier layer ranges from 0.1 μm to 3 μm.

[0011] In at least one embodiment of the present disclosure, the material of the barrier layer is selected from a group consisting of copper, nickel, chromium, aluminum, titanium, tungsten, tantalum, and combinations thereof.

[0012] In at least one embodiment of the present disclosure, the wafer resistor further includes a resistive repair region. The resistive repair region is located on the second surface of the resistive layer, and the barrier layer covers the resistive repair region.

[0013] The present disclosure also provides a method for manufacturing a wafer resistor, including providing a resistive layer having a first surface and a second surface opposite to the first surface; disposing a substrate on the first surface of the resistive layer; after disposing the substrate, depositing two first electrodes on the second surface of the resistive layer, and the first electrodes are spaced apart at opposite ends of the second surface; after depositing the first electrodes, depositing a barrier layer on the second surface of the resistive layer, and the barrier layer is located between the first electrodes; after depositing the barrier layer, forming a protective layer on the barrier layer, and the protective layer covers the top surface of each of the first electrodes and the barrier layer. The barrier layer is located between the protective layer and the second surface of the resistive layer.

[0014] In at least one embodiment of the present disclosure, the deposition of the barrier layer includes physical vapor deposition.

[0015] In at least one embodiment of the present disclosure, the method for manufacturing a wafer resistor further includes, after forming the protective layer, depositing second electrodes on the first electrodes, respectively, and the second electrodes cover the exposed blocks of the first electrodes by the protective layer; and after depositing the second electrodes, depositing a solder layer on the second electrodes, respectively. The second electrodes are located between the first electrodes and the solder layers.

[0016] In at least one embodiment of the present disclosure, the method for manufacturing a wafer resistor further includes, before depositing the barrier layer, removing a portion of the resistive layer to form a resistive repair region on the second surface of the resistive layer.

[0017] Based on the above, this disclosure provides at least one barrier layer between the second surface of the resistive layer and the protective layer. Due to the density and amorphous nature of this barrier layer, it not only reduces the possibility of external moisture passing through, thereby reducing the influence of moisture on the resistance of the wafer resistor, but also improves the temperature coefficient of resistance of the wafer resistor. Therefore, it helps to improve the overall resistance stability of the wafer resistor. Attached Figure Description

[0018] The embodiments disclosed herein can be understood from the following detailed description and accompanying drawings. It should be noted that many features are not drawn to industry-standard scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0019] FIG. 1A A perspective view of a chip resistor according to an embodiment of the present invention is shown.

[0020] FIG. 1B Draw FIG. 1A A cross-sectional view of the wafer resistor in the embodiment along section A.

[0021] FIG. 2A to FIG. 2D A cross-sectional view illustrating a method for manufacturing a wafer resistor according to an embodiment of the present invention is shown. Detailed Implementation

[0022] This disclosure will be described in detail with reference to the following embodiments. It should be noted that the following descriptions of the embodiments are for illustrative purposes only and are not intended to exhaustively disclose all embodiments or limit the specific embodiments of this disclosure. For example, the phrase "a first feature is formed on a second feature" includes various implementations, encompassing both direct contact between the first and second features and additional features formed between the first and second features so that they are not in direct contact. Furthermore, the same element symbols used in the drawings and specification will, as far as possible, represent the same or similar elements.

[0023] In the following text, to clearly present the technical features of this disclosure, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions) in the accompanying drawings will be enlarged proportionally. Therefore, the description and explanation of the embodiments below are not limited to the dimensions and shapes presented by the elements in the drawings, but should cover dimensions, shapes, and deviations from both due to actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the accompanying drawings of this disclosure are primarily for illustrative purposes and are not intended to precisely depict the actual shape of the elements, nor are they intended to limit the claims of this disclosure.

[0024] Please refer to FIG. 1A andFIG. 1B ,in FIG. 1A For at least one embodiment of the chip resistor 100 disclosed herein, and FIG. 1B The diagram shows a cross-sectional view of the wafer resistor 100 along section A. The wafer resistor 100 includes a substrate 110, a resistive layer 120, first electrodes 140a and 140b, a barrier layer 160, and a protective layer 180. The resistive layer 120 is disposed on the substrate 110 and has a first surface 120f and a second surface 120s opposite to the first surface 120f. The substrate 110 is located on the first surface 120f of the resistive layer 120, and the substrate 110 may be, for example, a polyimide (PI) film, a glass-reinforced epoxy resin laminate (e.g., FR4 fiberglass board), or a similar material.

[0025] On the other hand, although not shown in the figure, in detail, the resistive layer 120 may comprise an inner alloy base layer and an oxide layer covering the outer side of the alloy base layer. This alloy base layer may comprise, for example, copper manganese tin (CuMnSn), copper manganese nickel (CuMnNi), copper nickel alloy (CuNi), other suitable alloy materials, or any combination thereof, while the oxide layer may comprise, for example, manganese oxide, nickel oxide, copper oxide, or a combination of the aforementioned metal oxides.

[0026] First electrodes 140a and 140b are disposed at intervals at opposite ends of the second surface 120s of the resistive layer 120, such as... FIG. 1B As shown, the first electrode 140a is disposed at the left end of the resistive layer 120, while the first electrode 140b is disposed at the right end of the resistive layer 120, and there is a gap between the first electrode 140a and the first electrode 140b. The materials of the first electrode 140a and the first electrode 140b may include copper.

[0027] A barrier layer 160 is disposed between the first electrode 140a and the first electrode 140b, and covers the second surface 120s of the resistive layer 120. Notably, in this embodiment, the second surface 120s of the resistive layer 120 is completely covered by the barrier layer 160, except for the portion covered by the first electrode 140a and the first electrode 140b. In other words, the second surface 120s of the resistive layer 120 can be completely isolated from the protective layer 180.

[0028] The material of the barrier layer 160 is selected from the group consisting of copper, nickel, chromium, aluminum, titanium, tungsten, tantalum, and combinations thereof. For example, the barrier layer 160 may comprise copper-nickel (CuNi), nickel-chromium (NiCr), nickel-chromium-aluminum (NiCrAl), nickel-chromium-silicon (NiCrSi), titanium-tungsten (TiW), tantalum nitride (TaN), any combination of the above materials, or similar materials. It is worth noting that the lattice structure of the barrier layer 160 is an amorphous material. This amorphous lattice structure allows the water vapor transmission rate (WVTR) of the barrier layer 160 to be as low as 1 mg / m³. 2 • day • atm below, to help prevent external moisture from penetrating to the resistive layer 120.

[0029] In addition, the amorphous lattice structure also leads to a lower temperature coefficient of resistance (TCR). Since the barrier layer 160 and the resistive layer 120 are electrically connected in parallel, when the TCR of the barrier layer 160 is less than that of the resistive layer 120, the overall TCR of the wafer resistor 100 can be reduced through parallel connection. In other words, providing a barrier layer 160 connected in parallel with the resistive layer 120 in the wafer resistor 100 helps to improve the resistance stability of the wafer resistor 100.

[0030] In the various embodiments disclosed herein, the thickness t1 of the barrier layer 160 is less than 0.003 times the thickness t2 of the resistive layer 120. In short, the relationship between the thickness t1 of the barrier layer 160 and the thickness t2 of the resistive layer 120 is: t1 < 0.003 × t2. It is worth noting that in some embodiments, the thickness t1 of the barrier layer 160 can fall between 0.1 μm and 3 μm. Specifically, the number of barrier layers 160 in the embodiments disclosed herein is not limited to one. In other embodiments, the number of barrier layers 160 can also be one or more, such as two layers.

[0031] A protective layer 180 is disposed on the barrier layer 160 and covers the top surfaces 142t of the first electrodes 140a and 140b, as well as the barrier layer 160. FIG. 1BAs shown, the barrier layer 160 is located between the protective layer 180 and the second surface 120s of the resistive layer 120, and the barrier layer 160 also extends to the side surface 142s of the first electrode 140a (and the first electrode 140b) and the protective layer 180. Since the interface region C1 between the first electrodes 140a and 140b and the resistive layer 120 is also covered by the barrier layer 160, it can further prevent water vapor from penetrating from the interface region C1 to the resistive layer 120. The protective layer 180 may contain organic polymer materials such as polyimide or epoxy resin.

[0032] The chip resistor 100 further includes second electrodes 150a and 150b, which are respectively disposed on and electrically connected to the first electrodes 140a and 140b. The second electrodes 150a and 150b cover the area R1 of the first electrodes 140a and 140b exposed by the protective layer 180, with a portion of the protective layer 180 located between the first electrodes 140a and 150a, and another portion located between the first electrodes 140b and 150b. In other words, the second electrodes 150a and 150b also partially cover the protective layer 180.

[0033] It is worth mentioning that the second electrodes 150a and 150b cover the top surface 180t of the protective layer 180. In this embodiment, the top surface 150t of the second electrodes 150a (and 150b) is higher than the top surface 180t, and the distance d1 between the top surfaces 150t and 180t is 5 μm or more, but this disclosure is not limited thereto. In other embodiments, the distance d1 between the top surfaces 150t and 180t may be less than 5 μm. The material of the second electrodes 150a and 150b may include copper.

[0034] In addition, the chip resistor 100 also includes a solder layer 170a and a solder layer 170b. Solder layers 170a and 170b are respectively disposed on second electrodes 150a and 150b, wherein these second electrodes are located between the first electrode and the solder layers. Specifically, second electrode 150a is located between the first electrode 140a and the solder layer 170a, while second electrode 150b is located between the first electrode 140b and the solder layer 170b. The materials of solder layers 170a and 170b may include nickel, tin, similar solder metals, or combinations thereof.

[0035] The wafer resistor 100 also includes a resistance-correcting region 190. In this embodiment, the resistance-correcting region 190 is located on the second surface 120s of the resistive layer 120, and the barrier layer 160 covers the resistance-correcting region 190. However, the number and location of the resistance-correcting regions 190 in this disclosure are not limited to this embodiment. In other embodiments, the number of resistance-correcting regions 190 may be more than one, and the resistance-correcting regions 190 may be distributed on the first electrode 140a or the first electrode 140b.

[0036] Depend on FIG. 2A to FIG. 2D The following steps illustrate a method for manufacturing a wafer resistor according to at least one embodiment of this disclosure. Please refer to... FIG. 2A First, a resistive layer 120 is provided. In detail, the method of providing the resistive layer 120 in this embodiment includes: heating an alloy substrate (not shown) in a nitrogen environment with a low oxygen content (e.g., oxygen content ≤ 50 ppm), and maintaining the temperature of the nitrogen environment between 200°C and 400°C, so that the surface of the alloy substrate is oxidized to form an oxide layer (not shown).

[0037] Next, as FIG. 2A As shown, the substrate 110 can be disposed on the first surface 120f of the resistive layer 120 by, for example, thermoforming. Please refer to... FIG. 2B After the substrate 110 is set, the first electrode 140a and the first electrode 140b are deposited on the second surface 120s of the resistive layer 120. For example, a patterned anti-plating protective layer can be formed on the resistive layer 120 by printing (or lamination) and photolithography. This anti-plating protective layer can be a material such as photoresist, removable adhesive film or ink.

[0038] Then, a portion of the oxide layer of the resistive layer 120 (i.e., the oxide layer of the area to be electroplated) is removed by chemical etching (e.g., acidic solution etching) to expose the alloy substrate of the area to be electroplated to the second surface 120s. Next, a metal material, such as copper, is deposited on the resistive layer 120 by electroplating, and the patterned anti-plating protective layer is removed by using a film-removing solvent or water washing to form the first electrode 140a and the first electrode 140b on the resistive layer 120.

[0039] Next, please refer to FIG. 2CAfter depositing the first electrodes 140a and 140b, a barrier layer 160 can be deposited on the second surface 120s of the resistive layer 120 by means of physical vapor deposition (PVD), such as sputtering. Specifically, a patterned sputtered protective layer (not shown) can first be formed on the resistive layer 120 and the first electrodes 140a and 140b by printing (or lamination) and photolithography. This sputtered protective layer covers the top surface 142t of the first electrodes 140a and 140b and exposes the second surface 120s of the resistive layer 120. Then, an initial barrier layer (not shown) is deposited on the second surface 120s of the resistive layer 120 and the surface of the sputtered protective layer by sputtering. Next, the sputtered protective layer and a portion of the initial barrier layer covering the sputtered protective layer can be removed by chemical etching to form the barrier layer 160.

[0040] It is worth mentioning that, please return to FIG. 2B The method of manufacturing the wafer resistor 100 also includes removing a portion of the resistor layer 120 by laser trimming or mechanical processing before depositing the barrier layer 160, so as to form a trimming region 190 for resistance adjustment on the second surface 120s of the resistor layer 120, so that the resistor layer 120 obtains the desired target resistance value.

[0041] Next, please refer to FIG. 2D After depositing the barrier layer 160, a protective layer 180 is formed on the barrier layer 160. Specifically, an initial protective layer can be formed on the barrier layer 160 and the top surfaces 142t of the first electrodes 140a and 140b by means of, for example, lamination, printing, or coating. Next, a portion of the initial protective layer is removed by photolithography to form the protective layer 180, exposing the block R1 of the top surfaces 142t of the first electrodes 140a and 140b.

[0042] Please refer to this as well. FIG. 1B and FIG. 2D The method of manufacturing the wafer resistor 100 further includes: after forming the protective layer 180, depositing the second electrode 150a and the second electrode 150b on the first electrode 140a and the first electrode 140b respectively by means of, for example, electroplating, and making the second electrode 150a and the second electrode 150b cover the block R1 of the first electrode 140a and the first electrode 140b exposed by the protective layer 180.

[0043] In addition, after depositing the second electrode 150a and the second electrode 150b, a solder layer 170a and a solder layer 170b are deposited on the second electrode 150a and the second electrode 150b, respectively, to provide the function of soldering and bonding between the wafer resistor 100 and the external circuit board. Since the method of depositing the second electrode 150a (and the second electrode 150b) and the method of depositing the solder layer 170a (and the solder layer 170b) are the same as the method of depositing the first electrode 140a (and the first electrode 140b), they will not be repeated here. At this point, the wafer resistor 100 of at least one embodiment of this disclosure is essentially complete.

[0044] In summary, by providing at least one barrier layer between the second surface of the resistive layer and the protective layer, the density and amorphous nature of this barrier layer not only reduce the possibility of external moisture passing through it, thus reducing the influence of moisture on the resistance of the wafer resistor, but also improve the temperature coefficient of resistance of the wafer resistor. This, in turn, helps to improve the stability of the resistance value of the wafer resistor.

[0045] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art to which this disclosure pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

[0046] [Symbol Explanation]

[0047] 100: Chip Resistor

[0048] 110: Substrate

[0049] 120: Resistive layer

[0050] 120f: First surface

[0051] 120s: Second surface

[0052] 140a, 140b: First electrode

[0053] 142t, 150t, 180t: Top surface

[0054] 142s: Side surface

[0055] 150a, 150b: Second electrode

[0056] 160: Barrier layer

[0057] 170a, 170b: Weld layer

[0058] 180: Protective layer

[0059] 190: Repairing the obstruction zone

[0060] A: Cross section

[0061] C1: Boundary Area

[0062] d1: Spacing

[0063] R1: Block

[0064] t1, t2: thickness.

Claims

1. A wafer resistor, characterized in that, Include: Substrate; A resistive layer is disposed on the substrate, and the resistive layer has a first surface and a second surface opposite to the first surface, wherein the substrate is located on the first surface of the resistive layer; Two first electrodes are disposed at intervals at opposite ends of the second surface of the resistive layer; A barrier layer is disposed between the first electrodes and covers the second surface of the resistive layer; as well as A protective layer is disposed on the barrier layer and covers the top surface of each of the first electrodes and the barrier layer, wherein the barrier layer is located between the protective layer and the second surface of the resistive layer.

2. The wafer resistor according to claim 1, characterized in that, The temperature coefficient of resistance of the barrier layer is less than that of the resistance layer.

3. The wafer resistor according to claim 1, characterized in that, The barrier layer extends to the side surface of each of the first electrodes and between the protective layer.

4. The wafer resistor according to claim 1, characterized in that, Also includes: Two second electrodes are respectively disposed on the first electrode and electrically connected to the first electrode, wherein the second electrodes cover the area of ​​the first electrode exposed by the protective layer, and a portion of the protective layer is located between the second electrodes and the first electrode; as well as Two welding layers are respectively disposed on the second electrode, wherein the second electrode is located between the first electrode and the welding layers.

5. The wafer resistor according to claim 1, characterized in that, The thickness of the barrier layer is less than 0.003 times the thickness of the resistive layer.

6. The wafer resistor according to claim 1, characterized in that, The thickness of the barrier layer ranges from 0.1 μm to 3 μm.

7. The wafer resistor according to claim 1, characterized in that, The material of the barrier layer is selected from the group consisting of copper, nickel, chromium, aluminum, titanium, tungsten, tantalum and combinations thereof.

8. The wafer resistor according to claim 1, characterized in that, Also includes: A resistance repair region is located on the second surface of the resistive layer, wherein the barrier layer covers the resistance repair region.

9. A method for manufacturing a wafer resistor, characterized in that, Include: A resistive layer is provided, and the resistive layer has a first surface and a second surface opposite to the first surface; A substrate is disposed on the first surface of the resistive layer; After the substrate is disposed, two first electrodes are deposited on the second surface of the resistive layer, and the first electrodes are disposed at opposite ends of the second surface at a distance from each other. After depositing the first electrode, a barrier layer is deposited on the second surface of the resistive layer, and the barrier layer is located between the first electrodes; as well as After depositing the barrier layer, a protective layer is formed on the barrier layer, and the protective layer covers the top surface of each of the first electrodes and the barrier layer, wherein the barrier layer is located between the protective layer and the second surface of the resistive layer.

10. The method according to claim 9, characterized in that, The barrier layer is deposited via physical vapor deposition.

11. The method according to claim 9, characterized in that, Also includes: After the protective layer is formed, a second electrode is deposited on the first electrode, and the second electrode covers the area of ​​the first electrode exposed by the protective layer; as well as After depositing the second electrode, a weld layer is deposited on the second electrode, wherein the second electrode is located between the first electrode and the weld layer.

12. The method according to claim 9, characterized in that, Also includes: Before depositing the barrier layer, a portion of the resistive layer is removed to form a repair region on the second surface of the resistive layer.

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