Oblique wave compensation circuit of switching power supply and switching power supply

Abstract

The invention discloses a ramp compensation circuit of a switching power supply and the switching power supply, the switching power supply comprises a high-side power tube and a low-side power tube, and the ramp compensation circuit comprises a signal input module, a capacitor charging driving module, a current release module and a ramp compensation output module; the input end of the signal input module is connected to a common node of the high-side power tube and the low-side power tube, and the signal input module is used for generating direct-current voltage according to voltage on the common node and converting the direct-current voltage into direct current; the capacitor charging driving module is used for charging the capacitor unit according to the current formed by superposition of the direct current and the first bias current; the current release module is used for completely releasing the current or current of the capacitor unit; and the oblique wave compensation output module is used for converting the sampling current into a current sampling voltage, converting the second bias current into a direct current bias voltage, superposing the current sampling voltage, the voltage at the two ends of the capacitor unit and the direct current bias voltage and then outputting the superposed voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics, and particularly relates to a ramp compensation circuit of a switching power supply and the switching power supply. BACKGROUND

[0002] The control mode of power supply design is mainly divided into two categories of voltage mode control and current mode control. Compared with voltage mode control, current mode control has the advantages of fast dynamic response speed, large bandwidth gain, simplified feedback loop design and easy current sharing when parallel output, and is widely used.

[0003] Peak current mode control is the most common form of current mode control, but when the pulse width modulation (PWM) duty cycle is greater than 50%, the system is easy to enter the state of unstable subharmonic oscillation, and the switching waveform of the power tube alternately appears in the state of wide pulse and narrow pulse. Subharmonic oscillation will lead to poor stability of the system, so a ramp compensation signal needs to be introduced to suppress the occurrence of subharmonic oscillation.

[0004] The strength of the introduced ramp compensation signal is too small to meet the system stability under the condition of large duty cycle; the amplitude of the introduced ramp signal is too large, which will lead to the transition of peak current mode to voltage mode, and the advantages of current mode control are lost. At the same time, since the voltage mode needs to use three type compensation, it will also lead to the instability of the system. Therefore, the slope of the ramp compensation is the key factor affecting the ramp compensation signal. The ramp compensation signal affects the output voltage of the switching power supply, and the output voltage of the switching power supply needs to be compared with the output signal of the error amplifier in the peak current mode control loop after being processed by the voltage dividing resistor. Therefore, the range of the ramp compensation signal needs to consider the output range of the error amplifier in the loop, so the valley value of the ramp compensation signal needs to be reasonably designed. SUMMARY

[0005] The present application provides a ramp compensation circuit of a switching power supply and the switching power supply, which can output a ramp compensation signal with a fixed valley voltage, which is beneficial to avoid the output voltage of the error amplifier in the loop of the switching power supply exceeding the normal working range, thereby improving the stability of the switching power supply.

[0006] In a first aspect, an embodiment of the present application provides a ramp compensation circuit of a switching power supply, characterized in that the switching power supply comprises a high-side power transistor and a low-side power transistor, and the ramp compensation circuit comprises a signal input module, a capacitor charging driving module and a ramp compensation output module; the input end of the signal input module is connected to a common node of the high-side power transistor and the low-side power transistor, the signal input module is configured to generate a direct current voltage according to the voltage on the common node and convert the direct current voltage into a direct current; the capacitor charging driving module is connected to the signal input module and the first end of a capacitor unit in the ramp compensation output module and is connected to a first bias current, and is configured to charge the capacitor unit according to the current formed by superimposing the direct current and the first bias current; a current release module is connected to the capacitor charging driving module and the second end of the capacitor unit, and is configured to completely release the current of the capacitor unit; the ramp compensation output module is connected to a second bias current and a sampling current of the high-side power transistor, and is configured to convert the sampling current into a current sampling voltage, convert the second bias current into a direct current bias voltage, and superimpose the current sampling voltage, the voltage across the capacitor unit and the direct current bias voltage and output.

[0007] Optionally, the ramp compensation output module comprises a capacitor unit, a first resistor unit and a second resistor unit; the first end of the capacitor unit is connected to the capacitor charging driving module, the second end of the capacitor unit is connected to the current release module and the first end of the first resistor unit, and is connected to the second bias current; the second end of the first resistor unit is connected to the first end of the second resistor unit, and is connected to the sampling current of the high-side power transistor, and the second end of the second resistor unit is grounded.

[0008] Optionally, the capacitor unit comprises a first capacitor, the first resistor unit comprises a first resistor, and the second resistor unit comprises a second resistor; the first end of the first capacitor serves as the first end of the capacitor unit, and the second end of the first capacitor serves as the second end of the capacitor unit; the first end of the first resistor serves as the first end of the first resistor unit, and the second end of the first resistor serves as the second end of the first resistor unit; the first end of the second resistor serves as the first end of the second resistor unit, and the second end of the second resistor serves as the second end of the second resistor unit; and the resistance of the first resistor is much greater than the resistance of the second resistor.

[0009] Optionally, the signal input module comprises an amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a second capacitor, a third capacitor and a first transistor; a first end of the third resistor is an input end of the signal input module; a second end of the third resistor is connected with a first end of the fourth resistor and a first end of the fifth resistor; a second end of the fourth resistor is grounded; a second end of the fifth resistor is connected with a first end of the second capacitor and a first end of the sixth resistor; a second end of the second capacitor is grounded; a first end of the third capacitor is connected with a second end of the sixth resistor and a first input end of the amplifier; a second end of the third capacitor is grounded; a second input end of the amplifier is connected with a first pole of the first transistor and a first end of the seventh resistor; an output end of the amplifier is connected with a gate of the first transistor; a second pole of the first transistor is connected with the capacitor charging driving module; and a second end of the seventh resistor is grounded.

[0010] Optionally, the capacitor charging driving module comprises a first current mirror unit and a second current mirror unit; a first end of the first current mirror unit is connected with the second pole of the first transistor; a second end of the first current mirror unit is connected with a power supply voltage; a third end of the first current mirror unit is connected with the current release module; a fourth end of the first current mirror unit is connected with a first end of the capacitor unit and serves as an output end of the ramp compensation circuit; a first end of the second current mirror unit is connected with the second pole of the first transistor; a second end of the second current mirror unit is connected with a first bias current; and a third end of the second current mirror unit is grounded.

[0011] Optionally, the first current mirror unit comprises a second transistor, a third transistor and a fourth transistor; a first pole of the second transistor is connected with the power supply voltage; a second pole of the second transistor is connected with the second pole of the first transistor; a gate of the second transistor is connected with the second pole of the second transistor, a gate of the third transistor and a gate of the fourth transistor; a first pole of the third transistor is connected with the power supply voltage; a second pole of the third transistor is connected with the current release module; a first pole of the fourth transistor is connected with the power supply voltage; and a second pole of the fourth transistor is connected with the first end of the capacitor unit; and / or, the second current mirror unit comprises a fifth transistor and a sixth transistor; a first pole of the fifth transistor is grounded; a second pole of the fifth transistor is connected with the second pole of the first transistor; a gate of the fifth transistor is connected with a gate of the sixth transistor; a first pole of the sixth transistor is grounded; a second pole of the sixth transistor is connected with the gate of the sixth transistor and the first bias current.

[0012] Optionally, the current release module comprises a third current mirror unit; a first end of the third current mirror unit is connected with the capacitor charging driving module; a second end of the third current mirror unit is connected with a second end of the capacitor unit; and a third end of the third current mirror unit is grounded.

[0013] Optionally, the third current mirror unit comprises a seventh transistor and an eighth transistor; the first pole of the seventh transistor is connected to the ground, the second pole of the seventh transistor is connected to the capacitor charging driving module, and the gate of the seventh transistor is connected to the second pole of the seventh transistor and the eighth transistor; the first pole of the eighth transistor is connected to the ground, and the second pole of the eighth transistor is connected to the second end of the capacitor unit.

[0014] Optionally, the ramp compensation circuit of the switching power supply further comprises a switching module, the control end of the switching module is connected to the reset signal, the first end of the switching module is connected to the first end of the capacitor unit, the second end of the switching module is connected to the second end of the capacitor unit, and the switching module is used to control the conduction and the turn-off of the switching module according to the reset signal to realize the charging and discharging operation of the capacitor unit.

[0015] In the second aspect, the embodiments of the present application provide a switching power supply comprising the ramp compensation circuit of the switching power supply provided by any of the embodiments of the present application.

[0016] The ramp compensation circuit provided by the embodiments of the present application comprises a signal input module, a capacitor charging driving module, a current release module and a ramp compensation output module. The signal input module generates a direct current voltage from the voltage on the common node and converts the direct current voltage into a direct current. The capacitor charging driving module charges the capacitor unit by using the current obtained by superimposing the direct current and a first bias current, so that the voltage change related to the output voltage of the switching power supply is generated across the capacitor unit. The current release module ensures that the current of the capacitor unit can be completely released, and no additional voltage drop or voltage rise is generated in the ramp compensation output module, so that the ramp compensation output module can output the ramp compensation signal with a fixed valley voltage, which is beneficial to avoid the output voltage of the error amplifier in the loop of the switching power supply exceeding the normal working range, thereby improving the stability of the switching power supply.

[0017] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0019] Figure 1 is a structural schematic diagram of a ramp compensation circuit provided by the embodiments of the present application;

[0020] Figure 2This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention;

[0027] Figure 9 This is a waveform diagram of a ramp compensation circuit provided in an embodiment of the present invention;

[0028] Figure 10 This is a schematic diagram of a switching power supply provided in an embodiment of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0031] Figure 1This is a schematic diagram of a ramp compensation circuit provided in an embodiment of the present invention. The switching power supply includes a high-side power transistor and a low-side power transistor. For example... Figure 1 As shown, the ramp compensation circuit includes: a signal input module 11, a capacitor charging drive module 12, a current release module 13, and a ramp compensation output module 14.

[0032] The input terminal of the signal input module 11 is connected to the common node Com1 of the high-side power transistor and the low-side power transistor. The signal input module 11 is used to generate a DC voltage based on the voltage on the common node Com1 and convert the DC voltage into a DC current.

[0033] The capacitor charging drive module 12 is connected to the first end of the capacitor unit 140 in the signal input module 11 and the ramp compensation output module 14, and is connected to the first bias current I1, which is used to charge the capacitor unit 140 according to the current formed by the superposition of the DC current and the first bias current I1.

[0034] The current release module 13 is connected to the capacitor charging drive module 12 and the second end of the capacitor unit 140, and is used to completely release the current of the capacitor unit 140.

[0035] The ramp compensation output module 14 is connected to the second bias current I2 and the sampling current Is1 of the high-side power transistor. It is used to convert the sampling current Is1 into a current sampling voltage, convert the second bias current I2 into a DC bias voltage, and output the current sampling voltage, the voltage across the capacitor unit and the DC bias voltage.

[0036] Specifically, the signal input module 11 divides and filters the voltage on the common node Com1 to obtain a DC voltage, and then converts the DC voltage into a DC current, reflecting the changes in the voltage of the common node.

[0037] The capacitor charging drive module 12 is connected to the signal input module 11 on one hand to receive the DC current output by the signal input module 11; on the other hand, it is connected to the first bias current I1. It superimposes these two currents to form a new current, which is used to charge the capacitor unit 140 in the ramp compensation output module 14. In this way, the voltage across the capacitor unit 140 will gradually increase during the charging process, and this voltage change will be used as part of the ramp compensation signal VRAMP.

[0038] In the ramp compensation circuit, capacitor unit 140 is charged or discharged according to the current provided by capacitor charging drive module 12. When capacitor unit 140 is charging, current flows into capacitor unit 140, and the voltage across capacitor unit 140 increases; when capacitor unit 140 is discharging, current flows out of capacitor unit 140, and the voltage across capacitor unit 140 decreases. If the current in capacitor unit 140 is not properly managed, this current will generate additional voltage drop or voltage rise in ramp compensation output module 14, causing the valley voltage of ramp compensation signal VRAMP to be unstable, thereby affecting the normal operation of the switching power supply.

[0039] Specifically, during the operation of a switching power supply, the output voltage of the error amplifier in the control loop has a certain range. If the valley voltage of the ramp compensation signal is too low, the maximum duty cycle of the switching power supply will be limited, preventing the output voltage from rising further and reaching the set value. For example, if the reference voltage is a fixed value, but the feedback voltage is too low or too high, resulting in a large difference between the two, the error amplifier may not be able to output a sufficiently large or small voltage to correctly adjust the operating state of the switching power supply, and may even enter a saturated or cutoff state, causing the control loop to fail and severely affecting the stability of the switching power supply.

[0040] When capacitor unit 140 needs charging, the charging current provided by capacitor charging drive module 12 flows into capacitor unit 140 through its first terminal to charge it and flows out through its second terminal. When capacitor unit 140 needs discharging, the discharging current also flows out through its second terminal. In other words, regardless of whether capacitor unit 140 is charging or discharging, the current flows into current release module 13, which provides a low-impedance release path for the current in capacitor unit 140.

[0041] Through the function of the current release module 13, the current of the capacitor unit 140 is effectively guided and controlled, avoiding additional voltage fluctuations in the ramp compensation output module 14 caused by the current of the capacitor unit 140, thereby ensuring that the valley voltage of the ramp compensation signal can be fixed. For example, during one operating cycle of the switching power supply, when the ramp compensation signal is in the valley stage, if the capacitor unit 140 is discharging, the current release module 13 will ensure that the discharge current of the capacitor unit 140 does not cause an undue drop in the valley voltage, maintaining the valley voltage of the ramp compensation signal VRAMP fixed. This helps to prevent the output voltage of the error amplifier in the loop of the switching power supply from exceeding the normal operating range, thereby improving the stability of the switching power supply.

[0042] The ramp compensation output module 14 is connected to the second bias current I2 and the sampling current Is1 of the high-side power transistor. It converts the second bias current I2 and the sampling current Is1 of the high-side power transistor into a DC bias voltage and a current sampling voltage, respectively, and then superimposes them with the voltage across the capacitor unit before outputting the signal. This superimposed signal serves as the ramp compensation signal VRAMP, which is compared with the output signal of the error amplifier in the peak current mode control loop. This comparison controls the on / off state of the high-side and low-side power transistors in the switching power supply, suppressing subharmonic oscillations.

[0043] The ramp compensation circuit provided in this embodiment of the invention includes a signal input module, a capacitor charging drive module, a current release module, and a ramp compensation output module. The signal input module generates a DC voltage from the voltage at the common node and converts the DC voltage into a DC current. The capacitor charging drive module uses this DC current, combined with a first bias current, to charge the capacitor unit, causing a voltage change across the capacitor unit that is related to the output voltage of the switching power supply. The current release module ensures that the current in the capacitor unit is completely released, preventing additional voltage drops or rises in the ramp compensation output module. This allows the ramp compensation output module to output a ramp compensation signal with a fixed valley voltage, which helps prevent the output voltage of the error amplifier in the switching power supply loop from exceeding the normal operating range, thereby improving the stability of the switching power supply.

[0044] Figure 2 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention. Figure 2 As shown, optionally, the ramp compensation output module 14 includes a capacitor unit 140, a first resistor unit 141, and a second resistor unit 142. The first end of the capacitor unit 140 is connected to the capacitor charging drive module 12, and the second end of the capacitor unit 140 is connected to the current release module 13 and the first end of the first resistor unit 141, and is connected to the second bias current I2; the second end of the first resistor unit 141 is connected to the first end of the second resistor unit 142, and is connected to the sampling current Is1 of the high-side power transistor, and the second end of the second resistor unit 142 is grounded.

[0045] As a preferred embodiment of the present invention, Figure 3 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention. Figure 3 As shown, optionally, capacitor unit 140 includes a first capacitor C1, first resistor unit 141 includes a first resistor R1, and second resistor unit 142 includes a second resistor R2.

[0046] The first terminal of the first capacitor C1 serves as the first terminal of capacitor unit 140, and the second terminal of the first capacitor C1 serves as the second terminal of capacitor unit 140. The first terminal of the first resistor R1 serves as the first terminal of first resistor unit 141, and the second terminal of the first resistor R1 serves as the second terminal of first resistor unit 141. The first terminal of the second resistor R2 serves as the first terminal of second resistor unit 142, and the second terminal of the second resistor R2 serves as the second terminal of second resistor unit 142; wherein, the resistance of the first resistor R1 is much greater than the resistance of the second resistor R2.

[0047] The ramp compensation output module 14 superimposes the current sampling voltage, the voltage across the capacitor unit, and the DC bias voltage. The current sampling voltage is the product of the sampling current Is1 of the high-side power transistor and the second resistor R2. The DC bias voltage is the product of the second bias current I2 and the sum of the first resistor R1 and the second resistor R2. The sum of the current sampling voltage and the DC bias voltage is the lower plate voltage Vbottom of the first capacitor C1. Since the resistance of the first resistor R1 is much larger than the resistance of the second resistor R2, the DC bias voltage VDC of the lower plate voltage of the first capacitor C1 is approximately equal to the product of the second bias current I2 and the first resistor R1. The ramp compensation signal VRAMP is the lower plate voltage Vbottom of the first capacitor C1 superimposed with the voltage across the capacitor unit. The valley voltage of the ramp compensation signal VRAMP is the product of the second bias current I2 and the sum of the first resistor R1 and the second resistor R2. Since the second bias current I2, the first resistor R1, and the second resistor R2 are all fixed values, the valley voltage of the ramp compensation signal VRAMP is also a fixed value.

[0048] Figure 4 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention. Figure 4 As shown, optionally, the signal input module 11 includes an amplifier Av1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a second capacitor C2, a third capacitor C3, and a first transistor T1.

[0049] The first end of the third resistor R3 serves as the input terminal of the signal input module 11, and the second end of the third resistor R3 is connected to the first end of the fourth resistor R4 and the first end of the fifth resistor R5.

[0050] The second terminal of the fourth resistor R4 is grounded, the second terminal of the fifth resistor R5 is connected to the first terminal of the second capacitor C2 and the first terminal of the sixth resistor R6, and the second terminal of the second capacitor C2 is grounded.

[0051] The first terminal of the third capacitor C3 is connected to the second terminal of the sixth resistor R6 and the first input terminal of the amplifier Av1, and the second terminal of the third capacitor C3 is grounded.

[0052] The second input terminal of amplifier Av1 is connected to the first terminal of the first transistor T1 and the first terminal of the seventh resistor R7. The output terminal of amplifier Av1 is connected to the gate of the first transistor T1. The second terminal of the first transistor T1 is connected to the capacitor charging drive module 12. The second terminal of the seventh resistor R7 is grounded.

[0053] Specifically, the third resistor R3 serves as the input terminal of the signal input module 11, responsible for acquiring the voltage of the common node Com1 of the high-side power transistor and the low-side power transistor. The acquired voltage is divided in a voltage divider circuit composed of the third resistor R3, the fourth resistor R4, and the fifth resistor R5. The fourth resistor R4 is grounded, and its function is to provide a reference potential for the voltage division, so that the divided voltage has a stable reference.

[0054] The second terminal of the fifth resistor R5 is connected to the second capacitor C2 and the sixth resistor R6. The second capacitor C2 acts as a filter, effectively removing high-frequency noise and spurious waves from the voltage after voltage division, making the voltage signal more stable.

[0055] The filtered voltage is input to the first input terminal of amplifier Av1 through the third capacitor C3. The third capacitor C3 further isolates the DC component, preventing DC bias from interfering with the operation of amplifier Av1, while allowing AC signals to pass through. The second input terminal of amplifier Av1 is connected to the first terminal of the first transistor T1 and the seventh resistor R7. Amplifier Av1 amplifies and adjusts the input voltage signal. Its output terminal is connected to the gate of the first transistor T1, and the conduction level of the first transistor T1 is adjusted by controlling the gate voltage. The second terminal of the first transistor T1 is connected to the capacitor charging drive module 12, and the second terminal of the seventh resistor R7 is grounded. According to the characteristics of transistors and Ohm's law, in the circuit formed by the first transistor T1 and the seventh resistor R7, the voltage change output by amplifier Av1 is converted into a current change, thereby converting the previously obtained DC voltage into a DC current output to the capacitor charging drive module 12. Optionally, the first transistor T1 is an N-type transistor.

[0056] Figure 5 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention. Figure 5 As shown, optionally, the capacitor charging drive module 12 includes a first current mirror unit 121 and a second current mirror unit 122.

[0057] The first terminal of the first current mirror unit 121 is connected to the second terminal of the first transistor T1, the second terminal of the first current mirror unit 121 is connected to the power supply voltage VDD, the third terminal of the first current mirror unit 121 is connected to the current release module 13, and the fourth terminal of the first current mirror unit 121 is connected to the first terminal of the capacitor unit 140 and serves as the output terminal of the ramp compensation circuit.

[0058] The first terminal of the second current mirror unit 122 is connected to the second terminal of the first transistor T1, the second terminal of the second current mirror unit 122 is connected to the first bias current I1, and the third terminal of the second current mirror unit 122 is grounded.

[0059] Continue to refer to Figure 5 Optionally, the first current mirror unit 121 includes a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0060] The first terminal of the second transistor T2 is connected to the power supply voltage VDD. The second terminal of the second transistor T2 is connected to the second terminal of the first transistor T1. The gate of the second transistor T2 is connected to the second terminal of the second transistor T2, the gate of the third transistor T3, and the gate of the fourth transistor T4. The first terminal of the third transistor T3 is connected to the power supply voltage VDD, and the second terminal of the third transistor T3 is connected to the current release module 13. The first terminal of the fourth transistor T4 is connected to the power supply voltage VDD, and the second terminal of the fourth transistor T4 is connected to the first terminal of the capacitor unit 140.

[0061] And / or, the second current mirror unit 122 includes a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is grounded, the second terminal of the fifth transistor T5 is connected to the second terminal of the first transistor T1, and the gate of the fifth transistor T5 is connected to the gate of the sixth transistor T6. The first terminal of the sixth transistor T6 is grounded, the second terminal of the sixth transistor T6 is connected to the gate of the sixth transistor T6, and a first bias current I1 is applied.

[0062] Specifically, the second terminal of the fifth transistor T5 is connected to the second terminal of the first transistor T1, using the first bias current I1 as the reference current. According to the current mirror principle, assuming the scaling factor of the second current mirror unit 122 is k1, the current IT5 of the fifth transistor T5 is k1. I1.

[0063] The second transistor T2 operates in diode configuration, with its gate and drain connected. Its first terminal is connected to the power supply voltage VDD, and its second terminal is connected to the second terminal of the first transistor T1 in the signal input module 12. Thus, the sum of the DC current IT1 output by the first transistor T1 and the current of the fifth transistor T5 is used as the reference current Iref. That is, Iref = IT1 + k1 I1. Since the gates of the third transistor T3 and the fourth transistor T4 are connected to the gate of the second transistor T2, under good transistor characteristic matching, according to the current mirror principle, the currents of the third transistor T3 and the fourth transistor T4 will have a fixed proportional relationship with the current of the second transistor T2. This proportionality coefficient can usually be determined by designing the transistor's size ratio (e.g., aspect ratio). Assuming the proportionality coefficient of the first current mirror unit 121 is k2, then the current IT4 of the fourth transistor T4 = k2. Iref=I2 (IT1+k1) I1).

[0064] Figure 6 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention. Figure 6 As shown, optionally, the current release module 13 includes a third current mirror unit 130.

[0065] The first end of the third current mirror unit 130 is connected to the capacitor charging drive module 12, the second end of the third current mirror unit 130 is connected to the second end of the capacitor unit 140, and the third end of the third current mirror unit 130 is grounded.

[0066] Continue to refer to Figure 6 The third current mirror unit 130 includes a seventh transistor T7 and an eighth transistor T8.

[0067] The first terminal of the seventh transistor T7 is grounded, the second terminal of the seventh transistor T7 is connected to the capacitor charging drive module 12, and the gate of the seventh transistor T7 is connected to the second terminal of the seventh transistor T7 and the eighth transistor T8. The first terminal of the eighth transistor T8 is grounded, and the second terminal of the eighth transistor T8 is connected to the second terminal of the capacitor unit 140.

[0068] When the gate and second terminal (usually the drain) of the seventh transistor T7 are connected together, it operates in diode configuration, and its current IT7 can be used as a reference current. Since the gate of the eighth transistor T8 is connected to the gate of the seventh transistor T7, according to transistor characteristics, under certain conditions (such as identical transistor process parameters and temperature), the current IT8 of the eighth transistor T8 will be proportional to the current IT7 of the seventh transistor T7. Ideally, if the two transistors have the same dimensions (width-to-length ratio), then IT8 = IT7.

[0069] When capacitor cell 140 is charging, capacitor charging drive module 12 provides charging current to capacitor cell 140. When charging capacitor cell 140, current flows in from the first terminal and out from the second terminal. Simultaneously, the charging current also flows into the second terminal of the seventh transistor T7, causing the seventh transistor T7 to conduct and generate a reference current. Based on the characteristics of a current mirror, the current flowing through the eighth transistor T8 is equal to the current flowing through the seventh transistor T7. This means that when current flows out from the second terminal of capacitor cell 140, the eighth transistor T8 provides a low-impedance path for these currents. Since the eighth transistor T8 is connected to the second terminal of capacitor cell 140, all the current at the second terminal of capacitor cell 140 flows to the eighth transistor T8. If the current at the second terminal of capacitor cell 140 flows to the first resistor R1 and the second resistor R2, an additional voltage drop will be generated across the first resistor R1 and the second resistor R2. This will not only change the voltage distribution in the branches containing the first resistor R1 and the second resistor R2, but also affect the ramp compensation signal VRAMP output by ramp compensation output module 14. Because the ramp compensation output module 14 outputs the sum of the current sampling voltage, the voltage across the capacitor unit, and the DC bias voltage, the additional voltage drop will interfere with the normal voltage superposition process, causing deviations in the ramp compensation signal VRAMP and affecting the stability of the switching power supply. By directing all current to the eighth transistor T8, this interference is avoided, ensuring the accuracy and stability of the ramp compensation signal VRAMP, and thus improving the performance of the switching power supply.

[0070] Figure 7 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention. Figure 7 As shown, optionally, the ramp compensation circuit of the switching power supply also includes a switching module 15. The control terminal of the switching module 15 is connected to a reset signal RST. The first terminal of the switching module 15 is connected to the first terminal of the capacitor unit 140, and the second terminal of the switching module 15 is connected to the second terminal of the capacitor unit 150. The switching module 15 is used to control its own conduction and cutoff according to the reset signal RST to realize the charging and discharging operation of the capacitor unit 140.

[0071] Continue to refer to Figure 7 Optionally, the switching module 15 includes a ninth transistor T9. The gate of the ninth transistor T9 serves as the control terminal of the switching module 15, the first terminal of the ninth transistor T9 serves as the first terminal of the switching module 15, and the second terminal of the ninth transistor T9 serves as the second terminal of the switching module 15. The ninth transistor T9 is an N-type transistor.

[0072] When the reset signal RST is low, the ninth transistor T9 is turned off. At this time, the capacitor charging drive module 12 works normally, providing charging current to the capacitor unit 140. The current flows in from the first terminal of the capacitor unit 140 and flows out from the second terminal. The capacitor unit 140 is in a charging state, and the voltage across its terminals gradually increases, starting to accumulate charge and providing the basic voltage change for the ramp compensation signal.

[0073] When the reset signal RST is high, the ninth transistor T9 is turned on. At this time, the discharge channel of capacitor unit 140 is opened, and capacitor unit 140 begins to discharge. The discharge current flows out from the first terminal of capacitor unit 140, through the turned-on ninth transistor T9, and then through the second terminal of capacitor unit 140 into the current release module 13. In this way, capacitor unit 140 can quickly release the stored charge, preparing for the next charging and the generation of a stable ramp compensation signal. The presence of the switching module 15 allows for precise control of the charging and discharging process of capacitor unit 140. Flexible adjustment of the charging and discharging state of capacitor unit 140 via the reset signal RST helps optimize the waveform and characteristics of the ramp compensation signal.

[0074] Figure 8 This is a schematic diagram of another ramp compensation circuit provided in an embodiment of the present invention. Figure 8 As shown, optionally, the ramp compensation circuit includes: a signal input module 11, a capacitor charging drive module 12, a current release module 13, and a ramp compensation output module 14.

[0075] Optionally, the ramp compensation output module 14 includes a capacitor unit 140, a first resistor unit 141, and a second resistor unit 142. Optionally, the capacitor unit 140 includes a first capacitor C1, the first resistor unit 141 includes a first resistor R1, and the second resistor unit 142 includes a second resistor R2.

[0076] Optionally, the signal input module 11 includes an amplifier Av1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a second capacitor C2, a third capacitor C3, and a first transistor T1.

[0077] Optionally, the capacitor charging drive module 12 includes a first current mirror unit 121 and a second current mirror unit 122. The first current mirror unit 121 includes a second transistor T2, a third transistor T3, and a fourth transistor T4. The second current mirror unit 122 includes a fifth transistor T5 and a sixth transistor T6.

[0078] Optionally, the current release module 13 includes a third current mirror unit 130. The third current mirror unit 130 includes a seventh transistor T7 and an eighth transistor T8.

[0079] Optionally, the ramp compensation circuit of the switching power supply also includes a switching module 15, which includes a ninth transistor T9.

[0080] refer to Figure 8 The working principle of this ramp compensation circuit is as follows:

[0081] The input terminal of signal input module 11 is connected to the common node Com1 of the high-side power transistor and the low-side power transistor to acquire the voltage of this node. A voltage divider circuit composed of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 divides the acquired voltage, with the fourth resistor R5 grounded to provide a reference potential. The voltage after division is filtered by the second capacitor C2 to remove high-frequency noise, and then isolated by the third capacitor C3 before being input to amplifier Av1. Amplifier Av1 amplifies and adjusts the signal, and by controlling the gate voltage of the first transistor T1, it converts the DC voltage into DC current and outputs it to the capacitor charging drive module 12.

[0082] The capacitor charging drive module 12 is connected to the first capacitor C1 in the signal input module 11 and the ramp compensation output module 14, and is connected to the first bias current I1. Its first current mirror unit 121 and second current mirror unit 122 work together to superimpose the DC current output by the signal input module 11 with the first bias current I1 to charge the first capacitor C1. The second current mirror unit 122 uses the first bias current I1 as a reference current, and the first current mirror unit 122 generates a current to charge the first capacitor C1 based on the reference current, causing the voltage across the first capacitor C1 to rise with charging. This voltage change is part of the ramp compensation signal.

[0083] The current release module 13 is connected to the capacitor charging drive module 12 and the first capacitor C1. During the charging and discharging of the first capacitor C1, current flows into the current release module 13. The third current mirror unit 130 in the current release module 13 provides a low-impedance release path for the current in the first capacitor C1, preventing additional voltage fluctuations in the ramp compensation output module 14 and ensuring a fixed valley voltage for the ramp compensation signal. For example, when the first capacitor C1 is charging, the charging current flows into the seventh transistor T7 of the third current mirror unit 130, turning it on. Based on the current mirror characteristics, the eighth transistor T8 provides a path for the current flowing out from the second terminal of the first capacitor C1, preventing current from flowing into the first resistor R1 and the second resistor R2 and causing interference.

[0084] The ramp compensation output module 14 receives the second bias current I2 and the sampling current Is1 of the high-side power transistor, converting them into a DC bias voltage and a current sampling voltage, respectively. These are then superimposed with the voltage across the first capacitor C1 to output the ramp compensation signal. Specifically, the current sampling voltage is the product of the high-side power transistor's sampling current and the second resistor, while the DC bias voltage is approximately the product of the second bias current and the first resistor (because the resistance of the first resistor is much greater than that of the second resistor). This ramp compensation signal is compared with the output signal of the error amplifier in the peak current mode control loop to control the on / off state of the high-side and low-side power transistors in the switching power supply, suppressing subharmonic oscillations.

[0085] The control terminal of the switch module 15 is connected to the reset signal RST, which is also connected to the two ends of the first capacitor C1. When the reset signal RST is low, the ninth transistor T9 in the switch module 15 is turned off, and the capacitor charging drive module 12 charges the first capacitor C1 normally. When the reset signal RST is high, the ninth transistor T9 is turned on, and the first capacitor C1 discharges. By controlling the switch module 15 through the reset signal RST, the charging and discharging state of the first capacitor C1 can be adjusted, thus optimizing the waveform and characteristics of the ramp compensation signal.

[0086] Figure 9 This is a waveform diagram of a ramp compensation circuit provided in an embodiment of the present invention. (Reference) Figure 9 RST represents the reset signal, Vsw represents the voltage at the common node Com1 of the high-side power transistor and the low-side power transistor, Vin represents the input voltage connected to the high-side power transistor, Is1 represents the sampling current of the high-side power transistor, Vslope represents the uncompensated ramp signal, VRAMP represents the ramp compensation signal, VDC represents the DC bias voltage, and Vcom represents the output voltage of the error amplifier in the control loop of the switching power supply.

[0087] During the conduction of the high-side power transistor, the voltage Vsw of the common node Com1 is pulled up to the input voltage Vin; the sampling of the high-side power transistor current signal occurs during the conduction of the high-side power transistor. Whenever the ramp compensation signal VRAMP reaches the output voltage Vcom of the error amplifier, the high-side power transistor is turned off and the low-side power transistor begins to conduct.

[0088] Based on the same inventive concept, embodiments of the present invention also provide a switching power supply, including the ramp compensation circuit provided in any embodiment of the present invention. The switching power supply provided in the embodiments of the present invention has the beneficial effects of the ramp compensation circuit provided in the embodiments of the present invention. For details, please refer to the specific descriptions of the ramp compensation circuit in the above embodiments, which will not be repeated here.

[0089] Figure 10 This is a schematic diagram of a switching power supply provided in an embodiment of the present invention. Figure 10As shown, optionally, the switching power supply also includes: an error amplifier EA, a comparator CMP, an RS flip-flop U1, a first feedback resistor RFB1, a second feedback resistor RFB2, a current sampling module 301, a compensation network 302, a high-side power transistor M1, a low-side power transistor M2, an oscillator 303, and a drive module 304.

[0090] The gate of the high-side power transistor M1 is connected to the first output terminal of the drive module 303, and the first terminal of the high-side power transistor M1 is connected to the input voltage Vin. The second terminal of the high-side power transistor M1 is connected to the first terminal of the low-side power transistor M2. The gate of the low-side power transistor M2 is connected to the second output terminal of the drive module 303, and the second terminal of the low-side power transistor M2 is grounded.

[0091] The first end of the current sampling module 301 is connected to the common node Com1 of the high-side power transistor M1 and the low-side power transistor M2, and the second end of the current sampling module 301 is connected to the ramp compensation circuit 305 to input the sampling current of the high-side power transistor M1 into the ramp compensation circuit 305.

[0092] The first end of the first inductor L1 is connected to the common node Com1. The second end of the first inductor L1 is connected to the first end of the fourth capacitor C4 and the first end of the eighth resistor R8, and serves as the output terminal VOUT of the switching power supply. The second end of the fourth capacitor C4 and the second end of the eighth resistor R8 are grounded.

[0093] The first end of the first feedback resistor RFB1 is connected to the output terminal VOUT of the switching power supply, and the second end of the first feedback resistor RFB1 and the first end of the second feedback resistor RFB2 are connected to the feedback node Vfb.

[0094] The inverting input of error amplifier EA is connected to the feedback node Vfb, the non-inverting input of error amplifier EA is connected to the reference signal Vref, and the output of error amplifier EA is connected to the compensation network 302.

[0095] Optionally, the compensation network 302 includes a fifth capacitor C5, a sixth capacitor C6, and a ninth resistor R9. The first terminal of the ninth resistor R9 is connected to the output terminal of the error amplifier EA, the second terminal of the ninth resistor R9 is connected to the first terminal of the fifth capacitor C5, and the second terminal of the fifth capacitor C5 is grounded.

[0096] The first terminal of the sixth capacitor C6 is connected to the output terminal of the error amplifier EA and the non-inverting input terminal of the comparator CMP, and the second terminal of the sixth capacitor C6 is grounded.

[0097] The inverting input of comparator CMP is connected to the output of ramp compensation circuit 304 to receive ramp compensation signal VRAMP. The output of comparator CMP is connected to the reset terminal R of RS flip-flop U1.

[0098] The oscillator 303 is connected to the set terminal S of the RS flip-flop U1 and the ramp compensation circuit 305, respectively, to input the clock signal CLK to the set terminal S of the RS flip-flop U1 and the reset signal RST to the ramp compensation circuit 305. The output terminal Q of the RS flip-flop U1 is connected to the input terminal of the drive module 304.

[0099] The output voltage of the switching power supply is fed into a feedback voltage via the first feedback resistor RFB1 and the second feedback resistor RFB2. This feedback voltage, along with the reference voltage Vref, is input to the error amplifier EA. The difference between the two is amplified by the error amplifier EA to obtain the output voltage Vcom of the error amplifier EA. The output voltage Vcom of the error amplifier EA is used to control the duty cycle of the PWM signal. If the output voltage of the switching power supply changes, the output voltage Vcom of the error amplifier EA is adjusted accordingly, thereby changing the duty cycle of the PWM signal to stabilize the output voltage.

[0100] Oscillator 303 generates clock signal CLK. When clock signal CLK is high, the set terminal S of RS flip-flop U1 is triggered to 1, making the output terminal Q become 1, which in turn turns on the high-side power transistor M1. The power supply charges inductor L1, and the current of the first inductor L1 rises. At this time, the conduction time begins.

[0101] As the high-side power transistor M1 turns on, the inductor current increases. When the sampling current Is1 of the high-side power transistor M1 is greater than the output voltage Vcom of the error amplifier EA, the reset terminal R of the RS flip-flop U1 is triggered to 1, the set terminal Q becomes 0, the high-side power transistor M1 is turned off, the conduction time ends, and the turn-off time begins.

[0102] When the high-side power transistor M1 is off, the current sampling signal is 0, the non-inverting input of the comparator CMP is 0, the output voltage Vcom of the error amplifier EA is greater than 0, and the output of the comparator CMP is 0. This cycle continues until the next rising edge of the clock arrives, at which point the high-side power transistor M1 is turned on again, thus enabling the switching power supply to operate continuously.

[0103] The ramp compensation circuit 305 introduces a ramp compensation signal, which is superimposed on the current sampling signal. When the duty cycle is greater than 50%, this compensation signal can prevent subharmonic oscillations, improve system stability, and ensure reliable operation of the switching power supply.

[0104] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A ramp compensation circuit for a switching power supply, characterized in that, The switching power supply includes a high-side power transistor and a low-side power transistor, and the ramp compensation circuit includes: a signal input module, a capacitor charging drive module, a current release module, and a ramp compensation output module. The input terminal of the signal input module is connected to the common node of the high-side power transistor and the low-side power transistor. The signal input module is used to generate a DC voltage based on the voltage on the common node and convert the DC voltage into a DC current. The capacitor charging drive module is connected to the first end of the capacitor unit in the signal input module and the ramp compensation output module, and is connected to the first bias current to charge the capacitor unit according to the current formed by the superposition of the DC current and the first bias current. The current release module is connected to the capacitor charging drive module and the second end of the capacitor unit, and is used to completely release the current of the capacitor unit. The ramp compensation output module is connected to the second bias current and the sampling current of the high-side power transistor. It is used to convert the sampling current into a current sampling voltage, convert the second bias current into a DC bias voltage, and output the current sampling voltage, the voltage across the capacitor unit, and the DC bias voltage.

2. The ramp compensation circuit for the switching power supply according to claim 1, characterized in that, The ramp compensation output module includes the capacitor unit, the first resistor unit, and the second resistor unit. The first end of the capacitor unit is connected to the capacitor charging drive module, and the second end of the capacitor unit is connected to the current release module and the first end of the first resistor unit, and is connected to the second bias current. The second end of the first resistor unit is connected to the first end of the second resistor unit and is connected to the sampling current of the high-side power transistor. The second end of the second resistor unit is grounded.

3. The ramp compensation circuit for the switching power supply according to claim 2, characterized in that, The capacitor unit includes a first capacitor, the first resistor unit includes a first resistor, and the second resistor unit includes a second resistor; The first end of the first capacitor serves as the first end of the capacitor unit, and the second end of the first capacitor serves as the second end of the capacitor unit. The first end of the first resistor serves as the first end of the first resistor unit, and the second end of the first resistor serves as the second end of the first resistor unit. The first end of the second resistor serves as the first end of the second resistor unit, and the second end of the second resistor serves as the second end of the second resistor unit. The resistance of the first resistor is much greater than that of the second resistor.

4. The ramp compensation circuit for the switching power supply according to claim 1, characterized in that, The signal input module includes an amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a second capacitor, a third capacitor, and a first transistor; The first end of the third resistor serves as the input end of the signal input module, and the second end of the third resistor is connected to the first end of the fourth resistor and the first end of the fifth resistor. The second terminal of the fourth resistor is grounded, the second terminal of the fifth resistor is connected to the first terminal of the second capacitor and the first terminal of the sixth resistor, and the second terminal of the second capacitor is grounded. The first terminal of the third capacitor is connected to the second terminal of the sixth resistor and the first input terminal of the amplifier, and the second terminal of the third capacitor is grounded. The second input terminal of the amplifier is connected to the first terminal of the first transistor and the first terminal of the seventh resistor. The output terminal of the amplifier is connected to the gate of the first transistor. The second terminal of the first transistor is connected to the capacitor charging drive module. The second terminal of the seventh resistor is grounded.

5. The ramp compensation circuit for a switching power supply according to claim 4, characterized in that, The capacitor charging drive module includes a first current mirror unit and a second current mirror unit. The first terminal of the first current mirror unit is connected to the second terminal of the first transistor, the second terminal of the first current mirror unit is connected to the power supply voltage, the third terminal of the first current mirror unit is connected to the current release module, and the fourth terminal of the first current mirror unit is connected to the first terminal of the capacitor unit and serves as the output terminal of the ramp compensation circuit. The first terminal of the second current mirror unit is connected to the second terminal of the first transistor, the second terminal of the second current mirror unit is connected to the first bias current, and the third terminal of the second current mirror unit is grounded.

6. The ramp compensation circuit for a switching power supply according to claim 5, characterized in that, The first current mirror unit includes a second transistor, a third transistor, and a fourth transistor; The first terminal of the second transistor is connected to the power supply voltage, the second terminal of the second transistor is connected to the second terminal of the first transistor, and the gate of the second transistor is connected to the second terminal of the second transistor, the gate of the third transistor, and the gate of the fourth transistor. The first terminal of the third transistor is connected to the power supply voltage, and the second terminal of the third transistor is connected to the current release module; The first terminal of the fourth transistor is connected to the power supply voltage, and the second terminal of the fourth transistor is connected to the first terminal of the capacitor unit; And / or, the second current mirror unit includes a fifth transistor and a sixth transistor; The first terminal of the fifth transistor is grounded, the second terminal of the fifth transistor is connected to the second terminal of the first transistor, and the gate of the fifth transistor is connected to the gate of the sixth transistor; The first terminal of the sixth transistor is grounded, and the second terminal of the sixth transistor is connected to the gate of the sixth transistor and is connected to the first bias current.

7. The ramp compensation circuit for a switching power supply according to claim 1, characterized in that, The current release module includes a third current mirror unit; The first end of the third current mirror unit is connected to the capacitor charging drive module, the second end of the third current mirror unit is connected to the second end of the capacitor unit, and the third end of the third current mirror unit is grounded.

8. The ramp compensation circuit for a switching power supply according to claim 7, characterized in that, The third current mirror unit includes a seventh transistor and an eighth transistor; The first terminal of the seventh transistor is grounded, the second terminal of the seventh transistor is connected to the capacitor charging drive module, and the gate of the seventh transistor is connected to the second terminal of the seventh transistor and the eighth transistor. The first terminal of the eighth transistor is grounded, and the second terminal of the eighth transistor is connected to the second terminal of the capacitor unit.

9. The ramp compensation circuit for a switching power supply according to claim 1, characterized in that, It also includes a switch module, the control terminal of which is connected to a reset signal. The first terminal of the switch module is connected to the first terminal of the capacitor unit, and the second terminal of the switch module is connected to the second terminal of the capacitor unit. The switch module is used to control its own conduction and cutoff according to the reset signal to realize the charging and discharging operation of the capacitor unit.

10. A switching power supply, characterized in that, Includes the ramp compensation circuit of the switching power supply as described in any one of claims 1-9.

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