Full wave active rectifier control

Abstract

The invention relates to full wave active rectifier control. A full-wave active rectifier system includes a full-wave active rectifier to generate a DC voltage output signal based on an AC voltage input signal. The full wave active rectifier includes first and second transistors controllable by a controller, and third and fourth transistors controlled by an AC voltage input signal. The full wave active rectifier system includes a controller coupled to the first transistor. The full-wave active rectifier system is configured to: monitor a first voltage at a node shared by an AC voltage input signal and a first terminal of the first transistor when the first transistor is in an off state; and sensing a voltage transient of the first voltage caused by switching the first transistor between the on state and the off state. The controller is configured to control a phase angle of the first transistor switching between an on state and an off state in response to sensing a voltage transient.

Description

Technical Field

[0001] This application relates to methods and circuit layouts for controlling full-wave active rectifiers. Specifically, it relates to adaptive active control for full-wave rectifier circuits. Background Technology

[0002] Full-wave active rectifiers (also known as AC / DC power converters) are well-known. Full-wave active rectifiers are superior to full-wave passive rectifiers because they provide improved power efficiency during the AC-to-DC power conversion process. Summary of the Invention

[0003] According to the first aspect, a full-wave active rectifier system is provided, comprising:

[0004] A full-wave active rectifier for generating a DC voltage output signal based on an AC voltage input signal, the full-wave active rectifier comprising: a controller; a first transistor and a second transistor controllable by the controller; and a third transistor and a fourth transistor controllable by the AC voltage input signal; wherein the full-wave active rectifier system is configured as follows:

[0005] When the first transistor is in the off state, monitor the first voltage at the AC input node shared by the AC voltage input signal and the first terminal of the first transistor; and

[0006] The voltage transient of the first voltage caused by switching the first transistor between the on and off states is sensed.

[0007] The controller is configured as follows:

[0008] The phase angle by which the first transistor switches between the on and off states in response to sensing the voltage transient.

[0009] Optionally, the controller is coupled to the first transistor.

[0010] Optionally, the controller is coupled to a second transistor.

[0011] Optionally, the phase angle corresponds to the period of the AC voltage input signal.

[0012] Optionally, the operating frequency of the AC voltage input signal is between 5MHz and 20MHz.

[0013] Optionally, each transistor is a FET.

[0014] Optionally, each transistor is a MOSFET.

[0015] Optionally, each transistor includes a control terminal, as well as a first channel terminal and a second channel terminal (i.e., the current-carrying portion). Optionally, the full-wave active rectifier includes a first AC voltage input node coupled to the first channel terminal (drain) of the fourth transistor, the first channel terminal (drain) of the first transistor, and the control terminal of the third transistor. Optionally, the full-wave active rectifier includes a second AC voltage input node coupled to the first channel terminal (drain) of the third transistor, the first channel terminal (drain) of the second transistor, and the control terminal of the fourth transistor. Optionally, the full-wave active rectifier includes a voltage output node coupled to the second channel terminal (source) of the third transistor and the second channel terminal (source) of the fourth transistor. Optionally, the full-wave active rectifier includes a ground node coupled to the second channel terminal (source) of the first transistor and the second channel terminal (source) of the second transistor.

[0016] Optionally, the first terminal of the first transistor is the drain of the first transistor.

[0017] Optionally, the first terminal of the second transistor is the drain of the second transistor.

[0018] Optionally, the phase angle is an active phase angle. Optionally, the active phase angle is controlled to anticipate the switching of the first transistor from an off state to an on state in response to a sensed voltage transient.

[0019] Optionally, the phase angle is an active phase angle. Optionally, the active phase angle is controlled to delay the switching of the first transistor from the off state to the on state in response to the absence of a voltage transient detected during the period of the AC voltage input signal.

[0020] Optionally, the phase angle is a failure phase angle, which is controlled to delay the switching of the first transistor from the on state to the off state in response to a sensed voltage transient.

[0021] Optionally, the phase angle is a failure phase angle, which is controlled to respond to the expected switching of the first transistor from the on state to the off state in response to the absence of a voltage transient detected during the period of the AC voltage input signal.

[0022] Optionally, the controller is further configured to generate a changing voltage signal based on the frequency of the AC voltage input signal, wherein the phase angle is determined based on the changing voltage signal reaching a first threshold.

[0023] Optionally, the controller is further configured to switch the first transistor from the off state to the on state based on the activation phase angle. Optionally, the controller is further configured to switch the first transistor from the on state to the off state based on the failure phase angle.

[0024] Optionally, the phase angle is an activation phase angle. Optionally, the controller is further configured to switch the first transistor from an off state to an on state based on the activation phase angle. Optionally, the controller is further configured to switch the first transistor from an on state to an off state based on a failure phase angle. Optionally, the failure phase angle is determined based on a changed voltage signal reaching a second threshold.

[0025] Optionally, the second threshold is greater than the first threshold.

[0026] Optionally, a changed voltage signal is generated when it is determined that one of the third or fourth transistors is switching between an off state and an on state. Optionally, a changed voltage signal is generated when it is determined that the gate threshold voltage of one of the third or fourth transistors is reached and / or exceeded.

[0027] Optionally, the first changed voltage signal and / or the second changed voltage signal are "one-to-one functions" and track the frequency of the AC voltage input signal.

[0028] Optionally, the controller is configured to reset the changed voltage signal when the third or fourth transistor switches between an off state and an on state.

[0029] Optionally, the controller is configured to adjust a first threshold and / or adjust a second threshold in response to a sensed voltage transient.

[0030] Optionally, the first threshold is lowered in response to a sensed voltage transient.

[0031] Optionally, a second threshold is increased in response to a sensed voltage transient.

[0032] Optionally, the first threshold and the second threshold are adjusted by a fixed voltage level.

[0033] Optionally, the controller is further configured to set the first threshold to be equal to the second threshold when the full-wave active rectifier is started.

[0034] Optionally, the controller is configured to operate a frequency tracking algorithm, which is configured to: determine the peak value of the changed voltage signal, wherein the changed voltage signal has a corresponding rate of change; and if the peak value does not exceed a lower threshold, increase the rate of change of the changed voltage signal; or if the peak value exceeds an upper threshold, decrease the rate of change of subsequent changed voltage signals. The changed voltage signal may appear once or twice in each cycle (twice can compensate for asymmetrical input waveforms).

[0035] Optionally, the altered voltage signal appears once or twice in each cycle. Optionally, there are two altered voltage signals to compensate for asymmetrical input waveforms.

[0036] Optionally, the changed voltage signal is reset after it reaches its peak value.

[0037] Optionally, the frequency tracking algorithm is further configured to maintain the rate of change of the subsequently changed voltage signal if the peak value exceeds the lower threshold but does not exceed the upper threshold.

[0038] Optionally, the changed voltage signal is a ramp signal.

[0039] Optionally, voltage transients are sensed by comparing a first voltage with a control voltage threshold. Optionally, the control voltage threshold is between ground level (GND) and -Vt, where Vt is the cut-in voltage of the body diode of the first transistor, and optionally / preferably between GND and -Vt / 2.

[0040] Optionally, the control voltage threshold is determined by the IR voltage drop across the resistor.

[0041] Optionally, the full-wave active rectifier system includes a transient detection comparator that includes an input coupled to the AC input node and configured to compare a first voltage with a control voltage threshold.

[0042] Optionally, the transient detection comparator is configured to: deactivate when the first transistor is in the ON state (e.g., when the first changed voltage signal reaches a first threshold); and be activated when the first transistor is in the OFF state (e.g., when the first changed voltage signal reaches a second threshold).

[0043] Optionally, the first transient detection comparator is arranged to be activated when the fourth transistor fails; deactivated when the first transistor is activated (e.g., when the first changed voltage signal reaches a first threshold); activated when the first transistor fails (e.g., when the first changed voltage signal reaches a second threshold); and deactivated when the third transistor fails.

[0044] Optionally, the transient detection comparator generates a flag signal indicating that the first voltage exceeds a control voltage threshold. Optionally, the controller is configured to control the phase angle based on the flag signal and determine when the first transistor switches between an on and off state.

[0045] Optionally, the transient detection comparator is a first transient detection comparator. Optionally, the AC input node is a first AC input node, and optionally, the full-wave active rectifier layout includes a second transient detection comparator, which includes an input coupled to a second AC input node shared by the AC voltage input signal and a first terminal of the second transistor, and the second transient detection comparator is configured to compare a control voltage threshold with the voltage at the second AC input node.

[0046] Optionally, the second transient detection comparator is configured to: deactivate when the second transistor is in the ON state (e.g., when the first changed voltage signal reaches a third threshold); and be activated when the second transistor is in the OFF state (e.g., when the first changed voltage signal reaches a fourth threshold).

[0047] Optionally, the second transient detection comparator is arranged to be activated when the third transistor fails; deactivated when the second transistor is activated (e.g., when the first changed voltage signal reaches the third threshold); activated when the second transistor fails (e.g., when the first changed voltage signal reaches the fourth threshold); and deactivated when the fourth transistor fails.

[0048] Optionally, the first transient detection comparator is arranged to: deactivate when the first transistor is activated; activate when the first transistor fails; deactivate when the second transistor is activated; and activate when the second transistor fails.

[0049] Optionally, the full-wave active rectifier system includes: a digital-to-analog converter (DAC) configured to generate a first threshold and a second threshold, wherein the first threshold is adjusted by a voltage level corresponding to one least significant bit (LSB) of the DAC, and wherein the second threshold is adjusted by a voltage level corresponding to one least significant bit (LSB) of the DAC.

[0050] Optionally, the AC input node is a first AC input node, wherein the full-wave active rectifier system is further configured to: monitor a second voltage at the second AC input node shared by the AC voltage input signal and the first terminal of the second transistor when the second transistor is in the off state; and optionally sense a second voltage transient caused by switching the first transistor between the on and off states. Optionally, the controller is further configured to: control a second phase angle for switching the second transistor between the on and off states in response to sensing the second voltage transient.

[0051] Optionally, the second phase angle is a second activation phase angle. Optionally, the second activation phase angle is controlled to anticipate the switching of the second transistor from an off state to an on state in response to sensing a second voltage transient.

[0052] Optionally, the second phase angle is a second failure phase angle. Optionally, the second failure phase angle is controlled to delay the switching of the second transistor from the on state to the off state in response to sensing a second voltage transient.

[0053] Optionally, the changed voltage signal is a first changed voltage signal. Optionally, the full-wave active rectifier system is further configured to generate a second changed voltage signal based on the frequency of the AC voltage input signal. Optionally, the second phase angle is determined based on the second changed voltage signal reaching a third threshold.

[0054] Optionally, the second failure phase of the second transistor is determined based on the second changed voltage signal reaching a fourth threshold.

[0055] Optionally, the changed voltage signal is a first changed voltage signal, and the full-wave active rectifier system is further configured to: generate the first changed voltage signal when it is determined that the fourth transistor is switching between a turn-off state and a turn-on state; and optionally, generate the second changed voltage signal when it is determined that the third transistor is switching between a turn-off state and a turn-on state.

[0056] Optionally, the controller is configured to reset the changed voltage signal when the fourth transistor switches between an off state and an on state. Optionally, the controller is configured to reset the second changed voltage signal when the third transistor switches between an off state and an on state. Attached Figure Description

[0057] Figure 1 A schematic wiring diagram of an existing full-wave active rectifier is shown.

[0058] Figure 2 A schematic wiring diagram of a full-wave active rectifier in an example of the present invention is shown.

[0059] Figure 3 The graph illustrates a partial cycle of the AC voltage input signal over a time period.

[0060] Figure 4 An example is shown: a graph illustrating the cycle of the AC voltage input signal corresponding to the ramp signal over a time period.

[0061] Figure 5 The graph illustrates multiple cycles of the AC voltage input signal corresponding to two ramp signals over a time period.

[0062] Figure 6 A schematic wiring diagram of a full-wave active rectifier with optional features, as exemplified in an example of the present invention, is shown.

[0063] Figure 7An example is given of a method by which a controller generates control signals to be supplied to the control terminals of a transistor based on a voltage threshold and a ramp signal over a period of time.

[0064] Figure 8a The example illustrates how the ramp signal increases its rate of change with each reset until the desired rate of change is reached.

[0065] Figure 8b This example illustrates how the ramp signal reduces its rate of change on each reset until it reaches the desired rate of change.

[0066] Figure 8c Examples are given relative to Figure 8a or Figure 8b The graph shows when the frequency is locked over time.

[0067] Figure 9 The process of a frequency tracking algorithm that can be applied to one or more ramp signals to achieve a desired rate of change is illustrated.

[0068] Figure 10 A schematic wiring diagram of a full-wave active rectifier with optional features, as exemplified in an example of the present invention, is shown.

[0069] Figure 11 A graph illustrating the cycle of the AC voltage input signal corresponding to the ramp signal and the control signal applied to the control terminal of the active transistor is shown.

[0070] Figure 12 Five graphs are shown illustrating how the outputs of the first and second transient detection comparators corresponding to the AC voltage input signal are generated relative to time.

[0071] Figure 13 The diagram illustrates a partial line graph of the voltage at node D1 at the input of the transient detection comparator, and shows the corresponding curve of the output of the transient detection comparator relative to time.

[0072] Figure 14 The process of adjusting the algorithm is illustrated, which can be applied by the controller to control the phase angle of the active transistor switching between the on and off states in response to the output of the transient detection comparator.

[0073] Figure 15 Several signal diagrams corresponding to the switching of active transistors are illustrated, with a common time scale of three cycles of the AC voltage input signal.

[0074] Figure 16 A graph illustrating the DC voltage output signal generated from an AC voltage input signal by a full-wave active rectifier system according to an example of the present invention is shown.

[0075] Figure 17 The graph illustrates the DC voltage output signal generated from an AC voltage input signal using a full-wave passive rectifier, particularly a Schottky diode rectifier. Detailed Implementation

[0076] Figure 1 An example of a conventional full-wave active rectifier 10 is shown. The full-wave active rectifier 10 is suitable for applications based on an AC voltage input signal V. AC_IN To generate DC voltage output signal V DC_OUT The full-wave active rectifier 10 includes first and second transistors MN1 and MN2 (e.g., MOSFETs) that can be controlled by a controller, and an AC voltage input signal V. AC_IN The third and fourth transistors, MP2 and MP1, are controlled. AC voltage input signal V. AC_IN It is provided at the first node D1 and the second node D2.

[0077] The first and second transistors MN1 and MN2 can be called "active transistors" because they can be controlled by a controller; or they can be called "low-side transistors" because they are directly coupled to DC ground. The third and fourth transistors MP2 and MP1 can be called "passive transistors" because they are powered by the AC voltage input signal V. AC_IN Control; or referred to as "high-side transistors" because they are directly coupled to the DC voltage output signal V. DC_OUT .

[0078] Each transistor MN1, MN2, MP2, MP1 includes corresponding control terminals GN1, GH2, GP2, GP1, as well as a first channel terminal and a second channel terminal (i.e., the current-carrying portion). Each transistor MN1, MN2, MP2, MP1 can be an FET or more specifically a MOSFET. When each transistor MN1, MN2, MP2, MP1 is a MOSFET, the corresponding control terminals GN1, GN2, GP1, GP2 are gate terminals, the corresponding first channel terminal is the drain terminal, and the corresponding second channel terminal is the source terminal.

[0079] AC voltage input signal V AC_IN The first node D1 and the second node D2 provide power to the full-wave active rectifier. The first node D1 is electrically coupled to the first channel terminal (e.g., drain) of the fourth transistor MP1, the first channel terminal (e.g., drain) of the first transistor MN1, and the control terminal GP2 of the third transistor MP2. The second node D2 is electrically coupled to the first channel terminal (e.g., drain) of the third transistor MP2, the first channel terminal (e.g., drain) of the second transistor MN2, and the control terminal GP1 of the fourth transistor MP1. The DC voltage output signal V... DC_OUTA voltage output node 12 is provided, which is electrically coupled to the second channel terminal (e.g., source) of the third transistor MP2 and the second channel terminal (e.g., source) of the fourth transistor MP1. A ground node GND is electrically coupled to the second channel terminal (e.g., source) of the first transistor MN1 and the second channel terminal (e.g., source) of the second transistor MN2.

[0080] The existing full-wave active rectifier 10 requires the controller to provide appropriate control signals to the control terminal GN1 of the first transistor MN1 and the control terminal GN2 of the second transistor MN2.

[0081] One problem with known control of full-wave rectifiers is that precise and optimized control of the active transistors requires additional and complex circuitry. This leads to inefficiency and response time limitations. Therefore, controlling existing full-wave rectifiers is challenging, especially at high frequencies. Thus, there is a need to improve the control of full-wave active rectifiers.

[0082] Embodiments of the present invention utilize active transistors for controlling a full-wave active rectifier and for AC input V AC_IN A new control method for frequency tracking solves the above problems.

[0083] As a brief, non-limiting overview of the invention, this disclosure provides a method for predictively adjusting the switching control of active transistors in a full-wave active rectifier as part of a full-wave active rectifier system. This enables the controller to utilize a high-frequency AC voltage input signal V. AC_IN Operation is performed. The full-wave active rectifier system is configured to monitor the AC voltage input signal V. AC_IN At least one node is used to identify the AC voltage input signal V. AC_IN The frequency is measured, and the active transistor is detected by sensing the voltage transients that occur due to the switching on of one of the active transistors to detect whether the active transistor is switched on or off too early or too late.

[0084] Figure 2 An example of a schematic wiring diagram of a full-wave active rectifier system 20 for performing the method according to the invention is shown. The full-wave active rectifier system 20 includes a full-wave rectifier 10 and a controller 26. Figure 2 The AC voltage input signal V is shown. AC_IN The voltage source is provided by the secondary coil of the inductive charging antenna. That is, the full-wave active rectifier system 20 can be coupled to a larger battery charging system, thereby charging the battery from the power source via the full-wave active rectifier system 20. In such systems, the efficiency of the full-wave active rectifier system 20 is prioritized to reduce charging time and any heating effect. AC voltage input signal V AC_INIt can operate at frequencies greater than 20MHz because the full-wave active rectifier system 20 is well-suited for high-frequency operation. AC voltage input signal V AC_IN It can have an operating frequency between 5MHz and 20MHz, or between 13MHz and 14MHz.

[0085] The controller 26 generates a first control signal to be provided to the control terminal GN1 of the first transistor MN1. In response to the first control signal, the first transistor MN1 operates in either an ON or OFF state. That is, the controller 26 controls when the first transistor MN1 switches between the ON and OFF states. In the ON state, the first transistor MN1 is in its transistor region. In the OFF state, the first transistor MN1 is in its OFF region.

[0086] The full-wave active rectifier system 20 is configured to monitor the AC voltage input signal V when the first transistor MN1 is in the off state (i.e., the first control signal of the controller 26 indicates that the first transistor MN1 is operating in the off state). AC_IN The first voltage is shared at the first node D1 with the first terminal of the first transistor MN1. The full-wave active rectifier system 20 is configured to sense voltage transients of the first voltage caused by the switching of the first transistor MN1 between its on and off states. Each transistor MN1, MN2, MP2, MP1 includes a corresponding body diode 21, 22, 23, 24 inherent in the transistor structure. When the voltage between the anode and cathode of the first transistor MN1 is greater than its turn-off voltage (e.g., greater than 0.3V), the body diode 21 of the first transistor will conduct.

[0087] Figure 3 The AC voltage input signal V is shown. AC_IN The partial loop graph shows the activation phase angle 28A and deactivation phase angle 28B of the first transistor MN1. The result of the first transistor being in its on state between the activation phase angle 28A and the deactivation phase angle 28B is the DC voltage output signal V. DC_OUT .

[0088] Controller 26 is configured to control the phase angle (e.g., 28A or 28B) of the first transistor MN1 switching between an on and off state in response to a sensed voltage transient. The phase angle is relative to the AC voltage input signal V. AC_IN The phase is periodic. For example, controller 26 can be configured to switch the first transistor MN1 from the off state to the on state with a phase angle of 80 degrees, and in response to sensing a voltage transient, the phase angle can be adjusted to 79 degrees. Therefore, in the AC voltage input signal V AC_INDuring the next cycle, the controller 26 can be configured to switch the first transistor MN1 from the off state to the on state with a phase angle of 79 degrees.

[0089] Advantageously, the full-wave active rectifier system 20 provides a method for controlling and optimizing the switching of the first transistor MN1. This optimization is based on the statement that if the phase angle of the first transistor MN1 switching between the on and off states is adjusted, the full-wave active rectifier system 20 will operate more efficiently. Furthermore, the full-wave active rectifier system 20 provides a method for utilizing a high-frequency AC voltage input signal V. AC_IN The method of operation.

[0090] The phase angle can be an activation phase angle 28A. At the activation phase angle 28A of the first transistor MN1, the first transistor MN1 switches from its off state to its on state. The activation phase angle 28A can be controlled by the controller 26 to anticipate the first transistor MN1 switching from its off state to its on state in response to a sensed voltage transient.

[0091] The activation phase angle 28A can be controlled in response to the AC voltage input signal V. AC_IN The first transistor MN1 is delayed from its off state to its on state because no voltage transient is detected during the cycle. In other words, the switching of the AC voltage input signal V is determined. AC_IN There are no voltage transients within the cycle. In one example, this cycle is determined based on the transition of the first transistor MN1 from its off state to its on state. At the AC voltage input signal V... AC_IN The absence of a voltage transient detected during this cycle indicates that the first transistor MN1 is operating within the range of the AC voltage input signal V. AC_IN It is prematurely put into its on state during the cycle.

[0092] AC voltage input signal V AC_IN During the period, the full-wave active rectifier system 20 can be configured to sense a first voltage transient and a second voltage transient of the first voltage caused by the switching of the first transistor MN1 between its on and off states. The first voltage transient may correspond to the timing of the first transistor MN1 switching from its off state to its on state (i.e., at the active phase angle 28). The second voltage transient may correspond to the timing of the first transistor MN1 switching from its on state to its off state (i.e., at the inactive phase angle 28B).

[0093] The controller 26 can be configured to control the failure phase angle 28B for the first transistor MN1 to switch from its on state to its off state in response to sensing a second voltage transient. The failure phase angle 28B can be controlled by the controller 26 to delay the first transistor MN1 from its on state to its off state in response to sensing a second voltage transient. Alternatively, the failure phase angle 28B for the first transistor MN1 to switch from its on state to its off state can be predetermined.

[0094] The failure phase angle 28B can be controlled in response to the AC voltage input signal V. AC_IN No second voltage transient was sensed during the cycle, and the switching of the first transistor MN1 from its on state to its off state was anticipated. In one example, this cycle was determined based on the switching of the first transistor MN1 from its on state to its off state. At the AC voltage input signal V... AC_IN The absence of a second voltage transient during this cycle indicates that the first transistor MN1 is operating within the AC voltage input signal V. AC_IN It enters its off state too late in the loop.

[0095] Although the switching of the first transistor MN1 has been described, it should be understood that the controller 26 generates a second control signal provided to the control terminal GN2 of the second transistor MN2. The controller 26 can be configured to control a second (activation and / or deactivation) phase angle of the second transistor MN2 switching between an on and off state in response to sensing (first and / or second) voltage transients. For example, in the case of an AC voltage input signal V... AC_IN Under the assumption of symmetry, the second phase angle of the second transistor MN2 switching between the on and off states can be 180° out of phase with the phase angle (28A or 28B) of the first transistor MN1 switching between the on and off states.

[0096] The full-wave active rectifier system 20 can be configured to monitor the AC voltage input signal V when the second transistor MN2 is in the off state (i.e., the second control signal of the controller 26 indicates that the second transistor MN2 is operating in the off state). AC_IN The second voltage is shared at the second node D2, which is the first terminal of the second transistor MN2. The full-wave active rectifier system 20 can be configured to sense the voltage transients of the second voltage caused by the switching of the second transistor MN2 between its on and off states.

[0097] Controller 26 can be configured to control a second phase angle for switching the second transistor MN2 between an on and off state in response to a sensed voltage transient of the second voltage. The second phase angle is relative to the AC voltage input signal V. AC_IN The periodicity is such that the controller can respond to the AC voltage input signal V. AC_INDuring the period, two voltage transients of the second voltage are sensed. The controller 26 can control the second activation phase angle and / or the second deactivation phase angle of the second transistor MN2, similar to that described above with reference to the first transistor MN1. Advantageously, in response to the AC voltage input signal V... AC_IN Within a cycle, sensing one or more voltage transients of the second voltage controls the second active phase angle and / or the second inactive phase angle of the second transistor MN2, for example, independently of the control of the first transistor MN1, providing processing even asymmetric AC voltage input signals V. AC_IN This capability provides improved efficiency for the full-wave active rectifier system 20.

[0098] Figure 4 The AC voltage input signal V corresponding to ramp signal 30 is shown. AC_IN The graph shows the cycle. Ramp signal 30 can be used to determine the conduction angle of the first transistor MN1. The first switching signal 32a is high when the fourth transistor MP1 is in its on state and low when the fourth transistor MP1 is in its off state. The second switching signal 32b is high when the third transistor MP2 is in its on state and low when the third transistor MP2 is in its off state.

[0099] The controller 26 can be configured to generate a first ramp signal 30 and a second ramp signal 31 based on the frequency of the AC voltage input signal. For example... Figure 4 As shown, the first ramp signal 30 and the second ramp signal 31 are at the AC voltage input signal V AC_IN It resets once per cycle.

[0100] like Figure 4 As shown, controller 26 is configured to switch the fourth transistor MP1 from its off state to its on state (i.e., when...). Figure 4 At the time point / phase angle marked A1, the first ramp signal 30 is generated and reset. That is, the full-wave active rectifier system 20 is configured to determine when the gate threshold voltage 36 of the fourth transistor MP1 is reached and / or exceeded. The controller 26 can also be configured to generate and reset the first ramp signal 30 when the third transistor MP2 switches from its off state to its on state (i.e., at...). Figure 4 The second ramp signal 31 is generated or reset at the time point / phase angle marked as B1. That is, the full-wave active rectifier system 20 is configured to determine when the gate threshold voltage of the third transistor MP2 is reached and / or exceeded.

[0101] In an alternative example, the first ramp signal 30 can be connected to the AC voltage input signal V. AC_IN It resets twice per cycle, and the second ramp signal 31 may not exist. If the AC voltage input signal V AC_INIf it is symmetrical, then the instance may be advantageous. The first ramp signal 30 can be used with the AC voltage input signal V. AC_IN Reset at any phase angle. In an alternative example, controller 26 can be configured to reset ramp signal 30 when the fourth transistor MP1 switches from its on state to its off state. Where ramp signal 30 is reset at any phase angle of the AC voltage input signal V. AC_IN In an alternative instance where the controller 26 is reset twice per cycle, the controller 26 may be configured to generate / reset ramp signal 30 when the third transistor MP2 switches between its off and on states.

[0102] Figure 5 The AC voltage input signal V is shown. AC_IN Multiple cycles with the first ramp signal 30 and the second ramp signal 31.

[0103] Figure 6 An example of a schematic wiring diagram of a full-wave active rectifier system 40 for performing the method according to the invention is shown. In addition to certain optional features, Figure 6 The full-wave active rectifier system 40 has the same characteristics as... Figure 2 The system contains some of the same components. The same reference numerals are used to indicate... Figure 2 The same / corresponding features will not be described in detail below.

[0104] Figure 6 A device for comparing the voltage at the first node D1 with a control voltage threshold is shown in the first block 41. The sensing of voltage transients (at the first node D1) of the first voltage is based on the output of the first block 41. Figure 6 A device for comparing the voltage at the second node D2 with a control voltage threshold is shown in the second block 42. The sensing of voltage transients of the first voltage (at the second node D2) is based on the output of the second block 42. Figure 6 Also shown in block 43 are means for determining when the third transistor MP2 switches between its off and on states, or simply for determining when the third transistor MP2 switches from its off state to its on state. The first ramp signal 30 can be reset based on the output from block 43. Figure 6 A device for determining when the fourth transistor MP1 switches between its off and on states, or simply for determining when the fourth transistor MP1 switches from its off state to its on state, is shown in block 44. The second ramp signal 31 can be reset based on the output from block 44. While blocks 41, 42, 43, and 44 are... Figure 6 The boxes are shown as different boxes, but each box can be implemented by controller 26.

[0105] The control voltage threshold can be predetermined to be slightly below the DC ground level (GND), for example, at -70mV. Advantageously, this ensures that the body diode turn-on threshold is not met and the body diodes of the first and / or second transistors MN1, MN2 are not activated. Therefore, losses are avoided and efficiency is improved by preventing reverse conduction. Furthermore, a slightly negative control voltage threshold beneficially increases buffering to compensate for dynamic errors and offsets when the control voltage threshold is met, thereby preventing the low-side FET from turning on when the AC input voltage has reverse polarity, which would severely impact efficiency.

[0106] Figure 7 This illustrates a method by which controller 26 generates a first control signal 52 for supplying to control terminal GN1 of the first transistor MN1 based on ramp signal 30. Since ramp signal 30 corresponds to AC voltage input signal V... AC_IN The frequency, therefore each point on the ramp signal 30 corresponds to the AC voltage input signal V. AC_IN The phase angle is determined by the first ramp signal 30. The controller 26 generates an activation threshold voltage Vt_on and a failure threshold voltage Vt_off. The controller 26 monitors the first ramp signal 30 and compares the voltage of the ramp signal 30 with the activation threshold Vt_on (e.g., via the first comparator 46) and the failure threshold Vt_off (e.g., via the first comparator 48). Therefore, the activation phase angle 28A is determined by the ramp signal 30 reaching the activation threshold voltage Vt_on. The failure phase angle 28B is determined by the ramp signal 30 reaching the failure threshold voltage Vt_off. Therefore, the failure threshold voltage Vt_off is greater than the activation threshold voltage Vt_on. The controller 26 can control the activation phase angle 28A and / or the failure phase angle 28B of the first transistor MN1 by changing the activation threshold voltage Vt_on and / or the failure threshold voltage Vt_off, respectively.

[0107] The controller 26 can use logic 50 to generate a first control signal 52 for the control terminal GN1 of the first transistor MN1 based on comparisons (e.g., the outputs of the first comparator 46 and the second comparator 48).

[0108] Although Figure 7 An example of generating the first control signal 52 is shown; however, similarly, the second control signal provided to the control terminal GN2 of the second transistor MN2 can be based on the second ramp signal 31. Alternatively, if the AC voltage input signal V... AC_IN If it is symmetrical, then the second control signal can be based on the first ramp signal 30.

[0109] Advantageously, Figure 7The method of controller 26 shown allows the use of a single ramp signal to turn one or more transistors MN1, MN2 on and off. However, preferably, corresponding ramp signals 30, 31 can be used to turn the corresponding transistors MN1, MN2 on and off. The corresponding ramp signals 30, 31 for each of the first and second transistors MN1, MN2 can be generated / reset half a cycle earlier than actually strictly required (e.g., Figure 5 (As shown). Advantageously, this reduces the impact of the delays of comparators 46 and 48 on the dynamic range of the switch turn-on / turn-off timing, thereby relaxing the quiescent current requirement.

[0110] based on Figures 4 to 7 With at least some of these characteristics, the full-wave active rectifier system 20 can be adapted to accept an AC voltage input signal V of a specific predetermined frequency or a predetermined narrow frequency range. AC_IN However, in one instance, the full-wave active rectifier system 20 can be arranged to accept and adapt to AC voltage input signals V with a wide range of possible frequencies. AC_IN Figure 8 to Figure 9 The relevant description outlines the principles and algorithms for frequency tracking. Specifically, Figure 9 The process of the frequency tracking algorithm is illustrated.

[0111] Controller 26 can be configured to determine the AC voltage input signal V AC_IN The period (or frequency).

[0112] Figure 8a , Figure 8b and Figure 8c Three graphs are shown, illustrating the rate of change of the first ramp signal 30 as it increases or decreases until the rate of change of the first ramp signal 30 tracks the AC voltage input signal V. AC_INThe frequency. Specifically, Figure 8 illustrates the results of a frequency tracking algorithm used to control the rate of change of the first ramp signal 30, such that the dynamic range of the activation threshold voltage Vt_on and the failure threshold voltage Vt_off is within a suitable range of the controller 26. Advantageously, controlling the dynamic range of the first ramp signal 30 enables the full-wave active rectifier system to operate over a wide frequency range, thereby enabling the full-wave active rectifier 10 to operate with high efficiency. Conversely, if the rate of change of the first ramp signal 30 is constant, then at low frequencies, the first ramp signal 30 can reach its peak and stabilize at the supply voltage, thereby limiting the maximum possible phase angle of Vt_on and Vt_off to less than 360° and limiting the resolution of Vt_on and Vt_off to the least significant bit of the digital-to-analog converter (DAC) of the controller 26. Furthermore, if the rate of change of the first ramp signal 30 is constant, then at high frequencies, the first ramp signal 30 can reach its peak value far below the supply voltage, thereby limiting the resolution of Vt_on and Vt_off to the least significant bit of the DAC of the controller 26. In both scenarios, this will result in a smaller number of possible phase angles for the activation and deactivation phase angles 28A and 28B. Therefore, the efficiency of the full-wave active rectifier 10 is limited.

[0113] Figure 8a and Figure 8b Both show graphs of voltage changing over time. Figure 8a and Figure 8b The diagram shows how the rate of change of the first ramp signal 30 increases and decreases each time it is reset at time points / phase angles labeled A1, A1', and A1', respectively. Figure 8a and Figure 8b Each shows two voltage thresholds: the lower threshold V. TL and upper limit threshold V TU .

[0114] Controller 26 is configured to operate a frequency tracking algorithm to determine the peak value of the first ramp signal 30. Controller 26 is configured to: if the peak value fails to exceed a lower threshold V TL Then increase the rate of change of the subsequent slope; or if the peak exceeds the upper limit threshold V TU This reduces the rate of change of the subsequent ramps. Therefore, the rate of change of the first ramp signal 30 corresponds to the AC voltage input signal V. AC_IN Frequency. Advantageously, the rate of change of the first ramp signal 30 ensures that when the controller 26... Figure 7 When the layout shown is operated to generate the first control signal 52, the full-wave active rectifier systems 20 and 40 maintain high precision and resolution.

[0115] Figure 8aThe first ramp 30a of the first ramp signal 30 is shown, which fails to exceed the lower limit threshold V at the time point / phase angle marked A1. TL Therefore, controller 26 increases the rate of change of the second ramp 30b of the first ramp signal 30. The second ramp 30b of the first ramp signal 30 does not exceed the lower limit threshold V at the time point / phase angle marked A1'. TL Therefore, controller 26 increases the rate of change of the third ramp 30c of the first ramp signal 30. The third ramp 30c of the first ramp signal 30 exceeds the lower limit threshold V at the time point / phase angle marked A1". TL And less than the upper threshold V TU Therefore, Figure 8c The graph shows that the frequency is locked, that is, the rate of change of the first ramp 30 is maintained.

[0116] For each cycle (i.e., from the time point / phase angle labeled A1 to the next time point / phase angle labeled A1'), the rate of increase of the first ramp 30 can be increased by a predetermined amount corresponding to the DAC resolution (preferably the least significant bit (LSB)). In an alternative example, the controller 26 can be based on a peak and a lower threshold V. TL The voltage difference comes from the increase in the rate of change of the first ramp 30, which is adaptively altered.

[0117] Figure 8b The fourth ramp 30d of the first ramp signal 30 is shown, which exceeds the upper limit threshold V at the time point / phase angle marked A1. TL Therefore, controller 26 reduces the rate of change of the fifth ramp 30e of the first ramp signal 30. The fifth ramp 30e of the first ramp signal 30 exceeds the upper limit threshold V at the time point / phase angle marked A1'. TL Therefore, controller 26 reduces the rate of change of the sixth ramp 30f of the first ramp signal 30. The sixth ramp 30f of the first ramp signal 30 is less than the upper limit threshold V at the time point / phase angle marked A1". TL And it exceeds the lower threshold V TU Therefore, Figure 8c The graph shows that the frequency is locked, that is, the rate of change of the first ramp 30 is maintained.

[0118] like Figure 8c As shown, when controller 26 determines that two (or more) sequential ramps (e.g., in a regular order, without gaps) of the first ramp signal 30 have a value less than the upper limit threshold V TU And greater than the lower threshold V TL When the peak value is reached, the frequency can be considered "locked". The frequency tracking algorithm is then configured to track the frequency if the peak value remains less than (or equal to) an upper limit threshold V. TUAnd greater than (or equal to) the lower threshold V TL Then the rate of change of the first ramp signal 30 is maintained.

[0119] Figure 8a , Figure 8b and Figure 8c The effect of frequency tracking algorithm 60 relative to the first ramp signal 30 is shown. However, the frequency tracking algorithm can also be used to independently control the rate of change of the second ramp signal 31 in a similar manner.

[0120] Figure 9 The process of a frequency tracking algorithm 60 that can be applied to a first ramp signal 30 and / or a second ramp signal 31 is illustrated. Specifically, the frequency tracking algorithm 60 may include the following steps:

[0121] At step S1, the process begins, and subsequently enters a waiting state at steps S2 and S3 to allow the fourth transistor MP1 to switch from its off state to its on state (i.e., in...). Figure 4 (The time point / phase angle marked as A1 in the middle).

[0122] At process step S4, when it is determined that the fourth transistor MP1 switches from its off state to its on state (i.e., at...), Figure 4 At the time point / phase angle marked A1, this process determines the peak value of the first ramp signal 30 (e.g., the AC voltage input signal V). AC_IN (Once per cycle).

[0123] At decision step S5, the peak value is compared with the upper limit threshold V. TU and lower limit threshold V TL Compare the values. If the peak value is greater than the lower threshold V... TL And less than the upper threshold V TU Then the process continues to step S6. If the peak value is less than the lower threshold V TL or greater than the upper threshold V TU Then the process continues to step S7.

[0124] At process step S6, controller 26 signals that the locking condition has been met, and at process step S8, controller 26 does not adjust the rate of change of the first ramp signal 30.

[0125] At process step S7, controller 26 signals that the locking condition has not been met, and at process step S9, controller 26 is configured to adjust the rate of change of the first ramp signal 30. Specifically, if the peak value is equal to or greater than the upper limit threshold V... TU Then the rate of change of the first slope 30 decreases. If the peak value is equal to or less than the lower threshold V TL Then the rate of change of the first slope 30 increases.

[0126] from Figure 9 As can be seen, the frequency tracking algorithm 60 is repeated. This frequency tracking algorithm 60 ensures precise control of the ramp slope (i.e., the rate of change of the first ramp signal 30) to maintain system stability and performance within defined operating thresholds. The frequency tracking algorithm 60 is shown relative to the first ramp signal 30. However, the frequency tracking algorithm can also be used to independently control the rate of change of the second ramp signal 31 in a similar manner.

[0127] Figure 10 An example of a schematic wiring diagram of a full-wave active rectifier system 40 for performing the method according to the invention is shown. Figure 10 The full-wave active rectifier system 40 illustrates certain alternative examples of the first block 41, the second block 42, the third block 43, and the fourth block 44. The same reference numerals are used to indicate... Figure 6 The same / corresponding features will not be described in detail below. For clarity, Figure 10 Controller 26 is not shown in the diagram. It should be understood that the outputs of the first block 41, the second block 42, the third block 43, and the fourth block 44 can be provided as inputs to controller 26.

[0128] like Figure 10 As shown, the third block 43 includes a first sensing transistor 54a (which may also be referred to as a fifth transistor), a first resistor 56a, and a first comparator 58a. The first sensing transistor 54a is arranged to switch between its off and on states when the third transistor MP2 switches between its off and on states. The first comparator 58a is arranged to sense whether the first sensing transistor 54a is switched between its off and on states. The first ramp signal 30 can be reset based on the output from the first comparator 58a.

[0129] The control terminal of the first sensing transistor 54a is electrically coupled to the control terminal GP2 of the third transistor MP2. The second channel terminal (e.g., source) of the first sensing transistor 54a is electrically coupled to the voltage output node 12. The first channel terminal (e.g., drain) of the first sensing transistor 54a is electrically coupled to the first terminal of the first resistor 56a and the input of the first comparator 58a. The second terminal of the first resistor 56a is electrically coupled to DC ground (GND). The first resistor 56a can be arranged to limit the output signal V from the DC voltage when the first sensing transistor 54a is in its on state (e.g., having high resistance). DC_OUT Current flowing to DC ground (GND). The first comparator 58a can be a Schmitt trigger to provide noise immunity.

[0130] While the third block 43 has been described above, the fourth block 44 can provide corresponding components arranged in a similar manner. For example, the fourth block 44 is shown to include a second sensing transistor 54b (which may also be referred to as a sixth transistor), a second resistor 56b, and a second comparator 58b, corresponding to the first sensing transistor 54a, the first resistor 56a, and the first comparator 58a, respectively. The second ramp signal 31 can be reset based on the output from the second comparator 58b.

[0131] Figure 11 The AC voltage input signal V corresponding to the ramp signal 30 and the first control signal 52 is shown. AC_IN The cyclic curve. The first control signal 52 is provided to the control terminal GN1 of the first transistor MN1, which can be as follows: Figure 7 As shown, the second ramp signal 31 was not generated. Figure 11 As shown, but it can also exist in a similar manner to generate a second control signal provided to the control terminal GN2 of the second transistor MN2.

[0132] return Figure 10 The first block 41 includes a first transient detection comparator 41a. The first transient detection comparator 41a includes components coupled to the first node D1 and configured to compare a first voltage with a control voltage threshold (-V). th The second block 42 also includes a second transient detection comparator 42a. The second transient detection comparator 42a includes components coupled to the second node D2 and configured to compare the second voltage with a control voltage threshold (-V). th The input for comparison. In some instances, only a single transient detection comparator 41a may be arranged to compare the voltage at the first node D1 and the second node D2 with the control voltage threshold (-V). th The two transient detection comparators 41a and 42a are compared. Advantageously, they provide redundancy and reduce processing at controller 26, allowing controller 26 to respond more quickly. Sensing of voltage transients at the first node D1 is based on the output of the first transient detection comparator 41a. Sensing of voltage transients at the second node D2 is based on the output of the second transient detection comparator 42a. Figure 10 As shown, each of the first transient detection comparator 41a and the second transient detection comparator 42a can be enabled and disabled via the corresponding first comparator control signal en1 and the second comparator control signal en2.

[0133] refer to Figure 11The first transient detection comparator 41a can be arranged to deactivate when the first transistor MN1 is activated (i.e., at the activation phase angle 28A) and to activate when the first transistor MN1 deactivates (i.e., at the deactivation phase angle 28B). Advantageously, this avoids undesirable switching changes at the output of the first transient detection comparator 41a. Alternatively, the first transient detection comparator 41a can also be arranged to deactivate when the fourth transistor MP1 deactivates (i.e., at the phase angle 28B). It is activated at A1, and when the third transistor MP2 fails (i.e., at phase angle...). The first transient detection comparator 41a fails at point B1. Advantageously, since it is known that the first transient detection comparator 41a will not switch during this period, the failure of the first transient detection comparator 41a improves the efficiency of the system.

[0134] A first comparator control signal en1 can be provided to disable (i.e., deactivate) the first transient detection comparator 41a when the first transistor MN1 switches from its off state to its on state (i.e., at the activation phase angle 28A). That is, the first comparator control signal en1 can be provided to disable the first transient detection comparator 41a when the first ramp signal 30 reaches the activation threshold voltage Vt_on. Optionally, the first comparator control signal en1 can be provided to enable the first transient detection comparator 41a when the fourth transistor MP1 switches from its on state to its off state.

[0135] A first comparator control signal en1 can be provided to enable (i.e., activate) the first transient detection comparator 41a when the first transistor MN1 switches from its on state to its off state (i.e., at the failure phase angle 28B). That is, the first comparator control signal en1 can be provided to enable the first transient detection comparator 41a when the first ramp signal 30 reaches the failure threshold voltage Vt_off. Optionally, the first comparator control signal en1 can be provided to disable the first transient detection comparator 41a when the third transistor MP2 switches from its on state to its off state.

[0136] Although the first transient detection comparator 41a and the first comparator control signal en1 have been described above, the second transient detection comparator 42a and the second comparator control signal en2 can operate in a similar manner. Specifically, the second transient detection comparator 42a can be arranged to deactivate when the second transistor MN2 is activated, and can also be arranged to activate when the second transistor MN2 is deactivated. Advantageously, this avoids undesirable switching changes at the output of the second transient detection comparator 42a. Alternatively, the second transient detection comparator 42a can also be arranged to deactivate when the third transistor MP2 is deactivated (i.e., at the phase angle...). It is activated at B1, and when the fourth transistor MP1 fails (i.e., at the phase angle) The second transient detection comparator 42a fails at point A1. Advantageously, since it is known that the second transient detection comparator 42a will not switch during this period, the failure of the second transient detection comparator 42a also improves the efficiency of the system.

[0137] A second comparator control signal en2 can be provided to disable (i.e., disable) the second transient detection comparator 42a when the second transistor MN2 switches from its off state to its on state. That is, the second comparator control signal en2 can be provided to disable the second transient detection comparator 42a when the second ramp signal 31 reaches a second activation threshold voltage (similar to but independent of the activation threshold voltage Vt_on generation). Optionally, the second comparator control signal en2 can be provided to enable the second transient detection comparator 42a when the third transistor MP2 switches from its on state to its off state.

[0138] A second comparator control signal en2 can be provided to enable (i.e., activate) the second transient detection comparator 42a when the second transistor MN2 switches from its off state to its on state. That is, the second comparator control signal en2 can be provided to enable the second transient detection comparator 42a when the second ramp signal 31 reaches a second failure threshold voltage (similar to but independent of the failure threshold voltage Vt_off generation). Optionally, the second comparator control signal en2 can be provided to disable the second transient detection comparator 42a when the fourth transistor MP1 switches from its on state to its off state.

[0139] Figure 12 The first and second transient detection comparators 41a, 41b are shown relative to the AC voltage input signal V. AC_IN The output. AC voltage input signal V. AC_IN The two loops in Figure 12 The diagram shows that the first transistor MN1 is in its ON state twice, and the second transistor MN2 is in its ON state twice. AC voltage input signal V AC_IN It is shown as distorted. In an example, if the AC input voltage signal V AC_IN Whether the current is sinusoidal, generally non-sinusoidal, or distorted, the full-wave active rectifier systems 20 and 40 can operate equally well.

[0140] like Figure 12 As shown, line graph 62 illustrates the voltage difference between the first voltage at the first node D1 and the second voltage at the second node D2. Line graph 64 illustrates the negative (i.e., f(x) to -f(x)) of line graph 62. Partial line graphs 62a and 62b illustrate the reference DC voltage output signal V. DC_OUT The enlarged version of the line graph marked 62.

[0141] like Figure 12 As shown, the first signal 66 is the output of the first transient detection comparator 41a (or typically the output of the first block 41). The second signal 68 is the output of the second transient detection comparator 42a (or typically the output of the second block 42).

[0142] Figure 12 The second voltage transient 65b in partial line diagram 62a is shown, corresponding to the timing of the first transistor MN1 switching from its on state to its off state. The second voltage transient 65b is detected by a first transient detection comparator 41a. The first transient detection comparator 41a generates a second flag 66b [VT_NEG_RIS] in the first signal 66. The second flag 66b [VT_NEG_RIS] can be a detectable high voltage in the first signal 66. The failure phase angle 28B of the first transistor MN1 can be controlled by the controller 26 in response to the second flag 66b [VT_NEG_RIS] of the first signal 66 (to change the timing of the first transistor MN1 to its off state).

[0143] Figure 12 A first voltage transient 65a is shown in partial line diagram 62b, corresponding to the timing of the first transistor MN1 switching from its off state to its on state. The first voltage transient 65b is detected by a first transient detection comparator 41a to generate a first flag 66a [VT_NEG_FAL] in the first signal 66. The first flag 66a [VT_NEG_FAL] can be a detectable high voltage in the first signal 66. The activation phase angle 28A of the first transistor MN1 can be controlled by the controller 26 in response to the first flag 66a [VT_NEG_FAL] in the first signal 66 (to change the timing of the first transistor MN1 to its on state).

[0144] like Figure 12 As shown, partial line diagrams 64a and 64b illustrate the reference DC voltage output signal V. DC_OUT An enlarged version of the line graph marked 64. Voltage transients (e.g., 65c, 65d) in portions of line graphs 64a and 64b can be detected by a second transient detection comparator 42a to generate a first flag 68a [VT_NEG_FAL] and / or a second flag 68b [VT_NEG_RIS] in the second signal 68 in a similar manner to that described above. The activation phase angle and / or deactivation phase angle of the second transistor MN2 can be controlled by the controller 26 in response to the first flag 68a [VT_NEG_FAL] and / or the second flag 68b [VT_NEG_RIS] of the second signal 68 (to change the timing of the second transistor MN2 to its on or off state, respectively).

[0145] Figure 13A partial line graph 62a of the voltage at the first node D1 at the input of the first transient detection comparator 41a is shown, along with a corresponding graph showing the output of the first transient detection comparator 41a (i.e., the first signal 66) versus time. The first transient detection comparator 41a generates a second flag 66b [VT_NEG_RIS] in the first signal 66, indicating that the controller 26 prematurely controls the first transistor MN1 to switch between its on and off states. Therefore, by controlling the first transistor MN1 to switch between its on and off states at a later time point, the full-wave active rectifier systems 20, 40 can operate more efficiently. In response to sensing the first voltage transient 65b, the controller 25 can control the failure phase angle to delay the switch of the first transistor MN1 from the on state to the off state (e.g., by increasing the failure threshold voltage Vt_off).

[0146] Although Figure 13 Partial line diagram 62a is shown, but it can be used to generally understand how any voltage transient (e.g., 65a, 65b, 65c, 65d) can be detected by the first transient detection comparator 41a or the second transient detection comparator 42a.

[0147] Figure 13 The activation phase angle 28A and deactivation phase angle 28B of the first transistor MN1 are shown. Figure 10 and Figure 11 As described, when the first transistor MN1 is in its on state, the first transient detection comparator 41a can be disabled. That is, the first transient detection comparator 41a is disabled at the active phase angle 28A of the first transistor MN1 and enabled at the inactive phase angle 28B of the first transistor MN1. The first transient detection comparator 41a is configured to compare the voltage represented by partial line diagram 62a with a control voltage threshold (-V). th The first transient detection comparator 41a is configured to compare the voltage represented by the partial curve 62a with a control voltage threshold (e.g., -70mV). th If the first signal 66 is switched to a high level (as indicated by the second flag 66b [VT_NEG_RIS]), then the second voltage transient 65b is caused by the first transistor MN1 switching to its off state. This results in the AC voltage input signal V corresponding to the first node D1 (i.e., not connected to the ground node GND). AC_IN The second voltage transient of the voltage is 65b.

[0148] Figure 13 The second voltage transient 65b is shown to exceed the control voltage threshold (-V) between the failure phase angle 28B and the phase angle marked 69. thThe first transient detection comparator 41a detects the second voltage transient 65b and generates a second flag 66b [VT_NEG_RIS]. Due to circuit speed limitations, there may be a delay between the generation of the second voltage transient 65b and the generation of the second flag 66b [VT_NEG_RIS] (e.g., ...). Figure 13 (As shown). However, advantageously, this delay does not affect the efficiency of the full-wave active rectifier systems 20, 40, because the controller 26 responds to the AC voltage input signal V. AC_IN In the next cycle, the second flag 66b[VT_NEG_RIS] is applied (to delay the first transistor MN1 from switching from the on state to the off state). Figure 13 It is also shown that a minor voltage transient 67 prior to the first transient detection comparator 41a being disabled at the activation phase angle 28A of the first transistor MN1 is present. However, due to circuit speed limitations, there is not enough time for the minor voltage transient 67 to be sensed by the first transient detection comparator 41a and / or to generate the first flag 66a [VT_NEG_FAL] in the first signal 66.

[0149] In one example, transient detection comparators 41a and 42a can generate flag signals 66a, 66b, 68a, and 68b indicating that the voltage at nodes D1 and / or D2 exceeds a control voltage threshold. The controller can be configured to control the phase angle of the first or second transistor MN1, MN2 based on the flag signals 66a, 66b, 68a, and 68b and the determination of the switching between an on and off state of the first or second transistor MN1, MN2. For example, controller 26 can be configured to generate signals that switch the first or second transistor MN1, MN2 between their respective on and off states; thus, controller 26 can determine the correspondence between the received flag signals 66a, 66b, 68a, and 68b and the control of the first or second transistor MN1, MN2. Therefore, controller 26 can determine whether the activation or deactivation phase angle should be anticipated or delayed based on the received flag signals 66a, 66b, 68a, 68b and the determination of the switching between the on and off states of the first or second transistors MN1, MN2, for example, according to the discussion below. Figure 14 .

[0150] Figure 14 The process of adjustment algorithm 70 is illustrated, which can be applied by controller 26 to control the phase angle (e.g., ) of the first transistor MN1 switching between on and off states in response to a sensed voltage transient. Figure 7(28A or 28B). The adjustment algorithm 70 can be applied to anticipate or delay the first transistor MN1 switching from its off state to its on state, and to anticipate or delay the first transistor MN1 switching from its on state to its off state. Advantageously, the adjustment algorithm 70 improves the efficiency of the full-wave rectifier systems 20, 40 by controlling the activation phase angle and / or deactivation phase angle of the first transistor MN1.

[0151] like Figure 12 As shown, the full-wave active rectifier systems 20 and 40 can perform the frequency tracking algorithm 60 process (i.e., steps S1 to S9) before the adjustment algorithm 70 process. In an alternative example, the AC voltage input signal V AC_IN The frequency is known, and the rate of change of the first ramp signal 30 is predetermined.

[0152] Specifically, adjusting algorithm 70 may include the following steps:

[0153] In step S10, the process begins when it is determined that the frequency tracking algorithm 60 has reached the locking condition.

[0154] In optional step S11, when the full-wave active rectifier systems 20 and 40 are started, the controller 26 is arranged to set the activation phase angle 28A to be equal to the failure phase angle 28B. That is, the activation threshold voltage Vt_on can be set to be equal to the failure threshold voltage Vt_off. The activation phase angle 28A and failure phase angle 28B of the first transistor MN1 can be set to the AC voltage input signal Vt_off at the first node D1. AC_IN The peak value. The activation and deactivation phase angles of the second transistor MN2 can be set to the AC voltage input signal V at the second node D2. AC_IN The peak value (or 180° out of phase with respect to the activation phase angle 28A and failure phase angle 28B of the first transistor MN1). For example, the activation threshold voltage Vt_on and failure threshold voltage Vt_off can be set to approximately 75% (or 70%) of the peak value of the first ramp signal 30.

[0155] In step S12, the controller 26 determines the AC voltage input signal V. AC_IN The appropriate point to begin in the loop. For example, controller 26 determines the AC voltage input signal V. AC_IN A new half-cycle begins.

[0156] At step S13, the third transistor MP2 switches from its off state to its on state.

[0157] In step S14, the first block 41 compares the voltage at the first node D1 with the control voltage threshold -V. thA comparison is performed. First block 41 generates a first signal 66, which may or may not include a first flag 66a [VT_NEG_FAL]. Furthermore, the first transistor MN1 switches from its off state to its on state.

[0158] At decision step S15, controller 26 determines whether a first voltage transient 65a is detected and corresponds to switching the first transistor MN1 from its off state to its on state. For example, a first transient detection comparator 41a generates a first signal 66 including a first flag 66a [VT_NEG_FAL], and controller 26 detects the presence or absence of the first flag 66a in the first signal 66. Controller 26 can detect the presence or absence of the first flag 66a corresponding to the transition of the first transistor MN1 from its off state to its on state. In an alternative instance, controller 26 can use a first acceptance band or any other method to detect the presence or absence of the first flag 66a. The first acceptance band can be a first predetermined phase angle band (e.g., 10°). The activation phase angle 28A can be the limit of the first acceptance band. For example, if the activation phase angle 28A is 80°, the first acceptance band can be between 70° and 80°. Alternatively, the first acceptance band can be the activation phase angle 28A + x°, where it can be 5, 10, 15, 20, or 30, etc.

[0159] If controller 26 determines that it has detected (optionally, within the first acceptance band) a first voltage transient 65a corresponding to the first transistor MN1 switching from its off state to its on state, the process continues to step S16. If controller 26 determines that it has not detected (optionally, within the first acceptance band) a first voltage transient 65a corresponding to the first transistor MN1 switching from its off state to its on state, the process continues to step S17.

[0160] At step S16, controller 26 is configured to adjust the activation phase angle 28A (e.g., via an activation threshold voltage Vt_on). Specifically, controller 26 may be configured to decrease the activation phase angle 28A (e.g., via an activation threshold voltage Vt_on) in response to sensing a first voltage transient 65a. Controller 26 may reduce the activation threshold voltage Vt_on by a fixed voltage level. The fixed voltage level may be equivalent to at least one least significant bit (LSB) of a digital-to-analog converter (DAC). The DAC may be an internal component of controller 26. In some instances, the adjustment of the activation phase angle 28A (e.g., via the activation threshold voltage Vt_on) and / or the failure phase angle 28B (e.g., via a failure threshold voltage Vt_off) may be based on the length of the first flag 66a or the second flag 66b (e.g., the time length between the rising and falling edges). For example, the activation threshold voltage Vt_on may be reduced by a voltage proportional to the time length between the rising and falling edges of the first flag 66a of the first signal 66.

[0161] At step S17, controller 26 is configured to adjust the activation phase angle 28A (e.g., via the activation threshold voltage Vt_on). Specifically, controller 26 may be configured to increase the activation phase angle 28A (e.g., via the activation threshold voltage Vt_on) in response to sensing a first voltage transient 65a. Controller 26 may increase the activation threshold voltage Vt_on by a fixed voltage level (e.g., by increasing the DAC by 1 LSB).

[0162] In step S18, the first block 41 compares the voltage at the first node D1 with the control voltage threshold (-V). th The comparison is performed. First block 41 generates a first signal 66, which may or may not include a second flag 66b [VT_NEG_RIS]. Furthermore, the first transistor MN1 switches from its on state to its off state.

[0163] At decision step S19, controller 26 determines whether a second voltage transient 65a corresponding to switching the first transistor MN1 from its on state to its off state is detected. For example, first transient detection comparator 41a generates a first signal 66 including a second flag 66b [VT_NEG_RIS], and controller 26 detects the presence or absence of the second flag 66b in the first signal 66. Controller 26 can detect the presence or absence of the second flag 66b corresponding to the transition of the first transistor MN1 from its on state to its off state. Alternatively, controller 26 can use a second acceptance band or any other method to detect the presence or absence of the second flag 66b. The second acceptance band can be a second predetermined phase angle band (which can be equal to or different from the first predetermined phase angle band, for example, 10°). The failure phase angle 28B can be the limit of the second acceptance band. For example, if the failure phase angle 28B is 95°, the second acceptance band can be between 95° and 105°. Alternatively, the second acceptance band can be the failure phase angle 28B±y°, where y can be x, 5, 10, 15, 20 or 30, etc.

[0164] If the controller 26 determines that it has detected (optionally within the second acceptance band) a second voltage transient 65b corresponding to the first transistor MN1 switching from its on state to its off state, the process continues to step S20. If the controller 26 determines that it has detected (optionally within the second acceptance band) a second voltage transient 65b corresponding to the first transistor MN1 switching from its on state to its off state, the process continues to step S21.

[0165] At step S20, controller 26 is configured to adjust the failure phase angle 28B (e.g., via the failure threshold voltage Vt_off). Specifically, controller 26 may be configured to increase the failure phase angle 28B (e.g., via the failure threshold voltage Vt_off) in response to sensing a second voltage transient 65b. Controller 26 may increase the failure threshold voltage by a fixed voltage level (e.g., by increasing the DAC by 1 LSB).

[0166] At step S21, controller 26 is configured to adjust the failure phase angle 28B (e.g., via the failure threshold voltage Vt_off). Specifically, controller 26 may be configured to reduce the failure phase angle 28B (e.g., via the failure threshold voltage Vt_off) in response to sensing a second voltage transient 65b. Controller 26 may reduce the failure threshold voltage by a fixed voltage level (e.g., increase the DAC by 1 LSB).

[0167] At optional step S22, controller 26 may wait for AC voltage input signal V. AC_IN A new semi-cycle.

[0168] from Figure 14 As can be seen, adjustment algorithm 70 is repeated. This adjustment algorithm 70 ensures precise control of the phase angle of the first transistor MN1 switching between the on and off states in response to transient changes in the sensed voltage, so as to maintain system stability and optimize performance within a defined operating threshold. Adjustment algorithm 70 is shown relative to the first ramp signal 30. However, adjustment algorithm 70 can also be used to independently control the rate of change of the second ramp signal 31 in a similar manner.

[0169] In response to the sensing (or non-sensing) of a first voltage transient 65a and / or a second voltage transient 65b, the aforementioned adjustment algorithm 70 controls the activation phase angle 28A and the failure phase angle 28B of the first transistor MN1 as it switches between an on state and an off state. The adjustment algorithm 70 can similarly be configured to control the second activation phase angle and the second failure phase angle of the second transistor MN2 as it switches between an on state and an off state in response to the sensing (or non-sensing) of a third voltage transient 65c and / or a fourth voltage transient 65d.

[0170] Figure 15 Multiple signals corresponding to the switching of the first transistor MN1 (as previously described) are shown, their common time scale responding to the AC voltage input signal V. AC_IN The three cycles are shown. The activation threshold voltage Vt_on from V is illustrated in response to sensing a first voltage transient 65a. DAC2 Reduce to V DAC1 The diagram illustrates how, in response to the sensing of the absence of a voltage transient corresponding to the first transistor MN1 switching from its off state to its on state, the activation threshold voltage Vt_on is activated from V... DAC1 Increase to V DAC2 The diagram shows the failure threshold voltage Vt_off from V in response to the sensing of a second voltage transient 65b. DAC3 Increase to V DAC4 The diagram illustrates how, in response to the sensing of the absence of a voltage transient corresponding to the first transistor MN1 switching from its on state to its off state, the failure threshold voltage Vt_off changes from V... DAC4 Reduce to V DAC3 V DAC1 V DAC2 V DAC3 V DAC4 These represent the four possible output voltages of the DAC.

[0171] Although reference Figure 15 The signal corresponding to the switch of the first transistor MN1 is described, but it should be understood that the full-wave active rectifier systems 20 and 40 also generate the signal corresponding to the switch of the second transistor MN2 in a similar manner.

[0172] Figure 16The full-wave active rectifier systems 20 and 40 according to the present invention are shown to receive an AC voltage input signal V. AC_IN The generated DC voltage output signal V DC_OUT The curve graph. Figure 16 The first control signal 52 of the first transistor MN1 is also shown. Figure 16 This shows the AC voltage input signal V. AC_IN The frequency is 13.6MHz, and with an AC voltage input amplitude of 14V, it achieves a conversion efficiency of 93.1% in a typical BCD process.

[0173] In comparison, Figure 17 This illustrates the effect of a Schottky diode rectifier on the AC voltage input signal V. AC_IN The generated DC voltage output signal V DC_OUT The curve graph. Figure 17 This shows the AC voltage input signal V. AC_IN With a frequency of 13.6MHz, and with an AC voltage input amplitude of 14V, the Schottky diode rectifier achieves a conversion efficiency of 88.8% in the same BCD process as described above.

[0174] Therefore, the full-wave active rectifier systems 20 and 40 of the present invention improve efficiency by controlling the first and second transistors MN1 and MN2.

[0175] Each transistor MN1, MN2, MP2, MP1 includes corresponding control terminals GN1, GN2, GP2, GP1, as well as a first channel terminal and a second channel terminal (i.e., the current-carrying portion). Each transistor MN1, MN2, MP2, MP1 can be a FET or more specifically a MOSFET. When each transistor MN1, MN2, MP2, MP1 is a MOSFET, the corresponding control terminals GN1, GN2, GP1, GP2 are gate terminals, the corresponding first channel terminal is the drain terminal, and the corresponding second channel terminal is the source terminal.

[0176] Figure 2 and Figure 6 Each box is shown and defined for illustrative purposes only, and it will be well understood that the algorithm or function represented by each box can be implemented in many other ways, as long as the described function exists. For example, Figure 2 and / or Figure 6 The boxes can be combined and implemented as part of a circuit layout, on a single integrated circuit, processor, or computer, or by multiple circuit layouts, integrated circuits, processors, and / or computers.

[0177] While the examples in this paper describe a ramp signal 30, in alternative examples, any altered signal can be used. The altered signal can be a "one-to-one function" and track the frequency of the AC voltage input signal. The altered signal can be a changing voltage signal. For example, the altered signal can be generated by a charging capacitor, which would result in a non-linear voltage signal. In the examples in this paper, the altered signal is shown as increasing, but in alternative examples, the altered signal could be decreasing.

[0178] The control voltage threshold is between ground level (GND) and -Vt, where Vt is the cut-in voltage of the body diode of the first transistor MN1 and / or the second transistor MN2. Preferably, the control voltage threshold is between GND and -Vt / 2, and more preferably approximately 70mV.

[0179] In such Figure 2 , Figure 6 and Figure 10 In one example, the first node D1 is electrically coupled to the control terminal GP2 of the third transistor MP2, and the second node D2 is electrically coupled to the control terminal GP1 of the fourth transistor MP1. In an alternative example, the control terminals of the third transistor MP2 and the fourth transistor MP1, i.e., GP2 / GP1, can be generated by the voltages on the first node D1 and the second node D2 via one or more voltage limiting circuits. Advantageously, the VGS / VSG ratings of the third and fourth transistors can be low voltages (e.g., 2V), but the rectifier can be designed to operate (e.g., 14V), so that the voltage limiting circuits can generate the control terminal voltages GP1 / GP2 from D1 / D2 such that the voltage difference (VDC_OUT-VGP1) and (VDC_OUT-VGP2) does not exceed the low voltage (e.g., 2V).

[0180] An operating mode of a control loop (i.e., an industrial control loop or closed-loop control) for controlling an active transistor in a full-wave active rectifier according to this disclosure includes a controller for receiving an input signal representing the offset between a generated phase angle (e.g., at time t = -1) of a control signal for the active transistor and an ideal phase angle of the control signal for the active transistor, and for generating an output signal based on the input signal and corresponding to the generated phase angle of the control signal for the active transistor (e.g., at time t = 0). The active transistor is configured to receive the output signal at its control terminal. The controller can adjust the process in response to the output signal. The controller uses a control algorithm to generate an output signal for the current iteration of the loop (e.g., at time t = 0). The controllable device adjusts the process so that the output signal is oriented toward the ideal phase angle of the control signal for the active transistor, which is represented by a voltage transient at a channel terminal where no active transistor is detected, which will be used as the input for the next iteration of the loop (e.g., at time t = 1). The controller can be implemented as a computer program executing on a processor, and the active transistor can be connected to the controller via an electrical link or a communication link.

[0181] A symmetrical AC signal is a signal with half-wave symmetry, consisting of identical half-cycles with opposite polarities. Due to this alternating characteristic, the signal's average value is zero.

[0182] Unless the context explicitly requires otherwise, throughout the specification and claims, the terms “comprise”, “comprising”, “include”, “including”, etc., should be interpreted as inclusive rather than exclusive or exhaustive; that is, in the sense of “including but not limited to”.

[0183] As commonly used herein, the terms “coupled” or “connected” refer to two or more elements that can be directly connected or connected via one or more intermediate elements. Additionally, when used in this application, the terms “this article,” “above,” “below,” and terms with similar meanings should refer to the entire application and not any particular part of it. Where the context permits, singular or plural terms used in the specific embodiment may also include either the plural or the singular, respectively. When referring to a list of two or more items, the term “or” is intended to cover all of the following interpretations: any item in the list, all items in the list, and any combination of items in the list.

[0184] It should be understood that one or more features from one or more embodiments of the above embodiments may be combined with one or more features from one or more other embodiments of the above embodiments to form further embodiments within the scope of the appended claims.

[0185] Numbering Clauses

[0186] As a non-limiting example, some aspects of this disclosure are set forth in the following numbered clauses.

[0187] Clause 1 - A full-wave active rectifier system, said full-wave active rectifier system comprising:

[0188] A full-wave active rectifier for generating a DC voltage output signal based on an AC voltage input signal, the full-wave active rectifier comprising: a first transistor and a second transistor, the first transistor and the second transistor being controllable by a controller; and a third transistor and a fourth transistor, the third transistor and the fourth transistor being controlled by the AC voltage input signal; and

[0189] The controller is coupled to the first transistor;

[0190] The full-wave active rectifier system is configured as follows:

[0191] When the first transistor is in the off state, monitor the first voltage at the first node shared by the AC voltage input signal and the first terminal of the first transistor; and

[0192] The voltage transient of the first voltage caused by switching the first transistor between the on state and the off state is sensed;

[0193] The controller is configured as follows:

[0194] The phase angle by which the first transistor switches between the on state and the off state in response to sensing the voltage transient.

[0195] Clause 2 - In the system described in Clause 1, wherein the phase angle is an activation phase angle, which is controlled to anticipate the switching of the first transistor from the off state to the on state in response to sensing the voltage transient [(VT_NEG_FAL = 1)].

[0196] Clause 3 - A system according to any one of Clauses 1 or 2, [wherein the phase angle is an active phase angle], wherein the active phase angle is controlled to delay the switching of the first transistor from the off state to the on state in response to the failure to sense the voltage transient [(VT_NEG_FAL=0)] during the period of the AC voltage input signal.

[0197] Clause 4 - A system according to any one of Clauses 1 to 3, [wherein the phase angle is a failure phase angle, or the system further includes a failure phase angle], wherein the failure phase angle is controlled to delay the switching of the first transistor from the on state to the off state in response to sensing the voltage transient [(VT_NEG_RIS=1)].

[0198] Clause 5 - A system according to any one of Clauses 1 to 4, [wherein the phase angle is a failure phase angle, or the system further includes a failure phase angle], wherein the failure phase angle is controlled to anticipate the switching of the first transistor from the on state to the off state in response to the absence of sensing of the voltage transient [(VT_NEG_RIS = 0)] during the period of the AC voltage input signal.

[0199] Clause 6 - A system according to any of the preceding numbered clauses, wherein the controller is further configured to generate a modified voltage signal [optionally, the modified voltage signal is a ramp] based on the frequency of the AC voltage input signal, wherein the phase angle is determined based on the modified voltage signal reaching a first threshold.

[0200] Clause 7 - In the system described in Clause 6, when subject to Clause 4 or 5, the failure phase angle is determined based on the altered voltage signal reaching a second threshold.

[0201] Clause 8 - The system described in Clause 7, wherein the second threshold is greater than the first threshold.

[0202] Clause 9 - A system according to any one of Clauses 6 to 8, wherein the changed voltage signal is generated when it is determined that one of the third transistor or the fourth transistor is switching between an off state and an on state.

[0203] Clause 10 - A system according to any one of Clauses 6 to 9, wherein the [first and / or second] altered voltage signal is a "one-to-one function" and tracks the frequency of the AC voltage input signal.

[0204] Clause 11 - A system according to any one of Clauses 6 to 10, wherein the controller is configured to reset the [first and / or second] changed voltage signal when the third transistor or the fourth transistor switches between an off state and an on state.

[0205] Clause 12 - A system according to any one of Clauses 6 to 11, wherein the controller is configured to operate a frequency tracking algorithm, the frequency tracking algorithm being configured to: determine the peak value of the changed voltage signal, wherein the changed voltage signal has a corresponding rate of change; and if the peak value does not exceed a lower threshold, increase the rate of change of the changed voltage signal; or if the peak value exceeds an upper threshold, decrease the rate of change of subsequent changed voltage signals.

[0206] Clause 13 - The system according to Clause 12, wherein the changed voltage signal is reset after it reaches its peak value.

[0207] Clause 14 - A system according to any one of Clauses 12 or 13, wherein the frequency tracking algorithm is further configured to maintain the rate of change of the subsequently changed voltage signal if the peak value exceeds the lower threshold and does not exceed the upper threshold.

[0208] Clause 15 - A system according to any one of Clauses 6 to 14, wherein the changed voltage signal is a ramp signal.

[0209] Clause 16 - In a system pursuant to any of the preceding numbered clauses, when subject to Clause 7, the controller is further configured to set the first threshold to be equal to the second threshold when the full-wave active rectifier is started.

[0210] Clause 17 - In any of the preceding numbered clauses, the first terminal of the first transistor is the drain of the first transistor.

[0211] Clause 18 - In any of the preceding numbered clauses, the first terminal of the second transistor is the drain of the second transistor.

[0212] Clause 19 - In any of the preceding numbered clauses, the voltage transient is sensed by comparing the first voltage with a control voltage threshold, wherein the control voltage threshold is between ground level (GND) and -Vt, where Vt is the cut-in voltage of the body diode of the first transistor, and preferably between GND and -Vt / 2.

[0213] Clause 20 - A system according to any one of the preceding numbered clauses, wherein each transistor includes a control terminal and a first channel terminal and a second channel terminal (i.e., a current-carrying portion), wherein the full-wave active rectifier includes: a first AC voltage input node coupled to a first channel terminal (drain) of the fourth transistor, a first channel terminal (e.g., drain) of the first transistor, and a control terminal of the third transistor; a second AC voltage input node coupled to a first channel terminal (e.g., drain) of the third transistor, a first channel terminal (e.g., drain) of the second transistor, and a control terminal of the fourth transistor; a voltage output node coupled to a second channel terminal (e.g., source) of the third transistor and a second channel terminal (e.g., source) of the fourth transistor; and a ground node coupled to a second channel terminal (e.g., source) of the first transistor and a second channel terminal (e.g., source) of the second transistor.

[0214] Clause 21 - A system according to any one of Clauses 19 or 20, wherein the full-wave active rectifier system comprises: a transient detection comparator including an input coupled to the first AC voltage input node and configured to compare the first voltage with the control voltage threshold, wherein the first voltage is the voltage at the first AC voltage input node.

[0215] Clause 22 - The system according to Clause 21, wherein the transient detection comparator is configured to: disable (B2) when the first transistor is in the on state; and be activated (B3) when the first transistor is in the off state.

[0216] Clause 23 - A system according to any one of Clauses 21 or 22, wherein the transient detection comparator generates a flag signal indicating that the first voltage exceeds the control voltage threshold, wherein the controller is configured to control the phase angle based on the flag signal and a determination that the first transistor switches between the on state and the off state.

[0217] Clause 24 - A system according to any one of Clauses 21 to 23, wherein the transient detection comparator is a first transient detection comparator, and wherein the full-wave active rectifier layout includes: a second transient detection comparator, the second transient detection comparator including an input coupled to the second AC voltage input node and configured to compare the second voltage with the control voltage threshold, wherein the second voltage is the voltage at the second AC voltage input node.

[0218] Clause 25 - The system according to Clause 24, wherein the second transient detection comparator is configured to: disable when the second transistor is in the ON state (A2); and be activated when the second transistor is in the OFF state (A3).

[0219] Clause 26 - A system pursuant to any one of Clauses 6 to 25, wherein the controller is configured to: adjust the first threshold in response to sensing the voltage transient; and / or, when subject to Clause 7, adjust the second threshold in response to sensing the voltage transient.

[0220] Clause 27 - A system according to Clause 26, wherein the first threshold is reduced in response to sensing the voltage transient.

[0221] Clause 28 - A system according to any one of Clauses 26 or 27, wherein the second threshold is increased in response to sensing the voltage transient.

[0222] Clause 29 - A system according to any one of Clauses 26 to 28, wherein the first threshold and / or the second threshold is adjusted by a fixed voltage level.

[0223] Clause 30 - A system according to any one of Clauses 6 to 29, wherein the full-wave active rectifier system comprises: a digital-to-analog converter, DAC, configured to generate the first threshold, wherein the first threshold is adjusted by a voltage level corresponding to one least significant bit, LSB, of the DAC, and / or, when subject to Clause 7, the DAC is configured to generate the second threshold, wherein the second threshold is adjusted by a voltage level corresponding to one least significant bit, LSB, of the DAC.

[0224] Clause 31 - In any of the preceding numbered clauses, the operating frequency of the AC voltage input signal is between 5 MHz and 20 MHz.

[0225] Clause 32 - A system pursuant to any of the preceding numbered clauses, wherein each transistor is a FET and optionally a MOSFET.

[0226] It should be understood that the subject matter of at least any one of clauses 1 to 32 relates to features for controlling the first transistor. However, in other aspects of this disclosure, the features described in clauses 1 to 32 may relate to features for controlling a second transistor in a full-wave active rectifier system. The terms “first,” “second,” “third,” “fourth,” etc., are used herein as labels for identification purposes. The control of the second transistor may correspond to the control of the first transistor, or may differ at least based on instances relating to the control of the first transistor set forth herein. The following numbered clauses are some aspects of this disclosure that at least correspond to the control of the second transistor.

[0227] Clause 33 - According to any of the preceding numbered clauses, the full-wave active rectifier system is further configured as follows:

[0228] i. When the second transistor is in the off state, monitor the second voltage at the second node shared by the AC voltage input signal and the first terminal of the second transistor;

[0229] ii. Sensing a second voltage transient of the second voltage caused by switching the second transistor between the on state and the off state; and

[0230] The controller is configured as follows:

[0231] A second phase angle that controls the switching of the second transistor between an on state and an off state in response to sensing the second voltage transient.

[0232] Clause 34 - The system described in Clause 33, wherein the second phase angle is a second active phase angle, the second active phase angle being controlled to anticipate the switching of the second transistor from the off state to the on state in response to sensing the second voltage transient [(VT_NEG_FAL=1)].

[0233] Clause 35 - A system pursuant to any one of Clauses 33 or 34, [wherein the second phase angle is a second active phase angle], wherein the second active phase angle is controlled to delay the switching of the second transistor from the off state to the on state in response to the failure to sense the second voltage transient [(VT_NEG_FAL=0)] during the period of the AC voltage input signal.

[0234] Clause 36 - A system pursuant to any one of Clauses 33 to 35, [wherein the second phase angle is a second failure phase angle, or the system further includes a second failure phase angle], wherein the second failure phase angle is controlled to delay the switching of the second transistor from the on state to the off state in response to sensing the second voltage transient [(VT_NEG_RIS = 1)].

[0235] Clause 37 - A system according to any one of Clauses 33 to 36, [wherein the second phase angle is a second failure phase angle, or the system further includes a second failure phase angle], wherein the second failure phase angle is controlled to anticipate the switching of the second transistor from the on state to the off state in response to the absence of sensing of the second voltage transient [(VT_NEG_RIS = 0)] during the period of the AC voltage input signal.

[0236] Clause 38 - A system according to any one of Clauses 33 to 37, wherein the altered voltage signal is a first altered voltage signal, wherein the full-wave active rectifier system is further configured to generate a second altered voltage signal based on the frequency of the AC voltage input signal [optionally, the second altered voltage signal is a second ramp], wherein the second phase angle of the second transistor is determined based on the second altered voltage signal reaching a third threshold.

[0237] Clause 39 - In a system pursuant to any one of Clauses 33 to 38, when subject to Clause 36 or 37, the second failure phase of the second transistor is determined based on the second altered voltage signal reaching a fourth threshold, optionally said fourth threshold being greater than said third threshold.

[0238] Clause 40 - A system pursuant to any one of Clauses 33 to 39, wherein the changed voltage signal is a first changed voltage signal, and wherein the controller is configured to: reset the changed voltage signal when the fourth transistor switches between an off state and an on state, and, when subordinate to Clause 38, reset the second changed voltage signal when the third transistor switches between an off state and an on state.

Claims

1. A full-wave active rectifier system, the full-wave active rectifier system comprising: a full-wave active rectifier to generate a DC voltage output signal based on an AC voltage input signal, the full-wave active rectifier comprising: a controller; first and second transistors controllable by the controller; and third and fourth transistors controlled by the AC voltage input signal; wherein the full-wave active rectifier system is configured to: i. monitor a first voltage at an AC input node shared by the AC voltage input signal and a first terminal of the first transistor when the first transistor is in an off state; and ii. sense a voltage transient of the first voltage caused by switching the first transistor between an on state and the off state, wherein the controller is configured to: control a phase angle of the first transistor switching between the on state and the off state in response to sensing the voltage transient.

2. The system of claim 1, wherein the phase angle is an activation phase angle controlled to anticipate the switching of the first transistor from the off state to the on state in response to sensing the voltage transient.

3. The system of claim 1, wherein the phase angle is an activation phase angle controlled to delay the switching of the first transistor from the off state to the on state in response to not sensing the voltage transient within a cycle of the AC voltage input signal.

4. The system of claim 1, wherein the phase angle is a deactivation phase angle controlled to delay the switching of the first transistor from the on state to the off state in response to sensing the voltage transient.

5. The system of claim 1, wherein the phase angle is a deactivation phase angle controlled to anticipate the switching of the first transistor from the on state to the off state in response to not sensing the voltage transient within a cycle of the AC voltage input signal.

6. The system of claim 1, wherein the controller is further configured to generate a varying voltage signal based on a frequency of the AC voltage input signal, wherein the phase angle is determined based on the varying voltage signal reaching a first threshold value.

7. The system of claim 6, wherein the phase angle is an activation phase angle, wherein the controller is further configured to switch the first transistor from the off state to the on state based on the activation phase angle, wherein the controller is further configured to switch the first transistor from the on state to the off state based on a deactivation phase angle, wherein the deactivation phase angle is determined based on the varying voltage signal reaching a second threshold value.

8. The system of claim 7, wherein the controller is configured to: adjusting the first threshold in response to sensing the voltage transient and / or adjusting the second threshold in response to sensing the voltage transient.

9. The system of claim 7, wherein the controller is further configured to set the first threshold equal to the second threshold at startup of the full-wave active rectifier.

10. The system of claim 1, wherein the controller is configured to operate a frequency tracking algorithm, the frequency tracking algorithm configured to: determine a peak value of a changed voltage signal, wherein the changed voltage signal has a corresponding rate of change; and increase the rate of change of the changed voltage signal if the peak value does not exceed a lower threshold value; or decrease the rate of change of a subsequent changed voltage signal if the peak value exceeds an upper threshold value.

11. The system of claim 1, wherein the voltage transient is sensed by comparing the first voltage to a control voltage threshold, wherein the control voltage threshold is between a ground level, GND, and -Vt, where Vt is a turn-on voltage of a body diode of the first transistor, and preferably between GND and -Vt / 2.

12. The system of claim 11, wherein the full-wave active rectifier system includes a transient detection comparator, the transient detection comparator including an input coupled to the AC input node and configured to compare the first voltage to the control voltage threshold.

13. The system of claim 12, wherein the transient detection comparator is configured to: deactivate when the first transistor is in the on state; and activate when the first transistor is in the off state.

14. The system of claim 12, wherein the transient detection comparator generates a flag signal indicating that the first voltage exceeds the control voltage threshold, and wherein the controller is configured to control the phase angle and determine that the first transistor switches between the on state and the off state based on the flag signal.

15. The system of claim 12, wherein the transient detection comparator is a first transient detection comparator, wherein the AC input node is a first AC input node, and wherein a full-wave active rectifier layout includes a second transient detection comparator, the second transient detection comparator including an input coupled to a second AC input node shared by the AC voltage input signal and a first terminal of the second transistor, and the second transient detection comparator is configured to compare the control voltage threshold to a voltage at the second AC input node.

16. The system of claim 15, wherein the second transient detection comparator is configured to: deactivate when the second transistor is in an on state; and activate when the second transistor is in an off state.

17. The system of claim 1, wherein the AC input node is a first AC input node, wherein the full-wave active rectifier system is further configured to: iii. monitoring a second voltage at a second AC input node shared by the AC voltage input signal and a first terminal of the second transistor when the second transistor is in an off state; and iv. sensing a second voltage transient of the second voltage caused by switching the first transistor between an on state and the off state; and wherein the controller is further configured to: control a second phase angle at which the second transistor is switched between the on state and the off state in response to sensing the second voltage transient.

18. The system of claim 17, wherein the second phase angle is a second active phase angle controlled to anticipate the switching of the second transistor from the off state to the on state in response to sensing the second voltage transient.

19. The system of claim 17, wherein the second phase angle is a second inactive phase angle controlled to delay the switching of the second transistor from the on state to the off state in response to sensing the second voltage transient.

20. The system of claim 17, wherein the varying voltage signal is a first varying voltage signal, wherein the full-wave active rectifier system is further configured to generate a second varying voltage signal based on a frequency of the AC voltage input signal, wherein the second phase angle is determined based on the second varying voltage signal reaching a third threshold value.

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