Amplifier and circuit arrangement thereof

Abstract

A circuit arrangement comprises an output combiner circuit comprising: a first output network having a first amplifier output node for connection to a first output of a main amplifier; a second output network having a second amplifier output node for connection to a second output of the peaking amplifier; and a final summation node. The first output network includes: a first inductive element connected between the first amplifier output node and the first intermediate node; a second inductance element connected between the first intermediate node and the final summing node; and a third inductance element connected between the first intermediate node and the ground. The second output network includes: a fourth inductive element connected between the second amplifier output node and the second intermediate node; the fifth inductance element is connected between the second intermediate node and the ground; and a capacitance element connected between the second intermediate node and the final summing node.

Description

TECHNICAL FIELD

[0001] The present application relates generally to amplifiers, and more specifically to Doherty amplifiers and circuit arrangements for Doherty amplifiers. BACKGROUND

[0002] Massive MIMO technology is a key component and used in 5G and 6G communications, which requires multiple channels of high efficiency PA (Power Amplifier) in one base station. Compared with 5G systems that can include 32 channels or 64 channels, the number of channels in 6G systems will become larger, and 128 channels can be mainstream in 7GHz deployment. Therefore, it brings many challenges to cost and PCB size.

[0003] Therefore, there is a need for a Doherty amplifier that can have the advantages of size reduction, cost saving, and high efficiency at deep back-off and normal output power level. SUMMARY

[0004] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features of the claimed subject matter, nor is it meant to be used to determine the scope of the claimed subject matter.

[0005] According to one aspect of this application, a circuit arrangement for a Dougherty amplifier having a main amplifier and a peak amplifier is provided. The circuit arrangement includes: an output combiner circuit comprising: a first output network having a first amplifier output node for connection to a first output of the main amplifier; a second output network having a second amplifier output node for connection to a second output of the peak amplifier; and a final summing node. The first output network includes: a first inductor connected between the first amplifier output node and a first intermediate node; a second inductor connected between the first intermediate node and the final summing node; and a third inductor connected between the first intermediate node and ground. The second output network includes: a fourth inductor connected between the second amplifier output node and a second intermediate node; a fifth inductor connected between the second intermediate node and ground; and a capacitor connected between the second intermediate node and the final summing node. In this way, compared to conventional circuit arrangements for regular Dougherty amplifiers with fixed load impedance or only a modifiable real part of the load impedance, the proposed circuit arrangement provides an output Dougherty combiner for advanced composite combined load (ACCL) Dougherty amplifiers, which increases design freedom because the real and graphical parts of the composite load impedance can be adjusted separately to meet different requirements.

[0006] In one or more embodiments, the first output network includes a second capacitor (262), and the second output network includes a third capacitor (264), wherein a first terminal of the second capacitor is connected to the third inductor and the first power supply; a second terminal of the second capacitor is grounded, and wherein a first terminal of the third capacitor is connected to the fifth inductor and the second power supply, and a second terminal of the third capacitor is grounded.

[0007] In one or more embodiments, the voltage supplied by the first power supply is the same as the voltage supplied by the second power supply.

[0008] In one or more embodiments, the first capacitor is integrated within a first integrated passive device (IPD), the second capacitor is integrated within a second IPD, and the third capacitor is integrated within a third IPD.

[0009] In one or more embodiments, each of the first inductor, the second inductor, the third inductor, the fourth inductor, and the fifth inductor includes a corresponding set of bonding wires.

[0010] In one or more embodiments, the circuit arrangement comprises a further inductive element connected between the final summing node and a Doherty amplifier output.

[0011] In one or more embodiments, the circuit arrangement further comprises: a main amplifier comprising a first amplifier input connected to the first input, and a first amplifier output connected to the first output circuit; a peak amplifier comprising a second amplifier input connected to the second input, and a second amplifier output connected to the second output circuit.

[0012] In one or more embodiments, the main amplifier comprises a first input impedance matching network and a first power transistor, wherein the first input impedance matching network is configured to match an impedance between the first input terminal and the first power transistor; and the peak amplifier comprises a second input impedance matching network and a second power transistor, wherein the second input impedance matching network is configured to match an impedance between the second input terminal and the second power transistor.

[0013] In one or more embodiments, the first power transistor is a field effect transistor having a gate terminal connected to the first input impedance matching network, a drain terminal connected to the first inductive element, and a source terminal grounded, and the second power transistor is a field effect transistor having a gate terminal connected to the second input impedance matching network, a drain terminal connected to the fourth inductive element, and a source terminal grounded.

[0014] In one or more embodiments, the first inductive element and the second inductive element have the same inductance value.

[0015] In one or more embodiments, a ratio a of a peak amplifier die size to a main amplifier die size is in a range of 1 to 3.

[0016] According to a second aspect of the present application, a packaged amplifier device is provided. The device includes: a first input; a second input; an output; a main amplifier including: a first amplifier input connected to the first input; and a first amplifier output connected to a first combining network input of an output combiner circuit; a peak amplifier including: a second amplifier input connected to the second input; and a second amplifier output connected to a second combining network input of the output combiner circuit; and an output combiner circuit including: a first inductive element connected between the first amplifier output and a first integrated passive device (IPD); a second inductive element connected between the first IPD and a second IPD; and a third inductive element connected between the first IPD and ground, wherein the first, second, and third inductive elements are connected to each other via the first IPD; a fourth inductive element connected between the second amplifier output and a first capacitor; a fifth inductive element connected between the first capacitor and ground, and wherein the first capacitor is integrated within the second IPD connected to the output.

[0017] In one or more embodiments, each of the first, second, third, fourth, and fifth inductive elements includes a set of bondwires, respectively.

[0018] In one or more embodiments, the packaged amplifier device further includes a second capacitor and a third capacitor, and wherein the second capacitor is integrated in a second third IPD and the third capacitor is integrated in a fourth IPD.

[0019] In one or more embodiments, the first inductive element is connected to a first power supply and the fourth inductive element is connected to a second power supply.

[0020] In one or more embodiments, a voltage provided by the first power supply is the same as a voltage provided by the second power supply.

[0021] In one or more embodiments, the main amplifier includes a first input impedance matching network and a first power transistor, wherein the first input impedance matching network is configured to match impedance between the first input and the first power transistor; the peak amplifier includes a second input impedance matching network and a second power transistor, wherein the second input impedance matching network is configured to match impedance between the second input and the second power transistor.

[0022] In one or more embodiments, the first power transistor is a field effect transistor having a gate terminal connected to the first input impedance matching network, a drain terminal connected to the first inductive element, and a source terminal grounded, and the second power transistor is a field effect transistor having a gate terminal connected to the second input impedance matching network, a drain terminal connected to the fourth inductive element, and a source terminal grounded.

[0023] In one or more embodiments, a ratio a of a peak amplifier die size to a main amplifier die size is in a range of 1 to 3.

[0024] In one or more embodiments, a load modulation ratio β is greater than or equal to a + 1. BRIEF DESCRIPTION OF DRAWINGS

[0025] So that the manner in which the above-recited features of the present application can be understood in detail, a brief description of the

[0026] Figure 1 shows a simplified schematic diagram of a conventional Doherty amplifier;

[0027] Figure 2 shows a circuit arrangement for a Doherty amplifier according to an embodiment;

[0028] Figure 3 shows a Doherty amplifier model with a composite combined load according to an embodiment;

[0029] Figure 4 shows an apparatus for a Doherty amplifier according to an embodiment;

[0030] Figure 5 shows a physical layout of a packaged amplifier apparatus according to an embodiment;

[0031] Figure 6 A Smith chart is shown showing the impedance trajectory of Zc and Zp;

[0032] Figure 7A and Figure 7B A Smith chart showing the impedances of Zc, Zp, and ZL under full power conditions and backoff power conditions;

[0033] Figure 8A and Figure 8B A plot showing drain efficiency curves versus output backoff;

[0034] Figure 9 A flowchart showing a method of fabricating an RF amplifier according to an example combination. DETAILED DESCRIPTION

[0035] Figure 1 is a simplified schematic diagram of a conventional Doherty amplifier 100. The amplifier 100 includes a single input 102, an output 104, a power divider 110, a first amplifier path 130, a second amplifier path 140, and a combining terminal 160. In an embodiment, a load 106 (e.g., an antenna) can be connected to the combining terminal 160 through an impedance transformer 108. The impedance transformer 108 can impart a 90-degree phase delay to the output RF signal before supplying the output RF signal to the load 106.

[0036] The power divider 110 is configured to divide the input power of the input signal 102 received at the power divider input 112 into a main portion of the input signal and a peaking portion of the input signal. The main input signal is provided to the first amplifier path 130 at the power divider output 114, and the peaking input signal is provided to the second amplifier path 140 at the power divider output 116. During operation in a full power mode, when both the main amplifier 136 and the peaking amplifier 146 are supplying current to the load 106, the power divider 110 divides the input signal power between the amplifier paths 130, 140. For example, the power divider 110 can divide the power equally, providing about one-half of the input signal power to each path 130, 140 (e.g., for a symmetric Doherty amplifier configuration). Alternatively, the power divider 110 can divide the power unequally (e.g., for an asymmetric Doherty amplifier configuration).

[0037] In essence, the power divider 110 divides the input RF signal supplied at the input terminal 102 and separately amplifies the divided signals along the main amplifier path 130 and the second amplifier path 140. The amplified signals are then combined in phase at the combining terminal 160. Importantly, the phase coherency between the main amplifier path 130 and the second amplifier path 140 is dominant over the frequency band of interest to ensure that the amplified main signal and the peaking signal arrive at the combining terminal 160 in phase and thus ensure proper Doherty amplifier operation.

[0038] Each of the first amplifier 136 and the second amplifier 146 includes one or more single-stage or multi-stage power transistor integrated circuits (ICs) 138, 148 for amplifying the RF signals conducted through the amplifiers 136, 146. These power transistor ICs can be implemented, for example, using silicon-based field effect transistors (FETs) (e.g., laterally diffused metal oxide semiconductor FETs or LDMOS FETs), gallium nitride (GaN)-based FETs (e.g., high electron mobility transistors), or other types of power transistors. Although the main power transistor ICs and the peaking power transistor ICs can be of the same size (e.g., in a symmetric Doherty configuration), the main power transistor ICs and the peaking power transistor ICs can also be of different sizes (e.g., in various asymmetric Doherty configurations). As used herein, "size" refers to the gate width of the transistor or current carrying capacitor. In asymmetric Doherty configurations, the peaking power transistor ICs are typically some multiple larger than the main power transistor ICs, that is, the peaking power transistor ICs have a larger gate width or higher current carrying capacity. For example, the peaking power transistor ICs can be twice the size of the main power transistor ICs, so the peaking power transistor ICs have twice the current carrying capacity of the main power transistor ICs. Ratios of peaking to first amplifier IC size other than 2: 1 can also be implemented.

[0039] During operation of the Doherty amplifier 100, the first amplifier stage 136 is biased to operate in AB class mode and the second amplifier stage 146 is biased to operate in C class mode. More specifically, the transistor arrangement of the first amplifier stage 136 is biased to provide a conduction angle between 180 degrees and 360 degrees. In contrast, the transistor arrangement of the second amplifier stage 146 is biased to provide a conduction angle less than 180 degrees.

[0040] At low power levels (at which the power of the input signal at terminal 102 is lower than the turn-on threshold level of the second amplifier 146), the amplifier 100 operates in a low power (or back-off) mode in which the first amplifier 136 is the only amplifier supplying current to the load 106. When the power of the input signal exceeds the threshold level of the second amplifier 146, the amplifier 100 operates in a high power mode in which both the first amplifier 136 and the second amplifier 146 supply current to the load 106. At this time, the second amplifier 146 provides active load modulation at the combined terminal 160, allowing the current of the first amplifier 136 to continue to increase linearly.

[0041] An input impedance matching network 134 (input MNc) can be implemented at the input of the first amplifier 136. Similarly, an input impedance matching network 144 (input MNp) can be implemented at the input of the second amplifier 146. In each case, the matching networks 134, 144 can be used to incrementally increase the circuit impedance towards the load impedance. In addition, the first amplifier 136 and the second amplifier 146 can have additional pre-matching input and / or output impedance matching networks (not shown) integrated with the power transistor die, or within the power transistor die package.

[0042] The conventional Doherty amplifier 100 has a "non-inverting" load network configuration. In the non-inverting configuration, the input circuit is configured such that the input signal supplied to the second amplifier 146 is delayed by 90 degrees with respect to the input signal supplied to the first amplifier 136 at the operating center frequency fo of the amplifier 100. To ensure that the main input RF signal and the peaking input RF signal arrive at the main amplifier 136 and the second amplifier 146 with a phase difference of approximately 90 degrees, as is proper basic operation of a Doherty amplifier, a phase delay element 132 is provided in the input path to the second amplifier 146 that applies approximately 90 degrees of phase to the delayed peaking input signal. For example, the phase delay element 132 can be a quarter- wavelength transmission line, or another suitable type of delay element having an electrical length of approximately 90 degrees.

[0043] To compensate for the resulting 90-degree phase delay difference between the primary amplifier path 130 and the second amplifier path 140 at the input of the amplifiers 136, 146 (i.e., to ensure that the amplified signals arrive in phase at the combining terminal 160), the output circuit is configured to apply a phase delay of about 90 degrees to the signal between the first amplifier 136 and the output of the combining terminal 160. This is achieved by the additional delay element 150. Alternative embodiments of the Doherty amplifier can have an "inverted" load network configuration. In such configurations, the input circuit is configured to delay the input signal supplied to the first amplifier 136 by 90 degrees relative to the input signal supplied to the second amplifier 146 at the operating center frequency fo of the amplifier 100, and the output circuit is configured to apply a phase delay of about 90 degrees to the signal between the output of the second amplifier 146 and the combining terminal 160.

[0044] Figure 2 A simplified schematic of a circuit arrangement for a Doherty amplifier with a primary amplifier and a peak amplifier according to embodiments. The circuit arrangement 200 comprises an output combiner circuit 240 comprising a first output network 220 having a first amplifier output node 272 for connecting to a first output of a primary amplifier 236, a second output network 222 having a second amplifier output node 274 for connecting to a second output of a peak amplifier 246, and a final summing node 270.

[0045] The first output network 220 comprises a first inductive element 250 connected between the first amplifier output node 272 and a first intermediate node 266, a second inductive element 252 connected between the first intermediate node 266 and the final summing node 270, and a third inductive element 254 connected between the first intermediate node 266 and ground. The second output network 222 comprises a fourth inductive element 256 connected between the second amplifier output node 274 and a second intermediate node 268, a fifth inductive element 258 connected between the second intermediate node 268 and ground, and a first capacitive element 260 connected between the second intermediate node 268 and the final summing node 270. Compared to traditional circuit arrangements for conventional Doherty amplifiers with fixed load impedances or only a real part of the load impedance that can be modified, the proposed circuit arrangement can provide an output Doherty combiner for an advanced complex combined load (ACCL) Doherty amplifier that increases the design freedom due to the real part and the image part of the complex load impedance that can be individually adjusted to meet different requirements.

[0046] Together with Figure 2 and Figure 3 Together, we describe the theoretical and design methods used for circuit layout 200.

[0047] Figure 3 This is a Doherty amplifier model with a composite load. It can be derived from the composite load Z. L Constructing a 2-port combiner network Z using a carrier and peaking lossless output matching network 2P .like Figure 3 As shown, Z 2P Network Z L Load, carrier network Z 2P_C Hefeng Network Z 2P_P The cascading of Z. For convenience, the transfer matrix format (ABCD matrix) will be used to characterize Z. 2P_C and Z 2P_P .

[0048]

[0049] Where T 2P_c and T 2P_p The matrix is ​​Z 2P_c and Z 2P_p The transmission matrix format of the matrix, and T ZL For composite load Z L The transfer matrix format is as follows. α represents the ratio of the peak amplifier size (or the gate width of the peak amplifier's transistor) to the main amplifier size (or the gate width of the main amplifier's transistor), and β is the load modulation ratio, representing the ratio of the load impedance experienced by the carrier amplifier's inherent current generator under output back-off conditions to the load impedance experienced during maximum power operation. θ is the phase offset between the main path and the peaking path. R o This represents the optimal load impedance of the main amplifier at full power. The combined node impedance is the composite value Z. L The combined node impedance can be expressed in admittance form: Y L =G + j*B, where 1 / Z L =G + j*B.

[0050] Assuming the output matching networks for the main and peaking methods are inverse and lossless, then the diagonal elements (T) of the ABCD matrix... 2P_c and T 2P_p The elements of matrix ABCD are pure real values, while the off-diagonal elements are pure imaginary values.

[0051]

[0052] Ac, Bc, Cc, Dc, Ap, Bp, Cp, and Dp are real values.

[0053] Based on (Al) and (A2), the parameters of the main output matching network and the peaking output matching network can be calculated by the following equations:

[0054]

[0055]

[0056] where Ac is a free design variable, R o is the optimal load resistance of the main amplifier, G is the real part of the admittance of the combining node and B is the imaginary part of the admittance of the combining node (free design variable), and the function sign(x) is a sign function defined as follows:

[0057]

[0058] Since Dc has two solutions (using positive or negative sign), there are two sets of solutions: (1) when DC uses positive sign, the positive / negative sign (±) in other parameter expressions (Bc, Cc, Ap, Bp, Cp and Dp) will take negative sign; (2) when DC uses negative sign, the positive / negative sign (±) in other parameter expressions will take positive sign.

[0059] The optimal load impedance of the peaking amplifier is R0 / α, and the design output back-off (OBO) in dB is:

[0060] OBO = 10 log(β(1 + α)) (A13)

[0061] The expression of θ can be calculated as follows:

[0062]

[0063] The impedances at the combining node under both back-off and full power output conditions can be obtained:

[0064]

[0065]

[0066] where the subscripts of each impedance refer to different meanings and different conditions: "c" stands for the main amplifier (that is, the first amplifier), while "p" stands for the peaking amplifier (that is, the second amplifier), and "F" stands for the full power output condition, while "B" stands for the output back-off condition. For example, Z pB represents the impedance of the peaking amplifier under the output back-off condition, and Z pF represents the impedance of the peaking amplifier under the full output condition. Z cBrepresents the impedance of the main amplifier under the output back-off condition, and Z cF represents the impedance of the main amplifier under the full power output condition.

[0067] A conventional complex combined load (CCL) Doherty amplifier has the following assumptions: Zp B = ∞, and both impedances (Z cF and Z pF ) are related to Z L and have the same phase (e.g., for the symmetric case, Z cF = Z pF = 2Z L ) to satisfy the Doherty amplifier operation.

[0068] In contrast, in the proposed advanced complex combined load (ACCL) Doherty amplifier, there are no assumptions on the impedances Z cF , Z pF , Z pB , and Z cB , which can therefore be any values to satisfy the required Doherty operation.

[0069] And, when R (or G in Figure 3 ), a, and β are selected, the transmission matrix of the output matching network of both the main and peaking of the ACCL Doherty amplifier is not fully determined because it still has two free design variables. One of the two free design variables can be any of the following eight parameters: Ac, Bc, Cc, Dc, AP, Bp, Cp, and Dp. The other one is the image part X of the combined load impedance Z L (or B in Figure 3 ). The above two design free variables are independent of each other. Then, the two free design variables can be adjusted to obtain the required complex combined load impedance Z L .

[0070] Referring back to Figure 2 , there are six elements to form the output combiner circuit by using the advanced complex combined load (ACCL) technique. As shown in Figure 2 , the first inductor element 250 and the second inductor element 252 can have the same inductance value LI. The inductance value of the fourth inductor element 256 is L2. The inductance value of the fifth inductor element 258 is L3. The inductance value of the third inductor element 254 is L4. The capacitance of the first capacitor 260 is CI. The parasitic capacitances (C ds c and C ds_p) can be absorbed as part of the output combiner circuit. In one embodiment, for simplicity, the first inductive element 250 and the second inductive element 252 have the same inductance value LI. In some other embodiments, the first inductive element 250 and the second inductive element 252 can have different inductance values.

[0071] According to Figure 2 and Figure 3 , to form an ACCL Doherty combiner, the values of these above elements and the combiner node impedance must follow some relationships (A1 to A16). Given the Cds c and Cds p values of the main transistor and peaking transistor, the values of LI, L2, L3, L4 and the complex impedance Z L (or in admittance form Y L =G+j*B) at the combiner node can be obtained by the following equations:

[0072]

[0073] G L =G (6)

[0074] where Bc, Dc, Ap, Bp can be obtained by equations (A5, A6, A8 and A9), and G is a free design variable in equations (A5, A6, A8 and A9). CI is a free design variable that can be chosen freely. Having two free design variables (G and CI) means that the combiner node impedance (Z L ) can be adjusted freely, including its real and image parts. This provides flexibility to design the circuit according to the practical application or trade-off with other design aspects.

[0075] Figure 4 A circuit arrangement for a Doherty amplifier according to an embodiment. The circuit arrangement 400 includes two separate inputs 402a, 402b, an output 404, a first amplifier 236, a second amplifier 246 and an output combiner circuit 240. The circuit arrangement 400 is similar to the circuit arrangement 200 Figure 2 The main difference between the circuit arrangement 400 and the circuit arrangement 200

[0076] A first signal (RF_inl) received at the first input 402a is amplified by the first amplifier 236. A second signal (RF_in2) received at the second input 402b is amplified by the second amplifier 246.

[0077] The first amplifier (main amplifier) 236 includes a first transistor (carrier transistor) 238, which can include a control terminal connected to the input 402a, a source terminal grounded and a drain terminal as the first amplifier output.

[0078] The second amplifier (peaking amplifier) 246 includes a second transistor (peaking transistor) 248 that can include a control terminal connected to the second input 402b, a source terminal grounded, and a drain terminal as a second amplifier output.

[0079] The output combiner circuit 240 includes a first output network 220, a second output network 222, and a final summing node 270. The first output network 220 is connected to the first amplifier output, and the second output network 222 is connected to the second amplifier output. The first output network 220 can include a first inductive element 250 connected between the first amplifier output and a first intermediate node 266, a second inductive element 252 connected between the first intermediate node 266 and the final summing node 270. In one or more embodiments, the first inductive element and the second inductive element can have the same inductance value. The first output network 220 further includes a third inductive element 254 connected between the intermediate node 266 and ground. The second output network 222 includes a fourth inductive element 256 connected between the second amplifier output and a second intermediate node 268, and a first capacitor 260 connected between the second intermediate node 268 and the final summing node 270. The second output network 222 further includes a fifth inductive element 258 connected between the second intermediate node 268 and ground.

[0080] In one or more embodiments, the output combiner circuit 240 includes a second capacitor 262 connected between the third inductive element 254 and ground, and a third capacitor 264 connected between the fifth inductive element 258 and ground. Then, the third inductive element 254 and the fifth inductive element 258 can be referred to as connected to RF ground, which means that the RF signal from the first transistor 238 is grounded, and the DC current (Vdd c) from the first VDD power supply can be provided to the drain of the first transistor 238, and the RF signal from the second transistor 248 is grounded, and the DC current (Vdd p) from the second VDD power supply can be provided to the drain of the second transistor 248. Each of the first inductive element, the second inductive element, the third inductive element, the fourth inductive element, and the fifth inductive element includes a respective set of bond wires. The Doherty amplifier 200 includes integrated passive devices (IPDs) (shown in Figure 5 Figure 5

[0081] ​​In one or more embodiments, the main amplifier 236 includes a first amplifier input connected to the first input 402a and a first amplifier output connected to the first output network 220; and the peaking amplifier 246 includes a second amplifier input connected to the second input 402b and a second amplifier output connected to the second output network 222.

[0082] In one or more embodiments, the main amplifier 236 includes a first input impedance matching network 234 and a first power transistor 238. The first input impedance matching network 234 is configured to match an impedance between the first input 402a and the first power transistor 238; and the peaking amplifier 246 includes a second input impedance matching network 244 and a second power transistor 248. The second input impedance matching network 244 is configured to match an impedance between the second input 402b and the second power transistor 248.

[0083] In one or more embodiments, the first power transistor 238 is a field effect transistor having a gate terminal connected to the first input impedance matching network 234, a drain terminal connected to the first output network 220, and a source terminal connected to ground; and the second power transistor 248 is a field effect transistor having a gate terminal connected to the second input impedance matching network 244, a drain terminal connected to the second output network 222, and a source terminal connected to ground.

[0084] Figure 5 A physical layout for a packaged amplifier device according to an embodiment. The packaged amplifier device 500 is at least a portion of a Doherty amplifier.

[0085] The device can include a "flat no-lead" device package (e.g., quad flat no-lead QFN) or dual flat no-lead (DFN) device). Such devices include a "lead frame" composed of a conductive center flange ("exposed thermal pad") and a plurality of perimeter IO pads or leads (referred to in this application as "pin pads"). Plastic holds the flange and pads in fixed orientation relative to each other (and electrically isolated from each other).

[0086] Various amplifier dies and "integrated passive devices" (IPDs) referred to in this application can all be attached directly to the conductive flange, and wire bonds can be connected between the top inner surface of the pin pads and the dies / IPDs. Plastic molding compound can then be applied over the dies to encapsulate the device. When connected to a PCB, the flange is typically grounded; this provides a ground reference for the encapsulated dies / IPDs. Such devices are typically surface mount devices, so the bottom surface of the pin pads is connected (e.g., soldered) to corresponding pads on the top surface of the PCB.

[0087] As discussed herein, an IPD is a typically small semiconductor die that includes only "passive" components integrated therein (e.g., capacitors, resistors, inductive elements), rather than "active" devices of a semiconductor die that includes transistors. In this application, each IPD can include bond pads on its top surface to which bond wires can be connected. The IPD includes an integrated internal capacitor (typically a "metal-insulator-metal" or MIM capacitor). One end of the capacitor is connected to a top bond pad. The other end of the capacitor is connected to a conductive layer on the bottom of the IPD. When the IPD is connected (e.g., using solder) to the top surface of a conductive package flange, the second end of the capacitor can be grounded.

[0088] Referring again to Figure 5 , the packaged amplifier device 500 includes first and second input leads 502a and 502b, an output lead 504, a first amplifier 236, a second amplifier 246, a first inductive element 250, a second inductive element 252, a third inductive element 254, a fourth inductive element 256, a fifth inductive element 258, and first, second, and third capacitors CI, C2, and C3. Each of the first, second, third, fourth, and fifth inductive elements includes a respective set of bond wires. The first capacitor CI is integrated within a first integrated passive device (IPD) 560, the second capacitor C2 is integrated within a second IPD 562, and the third capacitor C3 is integrated within a third IPD 564. For example, the various leads 502a, 502b, 502c, 502d, 504 can each be ends (or pins) of a leadless package.

[0089] The first amplifier 236 (e.g., a main amplifier of a Doherty amplifier) can include a first transistor 238. The first transistor 238 includes a first transistor input connected to the first input lead 502a (e.g., through two sets of bond wires and a first input IPD, as shown), and a first transistor output. The second amplifier 246 (e.g., a first peaking amplifier of a Doherty amplifier) includes a second transistor 248. The second transistor 248 includes a second transistor input connected to the second input lead 502b (e.g., through two sets of bond wires and a second input IPD, as shown), and a second transistor output.

[0090] The first inductive element 250 is connected between the first transistor output and the IPD 566, the second inductive element 252 is connected between the IPD 566 and the first capacitor 260, and the third inductive element 254 is connected between the IPD 366 and ground. The first, second, and third inductive elements 250, 252, and 254 are then connected to each other through the IPD 366.

[0091] A fourth inductive element 256 is connected between the second transistor output and a first end of a first capacitor Cl. A second end of the first capacitor Cl is connected to the second inductive element 252. Both the first and second ends of the first capacitor Cl are integrated in one IPD 560. The first capacitor Cl can be connected to the output pin 504 through another inductive element 276. A fifth inductive element 258 is connected between the first end of the first capacitor Cl and ground.

[0092] In one or more embodiments, the amplifier device 500 can include a second capacitor C2 on an IPD 562 and a third capacitor C3 on another IPD 564. A first end of the second capacitor C2 is connected to one end of the third inductive element 254 and a pin 502c that can be connected to a power supply Vdd c. A first end of the third capacitor C3 is connected to one end of the fifth inductive element 258 and another pin 302d that can be connected to another power supply Vdd p. Thus, no external circuit for the drain bias is needed to be added since the packaged amplifier device 500 itself provides a drain voltage bias circuit that enables the drain voltage feed for the first amplifier 236 and the second amplifier 246.

[0093] Figure 6 A Smith chart of the impedance trajectories of Zc and Zp according to one embodiment is shown. In a conventional Doherty power amplifier (DPA) approach, β and θ are determined when the power ratio a is fixed. It is β = a + 1 and θ = ± 90°. However, according to one or more embodiments, many alternatives are enabled because of the presence of the free variable Ac. As shown in Figure 6 Ac = 0 belongs to the conventional DPA, where both Zc and Zp move along the real axis. When Ac is chosen to be one of -2, -1, 1, 2, our proposal can give other possible solutions.

[0094] Figure 7A and Figure 7B is a Smith chart showing the impedances of Zc, Zp, and ZL under the full power condition and the back-off power condition, where a = 1, β = 3, θ = 127.76°, and ZL = 50. Referring to Figure 8A , based on the simulated load-pull data under the full power condition, ZcF of the main PA (ml) is 6.613 - j 24.811, ZpF of the peaking PA (m2) is 6.541 + j 24.734, and ZLoad F of the output combiner circuit is 49.938 + j 0.391. Referring to Figure 8BZcB for the main PA (m4) is 19.834 - j 24.463, ZpB for the peaking PA (m5) is 0.361 + j 40.171, and ZLoad_B for the output combiner circuit (m6) is 49.448 + j 0.554. As shown in Figure 7A and Figure 7B the impedances combined by the main and peaking networks can be the same or very close to the complex load ZL we designed for (ZL = 50) under either full power output conditions or back-off conditions. Although Figure 7A and Figure 7B show ZL = 50, it should be understood that the load impedance can have any complex value as desired.

[0095] Figure 8A and Figure 8B show drain efficiency curves with different values of a and β versus output back-off (OBO). For a DPA circuit designer, based on the availability of main and peaking amplifiers and their real performance characteristics, more degrees of freedom are available in choosing the right ratio a and modulation range β to achieve the efficiency peak at the desired OBO.

[0096] Output back-off (OBO) is the power level at the output of an RF amplifier relative to the maximum output level possible using the RF amplifier. Deep output back-off means that the value of the output back-off is greater than a normal back-off value. For example, a normal output back-off has a value of -8 dB, and a deep output back-off has a value of -12 dB.

[0097] In one or more embodiments, the value of β can be selected to be any number equal to or greater than a + 1.

[0098] As shown in Figure 8A the desired drain efficiency can be achieved by adjusting the value of β when a is equal to 1.5. For example, if the desired drain efficiency is 50% when the OBO is -12 dB, then β can be one of the values 3.5, 4.5, and 5.5 when a is equal to 1.5. If the desired drain efficiency is higher than 70% when the OBO is -12 dB, then β can be selected to be 5.5 when a is equal to 1.5.

[0099] As shown in Figure 8B the desired drain efficiency can be achieved by adjusting the value of β when a is equal to 2. For example, if the desired drain efficiency is 50% when the OBO is -12 dB, then β can be one of the values 3, 4, 5, and 6 when a is equal to 2. If the desired drain efficiency is higher than 70% when the OBO is -12 dB, then β can be selected to be 5 when a is equal to 2.

[0100] Therefore, this application can achieve the following advantages: high efficiency under deep output back-off (OBO), reduced PCB size, low cost, PCB design friendliness and application flexibility.

[0101] Figure 9 This is a flowchart illustrating a method for manufacturing an RF amplifier system according to an example assembly. In block 902, manufacturing the packaged RF amplifier device may include bonding one or more active dies and other components (e.g., IPDs) to the top surface of a lead frame. In block 904, manufacturing the packaged RF amplifier device may further include interconnecting the dies, IPDs, and inductor elements in the form of several sets of bonding wires between the input leads or pin pads, active dies, IPDs, other components, and output leads or pin pads. The bonding wire connections essentially complete the formation of the amplifier path (including input and output impedance matching circuitry). After attaching the bonding wires, the packaging of a portion of the RF amplifier may be completed in block 906. For example, in block 906, portions of the active dies, IPDs, other components, bonding wires, input and output leads, and at least a portion of the top surface of the lead frame are encapsulated in a non-conductive molding compound. Then, in block 908, the completed device may be incorporated into an amplifier system, including mounting the device on a PCB (or other substrate) such that the device substrate is electrically connected to the system's ground voltage reference.

[0102] The use of the terms “a” and “an” and “the” and similar indicators in the context of describing the subject matter (specifically, in the context of the appended claims) should now be interpreted as encompassing both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise stated herein, references to ranges of values ​​herein are intended only as a way of individually referring to each individual value belonging to the range, and each individual value is incorporated into this specification as if individually referenced herein. Furthermore, the foregoing description is for illustrative purposes only and not for limiting purposes, as the scope of protection sought is defined by the appended claims and any equivalents thereof. Unless otherwise required, the use of any and all examples or exemplary language (e.g., “such as”) provided herein is merely intended to better illustrate the subject matter and does not limit the scope of the subject matter. The use of the term “based on” and other similar phrases indicating the conditions used to produce the result in both the claims and the written description is not intended to exclude other conditions that produce that result. Nothing in this specification should be construed as indicating that any unclaimed element is necessary for a practically claimed application.

[0103] Preferred embodiments are described herein, including the best mode known to the inventors of practicing the claimed subject matter. Of course, variations on these preferred embodiments will become apparent to those of ordinary skill in the art once the nature of the calculations involved is understood. It is intended that the scope of the claimed subject matter encompasses all changes and modifications that fall within the scope of the claims. Furthermore, although the preferred embodiments are described with reference to the preferred embodiments illustrated in the drawings, persons having ordinary skill in the art will readily appreciate that changes can be made to these preferred embodiments without departing from the scope of the claimed subject matter. Accordingly, the claimed subject matter is not limited to the preferred embodiments described herein, but is intended to encompass any and all modifications and equivalent arrangements.

Claims

1. A circuit arrangement for a Dougherty amplifier having a main amplifier and a peak amplifier, characterized in that, The circuit arrangement includes: An output combiner circuit, the output combiner circuit comprising: a first output network having a first amplifier output node for connection to a first output of the main amplifier; a second output network having a second amplifier output node for connection to a second output of the peak amplifier; and a final summing node; The first output network includes: a first inductor connected between the first amplifier output node and a first intermediate node; a second inductor connected between the first intermediate node and the final summing node; and a third inductor connected between the first intermediate node and ground. The second output network includes: a fourth inductor connected between the second amplifier output node and a second intermediate node; a fifth inductor connected between the second intermediate node and ground; and a first capacitor connected between the second intermediate node and the final summing node.

2. The circuit arrangement according to claim 1, characterized in that, The first output network includes a second capacitor (262), and the second output network includes a third capacitor (264), wherein a first end of the second capacitor is connected to the third inductor and the first power supply; a second end of the second capacitor is grounded, and wherein a first end of the third capacitor is connected to the fifth inductor and the second power supply, and a second end of the third capacitor is grounded.

3. The circuit arrangement according to claim 2, characterized in that, The voltage supplied by the first power supply is the same as the voltage supplied by the second power supply.

4. The circuit arrangement according to claim 2, characterized in that, The first capacitor is integrated within a first integrated passive device (IPD), the second capacitor is integrated within a second IPD, and the third capacitor is integrated within a third IPD.

5. The circuit arrangement according to claim 1, characterized in that, Each of the first inductor, the second inductor, the third inductor, the fourth inductor, and the fifth inductor includes a corresponding set of bonding wires.

6. A packaged amplifier device, characterized in that, include: First input terminal; Second input terminal; Output terminal; A main amplifier, the main amplifier comprising: a first amplifier input connected to a first input terminal; and a first amplifier output connected to a first combination network input of the output combiner circuit; A peak amplifier, comprising: a second amplifier input connected to a second input terminal; and a second amplifier output connected to a second combination network input of the output combiner circuit; and An output combiner circuit includes: a first inductor connected between a first amplifier output and a first integrated passive device (IPD); a second inductor connected between the first IPD and a second IPD; a third inductor connected between the first IPD and ground, wherein the first, second, and third inductors are interconnected via the first IPD; a fourth inductor connected between the second amplifier output and a first capacitor; and a fifth inductor connected between the first capacitor and ground, wherein the first capacitor is integrated within the second IPD connected to the output terminal.

7. The packaged amplifier device according to claim 6, characterized in that, Each of the first inductor, the second inductor, the third inductor, the fourth inductor, and the fifth inductor includes a set of bonding wires.

8. The packaged amplifier device according to claim 6, characterized in that, The packaged amplifier device further includes a second capacitor and a third capacitor, wherein the second capacitor is integrated in a second third IPD and the third capacitor is integrated in a fourth IPD.

9. The packaged amplifier device according to claim 6, characterized in that, The first inductor is connected to the first power supply, and the fourth inductor is connected to the second power supply.

10. The packaged amplifier device according to claim 6, characterized in that, The load modulation ratio β is greater than or equal to α+1, where α is the ratio of the peaking amplifier size to the main amplifier size.

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