Deep groove thin film passive equalizer in multi-core particle integrated system and manufacturing method of deep groove thin film passive equalizer

Abstract

The invention provides a deep groove film passive equalizer in a multi-chip integrated system and a manufacturing method thereof, the deep groove film passive equalizer comprises a resistance area, a capacitance area and an inductance area, the resistance area and the capacitance area are connected in parallel and then are bridged between two points of an interconnection line, one end of the inductance area is grounded, and the other end of the inductance area is grounded. The other ends of the resistors are connected between the two series resistors in the resistor region to form a T junction type passive equalizer structure; wherein the capacitance region, the resistance region and the inductance region are all of a deep groove type thin film stacking structure which is manufactured on the same silicon substrate through thin film growth, the deep groove type thin film stacking structure is formed by alternately depositing a polar plate layer and a dielectric layer from bottom to top, and the polar plate layer is arranged at the top of the deep groove type thin film stacking structure. An existing deep groove capacitor manufacturing process is ingeniously utilized and completely compatible, the production cost can be effectively reduced, and meanwhile extremely high transmission bandwidth is obtained.

Description

Technical Field

[0001] This invention relates to the field of integrated passive components / circuits, and more particularly to a deep trench thin-film passive equalizer in a multi-core integrated system and its manufacturing method. Background Technology

[0002] As transistor miniaturization technology approaches its physical limits, and with the constraints of step-by-step lithography, the area of ​​a single high-performance chip is also nearing its upper limit. The design paradigm in the integrated circuit field is evolving from single large-size System-on-Chip (SoC) packaging to the integration of multiple small-size chiplets. In multi-chip integration, the integration and performance of data interfaces and interconnect networks are increasingly crucial for improving the overall performance of the integrated chip system. To achieve higher data bandwidth, transmission channels require higher interconnect density and single-line transmission rates. However, the finer interconnects used for higher interconnect density introduce significant signal integrity problems with increased transmission rates, including signal attenuation, crosstalk, and inter-symbol interference (ISI). Although widely used transmitter pre-emphasis technology can improve signal integrity to some extent, its high power consumption and area overhead have become a design bottleneck for chip transmitter circuits. Therefore, inserting passive equalizers close to the transmitter or receiver end of the circuit in a high-speed interconnect adapter board has become a more cost-effective solution.

[0003] Based on the type of equalizer device, equalizer design in high-speed interconnects of multi-core integrated systems can be divided into active equalizers and passive equalizers:

[0004] Active equalizers utilize the switching characteristics and parasitic effects of transistors to achieve low-frequency suppression and high-frequency gain. For example, one active equalizer using a Cherry-Hooper topology has an area of ​​47μm × 85μm and a power consumption of 13.2mW, operating on a 10Gbps receiver. Another paper designs a DFE-IIR module for dynamic equalization on an 8×10Gbps transmission channel, with an area of ​​70μm × 65μm and a power consumption of 5.5mW. The advantage of active equalizers is that they can provide additional gain to the high-frequency components of high-speed signals. However, their disadvantages include complex manufacturing processes, larger chip area, and higher power consumption during equalization. They are suitable for equalizing long-distance critical paths rather than high-density, high-bandwidth parallel interfaces.

[0005] Passive equalizers primarily use integrated capacitors, integrated inductors, and integrated resistors to achieve equalization, and mainly include three types: parallel RC type, series RL type, and T-junction equalizer (also known as T-junction). For example, there is an existing technology for RL type equalizers suitable for high-bandwidth memory (HBM) interconnects, which has advantages such as simple structure and small footprint, but its power consumption is 8.24mW, which is too high compared to active solutions. Compared to series RC and parallel RL structures, T-junction equalizers have high design complexity, but their miniaturization remains a bottleneck for application.

[0006] In summary, compared with active equalizers, passive equalizers have the advantage of being able to be manufactured on silicon interposers to save chip area. However, current technologies do not have advantages in terms of device area (integration) and power consumption. Summary of the Invention

[0007] In view of this, the present invention provides a deep trench thin film passive equalizer in a multi-core integrated system and a method for manufacturing the same, in order to solve at least one of the problems mentioned above.

[0008] To achieve the above objectives, the present invention adopts the following solution:

[0009] According to a first aspect of the present invention, an embodiment of the present invention provides a deep trench thin film passive equalizer in a multi-core integrated system, comprising a resistor region, a capacitor region and an inductor region, wherein the resistor region and the capacitor region are connected in parallel and then connected across two points of an interconnect, one end of the inductor region is grounded and the other end is connected between two series resistors in the resistor region, together forming a T-junction passive equalizer structure.

[0010] The capacitor region, the resistor region, and the inductor region are all deep trench type thin film stacked structures fabricated on the same silicon substrate by thin film growth. The deep trench type thin film stacked structure is formed by alternating deposition of electrode layer and dielectric layer from bottom to top, and the top of the deep trench type thin film stacked structure is electrode layer.

[0011] Within the resistance region, the deep trench thin film stacked structure is connected through internal through holes, so that all or part of the electrode layers are connected in parallel, forming a conductive path with a specific resistance value, thereby constituting a deep trench thin film resistor.

[0012] Within the capacitor region, the deep trench thin film stacked structure is connected through internal through-holes, so that adjacent electrode layers are respectively connected to two different ends of the interconnect line, thereby forming a planar deep trench electrode capacitor.

[0013] Within the inductor region, the deep-groove thin-film stacked structure is connected through internal through-holes, allowing the electrode layers of the deep-groove thin-film stacked structure to form a multi-turn winding structure.

[0014] In one embodiment of this application, a silicon dioxide layer is further included between the silicon substrate and the bottom electrode layer.

[0015] In one embodiment of this application, the aforementioned deep trench thin-film passive equalizer further includes a copper metal layer connected to the through-hole. The copper metal layer is manufactured by damascus steel and electroplating to complete the internal interconnection of the planar thin-film passive equalizer and to connect to the interconnect line.

[0016] In one embodiment of this application, the thickness of the copper metal layer is 1 μm; the thickness of the interlayer dielectric is 1 μm; the thickness of the electrode layer is 50 nm; the thickness of the dielectric layer is 20 nm; the width of the deep trench is 0.5 μm, the trench spacing is 0.5 μm, the trench depth-to-width ratio is 5:1 to 10:1, the width of the resistance line in the resistance region is 1 μm; the length of the inductance region is 50 μm, the width of the inductance line is 3 μm, and the side length of the capacitor region is 11 μm.

[0017] In one embodiment of this application, the individual unit size of the deep trench thin film passive equalizer is less than 1050 μm².

[0018] In one embodiment of this application, the deep trench thin film stack structure and the vias are covered with silicon dioxide.

[0019] In one embodiment of this application, the conductive material used in the electrode layer is selected from one or more combinations of metals, metal nitrides, or metal alloys; the insulating material used in the dielectric layer is selected from one or more combinations of silicon nitride, metal oxides, or mixed materials.

[0020] In one embodiment of this application, the via is filled with sputtered tungsten metal and the excess tungsten on the surface is removed by a chemical mechanical planarization process.

[0021] In one embodiment of this application, the resistance ratio and the low-frequency voltage division ratio of the passive equalizer can be adjusted by adjusting the winding length of the resistor region and the inductor region. Different resistance and inductance values ​​can be obtained by adjusting the number of electrode layers, thereby adjusting the operating curve of the passive equalizer.

[0022] According to a second aspect of the present invention, embodiments of the present invention provide a method for manufacturing a deep trench thin-film passive equalizer in a multi-core integrated system, the method comprising:

[0023] Deep silicon etching is performed on a silicon substrate to create deep trench structures for capacitor, resistor and inductor regions.

[0024] A first silicon dioxide layer is grown on the silicon substrate to form an insulating layer;

[0025] On the insulating layer, conductive materials are alternately deposited to form an electrode layer and insulating materials to form a dielectric layer, thereby forming a deep trench type thin film stack structure;

[0026] The deep trench thin film stack structure is patterned using photolithography and etching processes to define the resistive region, the capacitive region, and the inductive region.

[0027] A second silicon dioxide layer is deposited on the surface of the deep trench type thin film stack structure and then planarized.

[0028] By photolithography, development, and etching of the second silicon dioxide layer, through-hole arrays for connecting electrode layers are respectively prepared in the resistive region, the capacitive region, and the inductive region;

[0029] Sputtering metallic tungsten fills the through-hole array, and chemical mechanical planarization removes excess metallic tungsten from the surface;

[0030] A copper metal layer connecting the via array is formed using the damascus process and electroplating to complete the internal interconnection of the resistive region, the capacitive region and the inductive region and connect them to external interconnect lines or ground lines.

[0031] The deep-groove thin-film passive equalizer and its manufacturing method proposed in this invention for a multi-core integrated system feature a compact equalizer design. The physical size of a single unit of the T-junction passive equalizer can be less than 1050 μm², an order of magnitude smaller than that of traditional T-junction passive equalizers. This ultra-small area allows for high-density integration onto silicon interposers or silicon interconnect bridges, making it particularly suitable for high-density parallel interface applications. Furthermore, the manufacturing method of this equalizer cleverly utilizes and is fully compatible with existing deep-groove capacitor manufacturing processes. This means that no additional photomask layer is required during production, significantly simplifying the manufacturing process and effectively reducing production costs. Finally, the deep-groove thin-film passive equalizer of this application, by incorporating optimized parameters, can effectively compensate for the attenuation of high-speed signals during transmission. For example, when applied to an 8-channel interconnect with a linewidth of 1 μm and a pitch of 5 μm, it can effectively equalize signals up to 32 Gbps NRZ over an interconnect distance of 10 mm, thereby achieving extremely high transmission bandwidth, such as an edge interconnect bandwidth of 6.4 Tbps / mm. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0033] Figure 1 This is a top view of the deep trench thin-film passive equalizer in the multi-core integrated system provided in this application embodiment;

[0034] Figure 2 This is a cross-sectional view of the deep trench thin-film passive equalizer in the multi-core integrated system provided in this application embodiment;

[0035] Figure 3 This is a diagram showing the arrangement of the deep trench thin-film passive equalizer and transmission lines provided in the embodiments of this application;

[0036] Figure 4 This is a flowchart illustrating the fabrication process of the deep trench thin-film passive equalizer in the multi-core integrated system provided in this application embodiment. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0038] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0039] Furthermore, it should be noted that the use of terms such as "first" and "second" to define related concepts is merely for the purpose of distinguishing the corresponding concepts. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0040] like Figure 1The image shown is a top view of a deep trench thin-film passive equalizer in a multi-core integrated system provided in this application embodiment. Figure 2 This is a cross-sectional view of a deep trench thin-film passive equalizer. Below is a combination of... Figure 1 and Figure 2 The deep trench thin-film passive equalizer of this application is described.

[0041] Depend on Figure 1 As can be seen, this deep trench thin-film passive equalizer includes a capacitor region A, a resistor region B, and an inductor region C. Capacitor region A, resistor region B, and inductor region C together form a T-junction passive equalizer structure. Capacitor region A and resistor region B are connected in parallel and then bridged across the high-speed signal transmission path (i.e., interconnection 1, see [link]). Figure 3 Between the two points, one end of the inductor region C is grounded, and the other end is connected between two series resistors in the resistor region B to balance the difference in transmission loss between the low-frequency and high-frequency components of the signal.

[0042] In this embodiment, the capacitor region A, resistor region B, and inductor region C are all deep trench multilayer thin film stacked structures fabricated on the same silicon substrate 2. This deep trench multilayer thin film stacked structure is formed by alternately depositing an electrode layer 3 (conductive material) and a dielectric layer 4 (insulating material) from bottom to top using thin film growth techniques such as atomic layer deposition (ALD) or physical vapor deposition (PVD). The top of the entire stacked structure is an electrode layer. This manufacturing process is fully compatible with existing deep trench capacitor processes.

[0043] Within the resistance region B, this multilayer thin-film stacked structure is connected through internal through-holes 5, allowing all electrode layers 3 to be connected in parallel, forming a conductive path with a specific resistance value, thus constituting a planar thin-film resistor. For example... Figure 2 As shown in (c), the graphical connection method of the plates in the resistance region B is given. The four conductor plates are connected in parallel, reducing the on-resistance. Of course, in this embodiment, some of the plate layers 3 can also be connected in parallel. That is, when making the through holes 5, only the through holes corresponding to the plate layers 3 need to be selectively made. It can be seen that in this embodiment of the deep trench thin film passive equalizer, when preparing the capacitor region A, the resistor region B, and the inductor region C, different parameters of the capacitor region A, the resistor region B, and the inductor region C can be combined by selectively making different through holes 5. The preparation process is flexible and controllable.

[0044] Depend on Figure 2 As shown in (c), each electrode layer can be considered an independent resistor. At the entrance of resistor region B, four through-holes and the copper metal layer 8 connect all four electrode layers together. At the exit of resistor region B, another four through-holes similarly connect these four electrode layers together. This is equivalent to connecting the two ends of four independent resistors to the same common point, forming a parallel circuit. Through this parallel connection, the total on-resistance is reduced.

[0045] Within capacitor region A, the deep-groove thin-film stacked structure is the same as that of resistor region B. The difference lies in the connection method between the through-hole 5 and the electrode layer 3. Within capacitor region A, adjacent electrode layers 3 are connected to two different endpoints of interconnect line 1 through the internal through-hole 5, thereby forming a deep-groove electrode capacitor.

[0046] Depend on Figure 2 As shown in Figure (b), there are multiple electrode layers 3 made of conductive material, with a dielectric layer 4 made of insulating material filling between every two electrode layers. Within capacitor region A, the vias 5 are connected alternately. As shown, the first and third electrode layers are connected to a copper metal layer 8 through vias 5, while the second and fourth electrode layers are connected to another copper metal layer 8 through vias 5.

[0047] This alternating connection method ensures that each pair of adjacent plates connected to different signal terminals (e.g., the first and second layers, the second and third layers, the third and fourth layers) constitutes an independent capacitor, forming a parallel connection in the circuit.

[0048] Figure 2 In section (b), the copper metal layers 8 on the left and right sides of capacitor region A are respectively connected to interconnect line 1, i.e., signal terminal A and signal terminal B, corresponding to... Figure 1 The lower half, namely the vertical bars on the left and right sides of the capacitor area, are connected to interconnect line 1.

[0049] Within the inductance region C, such as Figure 2 As shown in (d), the deep-groove thin-film stacked structure is connected through internal through-holes 5. The connection between through-holes 5 and electrode layer 3 is the same as that between the resistor region B and the electrode region B. Unlike the resistor region B, the deep-groove pattern of the inductor region is a single-groove winding or multi-groove parallel winding structure. The electrode layer 3 covers the groove structure, forming a consistent winding structure. The end of the winding connected to the resistor region and the end grounded are defined as the start end and the end of the winding, respectively. The end of the lower layer is reconnected to the start end of the upper layer through electrode patterning, internal contact holes, and short connecting lines of the copper interconnect layer, and so on. The end of the top layer is grounded, so that the electrode layer of the deep-groove thin-film stacked structure forms a multi-layer, multi-turn winding structure. Taking single-groove winding as an example, the copper metal ends 9 and 10 in the inductor region C are finally connected to signal ends A and B, respectively.

[0050] In one embodiment of this application, the resistance ratio and the low-frequency voltage division ratio of the passive equalizer can be adjusted by adjusting the winding length of the resistor region B and the inductor region C. Different resistance and inductance values ​​can be obtained by adjusting the number of electrode layers 3, thereby adjusting the operating curve of the passive equalizer.

[0051] Specifically, the equivalent resistance value can be changed by adjusting the length of the conductive film layer (electrode layer 3) in resistive region B. The longer the winding length, the greater the path impedance and the greater the equivalent resistance value; conversely, the shorter the winding length, the smaller the equivalent resistance value. Smaller or larger resistance values ​​can also be achieved by connecting more or fewer conductive film layers in parallel. Increasing the number of parallel layers can reduce the equivalent resistance and decrease the equivalent impedance of the parallel path; decreasing the number of parallel layers has the opposite effect.

[0052] Therefore, this embodiment can change the resistance value through the above means to adjust the low-frequency voltage division ratio, thereby affecting the attenuation compensation and signal distribution of the passive equalizer at the low-frequency end.

[0053] This embodiment can also achieve more turns of inductance (increasing the number of windings and thus increasing the inductance value) by connecting more or fewer conductive film layers in series, thereby obtaining different inductance values. Utilizing the electrode layer 3 in the deep groove structure, a patterned connection is achieved through internal through-holes, forming a winding path between the multiple electrode layers, thus increasing the self-inductance. Changing the inductance value can adjust the high-frequency characteristics and signal suppression / delay characteristics, thereby affecting the equalization effect of the passive equalizer on different frequency bands. In summary, adjusting the number of electrode layers can directly change the attenuation and gain distribution of the passive equalizer in different frequency bands, thereby enabling adjustment of the operating curve.

[0054] In another embodiment of this application, the surface of the silicon substrate 2 has a deep trench, and a first silicon dioxide layer 6 is further included between its surface and the bottom electrode layer 3. The first silicon dioxide layer 6 is prepared on the clean silicon substrate 2 by a thermo-oxidative growth process, and its main function is to achieve insulation of the silicon wafer surface. The first silicon dioxide layer 6 is the basis of the entire multilayer thin film structure, ensuring that all conductive electrode layers on it are completely isolated from the silicon substrate 2, which has a certain degree of conductivity, thus avoiding leakage and signal loss.

[0055] As described above, the deep trench thin film passive equalizer also includes a copper metal layer 8, which is connected to the through hole 5. The copper metal layer can be manufactured by damascusing and electroplating to complete the internal interconnection of the deep trench thin film passive equalizer and connect to the interconnect line.

[0056] The copper metal layer 8 plays a crucial role in the final connection and wiring within the entire deep-groove thin-film passive equalizer. This copper metal layer 8 is connected to specific electrode layers 3 in the multilayer thin-film stacked structure via through-holes 5 beneath it. Its core function is to aggregate the corresponding electrodes to the appropriate electrical nodes according to the design (e.g., capacitor, resistor, or inductor regions), thereby completing the internal interconnection of the equalizer. After completing the internal interconnection, the copper metal layer 8 extends outwards to connect with external circuitry, thus embedding the entire planar thin-film passive equalizer into the high-speed signal transmission path.

[0057] In another embodiment of this application, the aforementioned deep trench thin film stack structure and via 5 are covered by a second silicon dioxide layer 7. After the deep trench thin film stack structure is completed, the patterns of all conductor plates can be formed by photolithography and etching processes. Then, silicon dioxide is deposited using methods such as physical vapor deposition (PVD) to cover the entire structure. This second silicon dioxide layer 7 fills the etched gaps and unevenness of the structural surface, and then undergoes chemical mechanical planarization (CMP) to obtain a smooth surface. This flat second silicon dioxide layer 7 forms the basis for fabricating the via 5 and the top copper metal layer 8. Next, photolithography and etching are performed on this silicon dioxide layer to fabricate the via 5 connecting to the lower plates.

[0058] In another embodiment of this application, the vias 5 are filled with sputtered tungsten metal, and excess tungsten is removed from the surface using a chemical mechanical planarization (CMP) process. After forming a smooth silicon dioxide surface using physical vapor deposition (PVD) and chemical mechanical planarization (CMP) processes, the next step is to fabricate an array of vias on the silicon dioxide layer using photolithography, development, and etching techniques. The positions and depths of these vias 5 are precisely designed to accurately expose the underlying conductor electrode layers that need to be connected.

[0059] Sputtering is a physical vapor deposition technique that uniformly deposits tungsten metal onto the entire wafer surface, completely filling vias. Tungsten is chosen as the filler material because of its good electrical conductivity, thermal stability, and compatibility with silicon dioxide.

[0060] After the vias are completely filled, the wafer surface is covered with an excess of tungsten. To remove this excess metal and ensure the surface is flat again for subsequent copper wiring layer fabrication, a chemical mechanical planarization (CMP) process is required. CMP precisely removes the tungsten from the surface through the synergistic effect of chemical etching and mechanical polishing until a flat silicon dioxide layer is exposed again, leaving tungsten as conductive pillars inside the vias.

[0061] After completing this step, a structure with a flat surface and vertical electrical connections achieved internally through tungsten metal pillars is obtained, which prepares the final step for manufacturing the top copper metal layer 8.

[0062] In another embodiment of this application, the conductive material used in the electrode layer 3 can be selected from one or more combinations of metals, metal nitrides or metal alloys, such as TiN, TaN, Al, etc. It is required to have good adhesion to the materials of the first silicon dioxide layer 6 and the dielectric layer 4, which is crucial to ensuring the stability and reliability of the multilayer thin film structure.

[0063] The insulating material used in dielectric layer 4 is selected from one or more combinations of silicon nitride, metal oxide, or mixed materials, such as SiON. x Materials such as Al2O3, HfO2, ZrO2, or TiO2 are used. These materials, especially High-K materials (such as HfO2), help to achieve high capacitance density in a very small area.

[0064] The inventors found that, preferably, the dielectric layer 4 is made of HfO2 and the electrode layer 3 is made of TiN, which has good process compatibility.

[0065] Both the electrode layer 3 and the dielectric layer 4 can be prepared using processes such as atomic layer deposition (ALD) or physical vapor deposition (PVD). By alternating the deposition of these two materials, a multilayer thin-film structure with the desired number of layers can be constructed.

[0066] The aforementioned deep-groove thin-film passive equalizer is specifically designed for high-speed interconnects in multi-core integration. It can be integrated onto silicon interposers or silicon interconnect bridges, scenarios characterized by extremely high interconnect density and stringent size requirements for the equalizer. In this embodiment, when arranged in an interleaved configuration, high-density integration of the equalizer can be achieved, such as... Figure 3 The diagram shows the arrangement of the deep trench thin-film passive equalizer and transmission lines.

[0067] like Figure 3 As shown, eight independent deep-groove thin-film passive equalizers are placed on eight parallel interconnects. They are not placed side-by-side or aligned, but rather in a staggered arrangement. This staggered layout makes full use of the space above and below the transmission lines, allowing the equalizers to be closely packed together, thus integrating as many equalizers as possible within a limited area, achieving high-density integration. Figure 3 The example demonstrates how to effectively integrate eight equalizers with interconnect linewidths of 1 micrometer and line spacing of 5 micrometers. Assuming... Figure 3 The left side of the diagram represents the signal transmitter, and the right side represents the signal receiver. Each equalizer is connected in series in its respective transmission channel to equalize the high-speed signal emitted from the transmitter before the signal is transmitted to the receiver. This design is well-suited for protocols and standards such as UCIe and HBM (High Bandwidth Memory) that require high-speed parallel interconnection.

[0068] When the aforementioned passive equalizer is applied to a multi-core integrated system, by optimizing the design parameters, it can achieve extremely high-density integration while meeting high-performance requirements, effectively solving the signal integrity problem of high-speed parallel interfaces in multi-core systems.

[0069] Table 1 below is an example of parameter design optimization provided in the embodiments of this application:

[0070] Table 1

[0071]

[0072] The explanations for the above parameters can be found in the reference section. Figures 1-3 The corresponding annotations are provided, and no further textual description is needed. Based on the design parameters in Table 1, an ultra-small area (e.g., 1050 μm²) can be achieved for a single unit size of the T-junction passive equalizer. Furthermore, when this planar thin-film passive equalizer is applied to an 8-channel interconnect with a 1 μm linewidth, 5 μm line spacing, and 0-10 mm interconnect distance (i.e.,...),... Figure 3 It can achieve equalization of 32Gbps NRZ signals and achieve an edge interconnect bandwidth of 6.4Tbps / mm.

[0073] As described above, the deep trench thin-film passive equalizer proposed in this invention features a compact and ingenious design, with the physical size of a single unit being less than 1050 μm², an order of magnitude smaller than that of traditional T-junction passive equalizers. This ultra-small area allows for high-density integration onto silicon interposer boards or silicon interconnect bridges, making it particularly suitable for high-density parallel interface applications. Furthermore, the manufacturing method of this equalizer cleverly utilizes and is fully compatible with existing deep trench capacitor manufacturing processes. This means that no additional photomask layer is required during production, significantly simplifying the manufacturing process and effectively reducing production costs. Finally, by incorporating optimized parameters, the deep trench thin-film passive equalizer of this invention can effectively compensate for the attenuation of high-speed signals during transmission. For example, when applied to an 8-channel interconnect with a linewidth of 1 μm and a pitch of 5 μm, it can effectively equalize signals up to 32 Gbps NRZ, thereby achieving extremely high transmission bandwidth, such as an edge interconnect bandwidth of 6.4 Tbps / mm.

[0074] like Figure 4 The diagram shown is a flowchart illustrating a method for manufacturing a deep trench thin-film passive equalizer in a multi-core integrated system according to an embodiment of this application. The method includes the following steps:

[0075] Step S401: Perform deep silicon etching on a silicon substrate to create a deep trench structure for the capacitor region, resistor region, and inductor region.

[0076] Specifically, a smooth silicon wafer can be selected and subjected to photolithography and development to leave an etched pattern. This process forms a mask pattern on the silicon wafer surface through photolithography, which serves as a template for subsequent deep trench etching. Then, deep silicon etching is performed to create deep trench structures for capacitor, resistor, and inductor regions, and residual photoresist and etching products are cleaned.

[0077] Step S402: A first silicon dioxide layer is grown on the silicon substrate to form an insulating layer.

[0078] This step lays the electrical isolation foundation for the entire device structure, typically using a high-purity single-crystal silicon wafer as the mechanical support substrate. Through a thermal oxidation process, in a high-temperature, oxygen-containing environment, silicon atoms on the wafer surface react with oxygen to grow a dense, uniform silicon dioxide layer with excellent dielectric properties. This silicon dioxide layer completely isolates all subsequent functional structures from the conductive silicon substrate, preventing current leakage into the substrate and ensuring the equalizer functions accurately as an independent passive device.

[0079] Step S403: On the insulating layer, conductive materials are alternately deposited to form an electrode layer and insulating materials to form a dielectric layer, thereby forming a deep trench type thin film stack structure.

[0080] Deep trench thin-film stacked structures are sandwich structures composed of conductor plates and dielectric layers, forming the basis for capacitors, resistors, and inductors. This process employs atomic layer deposition (ALD) or physical vapor deposition (PVD) techniques. The advantage of ALD technology lies in its ability to grow at the atomic layer level, enabling extremely precise control over film thickness (e.g., a dielectric layer thickness of 20 nm and a plate thickness of 50 nm) with excellent conformal properties. This is crucial for fabricating high-quality, high-capacitance-density High-K dielectric layers.

[0081] This process is performed alternately, for example: depositing a conductive material (TiN) layer -> depositing an insulating material (HfO2) layer -> depositing a second conductive material (TiN) layer -> depositing a second insulating material (HfO2) layer... and so on, until the designed number of layers is reached (e.g., a total of 4 electrode layers and 3 dielectric layers). The last layer is the electrode layer.

[0082] Step S404: The deep trench thin film stack structure is patterned using photolithography and etching processes to define the resistive region, the capacitive region and the inductive region.

[0083] This step involves etching circuit patterns onto the aforementioned sandwich structure, clearly defining the resistive, capacitive, and inductive regions. This is a delicate subtractive process: a layer of photoresist is coated onto the surface of the multilayer thin-film stacked structure. A photomask with a pre-defined pattern (i.e., the shapes of capacitor region A, resistive region B, and inductive region C) is then exposed to ultraviolet light, causing changes in the chemical properties of the photoresist in specific areas. The exposed (or unexposed, depending on the photoresist type) photoresist is then washed away with a developer, exposing the underlying multilayer thin-film structure. Dry etching is then used to etch the exposed thin-film material layer by layer downwards. By precisely controlling the etching depth and range, the electrode layers in different regions are shaped into specific interconnection patterns.

[0084] Step S405: Deposit a second silicon dioxide layer on the surface of the deep trench thin film stack structure and perform planarization treatment.

[0085] This step fills in the trenches created after patterning and provides an absolutely flat worktable for subsequent interconnect processes. A layer of silicon dioxide can be deposited over the entire surface using methods such as physical vapor deposition (PVD). This SiO2 layer fills all the gaps etched in step S403, serving as protection and interlayer insulation. Then, a chemical mechanical planarization (CMP) process is employed. The CMP equipment acts like a precision polisher, using the synergistic effect of chemical etching solution and abrasive particles to polish the wafer surface to nanometer-level flatness. A flat surface is crucial for the focusing accuracy of subsequent photolithography and the yield of metal wiring.

[0086] Step S406: By photolithography, development, and etching the second silicon dioxide layer, through-hole arrays for connecting the electrode layers are respectively prepared in the resistive region, the capacitive region, and the inductive region.

[0087] The purpose of this step is to drill holes in the insulating silicon dioxide to create vertical conductive channels for connecting the different electrode layers buried deep beneath. This step repeats the "photolithography-development-etching" process, but this time the goal is to operate on the second silicon dioxide layer formed in S405. The etching depth needs to be precisely controlled to ensure that the vias stop precisely on the surface of the target electrode layer to be connected, without piercing through or under-etching.

[0088] Step S407: Sputter tungsten metal to fill the through-hole array, and chemically and mechanically planarize to remove excess tungsten metal from the surface.

[0089] This step involves filling the vias with conductive metal to form conductive pillars (Via). Specifically, a sputtering process is used to uniformly deposit high-melting-point, highly conductive tungsten metal across the entire wafer surface, completely filling all vias. Then, a chemical mechanical planarization (CMP) process is performed again. The goal here is to remove only the tungsten from the wafer surface, retaining the tungsten inside the vias. After this process, the wafer surface is restored to flat silicon dioxide, while embedded tungsten pillars are formed within the vias, creating a reliable vertical electrical connection.

[0090] Step S408: A copper metal layer connecting the via array is formed using the damascus process and electroplating to complete the internal interconnection of the resistive region, the capacitive region and the inductive region and connect them to external interconnect lines or ground lines.

[0091] The copper metal layer integrates the various components (resistors, capacitors, and inductors) inside the equalizer, which are connected via vias, into a complete circuit, and provides connection points for connection to external signal transmission lines. Using the damascus process, an insulating dielectric layer is first deposited on the surface, and then trenches with wiring patterns are etched into it using photolithography and etching. Next, copper is electroplated into the trenches. Finally, excess copper is removed using a CMP process, forming flat copper conductors embedded in the insulating dielectric. These copper conductors are precisely connected to the underlying tungsten vias, ultimately completing the manufacturing of the entire equalizer.

[0092] As described above, the manufacturing method of the deep trench thin-film passive equalizer proposed in this invention results in a compact and efficient equalizer design. The physical size of a single unit can be less than 1050 μm², which is an order of magnitude smaller than that of traditional T-junction passive equalizers. This ultra-small area allows for high-density integration onto silicon interposer boards or silicon interconnect bridges, making it particularly suitable for high-density parallel interface applications. Furthermore, the manufacturing method of this equalizer cleverly utilizes and is fully compatible with existing deep trench capacitor manufacturing processes. This means that no additional photomask layer is required during production, significantly simplifying the manufacturing process and effectively reducing production costs. Finally, the deep trench thin-film passive equalizer of this application, by incorporating optimized parameters, can effectively compensate for the attenuation of high-speed signals during transmission. For example, when applied to an 8-channel interconnect with a linewidth of 1 μm and a pitch of 5 μm, it can effectively equalize signals up to 32 Gbps NRZ, thereby achieving extremely high transmission bandwidth, such as an edge interconnect bandwidth of 6.4 Tbps / mm.

[0093] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A deep-groove thin-film passive equalizer in a multi-core integrated system, characterized in that, It includes a resistor region, a capacitor region, and an inductor region. The resistor region and the capacitor region are connected in parallel and then connected across two points of the interconnection line. One end of the inductor region is grounded, and the other end is connected between two series resistors in the resistor region, together forming a T-junction passive equalizer structure. The capacitor region, the resistor region, and the inductor region are all deep trench type thin film stacked structures fabricated on the same silicon substrate by thin film growth. The deep trench type thin film stacked structure is formed by alternating deposition of electrode layer and dielectric layer from bottom to top, and the top of the deep trench type thin film stacked structure is electrode layer. Within the resistance region, the deep trench thin film stacked structure is connected through internal through holes, so that all or part of the electrode layers are connected in parallel, forming a conductive path with a specific resistance value, thereby constituting a deep trench thin film resistor. Within the capacitor region, the deep trench thin film stacked structure is connected through internal through-holes, so that adjacent electrode layers are respectively connected to two different ends of the interconnect line, thereby forming a planar deep trench electrode capacitor. Within the inductor region, the deep-groove thin-film stacked structure is connected through internal through-holes, allowing the electrode layers of the deep-groove thin-film stacked structure to form a multi-turn winding structure.

2. The deep trench thin-film passive equalizer in the multi-core integrated system as described in claim 1, characterized in that, A silicon dioxide layer is also included between the silicon substrate and the bottom electrode layer.

3. The deep trench thin-film passive equalizer in the multi-core integrated system as described in claim 2, characterized in that, The deep trench thin-film passive equalizer also includes a copper metal layer connected to the through-hole. The copper metal layer is manufactured by damascus steel and electroplating and is used to complete the internal interconnection of the deep trench thin-film passive equalizer and connect to the interconnect line.

4. The deep trench thin-film passive equalizer in the multi-core integrated system as described in claim 3, characterized in that, The copper metal layer has a thickness of 1 μm; the interlayer dielectric has a thickness of 1 μm; the electrode layer has a thickness of 50 nm; the dielectric layer has a thickness of 20 nm; the deep trench has a trench width of 0.5 μm, a trench spacing of 0.5 μm, and a trench depth-to-width ratio of 5:1 to 10:1; the resistance line width of the resistance region is 1 μm; the inductance region has a length of 50 μm, an inductance line width of 3 μm, and the capacitor region has a side length of 11 μm.

5. The deep trench thin-film passive equalizer in the multi-core integrated system as described in claim 4, characterized in that, The individual unit size of the deep trench thin film passive equalizer is less than 1050 μm².

6. The deep trench thin-film passive equalizer in the multi-core integrated system as described in claim 1, characterized in that, The deep trench-type thin film stack structure and the through holes are covered with silicon dioxide.

7. The deep trench thin-film passive equalizer in the multi-core integrated system as described in claim 1, characterized in that, The conductive material used in the electrode layer is selected from one or more combinations of metals, metal nitrides, or metal alloys; the insulating material used in the dielectric layer is selected from one or more combinations of silicon nitride, metal oxides, or mixed materials.

8. The deep trench thin-film passive equalizer in the multi-core integrated system as described in claim 1, characterized in that, The through-holes are filled with sputtered tungsten metal and the excess tungsten on the surface is removed by a chemical mechanical planarization process.

9. The deep trench thin-film passive equalizer in the multi-core integrated system as described in claim 1, characterized in that, By adjusting the winding length of the resistor region and the inductor region, the resistance ratio and the low-frequency voltage division ratio of the passive equalizer can be adjusted. By adjusting the number of electrode layers, different resistance and inductance values ​​can be obtained, thereby adjusting the operating curve of the passive equalizer.

10. A method for manufacturing a deep trench thin-film passive equalizer in a multi-core integrated system, characterized in that, The method includes: Deep silicon etching is performed on a silicon substrate to create deep trench structures for capacitor, resistor and inductor regions. A first silicon dioxide layer is grown on the silicon substrate to form an insulating layer; On the insulating layer, conductive materials are alternately deposited to form an electrode layer and insulating materials to form a dielectric layer, thereby forming a deep trench type thin film stack structure; The deep trench thin film stack structure is patterned using photolithography and etching processes to define the resistive region, the capacitive region, and the inductive region. A second silicon dioxide layer is deposited on the surface of the deep trench type thin film stack structure and then planarized. By photolithography, development, and etching of the second silicon dioxide layer, through-hole arrays for connecting electrode layers are respectively prepared in the resistive region, the capacitive region, and the inductive region; Sputtering metallic tungsten fills the through-hole array, and chemical mechanical planarization removes excess metallic tungsten from the surface; A copper metal layer connecting the via array is formed using the damascus process and electroplating to complete the internal interconnection of the resistive region, the capacitive region and the inductive region and connect them to external interconnect lines or ground lines.

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