A closed-loop active current source GaN HEMT driving circuit
By using a closed-loop active current source GaN HEMT drive circuit, the problems of mis-enabling and delay in traditional drive circuits in ultra-high frequency applications are solved, achieving fast response and high reliability drive, which is suitable for high-frequency GaN HEMT devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAMEN UNIV
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-09
Smart Images
Figure CN121749963B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of pulse and gate drive control technology, and in particular to a closed-loop active current source type GaNHEMT drive circuit. Background Technology
[0002] With the rapid development of third-generation semiconductor technology, gallium nitride (GaN), as a typical wide-bandgap semiconductor material, has demonstrated its potential for ultra-high frequency switching due to its extremely low gate charge, extremely small input capacitance, and excellent electron mobility. It has become a core device for realizing high-power-density, high-efficiency power electronic devices. Especially in MHz-level ultra-high frequency applications, GaN high electron mobility transistors can significantly reduce the size of passive devices and improve system integration, demonstrating significant advantages.
[0003] The driving performance of power semiconductor devices directly determines their operating limits and reliability. The ultra-high frequency characteristics of GaN HEMTs place stringent requirements on the driving circuit. Traditional voltage source drivers control the switching process through an external gate resistor, which exposes the following insurmountable defects in high-frequency applications: First, the gate resistor value must be chosen between switching speed and oscillation suppression; a smaller resistor easily causes increased voltage and current oscillations, while a larger resistor significantly increases switching losses. Second, most of the energy from the charging and discharging of the gate capacitor is consumed in the resistor and converted into heat; as the switching frequency increases to the MHz level, the driving losses increase proportionally. Furthermore, the exponential decay characteristic of the gate current limits the charging and discharging rate of the input capacitor, failing to fully realize the ultra-high frequency potential of GaN devices.
[0004] More importantly, the device characteristics of GaN HEMTs and the ultra-high frequency operating conditions together present multiple reliability challenges, which are mainly manifested in two pairs of core contradictions: First, the contradiction between extremely fast switching speed and extremely low false turn-on threshold. The threshold voltage of GaN devices is typically only 1-2V. The high dv / dt under ultra-high frequency operation will inject displacement current through Miller capacitance, which can easily cause the gate voltage to exceed the threshold and cause false turn-on. Second, the contradiction between high-frequency drive requirements and device stress tolerance. The large drive current required for high-frequency drive is prone to overshoot of turn-on current and overshoot of turn-off voltage due to non-ideal factors such as loop parasitic inductance, device parasitic capacitance, and diode reverse recovery. This poses a severe test to the voltage and current stress tolerance of the device, which is particularly significant in MHz-level applications.
[0005] To overcome the shortcomings of traditional drive technologies, the industry has proposed a variety of advanced drive architectures: current source drivers shorten switching time through constant current charging and discharging, but they do not consider the delay caused by the setup time of the drive current source under high-frequency drive conditions, and it is difficult to suppress multiple types of parasitic coupling interference at the same time; resonant gate drivers use LC resonance to recover gate energy to reduce losses, but the resonant frequency is fixed, the adaptability is limited, and the sinusoidal drive waveform is not conducive to fast switching at ultra-high frequencies; although conventional active gate drivers can suppress oscillations by dynamically adjusting drive parameters, their closed-loop control is usually complex and discrete circuits are prone to introducing delays, making it difficult to meet the stringent real-time requirements of MHz-level drives. Summary of the Invention
[0006] To overcome the shortcomings of existing technologies that fail to address the ultra-high frequency operating characteristics of GaN HEMTs, and to solve the problems of mis-conduction, parasitic coupling interference, and drive current settling delay, the technical problem to be solved by this invention is to propose an integrable closed-loop active current source type GaN HEMT drive circuit, which adopts the following technical solution:
[0007] A closed-loop active current source type GaN HEMT drive circuit includes:
[0008] Control circuit;
[0009] The current-driven module has its output terminal used to connect the external gate and external source of the GaN HEMT to be driven.
[0010] The transient positioning module has its input terminal connected to the external drain of the GaN HEMT to be driven. It is used to detect the drain-source voltage and generate stage indication signals that characterize different transient stages during the switching process of the GaN HEMT to be driven. The stage indication signals are output to the control circuit. The stage indication signals include at least multiple logic signals obtained from the amplitude comparison result of the drain-source voltage and / or the rate of change comparison result of the drain-source voltage.
[0011] The aforementioned current steering module includes a pull-up constant current source, a pull-down constant current source, a current-guided switch network, and an auxiliary current path.
[0012] The aforementioned current-guided switching network, under the action of the aforementioned control circuit, has at least the following characteristics:
[0013] In the first working mode, the pull-up constant current source and the pull-down constant current source form a continuous current path through the auxiliary current path, and the output terminal is in a high-resistance or weak-drive state relative to the external gate.
[0014] In the second operating mode, the current-directed switching network directs the current of at least one of the pull-up constant current source and the pull-down constant current source to the output terminal to charge or discharge the external gate.
[0015] The control circuit controls the current-guided switch network to switch between the first operating mode and the second operating mode according to the stage indication signal, and selectively switches the magnitude of the drive current provided by at least one of the pull-up constant current source and the pull-down constant current source according to the stage indication signal in the second operating mode.
[0016] This invention uses a transient positioning module to detect and process the drain-source voltage during the switching process of the GaN HEMT to be driven, generating a stage indication signal and providing it to the control circuit. This allows the control circuit to switch between a first and a second operating mode based on the stage indication signal, and selectively switch the drive current and drive level in the second operating mode. Specifically, in the first operating mode, the pull-up constant current source and the pull-down constant current source form a continuous current path through an auxiliary current path, and the output terminal is in a high-impedance state to the external gate, thus keeping the constant current source continuously conducting during non-driving periods and reducing response hysteresis during drive mode switching. In the second operating mode, a current-directed switching network directs the current from the pull-up and / or pull-down constant current sources to the output terminal to charge or discharge the external gate, and switches the drive current and drive level according to the stage indication signal at different transient stages. This ensures that the driving process meets the requirements of rapid charging and discharging while also constraining stages prone to voltage overshoot, current overshoot, or parasitic oscillations, thereby reducing the risk of mis-shutdown and improving drive reliability and electromagnetic compatibility performance.
[0017] As a further improvement, the aforementioned current steering module also includes a bias and reference circuit, which includes at least a reference current source, a reference NMOS transistor, a mirror NMOS transistor, a first resistor, a seventh resistor, a twelfth resistor, a first adjustment switch, and a fifth adjustment switch.
[0018] The reference current source is connected to the drain of the reference NMOS transistor, the source of the reference NMOS transistor is grounded through the first resistor, and the first and / or fifth adjustment switches are controlled by the control circuit to selectively connect the seventh and / or twelfth resistors to the source branch of the reference NMOS transistor, thereby changing the equivalent resistance of the source branch of the reference NMOS transistor; the gate of the reference NMOS transistor is connected to the gate of the mirror NMOS transistor, so that the mirror NMOS transistor outputs a mirror bias signal to bias the pull-up constant current source and / or the pull-down constant current source.
[0019] In this embodiment, the bias and reference circuit controls the connection state of the seventh and / or twelfth resistors by adjusting the switch, thereby changing the equivalent resistance of the reference branch and causing the mirror bias signal to change accordingly, thus adjusting the bias of the pull-up constant current source and / or pull-down constant current source. In this way, the drive current has a controllable and adjustable setting basis, allowing the control circuit to switch different magnitudes of drive current at different transient stages in conjunction with the stage indication signal. This reduces the risk of overshoot and oscillation while ensuring switching speed, and improves the adaptability to different device parameters and operating conditions.
[0020] As a further improvement, the above-mentioned pull-up constant current source is composed of a first transistor, and the source of the first transistor is connected to the fixed power supply VCC through a source resistor.
[0021] The aforementioned pull-down constant current source is composed of a fifth transistor, and the source of the fifth transistor is grounded through a source resistor.
[0022] In this embodiment, the pull-up constant current source and the pull-down constant current source respectively achieve current setting and stabilization through source resistors, so that the charging current and the discharging current remain relatively stable. This provides a current basis for the current-guided switch network to perform predictable constant current charging and discharging on the external gate, improves the consistency and controllability of the drive current, and facilitates the switching of drive current magnitude in different transient stages.
[0023] As a further improvement, the current-guided switching network includes a second transistor, a third transistor, a fourth transistor, and a twelfth transistor; wherein the source of the second transistor and the source of the twelfth transistor are respectively connected to the drain of the first transistor, and the source of the third transistor and the source of the fourth transistor are respectively connected to the drain of the fifth transistor; the drain of the second transistor and the drain of the third transistor are connected to form a first node; the drain of the twelfth transistor and the drain of the fourth transistor are connected to form a second node, and the second node is connected to the external gate of the GaN HEMT to be driven through an external gate resistor.
[0024] In this embodiment, the aforementioned current-directed switching network forms a current-directed path using four transistors. This allows the control circuit to direct the current from the pull-up and / or pull-down constant current sources to the second node in the second operating mode to charge or discharge the external gate. Simultaneously, in the first operating mode, the constant current source current forms a continuous current path with the auxiliary current path through the first node, maintaining a high impedance state between the output terminal and the external gate. This guidance method achieves both continuous conduction of the constant current source and high impedance isolation at the output terminal, enabling rapid switching between the drive current direction and the output state between the two operating modes. This, in conjunction with the stage indication signal, allows for the adjustment of the drive strategy during transient phases.
[0025] As a further improvement, the auxiliary current path includes a unity-gain buffer, the two ends of which are respectively connected to the first node and the second node, and the unity-gain buffer is configured to follow the unity-gain, so as to form the continuous current path between the pull-up constant current source, the pull-down constant current source and the unity-gain buffer in the first operating mode.
[0026] In this embodiment, a unity-gain buffer is used to establish a following path between the first node and the second node in the first operating mode, enabling a continuous current path to be formed and maintained continuously between the pull-up constant current source, the pull-down constant current source, and the unity-gain buffer. When switching to the second operating mode, the current-directed switching network drives the current to the second node and charges or discharges the external gate through the external gate resistor. This setting makes the continuous current path in the first operating mode more stable, thereby further reducing the response hysteresis during drive mode switching and improving the smoothness and controllability of switching between the first and second operating modes.
[0027] As a further improvement, the aforementioned current steering module also includes a drive level switching stage, which includes a third NMOS transistor and a fourth NMOS transistor. The drain of the third NMOS transistor is connected to the power supply VEE, and the source of the fourth NMOS transistor is connected to ground potential. The source of the third NMOS transistor and the drain of the fourth NMOS transistor are connected together to the external source of the GaNHEMT to be driven, so as to select the external source reference potential under different control states.
[0028] In this embodiment, the drive level switching stage selects an external source reference potential so that the external source corresponds to different drive levels under different control states. This increases damping to suppress overshoot during transient phases where overshoot and oscillation are prone to occur, provides stronger turn-off margin for the turn-off state, reduces the risk of gate-source voltage rise under parasitic coupling conditions, thereby improving the anti-misleading turn-on capability and improving the consistency and safety margin of the turn-off process.
[0029] As a further improvement, the aforementioned current steering module also includes gate-source voltage detection, which includes a voltage divider resistor, a voltage divider resistor, and a Schmitt trigger. One end of the voltage divider resistor is connected to the external gate of the GaN HEMT to be driven, and the other end of the voltage divider resistor is connected to the external source of the GaN HEMT to be driven. The connection point of the voltage divider resistor is connected to the non-inverting input of the Schmitt trigger, and the inverting input of the Schmitt trigger is connected to a reference level.
[0030] In this embodiment, the gate-source voltage detection obtains the divided signal of the gate-source voltage through a voltage divider resistor, and a Schmitt trigger performs threshold determination based on a reference level to provide a stable determination basis for the control circuit. In this way, the control circuit can maintain a relatively stable threshold determination even under noise and oscillation conditions, thereby defining critical moments in the turn-on or turn-off process and triggering operating mode switching, improving the robustness of stage indication-related control, and reducing the risk of misjudgment leading to false activation.
[0031] As a further improvement, the aforementioned transient positioning module includes an RC voltage divider network, which is composed of an upper bridge arm RC branch and a lower bridge arm RC branch connected in series. The upper bridge arm RC branch includes an eighth resistor and a first capacitor connected in parallel, and the lower bridge arm RC branch includes a ninth resistor and a second capacitor connected in parallel. The common connection point of the upper and lower bridge arm RC branches outputs a drain-source voltage sampling signal. One end of the upper bridge arm RC branch is connected to the input terminal of the transient positioning module, and one end of the lower bridge arm RC branch is grounded.
[0032] In this embodiment, an RC voltage divider network is used to obtain the drain-source voltage sampling signal, enabling subsequent amplitude comparison to be processed based on the sampling signal. At the same time, through the parallel configuration of RC branches, the sampling signal maintains good tracking capability under high-frequency transient conditions, thereby improving the identification accuracy of different transient stages and reducing the impact of detection link delay on stage positioning.
[0033] As a further improvement, the transient positioning module includes a voltage differentiating circuit, which includes a differentiating capacitor, a differentiating resistor, and a zero-crossing comparator. The differentiating capacitor is connected in series with the drain-source voltage sampling signal and the non-inverting input of the zero-crossing comparator. The non-inverting input is grounded through the differentiating resistor. The inverting input of the zero-crossing comparator is connected to a first reference voltage, and the zero-crossing comparator outputs a second output signal.
[0034] In this embodiment, a voltage differentiating circuit is used to characterize the rate of change of the drain-source voltage, and a zero-crossing comparator, combined with a first reference voltage, outputs a second output signal to provide the control circuit with a logic indication related to the rate of change of the drain-source voltage. In this way, the control circuit can identify the rapid change phases in the switching process and accordingly switch the magnitude of the drive current in stages, thereby constraining the transient phases prone to overshoot and oscillation, improving the controllability of the switching process and the device stress safety margin.
[0035] As a further improvement, the aforementioned transient positioning module also includes:
[0036] A voltage sampling circuit, comprising a comparator, wherein the inverting input of the comparator is connected to a second reference voltage, the non-inverting input of the comparator is connected to the drain-source voltage sampling signal, and the comparator outputs a third output signal;
[0037] A voltage peak detection and holding circuit, comprising a first operational amplifier, a diode, a holding capacitor, a reset switch, and a buffer amplifier, wherein the buffer amplifier outputs a first output signal;
[0038] The first output signal, the second output signal, and the third output signal constitute the stage indication signal and are provided to the control circuit.
[0039] In this embodiment, the voltage sampling circuit outputs a third output signal based on a comparison between the drain-source voltage sampling signal and a second reference voltage, providing a logical indication that the drain-source voltage amplitude crosses a threshold. The voltage peak detection and hold circuit captures and holds the drain-source voltage peak information during the switching process and outputs a first output signal. The second output signal provides a logical indication related to the drain-source voltage change rate. Through the combination of the above multiple logic signals, the stage indication signal can more comprehensively reflect the key transient stages of the switching process, enabling the control circuit to more specifically switch the drive current magnitude of the pull-up constant current source and / or pull-down constant current source in the second operating mode, thereby reducing the risk of turn-on current overshoot and turn-off voltage overshoot, and improving the repeatability and adjustability of the drive strategy under different operating conditions. Attached Figure Description
[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.
[0041] Figure 1 This is a schematic diagram of the overall framework structure of the present invention;
[0042] Figure 2 This is a schematic diagram of the circuit structure of the current steering module and the GaN HEMT power stage of the present invention.
[0043] Figure 3 This is a schematic diagram of the circuit structure of the transient positioning module of the present invention.
[0044] Figure 4 In the diagram, (a) is a comparison of the drain current and drain-source voltage before (dashed line) and after (solid line) optimization during the switching process of the present invention; (b) is a schematic diagram of the driving level and driving current during different switching transient stages of the present invention. Detailed Implementation
[0045] To facilitate understanding by those skilled in the art, the structure of the present invention will now be described in further detail with reference to the accompanying drawings:
[0046] The following combination Figures 1 to 3 This paper describes the specific implementation of an active current-source GaN HEMT drive circuit. It should be understood that the following implementation is used to illustrate the feasible circuit composition, connection relationships, and workflow. Specific device dimensions, resistor and capacitor values, and logic thresholds can be engineered based on the target GaN HEMT device parameters, bus voltage level, and switching frequency. Equivalent substitutions are permitted without altering the core connection relationships and control flow.
[0047] like Figure 1 The driving circuit consists of a control circuit, a current-steering drive module, a GaN HEMT power transistor stage, and a transient positioning module. The control circuit provides control signals to the current-steering drive module. The output of the current-steering drive module is connected to the external gate and external source of the GaN HEMT to be driven, providing charging or discharging current to the external gate to change the gate-source voltage. The input of the transient positioning module is connected to the external drain of the GaN HEMT to be driven. It detects the drain-source voltage and generates a stage indication signal, which is then output to the control circuit. The control circuit performs staged control of the current-steering drive module based on the stage indication signal, selecting different drive currents at different transient stages and controlling the current-guided switching network to switch between different operating modes.
[0048] In one implementation, Figure 1 Each module is integrated into the same driver chip or driver board. The current-controlled drive module is positioned close to the GaN HEMT power transistor stage, with the external gate and external source connected via Kelvin pins. This separates the source parasitic inductance voltage drop caused by the power loop current from the gate drive reference ground, facilitating the control circuit to adjust the drive current based on the drain-source voltage changes fed back from the transient positioning module. The transient positioning module's sampling terminal is positioned close to the external drain of the GaN HEMT, reducing spike errors introduced by the parasitic inductance of the sampling loop and ensuring that the stage indication signal better reflects the true transient drain-source voltage of the device.
[0049] like Figure 2 In a GaN HEMT power transistor stage, the transistor is represented by Q. The external drain is connected to the power bus or load network via terminal T1, the external source is connected to the power circuit return current, and the external gate is connected via external gate resistor R. g,ext Connect the output node of the current steering module. This is to describe parasitic effects under high-speed switching. Figure 2 Schematic diagram of external drain parasitic inductance L d External source parasitic inductance Ls Gate parasitic resistance R g,int With gate parasitic inductance L g,int And the gate-source capacitance C is shown. gs Gate-drain capacitance C gd With drain-source capacitance C ds The parasitic parameters mentioned above can cause drain-source voltage and current spikes, gate voltage coupling, and ringing during fast switching of GaN HEMTs. The current-controlled module constrains the switching transients through staged current control.
[0050] The current steering module includes a pull-up constant current source, a pull-down constant current source, a current-directed switching network, and an auxiliary current path. The pull-up constant current source provides charging current to the external gate, the pull-down constant current source draws discharging current from the external gate, the current-directed switching network directs the constant current source current to the output terminal or to the internal loop under the action of a control signal, and the auxiliary current path forms a continuous current path during the non-driving phase, keeping the constant current source branch in a conducting state.
[0051] The pull-up constant current source is composed of a first transistor Q1. The source of the first transistor Q1 is connected to the fixed power supply VCC through a source resistor R6, and the drain of the first transistor Q1 serves as the pull-up current output terminal, connected to the input node on the pull-up side of the current-guided switching network. By controlling the gate bias of the first transistor Q1, an approximately constant charging current can be established between VCC and the output node.
[0052] The pull-down constant current source is composed of the fifth transistor Q5. The source of the fifth transistor Q5 is grounded through the source resistor R3, and the drain of the fifth transistor Q5 serves as the pull-down current input terminal, connected to the pull-down input node of the current-directed switching network. By controlling the gate bias of the fifth transistor Q5, an approximately constant discharge current can be established between the output node and ground potential.
[0053] The current-directed switching network includes a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and a twelfth transistor Q12. The sources of the second transistor Q2 and the twelfth transistor Q12 are connected to the drain of the first transistor Q1. The sources of the third transistor Q3 and the fourth transistor Q4 are connected to the drain of the fifth transistor Q5. The drains of the second transistor Q2 and the third transistor Q3 are connected to form a first node, which is used to connect to an auxiliary current path. The drains of the twelfth transistor Q12 and the fourth transistor Q4 are connected to form a second node, which is connected to an external gate resistor R. g,ext Connect the external gate of the GaN HEMT. By controlling the conduction states of the second transistor Q2, the twelfth transistor Q12, the third transistor Q3, and the fourth transistor Q4, the pull-up constant current source current or the pull-down constant current source current selectively flows into the second node, thereby charging or discharging the external gate.
[0054] The auxiliary current path includes a unity-gain buffer U5. The two ends of the unity-gain buffer U5 are connected to the first node and the second node respectively, and the unity-gain buffer U5 is configured as a unity-gain follower. In the first operating mode, the control circuit configures the current-directed switching network to an internal return state, allowing the pull-up and pull-down constant current sources to form a continuous current path with the unity-gain buffer U5 through the current-directed switching network. Simultaneously, the second node is made to be in a high-impedance state or an equivalent weak-drive state relative to the external gate. The first operating mode is used to maintain the continuity of the constant current source branch current, avoiding delays caused by re-establishing the bias current when switching to the drive phase. The second operating mode is used to direct the constant current source current to the second node to charge or discharge the external gate, and selectively switches the drive current magnitude according to the stage indication signal in the second operating mode.
[0055] The bias and reference circuits are used to generate a constant current source bias. Figure 2 In the implementation, the bias and reference circuit includes a reference current source I. ref The system consists of a reference NMOS transistor Q9, a mirrored NMOS transistor Q8, a first resistor R1, a seventh resistor R7, and a first regulating switch S1. Reference current source I... ref The drain of reference NMOS transistor Q9 is connected, and the source of reference NMOS transistor Q9 is grounded through the first resistor R1. The first regulating switch S1 is controlled by the control circuit, causing the seventh resistor R7 to be selectively connected to the source branch of reference NMOS transistor Q9, thereby changing the equivalent resistance of the source branch of reference NMOS transistor Q9. The gate of reference NMOS transistor Q9 is connected to the gate of mirror NMOS transistor Q8, and the mirror NMOS transistor Q8 outputs a mirror bias signal to bias the pull-down constant current source or related branches.
[0056] In one optional implementation of the above bias and reference circuit, the freewheeling NMOS transistor Q7, the freewheeling PMOS transistor Q13, the mirror PMOS transistor Q6, and the source resistor R5 together constitute the freewheeling holding branch, which is used to provide continuous bias current to the pull-up bias branch and the pull-down bias branch when the current steering drive circuit is in the first operating mode, so that the pull-up constant current source and the pull-down constant current source are kept in the pre-biased conduction state. Specifically, the gate of the freewheeling NMOS transistor Q7 is connected to the fixed power supply VCC to form a preset bias, so that the freewheeling NMOS transistor Q7 provides freewheeling current in its drain-source path; the gate of the freewheeling PMOS transistor Q13 is connected to the ground potential to form a preset bias, so that the freewheeling PMOS transistor Q13 and the freewheeling NMOS transistor Q7 form a freewheeling connection between the mirror current branch and the pull-up bias branch; the source of the mirror PMOS transistor Q6 is connected to the fixed power supply VCC through the source resistor R5, and the gate of the mirror PMOS transistor Q6 is led out to the current steering drive circuit so that the pull-up bias branch obtains a bias current corresponding to the mirror of the reference branch.
[0057] By setting up a freewheeling holding branch, when the current-guided switching network switches from the first operating mode to the second operating mode, the operating points of the pull-up constant current source and the pull-down constant current source do not need to be re-established, thereby reducing current build-up delay and minimizing transient fluctuations during mode switching. It should be understood that the device types and connection methods in the freewheeling holding branch can be equivalently replaced according to the manufacturing process, as long as they can provide continuous bias current and maintain the pre-biased state of the constant current source in the first operating mode.
[0058] To achieve multiple drive current levels, a twelfth resistor R12 is connected in parallel to the source branch of the reference NMOS transistor Q9. The connection or disconnection of the twelfth resistor R12 is controlled by the fifth adjustment switch S5, so that the equivalent resistance of the source branch has more selectable levels.
[0059] The control circuit achieves multi-level adjustment of the reference branch current through the combined states of the first adjusting switch S1 and the fifth adjusting switch S5, thereby enabling the pull-up constant current source and the pull-down constant current source to output different current magnitudes at different stages. In an executable current setting relationship, the pull-up side current I... source With pull-down side current I sink The following relationship must be satisfied:
[0060] ;
[0061] Where R s The equivalent source resistance of the constant current source branch is... Figure 2 In the illustration, R s = R2 = R3 = R5 = R6,R ref To reference the source equivalent resistance of NMOS transistor Q9, R ref The value changes depending on the connection state of the seventh resistor R7 and the twelfth resistor R12. R is adjusted by controlling the first adjusting switch S1 and the fifth adjusting switch S5. ref To achieve I source with I sink Multiple gears can be switched quickly.
[0062] The current steering wheel drive module also includes a drive level switching stage. Figure 2 The intermediate drive level switching stage includes a third NMOS transistor S3 and a fourth NMOS transistor S4. The drain of the third NMOS transistor S3 is connected to the power supply VEE, and the source of the fourth NMOS transistor S4 is connected to ground. The sources of the third NMOS transistor S3 and the drain of the fourth NMOS transistor S4 are connected to the external source of the GaN HEMT. The control circuit selects whether the third NMOS transistor S3 or the fourth NMOS transistor S4 is turned on based on the switching phase, thereby selecting the external source reference potential. By switching the external source reference potential, the damping is increased to suppress overshoot during transient phases prone to overshoot and oscillation, a more negative gate-source voltage margin is formed during the turn-off phase, and a suitable positive gate-source voltage range is obtained during the turn-on phase.
[0063] The current steering module also includes gate-source voltage detection. Figure 2 The gate-source voltage detection includes a voltage divider resistor R. H With voltage divider resistor R L And Schmitt trigger U7. Voltage divider resistor R H One end is connected to the second node and passes through the external gate resistor R. g,ext One end is connected to the external gate of the GaN HEMT, and the other end is connected to a voltage divider resistor R. L Voltage divider resistor R L The other end is connected to an external source reference node. Voltage divider resistor R H With voltage divider resistor R L The connection point is connected to the non-inverting input of Schmitt trigger U7, and the inverting input of Schmitt trigger U7 is connected to the reference level V. ref3 The output of Schmitt trigger U7 provides the gate-source voltage status signal OUT4 to the control circuit. The hysteresis characteristic of Schmitt trigger U7 is used to suppress jitter near the threshold, enabling the control circuit to obtain a stable gate-source voltage logic judgment result.
[0064] like Figure 3 The transient positioning module is used to detect the external drain voltage of the GaN HEMT and generate a stage indication signal. The input terminal of the transient positioning module is connected to the external drain of the GaN HEMT via terminal T2. The transient positioning module includes an RC voltage divider network, which is composed of an upper bridge arm RC branch connected in series with a lower bridge arm RC branch. The upper bridge arm RC branch includes a parallel eighth resistor R8 and a first capacitor C1, and the lower bridge arm RC branch includes a parallel ninth resistor R9 and a second capacitor C2. The drain-source voltage sampling signal V is output from the common connection point of the upper and lower bridge arm RC branches. ds_sense One end of the upper bridge arm's RC branch is connected to terminal T2, and one end of the lower bridge arm's RC branch is grounded. A voltage divider is formed by the eighth resistor R8 connected in parallel with the first capacitor C1 and the ninth resistor R9 connected in parallel with the second capacitor C2. V ds_sense This reflects the ratio of drain-source voltage amplitude. Through RC frequency compensation, V ds_sense To obtain the phase integrity of high-frequency signals, which is used to ensure the accurate capture of voltage transient signals.
[0065] The transient positioning module includes a voltage differentiating circuit. The voltage differentiating circuit includes a differentiating capacitor C. diff Differential resistance R diff With zero-crossing comparator U3. Differential capacitor C. diff Series connection of drain-source voltage sampling signal V ds_sense The non-inverting input of the zero-crossing comparator U3 is connected to the differentiating resistor R. diff Grounding, differential resistance R diff A differential voltage signal V is formed at both ends.ds_diff The inverting input of the zero-crossing comparator U3 is connected to the first reference voltage V. ref1 The zero-crossing comparator U3 outputs the second output signal OUT2. ds_diff In V ds_sense The polarity changes between the rising and falling edges, and the zero-crossing comparator U3 will change V. ds_diff With the first reference voltage V ref1 This comparison provides the control circuit with a logic indication related to the rate of change of the drain-source voltage.
[0066] The transient positioning module also includes a voltage sampling circuit. The voltage sampling circuit includes a comparator U4. The inverting input of comparator U4 is connected to a second reference voltage V. ref2 The non-inverting input is connected to the drain-source voltage sampling signal V. ds_sense The comparator U4 outputs a third output signal OUT3. This third output signal OUT3 indicates the magnitude of the drain-source voltage relative to the second reference voltage V. ref2 The relative relationship between them.
[0067] The transient positioning module also includes a voltage peak detection and hold circuit. This circuit comprises a first operational amplifier U1, a diode D2, a holding capacitor C4, a reset switch Q11, and a buffer amplifier U2. The first operational amplifier U1 drives the input sampling node, and the diode D2 conducts unidirectionally, charging the peak voltage into the holding capacitor C4, which stores the peak voltage V. peak The reset switch Q11 is turned on by the reset signal Reset to clear the peak value of the previous cycle. The buffer amplifier U2 buffers the voltage across the holding capacitor C4 and outputs the first output signal OUT1.
[0068] The stage indication signals include at least two logic signals: the second output signal OUT2 and the third output signal OUT3. The control circuit combines the gate-source voltage status signal OUT4 and the PWM signal to constrain the driving process. After receiving these signals, the control circuit outputs current-guided switch network control signals UP, UPn, DN, and DNn according to preset stage criteria, as well as control signals for the first and fifth regulating switches and drive level switching control for the third NMOS transistor S3 and the fourth NMOS transistor S4. A reset signal Reset is also output when necessary.
[0069] The following combination Figures 2 to 4 This illustrates an example of an executable phased process, wherein the current steering module, under the control of the control circuit, has at least a first operating mode and a second operating mode: the first operating mode is used to maintain the pull-up constant current source and the pull-down constant current source forming a continuous current path through the auxiliary current path, so that the constant current source branch remains in a pre-biased conducting state; the second operating mode is used to instantaneously guide the constant current source current to the second node and through the external gate resistor R.g,ext It enables the charging and discharging of the external gate.
[0070] Before execution, once the fixed power supply VCC and power supply VEE have stabilized, the control circuit enables the reset signal Reset, turning on the reset switch Q11 and discharging the holding capacitor C4, so that the first output signal OUT1 of the peak detection holding circuit returns to its initial level. Subsequently, the control circuit configures the current-directed switching network to the first operating mode, forming a continuous current path between the pull-up constant current source, the pull-down constant current source, and the auxiliary current path. At the same time, the second node is configured to a high-impedance state or an equivalent weak-drive state for the external gate to avoid undesirable pull-up or pull-down of the external gate at power-on.
[0071] Regarding the reference current level setting, the control circuit sets the combined state of the first adjustment switch S1 and the fifth adjustment switch S5 based on the maximum allowable gate charging and discharging current, target switching speed, electromagnetic compatibility constraints, and static power consumption constraints of the first operating mode. It then selects the combination of the seventh resistor R7 and the twelfth resistor R12 connected to the source branch of the reference NMOS transistor Q9, thereby setting the equivalent resistance R of the reference branch. ref The reference current level is obtained. The reference current is mapped to the first transistor Q1 and the fifth transistor Q5 via the mirrored NMOS transistor Q8 and the pull-up bias branch, enabling the pull-up constant current source and pull-down constant current source to obtain the corresponding level constant current value. In an executable current setting relationship, the maximum pull-up drive current level can be estimated using the following formula and used for level selection:
[0072] ;
[0073] Where C iss For GaN HEMT input capacitance, ΔV gs Δt represents the voltage change that the gate-source voltage needs to complete, and Δt represents the time window within which this voltage change is expected to be completed.
[0074] Regarding the threshold and reference level settings, the control circuit sets the first reference voltage V based on the PWM state. ref1 It has a negative value close to 0 when the PWM signal is 1, and a positive value close to 0 when the PWM signal is 0; the second reference voltage V ref2 Based on the bus voltage reference and RC voltage divider delay characteristics; reference reference level V ref3 Based on the desired gate-source voltage threshold setting, it is slightly less than VCC when the PWM signal is 1 and slightly greater than the negative VEE when the PWM signal is 0, serving as the threshold criterion for the Schmitt trigger U7 to output the gate-source voltage status signal OUT4. After completing the above preparations, the control circuit enters the closed-loop control flow of stages 1 to 10 described below.
[0075] Phase 1: Turn-on Delay Phase. When the PWM signal flips from low to high, the control circuit enters Phase 1 and switches the current steering module to the second operating mode to execute the turn-on drive. The control circuit configures the second transistor Q2 to be off and the twelfth transistor Q12 to be on, so that the current from the pull-up constant current source is directed to the second node; at the same time, it controls the first adjustment switch S1 and the fifth adjustment switch S5 to be disconnected to select the safe maximum pull-up drive current level I. gmax1 Injection is applied to the external gate; and the third NMOS transistor S3 in the drive level switching stage is turned off while the fourth NMOS transistor S4 is turned on, so that the external source reference potential is connected to the ground potential, thereby forming the turn-on drive condition with a drive voltage of VCC, and making the gate-source voltage V gs Rise to the threshold voltage V at maximum drive speed T Nearby. During this stage, the control circuit simultaneously turns off the third transistor Q3 and the fourth transistor Q4, causing the pull-down constant current source I... sink It does not participate in driver activation, thereby reducing unnecessary power consumption.
[0076] Phase 2: Current Rise Phase. When the gate-source voltage V... gs Exceeding the threshold voltage V T Afterwards, the drain current Ids begins to rise and causes the drain-source voltage V to rise. ds The bus voltage level began to drop. The voltage sampling circuit of the transient positioning module sampled the drain-source voltage signal V. ds_sense With the second reference voltage V ref2 Comparison, when the drain-source voltage sampling signal V ds_sense Less than V ref2 At this time, the third output signal OUT3 outputs a low level, and the control circuit enters stage 2. In stage 2, to suppress the turn-on current overshoot, the control circuit immediately turns on the first regulating switch S1 and turns off the fourth NMOS transistor S4, while turning on the third NMOS transistor S3, switching the drive voltage from VCC to VCC-VEE (VEE>0); simultaneously, it pulls up the constant current source I... source Downsizing limits the maximum drive current level to reduce gate charging capability and increase channel equivalent on-resistance, thereby reducing voltage-current change rate and suppressing turn-on current overshoot and ringing.
[0077] At this time, the driving level and the change in the device's on-resistance satisfy the following relationship:
[0078] ;
[0079] Among them, V gs and V T These represent the input gate voltage and the threshold voltage of the GaN HEMT power transistor, respectively. n For electron mobility, C oxWhere I is the oxide layer capacitance per unit area, W is the width, and L is the channel length. In the above embodiment, the control circuit reduces I... source Make V GS The rise is smoother, and by adjusting the drive level, the device is placed in a more damping on-resistance range, thereby restraining overshoot and ringing.
[0080] To illustrate the relationship between drive level switching and rate of change constraint, the drain current rate of change and the drain-source voltage rate of change can be characterized by the following formula:
[0081] During the activation phase, V ds decline:
[0082] ;
[0083] ;
[0084] During the shutdown phase, V ds rise:
[0085] ;
[0086] ;
[0087] Where I D For drain current, g m For transconductance, R g R is the equivalent gate resistance. g Includes external gate resistor R g,ext With gate parasitic resistance R g,int L s For external source parasitic inductance, C GD For gate-drain capacitance, V Miller This represents the Miller plateau voltage. It should be understood that the drain-source voltage decreases during the turn-on phase, hence dV ds / dt can be in negative form; during the turn-off phase, the drain-source voltage tends to increase, therefore dV ds / dt can be in positive form.
[0088] Stage 3: Voltage Drop Stage. As the drain-source voltage V... ds Entering the rapid descent range, the voltage differentiating circuit of the transient positioning module affects the drain-source voltage V. ds Differential processing is performed to obtain the differential voltage signal V. ds_diff Differential voltage signal V ds_diff Used to characterize the drain-source voltage change rate dV ds / dt. Zero-crossing comparator U3 will differentiate the voltage signal V. ds_diff With the first reference voltage V ref1 Compare and output the second output signal OUT2. When V ds_diffLess than V ref1 At this time, the second output signal OUT2 outputs a low level, and the control circuit enters stage 3. In stage 3, the control circuit keeps the first adjustment switch S1 on, and keeps the third NMOS transistor S3 on and the fourth NMOS transistor S4 off in the drive level switching stage, so that the drive condition is maintained at the overshoot suppression level, continuously limiting dI. D / dt and dV DS / dt.
[0089] Phase 4: To Fully Conducted Stage. Once the drain-source voltage Vds has decreased and stabilized, the voltage differentiating circuit detects dV. ds When / dt is greater than Vref1, the second output signal OUT2 flips and outputs a high-level signal, and the control circuit enters stage 4. In stage 4, the control circuit immediately disconnects the first adjustment switch S1, and controls the drive level switching stage to turn on the fourth NMOS transistor S4 and disconnect the third NMOS transistor S3, so that the drive level is restored to the turn-on drive condition, and pulls up the constant current source I. source Switching to a higher drive current level accelerates the charging of the gate capacitor, making V gs It quickly reaches the preset drive voltage and completes the final charging stage of the start-up process.
[0090] Phase 5: Maintenance phase after turn-on. When the gate-source voltage V... gs When the preset drive voltage VCC is reached, the gate-source voltage status signal OUT4 output by the gate-source voltage detection circuit represents the logic result indicating that the turn-on is complete, and the control circuit enters stage 5. In stage 5, the control circuit configures the twelfth transistor Q12 to be turned off, the second transistor Q2 to be turned on, the third transistor Q3 to be turned on, and the fourth transistor Q4 to be turned off, and turns on the first regulating switch S1 and the fifth regulating switch S5, so that the constant current source I is pulled down. sink The generated current flows through the auxiliary current path and the pull-up constant current source I with a minimum quiescent current. source This allows for freewheeling, thereby reducing static losses while maintaining the pre-biased on state, and providing a fast response basis with no current setup delay for the turn-off command in the next cycle.
[0091] Phase 6: Turn-off Delay Phase. When the PWM signal flips from high to low, the control circuit enters Phase 6 and switches the current steering module to the second operating mode to execute the turn-off drive. The control circuit configures the third transistor Q3 to turn off and the fourth transistor Q4 to turn on, so that the current from the pull-down constant current source is directed to the second node; at the same time, the first adjustment switch S1 and the fifth adjustment switch S5 are disconnected to select the safe maximum pull-down drive current level to draw charge from the external gate; and the drive level switching stage is controlled to turn on the third NMOS transistor S3 and turn off the fourth NMOS transistor S4, so that the external source reference potential is connected to the power supply VEE, thereby forming the turn-off drive condition with a negative drive voltage VEE, so that Vgs The speed drops to the Miller plateau voltage V at maximum drive speed. miller Nearby. During this stage, the control circuit configures the second transistor Q2 to turn off and the twelfth transistor Q12 to turn off, thus pulling up the constant current source I. source It does not participate in the turn-off extraction process, thereby reducing the static current path and static power consumption of the corresponding branch.
[0092] Stage 7: Voltage Rise Stage. When the gate-source voltage V... gs Drop to Miller plateau voltage V miller After entering the plateau region, the V of the GaN HEMT power transistor... ds It begins to rise, dV ds When / dt is greater than 0, the voltage differentiating circuit of the transient positioning module affects the drain-source voltage V. ds Differentiate and compare with the first reference voltage V ref1 Comparison, when dV is detected ds / dt is greater than V ref1 When the second output signal OUT2 is high, the control circuit enters stage 7. In stage 7, the control circuit keeps the first adjustment switch S1 and the fifth adjustment switch S5 in the open state, and keeps the third NMOS transistor S3 in the drive level switching stage in the on state.
[0093] Stage 8: Current Decrease Stage. When the drain-source voltage V... ds When the voltage rises to the bus voltage range, the voltage sampling circuit of the transient positioning module compares the drain-source voltage sampling signal V. ds_sense With the second reference voltage V ref2 When the drain-source voltage sampling signal V ds_sense When the voltage exceeds Vref2 and the third output signal OUT3 outputs a corresponding high level, the control circuit enters stage 8. In stage 8, to suppress the overshoot of the turn-off voltage, the control circuit immediately turns on the first adjustment switch S1 and controls the drive level switching stage to disconnect the third NMOS transistor S3 and turn on the fourth NMOS transistor S4, thus reducing the drive level; simultaneously, it pulls down the constant current source I... sink The maximum drive current level is adjusted to the overshoot limit to reduce the rate of change of the turn-off tap and increase the equivalent damping, thereby suppressing turn-off voltage overshoot and ringing.
[0094] Stage 9: To complete shutdown stage. When the drain-source voltage V ds When the voltage exceeds the overshoot peak and enters the stabilization process, the voltage differentiating circuit detects that dv / dt has left the rapid change range, and the second output signal OUT2 outputs a low level, causing the control circuit to enter stage 9. In stage 9, the control circuit disconnects the first adjustment switch S1 again and controls the drive level switching stage to turn on the third NMOS transistor S3 and disconnect the fourth NMOS transistor S4, causing the pull-down constant current source I to... sinkSwitching to a larger drive current level enhances the ability to extract residual charge from the gate, thereby accelerating V. gs The discharge process descends and completes the final stage of shutdown, bringing the device into a fully shut-off state.
[0095] Phase 10: The maintenance phase after turn-off. When the gate-source voltage V... gs When the preset driving voltage negative VEE is reached, the gate-source voltage status signal OUT4 output by the gate-source voltage detection circuit represents the logic result indicating that the turn-off is complete, and the control circuit enters stage 10. In stage 10, the control circuit configures the fourth transistor Q4 to be turned off, the third transistor Q3 to be turned on, the second transistor Q2 to be turned on, and the twelfth transistor Q12 to be turned off, and turns on the first regulating switch S1 and the fifth regulating switch S5, so that the constant current source I is pulled up. source The generated current flows through the auxiliary current path and the pull-down constant current source I with a minimum quiescent current. sink It forms a follow current, maintains a continuous flow mode and retains a pre-biased state, thereby providing a fast response basis with no current setup delay for the turn-on command in the next cycle.
[0096] Furthermore, when the GaN HEMT is in the off-state steady state, if the switching of the bridge arm transistors causes a rapid change in their drain-source voltage, the Miller capacitance C will be affected. gd The coupled displacement current may raise the gate voltage. At this time, the stage indicator signal level exhibits an abnormal jump. The control circuit monitors the stage indicator signal level in real time. Once an abnormal jump is detected during the non-active drive stage, the control current-directed switching network turns off the third transistor Q3 and turns on the fourth transistor Q4, causing the pull-down constant current source I... sink The current is instantaneously directed to the second node, quickly removing the coupled charge and restoring the gate voltage to a safe value. Since the pull-down constant current source is always in a pre-biased state, the control circuit can complete the current-directed switching in a very short time, thereby suppressing crosstalk-induced turn-on. After completing the phased drive of turn-on or turn-off, the control circuit can switch the current-directed switching network back to the first operating mode, so that the pull-up constant current source and the pull-down constant current source form a continuous current path through the auxiliary current path, and restore the second node to a high-resistance state or an equivalent weak-drive state to the external gate, so as to reduce static losses and maintain the continuity of the constant current source bias current during the switching gap.
[0097] Figure 4 In the above embodiment, (a) shows a schematic diagram comparing the drain current and drain-source voltage before and after optimization during the switching process, where the dashed line represents the state before optimization and the solid line represents the state after optimization. Figure 4 In Figure (b), a schematic diagram of the drive level and drive current during different switching transient phases in the above embodiments is shown. The indicator signal levels for different switching transient phases in the above embodiments are shown in the following table:
[0098]
[0099] Table 1: Indicator signal levels during different switching transient phases
[0100] Through the above implementation methods Figure 1 The division of labor of the modules shown Figure 2 , Figure 3 The specific circuit connections shown form a complete and implementable GaN HEMT gate drive scheme. The transient positioning module generates multiple logic signals—first output signal OUT1, second output signal OUT2, and third output signal OUT3—based on the comparison results of drain-source voltage amplitude and rate of change. The control circuit switches the current-guided switching network between the first and second operating modes according to these logic signals and the PWM signal. In the second operating mode, it switches the reference current levels of the pull-up constant current source and pull-down constant current source in stages. Simultaneously, it combines the drive level switching stage and gate-source voltage detection to constrain the external source reference potential and gate-source state. This allows those skilled in the art to implement this scheme and complete the drive control for different transient stages of the GaN HEMT switching process.
[0101] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.
Claims
1. A closed-loop active current source type GaN HEMT driving circuit, characterized in that, include: Control circuit; The current-driven module has its output terminal used to connect the external gate and external source of the GaN HEMT to be driven. The transient positioning module has its input terminal connected to the external drain of the GaN HEMT to be driven, and is used to detect the drain-source voltage (V). ds The control circuit generates stage indication signals characterizing different transient stages during the driving of the GaN HEMT switch and outputs these stage indication signals to the control circuit. The stage indication signals at least include signals generated by the drain-source voltage (V...). ds The amplitude comparison results and / or drain-source voltage (V) ds The multi-path logic signal is obtained by comparing the rate of change of ) The current steering module includes a pull-up constant current source, a pull-down constant current source, a current-guided switch network, and an auxiliary current path. The current-directed switching network, under the action of the control circuit, has at least the following characteristics: In the first working mode, the pull-up constant current source and the pull-down constant current source form a continuous current path through the auxiliary current path, and the output terminal is in a high-impedance or weak-drive state relative to the external gate. In the second operating mode, the current-directed switching network directs the current of at least one of the pull-up constant current source and the pull-down constant current source to the output terminal to charge or discharge the external gate. The control circuit controls the current-guided switching network to switch between the first operating mode and the second operating mode according to the stage indication signal, and selectively switches the magnitude of the drive current provided by at least one of the pull-up constant current source and the pull-down constant current source according to the stage indication signal in the second operating mode. The current steering module further includes a bias and reference circuit, which at least includes a reference current source (I0). ref ), reference NMOS transistor (Q9), mirror NMOS transistor (Q8), first resistor (R1), seventh resistor (R7), twelfth resistor (R12), first adjustment switch (S1), and fifth adjustment switch (S5); Wherein, the reference current source (I) ref The drain of the reference NMOS transistor (Q9) is connected, and the source of the reference NMOS transistor (Q9) is grounded through the first resistor (R1). The first adjustment switch (S1) and / or the fifth adjustment switch (S5) are controlled by the control circuit to selectively connect the seventh resistor (R7) and / or the twelfth resistor (R12) to the source branch of the reference NMOS transistor (Q9), thereby changing the equivalent resistance of the source branch of the reference NMOS transistor (Q9). The gate of the reference NMOS transistor (Q9) is connected to the gate of the mirror NMOS transistor (Q8) so that the mirror NMOS transistor (Q8) outputs a mirror bias signal to bias the pull-up constant current source and / or the pull-down constant current source.
2. The closed-loop active current source type GaN HEMT drive circuit according to claim 1, characterized in that, The pull-up constant current source is composed of a first transistor (Q1), and the source of the first transistor (Q1) is connected to the fixed power supply VCC through a source resistor (R6). The pull-down constant current source is composed of a fifth transistor (Q5), and the source of the fifth transistor (Q5) is grounded through a source resistor (R3).
3. The closed-loop active current source type GaN HEMT drive circuit according to claim 2, characterized in that, The current-guided switching network includes a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), and a twelfth transistor (Q12). The sources of the second transistor (Q2) and the twelfth transistor (Q12) are respectively connected to the drain of the first transistor (Q1). The sources of the third transistor (Q3) and the fourth transistor (Q4) are respectively connected to the drain of the fifth transistor (Q5). The drains of the second transistor (Q2) and the third transistor (Q3) are connected to form a first node. The drain of the twelfth transistor (Q12) and the drain of the fourth transistor (Q4) are connected to form a second node, and the second node is connected via an external gate resistor (R). g,ext Connect the external gate of the GaN HEMT to be driven.
4. The closed-loop active current source type GaN HEMT drive circuit according to claim 3, characterized in that, The auxiliary current path includes a unity-gain buffer (U5), the two ends of which are connected to the first node and the second node respectively, and the unity-gain buffer (U5) is configured to follow the unity-gain to form the continuous current path between the pull-up constant current source, the pull-down constant current source and the unity-gain buffer (U5) in the first operating mode.
5. The closed-loop active current source type GaN HEMT drive circuit according to claim 4, characterized in that, The current steering module further includes a drive level switching stage, which includes a third NMOS transistor (S3) and a fourth NMOS transistor (S4). The drain of the third NMOS transistor (S3) is connected to the power supply VEE, and the source of the fourth NMOS transistor (S4) is connected to ground potential. The source of the third NMOS transistor (S3) and the drain of the fourth NMOS transistor (S4) are connected to the external source of the GaNHEMT to be driven, so as to select the external source reference potential under different control states.
6. The closed-loop active current source type GaN HEMT driving circuit according to claim 5, characterized in that, The current steering module also includes gate-source voltage detection, which includes a voltage divider resistor (R). H ), voltage divider resistor (R) L ) and Schmitt trigger (U7), the voltage divider resistor (R H One end of the voltage divider resistor (R) is connected to the external gate of the GaN HEMT to be driven. H The other end of the resistor is connected to the voltage divider resistor (R). L The voltage divider resistor (R) is connected to the external source of the GaN HEMT to be driven. H ) and the voltage divider resistor (R) L The connection point is connected to the non-inverting input of the Schmitt trigger (U7), and the inverting input of the Schmitt trigger (U7) is connected to the reference level (V). ref3 ).
7. The closed-loop active current source type GaN HEMT drive circuit according to claim 6, characterized in that, The transient positioning module includes an RC voltage divider network, which is composed of an upper bridge arm RC branch and a lower bridge arm RC branch connected in series. The upper bridge arm RC branch includes an eighth resistor (R8) and a first capacitor (C1) connected in parallel, and the lower bridge arm RC branch includes a ninth resistor (R9) and a second capacitor (C2) connected in parallel. The drain-source voltage sampling signal (V) is output at the common connection point of the upper and lower bridge arm RC branches. ds_sense One end of the upper arm RC branch is connected to the input terminal of the transient positioning module, and one end of the lower arm RC branch is grounded.
8. The closed-loop active current source type GaN HEMT drive circuit according to claim 7, characterized in that, The transient positioning module includes a voltage differentiating circuit, which includes a differentiating capacitor (C). diff Differential resistance (R) diff ) and zero-crossing comparator (U3), the differential capacitor (C diff The drain-source voltage sampling signal (V) is connected in series. ds_sense The non-inverting input of the zero-crossing comparator (U3) is connected to the differential resistor (R). diff The zero-crossing comparator (U3) is grounded; its inverting input is connected to the first reference voltage (V). ref1 The zero-crossing comparator (U3) outputs a second output signal (OUT2).
9. The closed-loop active current source type GaN HEMT drive circuit according to claim 8, characterized in that, The transient positioning module further includes: A voltage sampling circuit, comprising a comparator (U4), wherein the inverting input of the comparator (U4) is connected to a second reference voltage (V). ref2 The non-inverting input of the comparator (U4) is connected to the drain-source voltage sampling signal (V). ds_sense The comparator (U4) outputs a third output signal (OUT3). A voltage peak detection and hold circuit, comprising a first operational amplifier (U1), a diode (D2), a holding capacitor (C4), a reset switch (Q11), and a buffer amplifier (U2), wherein the buffer amplifier (U2) outputs a first output signal (OUT1). The first output signal (OUT1), the second output signal (OUT2), and the third output signal (OUT3) constitute the stage indication signal and are provided to the control circuit.