Digital isolator circuit with isolated tandem capacitance

Abstract

The invention discloses a digital isolator circuit with isolated tandem capacitors, which comprises a first integrated circuit region and a second integrated circuit region, and is characterized in that the first integrated circuit region is provided with a first transceiver circuit and a plurality of tandem high-voltage isolation capacitors; the second integrated circuit area is provided with a second transceiver circuit and a plurality of high-voltage isolation capacitors which are connected in series, and a metal wire is connected between the high-voltage isolation capacitors of the first integrated circuit area and the second integrated circuit area and is not in contact with the high-voltage isolation capacitors which are electrically coupled with the first transceiver circuit and the second transceiver circuit. The digital isolator circuit disclosed by the invention is provided with a plurality of serially connected isolation capacitors, so that the damage of hard force of metal wire bonding to a dielectric layer can be effectively reduced, the overall yield is improved, the voltage endurance capability of elements is ensured, and the digital isolator circuit has higher environmental tolerance to a packaging wire environment.

Description

Technical Field

[0001] This invention relates to a circuit architecture for a digital isolator, specifically a digital isolator circuit with multiple series-connected isolation capacitors that can effectively mitigate the damage to the dielectric layer caused by the hard force of metal wire bonding, improve overall yield, ensure withstand voltage capability, and have higher environmental tolerance to the packaging wire bonding environment. Background Technology

[0002] As is well known, many electronic circuit systems require the isolation of electrical signals from one part of the system to those from another. For example, in many control systems, both high-voltage and low-voltage signals are generated and monitored; therefore, providing appropriate isolation between these signals is essential to ensure the proper operation of the electronic circuit system. Currently, existing isolation circuits are known to be intermediary circuits that provide voltage isolation between two communication blocks, such as a transmitter circuit (TX) and a receiver circuit (RX). Such isolation circuits are generally used to eliminate unavoidable ground loops and protect high-voltage sensitive circuits. Using isolation circuits not only ensures electrical insulation and signal isolation between circuits but also establishes reliable data transmission between two dissimilar communication circuits, preventing signal interference from fast transient common-mode noise.

[0003] In practical applications, various existing devices and technologies have been proposed to transmit signals from one part of a system to another while maintaining isolation between the parts. Among these, digital isolators (DIS) circuits are commonly used to effectively provide communication and isolation functions. In actual operation, a DIS circuit first receives an input electrical signal from a first part of the system, converts the signal into a corresponding signal, and then passes it through an isolation barrier. After passing through the barrier, it is converted into an isolated output electrical signal, which is then received by a second part of the system. In this case, the electrical signal received by the second part of the system responds to the input electrical signal from the first part of the system.

[0004] However, it is worth noting that in existing digital isolator circuits, a metal wire bonding process is generally used between the first and second parts of the system. The rigidity generated by such metal wire bonding often damages the high-voltage capacitors in the isolator circuit, thereby affecting and degrading their voltage withstand capability. This is known to be a major challenge facing existing technologies. In view of this, the applicant of this invention believes that existing digital isolator architectures still have many shortcomings and defects as described above, and therefore lack widespread practicality and are insufficient for effective and widespread application in the industry.

[0005] Therefore, considering the numerous problems listed above, it is essential to adopt a multi-faceted approach. Consequently, the inventors of this invention, recognizing the potential for improvement in the aforementioned deficiencies and drawing upon years of experience in this field, have carefully observed and researched the subject, applying theoretical principles to propose a novel design that effectively addresses these deficiencies. This invention provides a novel digital isolator circuit architecture. This innovative digital isolator circuit architecture solves many long-standing deficiencies in existing technologies, maintains better voltage withstand capability of components, and provides high tolerance to wire bonding packaging environments. The specific architecture and implementation methods provided by this invention will be detailed below. Summary of the Invention

[0006] To address the problems existing in the prior art, one objective of this invention is to provide a novel and highly innovative digital isolator circuit. This circuit employs a digital isolator circuit with series-connected isolation capacitors. By connecting multiple high-voltage isolation capacitors in series within an isolation barrier, the metal wires are electrically coupled only to the high-voltage isolation capacitors of adjacent isolation barriers, without making contact with the high-voltage isolation capacitors electrically coupled to the transceiver circuit. This design architecture mitigates damage to the high-voltage isolation capacitors caused by the metal wires, maintaining the component's withstand voltage and reliability.

[0007] On the other hand, another objective of the present invention is to provide a novel digital isolator circuit with series-connected isolation capacitors. Based on the configuration of multiple series-connected high-voltage isolation capacitors in the digital isolator circuit, the damage to the high-voltage isolation capacitors caused by metal wire bonding can be effectively mitigated. Therefore, the overall packaging yield can be further improved, and it can also have higher environmental tolerance to the existing packaging wire bonding environment.

[0008] Furthermore, another objective of this invention is to provide a digital isolator circuit with an isolation series capacitor. This digital isolator circuit offers higher environmental tolerance to existing wire bonding environments. In other words, during wire bonding, less expensive metal wires, such as copper or silver wires, can be used, avoiding the use of expensive metal wires, such as gold wires. This significantly reduces the cost of wire bonding, providing a greater market advantage and competitiveness. The technical solutions disclosed in the following embodiments effectively demonstrate that the digital isolator circuit with an isolation series capacitor provided by this invention possesses high industrial competitiveness and can be widely applied in any related industrial technology.

[0009] In view of the numerous inventive objectives of the present invention provided above, these are aspects that cannot be achieved or applied by patents or papers that significantly improve upon existing technologies. Therefore, based on achieving the aforementioned inventive objectives, the present invention provides a digital isolator circuit with isolated series capacitors. In one embodiment of the present invention, the provided digital isolator circuit includes: a first integrated circuit region and a second integrated circuit region, wherein the first integrated circuit region has a first transceiver circuit and a first isolation barrier, the first isolation barrier including a plurality of first isolation capacitors, and the plurality of first isolation capacitors are connected in series.

[0010] The second integrated circuit region includes a second transceiver circuit and a second isolation barrier, wherein the second isolation barrier comprises a plurality of second isolation capacitors connected in series. According to an embodiment of the present invention, the plurality of first isolation capacitors in the first integrated circuit region and the plurality of second isolation capacitors in the second integrated circuit region are joined by a first metal wire bonding, wherein the first metal wire bonding is electrically coupled only between one of the first isolation capacitors and one of the second isolation capacitors, and does not contact another first isolation capacitor and another second isolation capacitor electrically coupled to the first transceiver circuit and the second transceiver.

[0011] The present invention provides a second embodiment in which the first isolation barrier optionally includes a plurality of third isolation capacitors, wherein the plurality of third isolation capacitors are connected in series and in parallel with the aforementioned plurality of first isolation capacitors. The plurality of first isolation capacitors are electrically coupled to the first transceiver circuit to provide a first data transmission channel, and the plurality of third isolation capacitors are electrically coupled to the first transceiver circuit to provide a second data transmission channel.

[0012] Similarly, according to a second embodiment of the present invention, the second isolation barrier may optionally further include a plurality of fourth isolation capacitors, which are connected in series and connected in parallel with the aforementioned second isolation capacitors, so that the plurality of second isolation capacitors are electrically coupled to the plurality of first isolation capacitors and the second transceiver circuit, thereby providing the first data transmission channel. The plurality of fourth isolation capacitors are electrically coupled to the plurality of third isolation capacitors and the second transceiver circuit, thereby providing the second data transmission channel.

[0013] In a second embodiment of the present invention, the plurality of first isolation capacitors and the plurality of second isolation capacitors are connected by a first metal wire bonding, and the plurality of third isolation capacitors and the plurality of fourth isolation capacitors are connected by a second metal wire bonding. The first metal wire bonding is only electrically coupled between one of the first isolation capacitors and one of the second isolation capacitors, and does not contact the other first isolation capacitor and the other second isolation capacitor that are electrically coupled to the first transceiver circuit and the second transceiver.

[0014] Furthermore, the second metal wire is only electrically coupled between one of the third isolation capacitors and one of the fourth isolation capacitors, and does not contact the other third isolation capacitor and the other fourth isolation capacitor that are electrically coupled to the first transceiver circuit and the second transceiver.

[0015] According to the first and second embodiments of the present invention, each of the first, second, third, and fourth isolation capacitors includes an upper metal plate, a lower metal plate, and a dielectric layer disposed between the upper and lower metal plates, forming two series-connected first, second, third, and fourth isolation capacitors. The lower metal plate of one isolation capacitor and the upper metal plate of the other isolation capacitor are electrically connected through an inner metal via.

[0016] Optionally, a first isolation capacitor and a third isolation capacitor connected in parallel with it in the first isolation barrier may be configured to share a metal electrode plate. A second isolation capacitor and a fourth isolation capacitor connected in parallel with it in the second isolation barrier may also be configured to share a metal electrode plate.

[0017] On the other hand, the digital isolator circuit provided by the present invention can provide bidirectional data signal transmission. For example, in a feasible embodiment, when the first transceiver circuit in the first integrated circuit area optionally responds to a data input signal to generate an isolated output signal, the second transceiver circuit in the second integrated circuit area optionally receives the isolated output signal to generate a data output signal.

[0018] In another embodiment, when the second transceiver circuit in the second integrated circuit area optionally responds to a data input signal to generate an isolated output signal, the first transceiver circuit in the first integrated circuit area optionally receives the isolated output signal to generate a data output signal.

[0019] Therefore, in summary, it can be confidently stated that the present invention provides a well-designed architecture for series-connected high-voltage isolation capacitors suitable for digital isolator circuits. This innovative design, which involves connecting multiple high-voltage isolation capacitors in series, effectively mitigates the damage to the dielectric layer of the high-voltage isolation capacitors caused by wire bonding. Since the withstand voltage capability of digital isolator circuit components depends on the dielectric layer of the high-voltage isolation capacitors, maintaining optimal withstand voltage capability naturally ensures that the components are protected from damage. Furthermore, it has been verified that the present invention successfully minimizes the hard interference from wire bonding, thereby ensuring withstand voltage capability and achieving higher overall yield. It also exhibits greater environmental tolerance to the wire bonding environment. Simultaneously, the digital isolator circuit provided by the present invention can maintain data signal transmission without interference. Therefore, it can be confidently stated that the digital isolator circuit with series-connected isolation capacitors disclosed in the present invention contributes to achieving excellent system robustness and accurate data transmission results. Compared with the prior art, the advantage of the present invention lies in its ability to provide good system-level control stability and maintain precise control over the isolation circuit.

[0020] The present invention will be further described in detail below through specific embodiments and accompanying drawings, so that the purpose, technical content, features and effects of the present invention can be more easily understood. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a digital isolator circuit with an isolation series capacitor according to a first embodiment of the present invention.

[0022] Figure 2 A schematic diagram of the structure of the first isolation barrier in the first embodiment of the present invention is disclosed.

[0023] Figure 3 The present invention is based on Figure 2 A schematic diagram of a further extended embodiment having multiple first isolation capacitors C11, C12, C13...C1N.

[0024] Figure 4 A schematic diagram of the structure of the second isolation barrier in the first embodiment of the present invention is disclosed.

[0025] Figure 5The present invention is based on Figure 4 A schematic diagram of a further extended embodiment having multiple second isolation capacitors C21, C22, C23...C2N.

[0026] Figure 6 This invention is disclosed Figure 1 The embodiment is a schematic diagram of a digital isolator circuit in which a signal is coupled from a first transceiver circuit to a second transceiver circuit.

[0027] Figure 7 This invention is disclosed Figure 1 The embodiment is a schematic diagram of a digital isolator circuit in which a signal is coupled from a second transceiver circuit to a first transceiver circuit.

[0028] Figure 8 This is a schematic diagram of a digital isolator circuit with an isolation series capacitor according to a second embodiment of the present invention, wherein the digital isolator circuit is electrically coupled to the first and second data transmission channels.

[0029] Figure 9 The present invention discloses a schematic diagram of a first isolation barrier comprising a plurality of first isolation capacitors connected in series and a plurality of third isolation capacitors connected in series in the second embodiment of the present invention.

[0030] Figure 10 The present invention discloses a schematic diagram of the structure of a second isolation barrier comprising a plurality of second isolation capacitors connected in series and a plurality of fourth isolation capacitors connected in series in the second embodiment of the present invention.

[0031] Figure 11 This invention is disclosed Figure 8 The embodiment is a schematic diagram of a digital isolator circuit in which a signal is coupled from a first transceiver circuit to a second transceiver circuit.

[0032] Figure 12 This invention is disclosed Figure 8 The embodiment is a schematic diagram of a digital isolator circuit in which a signal is coupled from a second transceiver circuit to a first transceiver circuit.

[0033] Explanation of reference numerals in the attached diagram: 100 - Digital isolator circuit with isolation series capacitor; 111 - First isolation barrier; 112 - Second isolation barrier; 200 - Digital isolator circuit with isolation series capacitor; 211 - First isolation barrier; 212 - Second isolation barrier; C11, C12, C13, C1N - First isolation capacitor; C21, C22, C23, C2N - Second isolation capacitor; C31, C32 - Third isolation capacitor; C41, C42 - Fourth isolation capacitor; M1 - First metal bonding wire; M2 - Second metal bonding wire; E1, E3, E5, F1, F3, F5, G1, G3, H1 H3 - Upper electrode plate; E2, E4, E6, F2, F4, F6, G2, G4, H2, H4 - Lower electrode plates; IMD1, IMD2, IMD3, IMDN, IMY1, IMY2, IMY3, IMYN, IMX1, IMX2, IMZ1, IMZ2 - Dielectric layers; P1, Q1, R1, S1 - Bonding pads; V1 - First metal conductive post; V2 - Second metal conductive post; V3 - Third metal conductive post; V4 - Fourth metal conductive post; DI - Data input signal; RO - Data output signal; CHIP1 - First integrated circuit area; CHIP2 - Second integrated circuit area; V ss1 - First grounding voltage; V ss2 - Second ground voltage; TR1 - First transceiver circuit; TR2 - Second transceiver circuit. Detailed Implementation

[0034] The foregoing description of the present invention, along with the following embodiments, are intended to demonstrate and explain the spirit and principles of the invention, and to provide a further explanation of the claims. Please refer in detail to the preferred embodiments of the invention, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals will be used in the drawings and description to refer to the same or similar elements. It should be understood that, for clarity and convenience, the invention may be enlarged in terms of shape and thickness in the drawings, and elements not specifically shown or described may take various forms known to those skilled in the art. Once disclosed in this disclosure, such alternatives and modifications will be apparent to those skilled in the art.

[0035] To illustrate the technical content and features of this invention and to enable those skilled in the art to understand, create, and use it, numerous embodiments are described below. However, it should be noted that these embodiments are not intended to limit the scope of this invention. Therefore, all equivalent modifications or variations made in accordance with the spirit of this invention should be included within the scope of protection of this invention.

[0036] Unless otherwise stated, certain conditional phrases or words, such as “may” or “possibly,” are generally used to express that embodiments of the invention “have,” but may also be interpreted as unnecessary features, elements, or steps. In other embodiments, these features, elements, or steps may not be required.

[0037] In the embodiments described in this specification, the reference to "one embodiment" or "in one embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, "one embodiment" or "in one embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment.

[0038] In the specific embodiments and claims of this invention, specific terms are used to refer to specific elements. Those skilled in the art should understand that the same element can have different names. This invention does not distinguish between elements with different names but the same function. In this specification and claims, "comprising" is used in an open-ended manner and should therefore be interpreted as "including but not limited to". "Coupled with" is intended to cover any indirect or direct connection. In other words, if this invention provides a first device coupled to a second device, it means that the first device can be connected to the second device directly or indirectly through other intermediate devices or connection methods via electrical connection, wireless communication, optical communication, or other signal connections, with or without signal connections.

[0039] The present invention is described in detail through the following embodiments, which are merely illustrative examples. Those skilled in the art can readily make appropriate modifications and variations to the apparatus and methods while retaining the teachings of the invention. Therefore, the following disclosure of the invention should be interpreted as being limited only by the scope of the appended claims. Throughout the specification and claims, except where explicitly described, the meanings of "a" and "the" include "a or at least one" of an element or component. Furthermore, throughout the specification and claims, the singular includes descriptions of multiple elements or components, except where the context clearly excludes multiples. Throughout the specification and claims, unless the meaning of certain words is explicitly defined, the word "wherein" includes "among" or "on top of". Generally, the meaning of each term used in the claims and specification of this invention refers to its common meaning known to those skilled in the art, unless otherwise noted. Some terms used to describe the invention and to guide those skilled in the art in understanding the invention may be discussed. Each illustrative example in this specification should not be used to limit the scope of protection of the invention.

[0040] The terms “basically,” “approximately,” “about,” and “probably” can refer to a value within 20% of a given value or range, preferably within 10%. Furthermore, the quantities or figures provided in this invention can be approximate values, and unless otherwise specified, can be described using the terms described above. When a quantity, density, or other parameter includes a specified range, preferred range, or listed ideal value, its value can be considered as any number within that given range.

[0041] Please refer to the illustrations of this invention first. Figure 1 As shown in the attached figure, this is a schematic diagram of a digital isolator circuit with an isolation series capacitor according to a first embodiment of the present invention. Figure 1 As shown, this digital isolator circuit 100 with isolation series capacitors includes a first integrated circuit (IC) CHIP1 and a second integrated circuit (IC) CHIP2. The first IC CHIP1 is electrically coupled to a first ground voltage V. ss1 The second integrated circuit region CHIP2 is electrically coupled to a second ground voltage V. ss2 .

[0042] The first integrated circuit area CHIP1 includes a first transceiver circuit (TX / RX) TR1 and a first isolation barrier 111. The first isolation barrier 111 includes a plurality of first isolation capacitors C11 and C12, which are high-voltage (HV) isolation capacitors, and the plurality of first isolation capacitors C11 and C12 are connected in series.

[0043] On the other hand, the second integrated circuit region CHIP2 has a second transceiver circuit TR2 and a second isolation barrier 112. The second isolation barrier 112 includes multiple second isolation capacitors C21 and C22, which are high-voltage isolation capacitors (HV isolation capacitors) and are connected in series. With this structural configuration, the first transceiver circuit TR1 in the first integrated circuit region CHIP1 and the second transceiver circuit TR2 in the second integrated circuit region CHIP2 are electrically coupled through the first isolation barrier 111 and the second isolation barrier 112 designed in this invention.

[0044] For example, the first isolation barrier 111 and / or the second isolation barrier 112 used in this invention may optionally be composed of at least one isolation capacitor or an equivalent element thereof. This invention is not limited thereto.

[0045] Specifically, according to the first embodiment of the present invention, the first isolation capacitor C11 in the first integrated circuit region CHIP1 and the second isolation capacitor C21 in the second integrated circuit region CHIP2 are connected by a first metal bonding wire M1, such as... Figure 1 As shown, the first metal bonding wire M1 is only electrically coupled between the first isolation capacitor C11 and the second isolation capacitor C21, and does not contact the other first isolation capacitor C12 which is electrically coupled to the first transceiver circuit TR1. Furthermore, the first metal bonding wire M1 does not contact the other second isolation capacitor C22 which is electrically coupled to the second transceiver TR2.

[0046] Please see Figure 2 As shown in the attached figure, the structure of the first isolation barrier 111 in the first embodiment of the present invention is schematically illustrated. Figure 2 As shown, the first isolation barrier 111 provided in the first embodiment is composed of a plurality of first isolation capacitors C11 and C12 connected in series. The first isolation capacitor C11 includes an upper electrode plate E1, a lower electrode plate E2, and a dielectric layer IMD1 disposed between the upper electrode plate E1 and the lower electrode plate E2. An open pad P1 is disposed on the upper electrode plate E1 to provide a first metal wire bonding M1 for wire bonding.

[0047] Similarly, the first isolation capacitor C12 includes an upper electrode plate E3, a lower electrode plate E4, and a dielectric layer IMD2 disposed between the upper electrode plate E3 and the lower electrode plate E4. In the two series-connected first isolation capacitors C11 and C12, the lower electrode plate E2 of the first isolation capacitor C11 and the upper electrode plate E3 of the first isolation capacitor C12 are electrically connected through a first metal via V1. With this structural configuration, since the first isolation barrier 111 is composed of multiple series-connected isolation capacitors, and both the upper and lower electrode plates are made of metal, the relatively soft nature of metal can mitigate the damage to the dielectric layer caused by the hard force generated by the first metal bonding wire M1. In other words, even if the hard force generated by the first metal bonding wire M1 affects the dielectric layer, its influence is limited to the dielectric layer IMD1 of the first isolation capacitor C11 and does not affect the underlying dielectric layer IMD2.

[0048] Furthermore, in another embodiment of the present invention, a greater number of first isolation capacitors may be connected in series in the first isolation barrier 111. Figure 3 The present invention is based on Figure 2 For further extended embodiments, please refer to, for example... Figure 3 As shown, the first isolation barrier 111 may optionally include a plurality of first isolation capacitors C11, C12, C13...C1N connected in series. In this embodiment, when metal wire bonding is performed, even if the hard force generated by the first metal wire M1 affects the dielectric layer, its influence is limited to the dielectric layer IMD1 of the uppermost first isolation capacitor C11, and does not affect the dielectric layers IMD2, IMD3...IMDN of the other first isolation capacitors C12, C13...C1N below. Therefore, according to the technical solution provided by the present invention, when applied to a digital isolator circuit, it can effectively ensure that the dielectric layer of the component is not damaged, and thus still has better withstand voltage capability.

[0049] Based on the same design principles, Figure 4 A schematic diagram of the structure of the second isolation barrier 112 in the first embodiment of the present invention is provided, as shown in the attached figure. Figure 4 As shown, the second isolation barrier 112 provided in the first embodiment is composed of a plurality of second isolation capacitors C21 and C22 connected in series. The second isolation capacitor C21 includes an upper electrode plate F1, a lower electrode plate F2, and a dielectric layer IMY1 disposed between the upper electrode plate F1 and the lower electrode plate F2. An open pad Q1 is disposed on the upper electrode plate F1 to provide a first metal wire bonding M1 for wire bonding.

[0050] The second isolation capacitor C22 includes an upper electrode plate F3, a lower electrode plate F4, and a dielectric layer IMY2 disposed between the upper electrode plate F3 and the lower electrode plate F4. In the two series-connected second isolation capacitors C21 and C22, the lower electrode plate F2 of the second isolation capacitor C21 and the upper electrode plate F3 of the second isolation capacitor C22 are electrically connected through a second inner metal via V2. With this structural configuration, since the second isolation barrier 112 is composed of multiple series-connected isolation capacitors, and both the upper and lower electrode plates are made of metal, the relatively flexible nature of metal can mitigate the damage to the dielectric layer caused by the hard force generated by the first metal bonding wire M1. In other words, even if the hard force generated by the first metal bonding wire M1 affects the dielectric layer, its impact is limited to the dielectric layer IMY1 of the second isolation capacitor C21 and does not affect the underlying dielectric layer IMY2.

[0051] Furthermore, in another embodiment of the present invention, a greater number of second isolation capacitors may be connected in series in the second isolation barrier 112, such as... Figure 5As shown, the second isolation barrier 112 can also be composed of multiple second isolation capacitors C21, C22, C23...C2N connected in series. In this embodiment, when metal wire bonding is performed, even if the hard force generated by the first metal wire bonding M1 affects the dielectric layer, its influence is limited to the dielectric layer IMY1 of the uppermost second isolation capacitor C21, and does not affect the dielectric layers IMY2, IMY3...IMYN of the other second isolation capacitors C22, C23...C2N below. Therefore, the technical solution provided by this invention, when applied to digital isolators, can effectively ensure that the dielectric layer of the component is not damaged, and thus still has good withstand voltage capability.

[0052] In addition, the digital isolator circuit with isolation series capacitor provided by the present invention can provide bidirectional data transmission, as illustrated in an exemplifiable example, such as... Figure 6 As shown, when the first transceiver circuit TR1 in the first integrated circuit area CHIP1 is adapted to receive and respond to a data input signal DI, and generates an isolated output signal through the first isolation barrier 111, the signal coupling through the second isolation barrier 112 enables the second transceiver circuit TR2 in the second integrated circuit area CHIP2 to receive the isolated output signal and generate a data output signal RO.

[0053] Alternatively, according to another illustrative example of the invention, then as follows Figure 7 As shown, when the second transceiver circuit TR2 in the second integrated circuit area CHIP2 is adapted to receive and respond to a data input signal DI, and generates an isolated output signal through the second isolation barrier 112, it can then be coupled through the signal of the first isolation barrier 111, thereby enabling the first transceiver circuit TR1 in the first integrated circuit area CHIP1 to receive the isolated output signal and generate a data output signal RO.

[0054] To take it a step further, please refer to... Figure 8The diagram illustrates a digital isolator circuit with series-connected isolation capacitors according to a second embodiment of the present invention. In this second embodiment, the digital isolator circuit 200 with series-connected isolation capacitors includes the aforementioned first transceiver circuit TR1, second transceiver circuit TR2, first isolation capacitors C11 and C12 connected in series, and second isolation capacitors C21 and C22 connected in series. Furthermore, the first isolation barrier 211 in this second embodiment further includes a plurality of third isolation capacitors C31 and C32 connected in series, and the plurality of third isolation capacitors C31 and C32 are connected in parallel with the aforementioned first isolation capacitors C11 and C12. According to the second embodiment of the present invention, the plurality of series-connected first isolation capacitors C11 and C12 are electrically coupled to the first transceiver circuit TR1, thereby providing a first data transmission channel. On the other hand, the plurality of series-connected third isolation capacitors C31 and C32 are electrically coupled to the first transceiver circuit TR1, thereby providing a second data transmission channel.

[0055] In this second embodiment, the second isolation barrier 212 includes not only the second isolation capacitors C21 and C22 from the first embodiment, but also a plurality of fourth isolation capacitors C41 and C42. These fourth isolation capacitors C41 and C42 are connected in series, and are also connected in parallel with the aforementioned second isolation capacitors C21 and C22. According to the second embodiment of the present invention, the plurality of series-connected second isolation capacitors C21 and C22 are electrically coupled between the second transceiver circuit TR2 and the first isolation capacitors C11 and C12, thereby providing the first data transmission channel. On the other hand, the plurality of series-connected fourth isolation capacitors C41 and C42 are electrically coupled between the second transceiver circuit TR2 and the third isolation capacitors C31 and C32, thereby providing the second data transmission channel.

[0056] Specifically, according to the second embodiment of the present invention, the first isolation capacitor C11 in the first integrated circuit region CHIP1 and the second isolation capacitor C21 in the second integrated circuit region CHIP2 are connected by a first metal bonding wire M1, and the third isolation capacitor C31 and the fourth isolation capacitor C41 are connected by a second metal bonding wire M2. Therefore, according to the technical solution provided by the present invention, as Figure 8 As shown, the first metal bonding wire M1 is only electrically coupled between the first isolation capacitor C11 and the second isolation capacitor C21, and does not contact the other first isolation capacitor C12 which is electrically coupled to the first transceiver circuit TR1. Furthermore, the first metal bonding wire M1 does not contact the other second isolation capacitor C22 which is electrically coupled to the second transceiver TR2.

[0057] Similarly, the second metal wire M2 is only electrically coupled between the third isolation capacitor C31 and the fourth isolation capacitor C41, and does not contact the other third isolation capacitor C32 electrically coupled to the first transceiver circuit TR1. Furthermore, the second metal wire M2 does not contact the other fourth isolation capacitor C42 electrically coupled to the second transceiver TR2. It is understood that when metal wire bonding is performed, even if the force generated by the second metal wire M2 affects the dielectric layer, its influence is limited to the dielectric layers of the third isolation capacitor C31 and the fourth isolation capacitor C41 connected to the second metal wire M2, without affecting the dielectric layers of other isolation capacitors. Therefore, it ensures that the remaining dielectric layers of the component are not damaged, and it can still maintain excellent withstand voltage capability.

[0058] For more details, please refer to the following documents. Figure 9 As shown in the attached figure, the structure of the first isolation barrier 211 in the second embodiment of the present invention is schematically illustrated. Figure 9 As shown, the first isolation barrier 211 provided in the second embodiment is composed of multiple first isolation capacitors C11 and C12 connected in series and multiple third isolation capacitors C31 and C32 connected in series. The first isolation capacitor C11 includes an upper electrode plate E1, a lower electrode plate E2, and a dielectric layer IMD1 disposed between the upper electrode plate E1 and the lower electrode plate E2. An open pad P1 is disposed on the upper electrode plate E1 to provide a first metal wire bond M1 for wire bonding. The third isolation capacitor C31 includes an upper electrode plate G1, a lower electrode plate G2, and a dielectric layer IMX1 disposed between the upper electrode plate G1 and the lower electrode plate G2. An open pad R1 is disposed on the upper electrode plate G1 to provide a second metal wire bond M2 for wire bonding.

[0059] The first isolation capacitor C12 includes an upper electrode plate E3, a lower electrode plate E4, and a dielectric layer IMD2 disposed between the upper electrode plate E3 and the lower electrode plate E4. The third isolation capacitor C32 includes an upper electrode plate G3, a lower electrode plate G4, and a dielectric layer IMX2 disposed between the upper electrode plate G3 and the lower electrode plate G4. In the two series-connected first isolation capacitors C11 and C12, the lower electrode plate E2 of the first isolation capacitor C11 and the upper electrode plate E3 of the first isolation capacitor C12 are electrically connected through a first metal via V1. In the two series-connected third isolation capacitors C31 and C32, the lower electrode plate G2 of the third isolation capacitor C31 and the upper electrode plate G3 of the third isolation capacitor C32 are electrically connected through a third metal via V3.

[0060] In this first isolation barrier 211, a first isolation capacitor C11 and a third isolation capacitor C31 connected in parallel therewith optionally share a metal electrode plate. A first isolation capacitor C12 and a third isolation capacitor C32 connected in parallel therewith optionally share a metal electrode plate.

[0061] Therefore, through this structural configuration, since the first isolation barrier 211 is composed of multiple series-connected first isolation capacitors C11 and C12 and multiple series-connected third isolation capacitors C31 and C32, and the upper and lower electrode plates are both made of metal, and since metal is relatively flexible, it can simultaneously mitigate the damage to the dielectric layer caused by the hard force generated by the first metal bonding wire M1 and the second metal bonding wire M2. In other words, even if the hard force generated by the first metal bonding wire M1 and the second metal bonding wire M2 affects the dielectric layer, its impact is limited to the dielectric layers IMD1 of the first isolation capacitor C11 and IMX1 of the third isolation capacitor C31 in contact with it, and will not affect the underlying dielectric layers IMD2 and IMX2.

[0062] Furthermore, according to another extended embodiment of the present invention, the first isolation barrier 211 in the second embodiment may also be further connected in series with a greater number of first isolation capacitors and a greater number of third isolation capacitors, as disclosed above. Figure 3 The disclosed embodiments further include multiple series-connected first isolation capacitors C11, C12, C13...C1N and multiple series-connected third isolation capacitors C31, C32... Therefore, when metal wire bonding is performed, even if the hard force generated by the first metal wire M1 and the second metal wire M2 affects the dielectric layer, the range of influence is limited to the dielectric layer IMD1 of the topmost first isolation capacitor C11 and the dielectric layer IMX1 of the third isolation capacitor C31, and will not affect the dielectric layers IMD2, IMD3...IMDN of the other first isolation capacitors C12, C13...C1N and the dielectric layers IMX2... of the other third isolation capacitors C32..., etc., so that the inventive effects of the present invention can still be implemented.

[0063] Similarly, please refer to Figure 10 As shown in the attached figure, a structural schematic diagram of the second isolation barrier 212 in the second embodiment of the present invention is provided. Figure 10As shown, the second isolation barrier 212 provided in the second embodiment includes a plurality of second isolation capacitors C21 and C22 connected in series with the first data transmission channel, and a plurality of fourth isolation capacitors C41 and C42 connected in series with the second data transmission channel. The second isolation capacitor C21 includes an upper electrode plate F1, a lower electrode plate F2, and a dielectric layer IMY1 disposed between the upper electrode plate F1 and the lower electrode plate F2. An open pad Q1 is disposed on the upper electrode plate F1 to provide a first metal wire bond M1 for wire bonding. The fourth isolation capacitor C41 includes an upper electrode plate H1, a lower electrode plate H2, and a dielectric layer IMZ1 disposed between the upper electrode plate H1 and the lower electrode plate H2. An open pad S1 is disposed on the upper electrode plate H1 to provide a second metal wire bond M2 for wire bonding.

[0064] On the other hand, the second isolation capacitor C22 includes an upper electrode plate F3, a lower electrode plate F4, and a dielectric layer IMY2 disposed between the upper electrode plate F3 and the lower electrode plate F4. The fourth isolation capacitor C42 includes an upper electrode plate H3, a lower electrode plate H4, and a dielectric layer IMZ2 disposed between the upper electrode plate H3 and the lower electrode plate H4. In the two series-connected second isolation capacitors C21 and C22, the lower electrode plate F2 of the second isolation capacitor C21 and the upper electrode plate F3 of the second isolation capacitor C22 are electrically connected through a second metal conductive post V2. In the two series-connected fourth isolation capacitors C41 and C42, the lower electrode plate H2 of the fourth isolation capacitor C41 and the upper electrode plate H3 of the fourth isolation capacitor C42 are electrically connected through a fourth metal conductive post V4.

[0065] In this second isolation barrier 212, a second isolation capacitor C21 and a fourth isolation capacitor C41 connected in parallel therewith optionally share a metal electrode plate. A second isolation capacitor C22 and a fourth isolation capacitor C42 connected in parallel therewith optionally share a metal electrode plate.

[0066] With this structural configuration, the second isolation barrier 112 is composed of multiple series-connected second isolation capacitors C21 and C22 and multiple series-connected fourth isolation capacitors C41 and C42. Furthermore, both the upper and lower electrode plates are made of metal. Since metal is relatively flexible, it can simultaneously mitigate the damage to the dielectric layer caused by the hard force generated by the first metal bonding wire M1 and the second metal bonding wire M2. In other words, even if the hard force generated by the first metal bonding wire M1 and the second metal bonding wire M2 affects the dielectric layer, its impact is limited to the dielectric layers IMY1 of the connected second isolation capacitor C21 and IMZ1 of the connected fourth isolation capacitor C41, and does not affect the underlying dielectric layers IMY2 and IMZ2.

[0067] Similarly, according to the extended embodiment of the present invention, the second isolation barrier 212 in the second embodiment may also be further connected in series with a greater number of second isolation capacitors and a greater number of fourth isolation capacitors, as disclosed above. Figure 5 The disclosed embodiments further include multiple series-connected second isolation capacitors C21, C22, C23...C2N and multiple series-connected fourth isolation capacitors C41, C42...etc. Therefore, when metal wire bonding is performed, even if the hard force generated by the first metal wire M1 and the second metal wire M2 affects the dielectric layer, the range of influence is limited to the dielectric layer IMY1 of the uppermost second isolation capacitor C21 and the dielectric layer IMZ1 of the fourth isolation capacitor C41, and will not affect the dielectric layers IMY2, IMY3...IMYN of the other second isolation capacitors C22, C23...C2N and the dielectric layers IMZ2...etc. of the other fourth isolation capacitors C42...etc., so that the inventive effects of the present invention can also be implemented.

[0068] Specifically, in summary, the digital isolator circuit with isolation series capacitor provided according to the second embodiment of the present invention can similarly provide bidirectional data transmission. In an exemplifiable example, such as... Figure 11 As shown, when the first transceiver circuit TR1 in the first integrated circuit area CHIP1 provided in the second embodiment of the present invention is adapted to receive and respond to a data input signal DI, and generates an isolated output signal through the first isolation barrier 211, it can then be coupled through the signal of the second isolation barrier 212, thereby enabling the second transceiver circuit TR2 in the second integrated circuit area CHIP2 to receive the isolated output signal and generate a data output signal RO.

[0069] Alternatively, according to another illustrative example of the invention, then as follows Figure 12As shown, when the second transceiver circuit TR2 in the second integrated circuit area CHIP2 provided in the second embodiment of the present invention is adapted to receive and respond to a data input signal DI, and generates an isolated output signal through the second isolation barrier 212, it can then be coupled through the signal of the first isolation barrier 211, thereby enabling the first transceiver circuit TR1 in the first integrated circuit area CHIP1 to receive the isolated output signal and generate a data output signal RO. Therefore, as shown in the accompanying drawings of the present invention... Figure 8 , Figure 9 , Figure 10 Please refer to the disclosed digital isolator circuit with first and second data transmission channels. Figures 11-12 As shown, it can also provide bidirectional data transmission functionality.

[0070] Therefore, in summary, it can be confidently stated that, through the technical solution provided by this invention, the present invention can effectively mitigate the impact of the hard force generated by metal wire bonding in the prior art on components, thereby maintaining the withstand voltage capability of the digital isolator circuit. Furthermore, since the hard force interference from metal wire bonding can be effectively mitigated, when applying the digital isolator circuit provided by this invention, it has higher environmental tolerance to existing packaging wire bonding environments. In other words, when performing packaging wire bonding, relatively inexpensive materials such as copper or silver wire can be used for metal wire bonding, avoiding the use of expensive metal wires such as gold wire, significantly reducing the cost of metal wire bonding for the product and providing a better market advantage and competitiveness.

[0071] The present invention has been described in detail in the above-described embodiments and related paragraphs, and its feasibility and the inventive effects it can achieve have been well verified. In summary, those skilled in the art can make modifications or variations according to the specifications and requirements of their actual circuits without departing from the spirit and intent of the invention; however, even with equivalent modifications, these modifications should still fall within the scope of the invention. In other words, the present invention is not limited to the above-described embodiments.

[0072] Therefore, based on at least one embodiment disclosed in the present invention, it can be confirmed that the digital isolator circuit provided by the present invention is novel and unprecedented. It aims to provide an innovative digital isolator circuit with an isolation series capacitor. By applying this innovative isolation series capacitor to the digital isolator circuit, in addition to achieving the above-mentioned inventive effects, it can also ensure the accuracy of data transmission and successfully maintain the robustness of the system output voltage while reducing signal jitter interference.

[0073] Therefore, in view of the above, compared with the prior art, it is obvious that the embodiments and circuit architecture disclosed in this invention can effectively solve many shortcomings of the prior art and present more efficient circuit performance. Furthermore, the technical solution provided by this invention can be applied not only to common electronic components, but also widely to various electronic circuit components in the semiconductor industry, integrated circuit industry, or power electronics. Clearly, the technical solution claimed herein has excellent industrial applicability and competitiveness. At the same time, this invention also verifies through various experimental and empirical data that the technical features, methods, and effects achieved by this invention are significantly different from existing solutions, and cannot be easily accomplished by those skilled in the art.

[0074] The embodiments described above are merely illustrative of the technical ideas and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should still be covered within the protection scope of the present invention.

Claims

1. A digital isolator circuit with an isolation series capacitor, characterized in that, include: A first integrated circuit region, comprising a first transceiver circuit and a first isolation barrier, wherein the first isolation barrier includes a plurality of first isolation capacitors connected in series; and A second integrated circuit region having a second transceiver circuit and a second isolation barrier, wherein the second isolation barrier includes a plurality of second isolation capacitors connected in series; The plurality of first isolation capacitors in the first integrated circuit area and the plurality of second isolation capacitors in the second integrated circuit area are connected by a first metal wire bonding. The first metal wire bonding is only electrically coupled between one of the first isolation capacitors and one of the second isolation capacitors, and does not contact the other first isolation capacitor and the other second isolation capacitor that are electrically coupled to the first transceiver circuit and the second transceiver.

2. The digital isolator circuit with isolation series capacitor as described in claim 1, characterized in that, The first transceiver circuit in the first integrated circuit area may optionally respond to a data input signal to generate an isolated output signal.

3. The digital isolator circuit with isolation series capacitor as described in claim 2, characterized in that, The second transceiver circuit in the second integrated circuit area may optionally receive the isolated output signal to generate a data output signal.

4. The digital isolator circuit with isolation series capacitor as described in claim 1, characterized in that, The second transceiver circuit in the second integrated circuit area may optionally respond to a data input signal to generate an isolated output signal.

5. The digital isolator circuit with an isolation series capacitor as described in claim 4, characterized in that, The first transceiver circuit in the first integrated circuit area may optionally receive the isolated output signal to generate a data output signal.

6. The digital isolator circuit with an isolation series capacitor as described in claim 1, characterized in that, The first isolation barrier also includes a plurality of third isolation capacitors, which are connected in series and in parallel with the plurality of first isolation capacitors. The plurality of third isolation capacitors are electrically coupled to the first transceiver circuit, thereby providing another data transmission channel.

7. The digital isolator circuit with an isolation series capacitor as described in claim 6, characterized in that, The second isolation barrier also includes a plurality of fourth isolation capacitors, which are connected in series, connected in parallel with the plurality of second isolation capacitors, and electrically coupled to the plurality of third isolation capacitors and the second transceiver circuit, thereby providing the other data transmission channel.

8. The digital isolator circuit with an isolation series capacitor as described in claim 7, characterized in that, The third isolation capacitor and the fourth isolation capacitor are connected by a second metal wire. The second metal wire is only electrically coupled between the third isolation capacitor and the fourth isolation capacitor, and does not contact the other third isolation capacitor and the other fourth isolation capacitor that are electrically coupled to the first transceiver circuit and the second transceiver.

9. The digital isolator circuit with an isolation series capacitor as described in claim 1, characterized in that, Each of the first isolation capacitors includes an upper electrode plate, a lower electrode plate, and a dielectric layer disposed between the upper electrode plate and the lower electrode plate. In the two series-connected first isolation capacitors, the lower electrode plate of one first isolation capacitor and the upper electrode plate of the other first isolation capacitor are electrically connected through a first metal conductive post.

10. The digital isolator circuit with an isolation series capacitor as described in claim 1, characterized in that, Each of the second isolation capacitors includes an upper electrode plate, a lower electrode plate, and a dielectric layer disposed between the upper electrode plate and the lower electrode plate. In the two second isolation capacitors connected in series, the lower electrode plate of one second isolation capacitor and the upper electrode plate of the other second isolation capacitor are electrically connected through a second metal conductive post.

11. The digital isolator circuit with an isolation series capacitor as described in claim 8, characterized in that, Each of the third isolation capacitors includes an upper electrode plate, a lower electrode plate, and a dielectric layer disposed between the upper electrode plate and the lower electrode plate. In the two third isolation capacitors connected in series, the lower electrode plate of one third isolation capacitor and the upper electrode plate of the other third isolation capacitor are electrically connected through a third metal conductive post.

12. The digital isolator circuit with an isolation series capacitor as described in claim 8, characterized in that, Each of the fourth isolation capacitors includes an upper electrode plate, a lower electrode plate, and a dielectric layer disposed between the upper electrode plate and the lower electrode plate. In the two fourth isolation capacitors connected in series, the lower electrode plate of one fourth isolation capacitor and the upper electrode plate of the other fourth isolation capacitor are electrically connected through a fourth metal conductive post.

13. The digital isolator circuit with an isolation series capacitor as described in claim 8, characterized in that, The first isolation capacitor in the first isolation barrier and the third isolation capacitor connected in parallel therewith may optionally share a metal electrode plate.

14. The digital isolator circuit with an isolation series capacitor as described in claim 8, characterized in that, The second isolation capacitor in the second isolation barrier and the fourth isolation capacitor connected in parallel therewith may optionally share a metal electrode plate.

15. A digital isolator circuit with an isolation series capacitor, characterized in that, include: A first integrated circuit region, wherein a first transceiver circuit and a first isolation barrier are included; as well as A second integrated circuit region, wherein a second transceiver circuit and a second isolation barrier are included; The first isolation barrier includes a plurality of first isolation capacitors and a plurality of third isolation capacitors. The plurality of first isolation capacitors are connected in series, the plurality of third isolation capacitors are connected in series, the plurality of third isolation capacitors are connected in parallel with the plurality of first isolation capacitors, the plurality of first isolation capacitors are electrically coupled to the first transceiver circuit to provide a first data transmission channel, and the plurality of third isolation capacitors are electrically coupled to the first transceiver circuit to provide a second data transmission channel. The second isolation barrier includes a plurality of second isolation capacitors and a plurality of fourth isolation capacitors. The plurality of second isolation capacitors are connected in series, the plurality of fourth isolation capacitors are connected in series, the plurality of fourth isolation capacitors are connected in parallel with the plurality of second isolation capacitors, the plurality of second isolation capacitors are electrically coupled to the plurality of first isolation capacitors and the second transceiver circuit, thereby providing the first data transmission channel, and the plurality of fourth isolation capacitors are electrically coupled to the plurality of third isolation capacitors and the second transceiver circuit, thereby providing the second data transmission channel. The plurality of first isolation capacitors and the plurality of second isolation capacitors are connected by a first metal wire, and the plurality of third isolation capacitors and the plurality of fourth isolation capacitors are connected by a second metal wire. The first metal wire is electrically coupled only between one of the first isolation capacitors and one of the second isolation capacitors, and does not contact the other first isolation capacitor and the other second isolation capacitor that are electrically coupled to the first transceiver circuit and the second transceiver. The second metal wire is electrically coupled only between one of the third isolation capacitors and one of the fourth isolation capacitors, and does not contact the other third isolation capacitor and the other fourth isolation capacitor that are electrically coupled to the first transceiver circuit and the second transceiver.

16. The digital isolator circuit with an isolation series capacitor as described in claim 15, characterized in that, The first isolation capacitor in the first isolation barrier and the third isolation capacitor connected in parallel therewith may optionally share a metal electrode plate.

17. The digital isolator circuit with an isolation series capacitor as described in claim 15, characterized in that, The second isolation capacitor in the second isolation barrier and the fourth isolation capacitor connected in parallel therewith may optionally share a metal electrode plate.

18. The digital isolator circuit with an isolation series capacitor as described in claim 15, characterized in that, The first transceiver circuit in the first integrated circuit area can optionally respond to a data input signal to generate an isolated output signal, and the second transceiver circuit in the second integrated circuit area can optionally receive the isolated output signal to generate a data output signal.

19. The digital isolator circuit with an isolation series capacitor as described in claim 15, characterized in that, The second transceiver circuit in the second integrated circuit area can optionally respond to a data input signal to generate an isolated output signal, so that the first transceiver circuit in the first integrated circuit area can optionally receive the isolated output signal to generate a data output signal.

20. The digital isolator circuit with an isolation series capacitor as described in claim 15, characterized in that, Each of the first, second, third, and fourth isolation capacitors includes an upper electrode plate, a lower electrode plate, and a dielectric layer disposed between the upper and lower electrode plates. In two series-connected first isolation capacitors, the lower electrode plate of one first isolation capacitor is electrically connected to the upper electrode plate of the other first isolation capacitor through a first metal conductive post. In two series-connected second isolation capacitors, the lower electrode plate of one second isolation capacitor is electrically connected to the upper electrode plate of the other second isolation capacitor through a second metal conductive post. In two series-connected third isolation capacitors, the lower electrode plate of one third isolation capacitor is electrically connected to the upper electrode plate of the other third isolation capacitor through a third metal conductive post. In two series-connected fourth isolation capacitors, the lower electrode plate of one fourth isolation capacitor is electrically connected to the upper electrode plate of the other fourth isolation capacitor through a fourth metal conductive post.

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