Cell programming of digital-to-analog converters

Abstract

An electronic device may include a digital-to-analog converter that includes programmable features in corresponding unit cells of the digital-to-analog converter. Programming data may be written into appropriate unit cells using addresses and strobe signals. If desired, a read flag and a read data path may be provided to read data from an appropriate unit cell. The digital-to-analog converter may include address decoding circuitry at each unit cell and / or address decoding circuitry shared among a plurality of unit cells.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 897,739, filed September 26, 2024, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates generally to electronic devices, such as electronic devices having digital-to-analog converters. BACKGROUND

[0003] Electronic devices often have wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless communication circuitry. The wireless communication circuitry can include a digital-to-analog converter. It can be desirable to program the digital-to-analog converter to operate in an appropriate manner when converting digital data to analog voltages. Facilitating programming of the digital-to-analog converter can be challenging, especially when a large number of fine-grained features are to be programmed in the digital-to-analog converter. SUMMARY

[0004] An electronic device can include a digital-to-analog converter that includes programmable features (such as configurable circuits) in corresponding unit cells of the digital-to-analog converter. Programming data that is to be conveyed on a write data path can be written into the appropriate unit cells using address and strobe signals. If desired, a read flag and a data read path can be provided to read data from the appropriate unit cells. The digital-to-analog converter can include (address) decoding circuitry at each unit cell and / or (address) decoding circuitry that is shared among multiple unit cells.

[0005] An aspect of the present disclosure provides a wireless communication circuit. The wireless communication circuit can include a digital-to-analog converter having a plurality of unit cells, a programming circuit configured to program the plurality of unit cells, and a plurality of data paths coupled to the programming circuit and the digital-to-analog converter and including an address data path. The programming circuit can be configured to convey address bits to the digital-to-analog converter through the address data path, the address bits collectively forming an address that identifies a given unit cell of the plurality of unit cells.

[0006] One aspect of this disclosure provides a digital-to-analog converter (DAC). The DAC may include a plurality of unit cells. A given unit cell may have a programmable feature and storage circuitry configured to store programming data for the programmable feature. The DAC may include: a plurality of address data paths coupled to the plurality of unit cells and configured to transmit an address of the given unit cell; a strobe signal path coupled to the plurality of unit cells and configured to transmit a strobe signal; and a write data path coupled to the plurality of unit cells and configured to provide the programming data to the storage circuitry based on the address and the strobe signal.

[0007] One aspect of this disclosure provides a digital-to-analog converter (DAC). The DAC may include: a plurality of unit cells, each unit cell having configurable circuitry; an input terminal coupled to the plurality of unit cells and configured to receive digital data; an output terminal coupled to the plurality of unit cells and configured to use the plurality of unit cells to provide an analog voltage corresponding to the digital data; and a plurality of programming input terminals coupled to the plurality of unit cells and configured to receive an address and programming data, the programming data being used to control the configurable circuitry of the unit cell identified by the address among the plurality of unit cells. Attached Figure Description

[0008] Figure 1 This is a diagram of an exemplary electronic device with wireless communication circuitry according to some implementation schemes.

[0009] Figure 2 This is a diagram illustrating an exemplary wireless communication circuit based on some implementation schemes.

[0010] Figure 3 This is a diagram illustrating an exemplary digital-to-analog converter circuit based on some implementation schemes.

[0011] Figure 4 This is a diagram of an exemplary programming circuit for a digital-to-analog converter according to some implementation schemes.

[0012] Figure 5 This is a diagram of a local address decoding circuit that is communicatively coupled to a unit cell of a digital-to-analog converter programming circuit according to some implementation schemes.

[0013] Figure 6 This is a diagram of an exemplary digital-to-analog converter unit that includes local address decoding circuitry, according to some implementation schemes.

[0014] Figure 7 This is a diagram illustrating an exemplary digital-to-analog converter unit that is communicatively coupled to a shared address decoding circuit according to some implementation schemes.

[0015] Figure 8 This is a diagram illustrating an exemplary shared address decoding circuit at the bifurcation between units according to some implementation schemes.

[0016] Figure 9 This is a flowchart illustrating exemplary operations for performing shared and local address decoding for a digital-to-analog converter, according to some implementation schemes. Detailed Implementation

[0017] Electronic devices may include one or more digital-to-analog converters (DACs). In the exemplary configurations sometimes described herein as examples, one or more DACs may be provided as part of wireless communication circuitry (e.g., formed as part of transmitter circuitry, interfacing between digital baseband circuitry and analog radio frequency circuitry). To facilitate desired conversion operations, the DAC may include features to be programmed in each unit cell. Given a large number of units to be programmed and corresponding features, routing the same large number of lines to each unit cell to provide programming data for the features in each unit cell can be challenging.

[0018] To better facilitate programming of these unit cells (e.g., features therein), the DAC programming circuitry can transmit programming data along with the corresponding address and strobe signal to the DAC. If needed, the DAC can also provide a read flag and a corresponding read path (for reading data from the unit cell). The transmitted information (including programming data, address, strobe signal, and read flag) can be processed by the DAC to write programming data to the appropriate cell of the appropriate feature (e.g., as indicated by the address) during a write operation, and / or read the corresponding data from the appropriate cell (e.g., as indicated by the address) during a read operation. The DAC may include local address decoding circuitry at each unit cell and / or shared address decoding circuitry at bifurcation points between multiple cells (e.g., branching into the multiple cells). Figure 1 The illustration shows an exemplary electronic device in which a DAC circuit (e.g., a DAC and programming circuit configured in the exemplary manner described above) may be employed.

[0019] Figure 1This is an illustration of an exemplary electronic device (such as electronic device 10). Electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a wristband device, a headset or handset device, a device embedded in glasses or other equipment worn on a user's head, or other wearable or micro-devices; a television set, a computer monitor without an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in an information kiosk or a car), a voice-controlled speaker connected to the wireless Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that enables the functions of two or more of these devices; or other electronic equipment.

[0020] like Figure 1 As illustrated in the schematic diagram, device 10 may include components located on or within an electronic device housing (such as housing 12). Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations thereof. In some cases, part or all of housing 12 may be formed of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, housing 12 or at least some of the structures constituting housing 12 may be formed of metallic elements.

[0021] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage device circuitry 16. Storage device circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage device circuitry 16 may include storage devices integrated within device 10, and / or removable storage media.

[0022] Control circuitry 14 may include processing circuitry such as processing circuitry 18 (e.g., one or more processors 18). Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application processors, application-specific integrated circuits, central processing units (CPUs), general-purpose processors, or other types of processors. Control circuitry 14 may be configured to perform operations within device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations within device 10 may be stored on storage device circuitry 16 (e.g., storage device circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage device circuitry 16 may be executed by processing circuitry 18.

[0023] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include: Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as...). Protocols for other short-range wireless communication links, such as This protocol may be any of the following: wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G New Radio (NR) protocols, etc.), MIMO protocols, antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols for signals transmitted at millimeter and centimeter wave frequencies, or other desired distance detection protocols), or any other desired communication protocol. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0024] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays, light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice, electronic pens (e.g., styluses), joysticks, and other input-output devices can be coupled to device 10 using wired or wireless connections (e.g., some input-output devices in input-output devices 22 may be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0025] The input-output circuit 20 may include wireless communication circuitry for wirelessly transmitting radio frequency signals, such as wireless communication circuitry 24 (sometimes referred to herein as wireless circuitry 24). Figure 2 This is a diagram showing exemplary components within wireless circuit 24. For example... Figure 2 As shown, wireless circuitry 24 may include one or more processors (such as processor 26), radio frequency (RF) transceiver circuitry (such as RF transceiver circuitry 28), RF front-end circuitry (such as RF front-end circuitry 40) (which may be referred to as front-end module 40 when integrated), and one or more antennas (such as antenna 42). Processor 26 may be a baseband processor, application processor, general-purpose processor, microprocessor, microcontroller, digital signal processor, host processor, or other type of processor. If desired, processor 26 may be implemented as part of control circuitry 14. Processor 26 may be communicatively coupled to transceiver circuitry 28 via path 34. Transceiver circuitry 28 may be communicatively coupled to antenna 42 via RF transmission line path 36. RF front-end circuitry 40 may be disposed along (e.g., disposed thereon) the RF transmission line path 36 between transceiver circuitry 28 and antenna 42.

[0026] exist Figure 2In the example, for clarity, wireless circuit 24 is illustrated as including a single processor 26, a single instance of transceiver circuitry 28, a single instance of front-end circuitry 40, and a single set of antennas 42. Generally, wireless circuit 24 may include any number of processors 26, any number of instances of transceiver circuitry 28, any number of instances of front-end circuitry 40, and any number of antennas 42. Each processor 26 may be communicatively coupled to one or more transceivers (e.g., instances of transceiver circuitry 28) via a corresponding path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be communicatively coupled to one or more antennas 42 via a corresponding RF transmission line path 36. Each RF transmission line path 36 may have a corresponding front-end circuitry 40 disposed thereon. If desired, two or more instances of front-end circuitry 40 (e.g., different types of front-end circuitry) may be disposed on the same RF transmission line path 36. If necessary, one or more of the radio frequency transmission line paths 36 in the radio frequency transmission line path 24 can be implemented without any front-end circuitry 40.

[0027] Antenna 42 can be formed using any desired antenna structure. For example, each antenna 42 can be an antenna with an antenna resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole antenna, a combination of these designs, etc. Two or more antennas 42 can be arranged into one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements can be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 can be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0028] Each RF transmit line path 36 may be communicatively coupled to an antenna feed section on the antenna 42. The antenna feed section may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmit line path 36 may have a positive transmit line signal path communicatively coupled to a positive antenna feed terminal on the antenna 42. The RF transmit line path 36 may have a ground transmit line signal path communicatively coupled to a ground antenna feed terminal on the antenna 42. This example is merely illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feed sections communicatively coupled to one or more RF transmit line paths 36.

[0029] RF transmission path 36 may include a means for communication with device 10 (Figure 1 The RF transmission path 36 is a transmission line that routes the radio frequency signals within the circuit. These transmission lines may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, and combinations of these types of transmission lines. If desired, the transmission lines in RF transmission path 36 may be integrated into a rigid printed circuit board and / or a flexible printed circuit substrate.

[0030] When transmitting wireless signals, processor 26 can provide a transmit signal (e.g., a digital or baseband signal) to transceiver circuit 28 via path 34. Transceiver circuit 28 may also include circuitry for converting the transmit (baseband) signal received from processor 26 into a corresponding radio frequency (RF) signal. For example, transceiver circuit 28 may include mixer circuitry for up-converting (or modulating) the transmit (baseband) signal to RF before transmission via antenna 42. The processor 26 communicates with transceiver circuit 28. Figure 2 The examples provided are merely illustrative. Generally, transceiver circuitry 28 can communicate with a baseband processor, application processor, general-purpose processor, microcontroller, microprocessor, or one or more processors within circuitry 18 (e.g., implementing the functionality of processor 26). Transceiver circuitry 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver circuitry 28 can transmit radio frequency (RF) signals via transmitter (TX) 30 through RF transmission line path 36 and front-end circuitry 40 via antenna 42. Antenna 42 can transmit RF signals to external wireless equipment by radiating the RF signals into free space.

[0031] During wireless reception, antenna 42 can receive radio frequency (RF) signals from external wireless equipment. The received RF signals can be transmitted to transceiver circuitry 28 via RF transmission path 36 and front-end circuitry 40. Transceiver circuitry 28 may include circuitry (such as receiver (RX) 32) for receiving signals from front-end circuitry 40 and for converting the received RF signals into corresponding baseband signals. For example, transceiver circuitry 28 may include mixer circuitry for down-converting (or demodulating) the received RF signals to baseband frequencies before transmitting the received signals via path 34 to processor 26 (or control circuitry 18 that implements the functions of processor 26).

[0032] The RF front-end circuitry 40 operates on RF signals transmitted (transmitted and / or received) via RF transmission line path 36. The front-end circuitry 40 may include, for example, front-end module (FEM) components such as RF filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexing circuitry, duplexer circuitry, dual-signal circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more RF switches), RF amplifier circuitry 48 (e.g., one or more power amplifier circuitry and / or one or more low-noise amplifier circuitry), impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 to the impedance of RF transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), RF coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on RF signals transmitted and / or received by antenna 42. Each of the front-end module components may be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If needed, various front-end module components can also be integrated into a single integrated circuit chip.

[0033] Filter circuit 44, switching circuit 46, amplifier circuit 48, and other circuits may be disposed along (e.g., disposed thereon) the RF transmission line path 36, may be incorporated into the front-end module, and / or may be incorporated into the antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). At least some of these components may form an antenna tuning component (e.g., using control circuit 14) to adjust the frequency response and wireless performance of the antenna 42 over time.

[0034] Although for clarity, in Figure 1 In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18, and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, portions of transceiver circuitry 28 (e.g., a host processor on transceiver circuitry 28) and / or processor 26 may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on processor 26, portions of control circuitry 14 formed on transceiver circuitry 28, and / or portions of control circuitry 14 separate from wireless circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) for the operation of front-end circuitry 40.

[0035] The transceiver circuit 28 can be separate from the front-end circuit 40. For example, the transceiver circuit 28 can be formed on a different substrate (such as the main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit) than the substrate on which the front-end circuit 40 is disposed.

[0036] The radio frequency transceiver circuit 28 (and other parts of the wireless circuit 24, such as the front-end circuit 40) can handle the transmission and / or reception of radio frequency signals in various radio frequency communication bands. For example, the radio frequency transceiver circuit 28 (and other parts of the wireless circuit 24, such as the front-end circuit 40) can handle radio frequency signals in wireless local area network (WLAN) communication bands, such as 2.4 GHz and 5 GHz. (IEEE 802.11) bands, Wireless Personal Area Network (WPAN) communication bands such as 2.4 GHz Communication frequency bands, cellular telephone communication frequency bands such as the cellular low frequency band (LB) (e.g., 600MHz to 960MHz), the cellular low intermediate frequency band (LMB) (e.g., 1400MHz to 1550MHz), the cellular intermediate frequency band (MB) (e.g., 1700MHz to 2200MHz), the cellular high frequency band (HB) (e.g., 2300MHz to 2700MHz), the cellular ultra-high frequency band (UHB) (e.g., 3300MHz to 5000MHz), or other cellular communication frequency bands between approximately 600MHz and approximately 5000MHz (e.g., 3G bands, 4G bands). LTE bands, 5G New Radio Frequency Range 1 (FR1) bands below 10 GHz, 5G New Radio Frequency Range 2 (FR2) bands with millimeter and centimeter wavelengths between 20 GHz and 60 GHz, etc., near field communication (NFC) bands (e.g., 13.56 MHz), satellite navigation bands (e.g., L1 Global Positioning System (GPS) band at 1575 MHz, L5 GPS band at 1176 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.), UWB communication bands supported by the IEEE 802.15.4 protocol and / or other ultra-wideband (UWB) communication protocols (e.g., a first UWB communication band at 6.5 GHz and / or a second UWB communication band at 8.0 GHz) and / or any other desired communication bands. The communication band processed (e.g., covered) by the radio frequency transceiver circuit 28 (and other parts of the wireless circuit 24, such as the front-end circuit 40) may be referred to herein as a frequency band or simply "band" and may span the corresponding frequency range.

[0037] Electronic devices 10 ( Figure 1The electronic device 10 may include a first circuit operating in the digital domain and a second circuit operating in the analog domain. To interface between the first and second circuits, or more specifically, to perform operations in the analog domain based on operations in the digital domain, the electronic device 10 may include one or more digital-to-analog converters (DACs). Figure 3 The diagram illustrates an exemplary DAC circuit including DAC 50. Specifically, DAC 50 may include an input terminal DIN configured to receive digital data containing any number of bits (e.g., from circuitry in the digital domain), the values ​​of which collectively indicate a corresponding digital data value. DAC 50 may convert the received digital data value into a corresponding analog voltage value (e.g., provided to circuitry in the analog domain) supplied at the output terminal DOUT of DAC 50. This analog voltage value may be a reference voltage level corresponding to different input digital data values ​​indicated by different combinations of digital data bit values.

[0038] The conversion operation performed by DAC 50 can utilize a cell array 52 comprising any suitable number of unit cells 54 (sometimes referred to as cells 54). Each unit cell 54 may include a combination of circuit elements such as resistors, capacitors, inductors, transistors (e.g., switches), and / or combinational logic circuitry (e.g., logic gates). In some exemplary configurations sometimes described herein as examples, DAC 50 may be a capacitive DAC, and each unit cell 54 may include one or more capacitors (e.g., combinations of these capacitors form one or more capacitor banks). Based on the configuration of the circuit elements of each unit cell 54, each unit cell may generate a voltage (or current) based on a digital data value (e.g., one or more bits of that digital data value), which, together with one or more other unit cells 54, provides or otherwise causes the final analog voltage value provided at the output DOUT.

[0039] In some of the exemplary configurations described in this article as examples, Figure 3 The DAC circuit (including DAC 50) can be used as Figure 2A portion of the wireless communication circuitry 24 is provided. For example, the radio frequency transceiver circuitry 28 or more specifically, the transmitter 30 may include a DAC 50. Specifically, the DAC 50 may be positioned between the (digital baseband) processor 26 and a corresponding analog radio frequency processing (e.g., filtering, switching, amplification) stage in the transmitter 30 and front-end circuitry 40. In other words, the input terminal DIN of the DAC 50 may be communicatively coupled to the digital baseband portion of the processor 26, and the output terminal VOUT of the DAC 50 may be communicatively coupled to the analog signal processing portion of the transmitter 30 and / or the front-end circuitry 40. If desired, the DAC 50 may be located elsewhere in the wireless circuitry 24 to provide digital-to-analog conversion functionality. If desired, the DAC 50 may be located elsewhere in the device 10 (e.g., outside the wireless circuitry 24).

[0040] To provide and / or enhance the conversion functionality of DAC 50, each unit 54 may include one or more circuit features 56 (sometimes referred to as circuits 56), each of which is programmable (e.g., configurable between different states depending on stored programming data). Circuits 56 programmed in different ways can provide different properties to the conversion functionality of DAC 50 (e.g., causing DAC 50 to convert the same digital data value at input DIN to a (slightly) different analog voltage value). In this way, a set of programmed states can be used to enhance the conversion functionality of DAC 50 (e.g., by providing a more accurate analog voltage value for the input digital data value).

[0041] As an example, a circuit feature 56 of a given cell 54 may include configurable circuitry that enables or disables the entire cell, enables or disables portions or certain circuit elements of the cell, adjusts (e.g., tunes) the properties of the circuit elements in the cell (e.g., adjusts the resistance of a resistor, adjusts the capacitance of a capacitor, adjusts the inductance of an inductor, adjusts the bias voltage or current of a transistor, etc.), and / or generally connects or disconnects paths within the cell. This document sometimes describes exemplary configurations in which these configurable circuits, each depending on a corresponding control input (e.g., a control bit), toggle the configurable circuitry between two or more states (e.g., between an enabled state and a disabled state, between a connected state and a disconnected state, between multiple states corresponding to values ​​of corresponding properties, etc.). These control bits used to control the state of the configurable circuitry 56 (feature 56) are sometimes referred to herein as programming bits. Each cell 54 may store programming bits (e.g., bit values ​​corresponding to programming bits) that program (e.g., control, induce, etc.) the corresponding configurable circuitry 56 to exhibit specific (programmed) states.

[0042] In some cases, for all features in all cells, the DAC can be configured to receive programming bits via a corresponding dedicated routing path (e.g., from external programming circuitry to the corresponding cell). However, as the number of cells in the DAC and / or the number of programmable features within each cell increases, the number of routing paths used to route programming bits to each cell also increases. For example, in the case of a DAC comprising 256 cells (each with a programmable feature), 256 routing paths would be provided to route programming data to each of those 256 cells. Allocating such a large area to provide all these routing paths may be impractical and undesirable. Therefore, this limits the number of cells and / or features that can be implemented in the DAC, thus undesirably limiting the DAC's functionality.

[0043] To overcome these limitations and / or to provide other advantages (e.g., to offer a scalable programmable DAC architecture), Figure 3 The DAC circuit may be provided with a programming circuit 58 (sometimes referred to as programming interface circuit 58 or DAC programming circuit 58) communicatively coupled to the DAC 50 (e.g., at the corresponding programming inputs and / or programming outputs of the DAC 50). The programming circuit 58 may be communicatively coupled to the cell array 52 via paths for programming (writing) data, for addresses, for strobe signals, for reading flags, and for reading data, rather than via at least one programming data path to each cell 54 of the DAC 50 (thus requiring a large number of programming data paths (each for a given cell)). The corresponding programming inputs and / or programming outputs of the DAC 50 may be externally coupled to the programming circuit 58 via these paths and / or internally coupled to the cell array 53 via these paths. The number of programming (writing) data paths may correspond to (e.g., greater than or equal to) the number of features implemented on a given cell 54 (e.g., the cell 54 with the largest number of features in the cell array 52). The number of address data paths used to transmit address bits may correspond to (e.g., greater than or equal to) the number of bits required to uniquely address each cell 54 in array 52. ​​The strobe path and the read flag path may each be a single bit path. Any suitable number (e.g., one or more) of read data paths may be provided to access the desired data (e.g., programmed data and / or other data) in a given cell 54.

[0044] Figure 4 It is an exemplary DAC programming circuit (e.g., it can be used to implement...) Figure 3 A diagram of the programming circuit 58). Figure 4In the example, programming circuitry 58 may include data storage circuitry implementing lookup table 60 (e.g., storing entries of the lookup table). Lookup table 60 may include entries such as 62-1, 62-2, 62-3, each containing programming data and an address associated with that programming data (e.g., for programming features of cell 54 identified by that address). Multiplexing circuitry 64 (sometimes referred to as multiplexer 64), communicatively coupled to the data storage circuitry (providing table 60), may select a corresponding entry 62 (e.g., entry 62-1) for transmission based on its control inputs communicatively coupled to path 65. Multiplexing circuitry 64 may transmit programming data (e.g., DATA1) from entry 62 along one or more (programming data) paths 70 for writing write data (WDATA) to the appropriate cell, and may transmit addresses (bits) (e.g., ADDR1) along address data path 72. When the data on path 70 and path 72 have stabilized, programming circuit 58 can send an assertion strobe signal along strobe signal path 74, such that (e.g., based on the address data on path 72) the appropriate cell can latch the data sent on path 70.

[0045] Path 74 is communicatively coupled to latch 66 and provides a strobe signal to latch 66 to increment the output value using incremental circuitry 68 communicatively coupled between the output Q and input D of latch 66. Therefore, the output Q of latch 66, communicatively coupled to path 65, can subsequently provide an increment value to the control input of multiplexed circuitry 64, thereby allowing the contents of the next entry 62 (e.g., the programming data DATA2 and address ADDR2 of entry 62-2) to be sent along paths 70 and 72 (along with the strobe signal for the next assertion on path 74). In this way, the programming data in each entry 62 can be iteratively programmed in the cell matching the address in the corresponding entry 62.

[0046] To facilitate cell read operations, programming circuitry 58 may additionally provide a read flag (e.g., a read bit) along data path 76 and provide a read data path 78 on which read data can be obtained. Specifically, when the address of the cell to be read is provided on path 72 and the read flag on path 76 is set, data from the corresponding cell can be accessed on read data path 78. Therefore, programming circuitry 58 may store data read from path 78 and / or otherwise use the read data on path 78. The read data may include any suitable (digital) data (e.g., stored programming data) configured to be accessed from the cell.

[0047] Programming circuitry 58 can provide multiple write data paths 70 (e.g., for providing multiple programming bits (simultaneously) for the same or different features in the addressed cell). Similarly, programming circuitry 58 can provide multiple read data paths 80 (e.g., for reading multiple bits (simultaneously) from the addressed cell).

[0048] The use of lookup table 60 and the process of iteratively writing programming data into the cell based on entries 62 in lookup table 60, as described above, are merely illustrative. If needed, DAC programming circuit 58 can obtain the programming data and address of the cell to be programmed in any suitable manner (e.g., as a command from processing circuit 18). Figure 1 The control circuit 14 obtains and / or obtains programming data stored on the storage device circuit 16, or obtains commands from the processor 26 based on the operation of the wireless circuit 24, etc.

[0049] In some exemplary configurations, each of paths 70, 72, 74, and 76 is communicatively coupled to each cell 54 of array 52 (e.g., via the outputs and / or inputs of programming circuitry 58 and via the programming inputs and / or programming outputs of DAC 50). Based on the decoding of the address on path 72 during a write operation, only the appropriate (addressed) cell 54 can store (e.g., latch) the write data on path 70 when a strobe signal is asserted. The stored write data (e.g., programming data) can be used to control these configurable circuits by placing configurable circuitry 56 in the corresponding state. Based on the decoding of the address on path 72 during a read operation, only the appropriate (addressed) cell 54 can provide read data on path 78.

[0050] Figure 5 This is a diagram illustrating an example address decoding circuit, such as address decoding circuit 80 implemented at cell 54 of array 52 (e.g., a corresponding instance of which is implemented at each cell 54 of array 52). Because address decoding circuit 80 is implemented at cell 54, decoding circuit 80 may sometimes be referred to as local decoding circuit or local address decoding circuit.

[0051] Decoding circuit 80 can determine whether the unit 54 in which the decoding circuit is configured is the unit addressed (e.g., indicated) by an address on address data path 72. Specifically, decoding circuit 80 may include comparison circuit 82. Circuit 82 may receive an address on path 72 at a first input and compare that address with a local mask (e.g., the address locally stored in the unit where circuit 80 is configured) received at a second input. Based on this comparison, if the received address matches the local address (mask), circuit 82 may provide a first binary value (e.g., "1") at its output, and if no match is found, a second binary value (e.g., "0") is provided.

[0052] The AND gate 84 of circuit 80 may have a first input communicatively coupled to the output of circuit 82 and a second input communicatively coupled to strobe path 74. Based on the strobe signal on path 74 being asserted and based on circuit 82 matching the received address on path 72 with the local address (and providing a first binary value as output), the output of the AND gate 84 can provide a first binary value (e.g., "1"), and thus provide a rising edge to the clock input of latch 86. Therefore, based on the output of gate 84, the write data WDATA on path 70, communicatively coupled to input D of latch 86, can be latched (e.g., stored) and provided at output Q.

[0053] The stored data WDATA (e.g., programming data) can be used to determine the state of control unit 54 (e.g., the state of configurable circuitry 56 within unit 54). In other words, the data storage circuitry (e.g., latch 86) storing this programming data is communicatively coupled to configurable circuitry 56. Figure 3 The configurable circuit 56 can be programmed using stored programming data (e.g., provided as control input to the configurable circuit 56). If needed, write data (e.g., programming data) on multiple data paths 70 can be stored by corresponding data storage circuits (e.g., multiple latches, registers, other data storage circuits, etc.) based on the (clock) output signal of an AND logic gate 84. These corresponding data storage circuits can be coupled to different configurable circuits 56 to program the configurable circuit 56 using different stored segments of programming data (e.g., provided as control input to the configurable circuit 56).

[0054] For read operations, the AND gate 88 of circuit 80 may have a first input communicatively coupled to the output of circuit 82 and a second input communicatively coupled to the read flag data path 76. Based on the read flag being set (asserted) on path 76 and based on circuit 82 matching the received address on path 72 with the local address (and providing a first binary value as output), the output of the AND gate 88 may provide a first binary (logic high) value (e.g., "1") to the tri-state buffer 90. When placed in the logic high state, read data may be passed from cell 54 to the read data path 78 for output (e.g., output to programming circuit 58). The use of the tri-state buffer 90 (e.g., when buffer 90 is placed in a high-impedance state when the cell is not addressed) allows the same path 78 to be used to read other cells (e.g., by placing other tri-state buffers in a high-impedance state).

[0055] Figure 6 An exemplary portion 52-1 of the unit cells in array 52 is shown. The cells in array 52 are provided herein in a fractal arrangement (e.g., in conjunction with...). Figure 6 and Figure 7 Sometimes described as illustrative examples. However, if desired, the cells in array 52 may be provided in a matrix cell arrangement or other suitable arrangement, and this document (e.g., in conjunction with...) Figure 3 to Figure 9 The implementation scheme described can be similarly applied to these arrangements.

[0056] exist Figure 6 In the example, each unit cell in part 52-1 may have local address decoding circuitry, such as Figure 5 Circuit 80 in the program. Programming circuit 58 ( Figure 4 A set of data paths 92 (e.g., including write data path 70, address data path 72, strobe signal path 74, read flag data path 76 and read data path 78) can be provided to one or more unit cells 54-1, one or more unit cells 54-2, one or more unit cells 54-3 and one or more unit cells 54-4 in part 52-1.

[0057] Specifically, when path 92 is routed to (e.g., into) portion 52-1 of a unit cell, path 92 may have a width of M bits (e.g., a set of paths of M bits width, or an M-bit data bus). Even when assigned to (e.g., when routed to, when entering) each of unit cells 54-1, 54-2, 54-3, and 54-4, the width of path 92 may remain the same. Furthermore, each set of unit cells 54-1 may represent multiple unit cells within it, and a path 92 with a bit width of M may be further assigned to each unit cell in that set of unit cells 54-1. Therefore, if desired, using this routing scheme, the same set of data paths 92 with the same width can extend between the programming circuit 58 and each unit cell 54-1 in portion 52-1 and communicatively couple the programming circuit and each unit cell in that portion. Figure 6 The portion 52-1 shown is an exemplary configuration of the entire array 52, in which the same set of data paths 92 with the same bit width M can extend between the programming circuit 58 and each unit cell 54 in the array 52 and communicatively couple the programming circuit and each unit cell in the array.

[0058] Using this routing scheme, the local address decoding circuitry of each unit 54 in section 52-1 can be configured to receive and process that set of data paths 92, or more specifically, to receive and decode all (e.g., all bits) of the address in the address data path within data path 92. (See also: ...) Figure 5 As described, the comparator circuit 82 can receive all bits of the address on the corresponding address data path 72 (e.g., provided by the programming circuit 58), and the local mask (e.g., the stored local address) can have the same number of bits as the address.

[0059] While providing routing paths for writing data (e.g., programming data), strobe signals, and addresses (and, if necessary, for reading flags and reading data) reduces the number of routing paths required (compared to providing a separate programming path for each cell of the array), it may be necessary to further reduce the number of routing paths, for example, at least for routing to a subset of cells within the array. Figure 7 This is a diagram of an exemplary portion 52-2 of the unit cells in array 52, which has shared address decoding circuitry that reduces the number of lower-level routing paths (e.g., branches of routing paths that are farther from the original set of incoming routing paths 94). Figure 7 In the example, all paths in path 94 lead to... Figure 7 Before each unit cell in section 52-2 shown, a portion of the address decoding may occur at a shared address decoding circuit (e.g., address decoding circuits 96, 100, and 100 communicatively coupled to path 94).

[0060] Specifically, programming circuit 58 ( Figure 4 A set of data paths 94 (e.g., including write data path 70, address data path 72, strobe signal path 74, read flag data path 76, and read data path 78) may be provided to one or more unit cells 54-5, one or more unit cells 54-6, one or more unit cells 54-7, and one or more unit cells 54-8 in section 52-2. When path 94 is routed to (e.g., into) section 52-2 of unit cells, path 94 may have a width of N bits (e.g., a set of paths that are N bits wide, or an N-bit data bus).

[0061] After being routed to unit cell portion 52-2, path 94 can first be received by address decoding circuitry 96. In other words, path 94 can be communicatively coupled to decoding circuitry 96. Address decoding circuitry 96 can process (e.g., parse, perform decoding, etc.) the first bit (e.g., most significant bit) of the address data bits on address data path 72 in path 94. Specifically, decoding circuitry 96 can determine, based on this (most significant) bit of the address, whether the addressed cell is on the left side of array portion 52-2 (e.g., a cell in a set of cells 54-5 or a set of cells 54-7) or on the right side of array portion 52-2 (e.g., a cell in a set of cells 54-6 or a set of cells 54-8).

[0062] In response to the addressed cell being on the left, the remaining signal on path 94 (e.g., besides the resolved bits of the address) can be passed to path 98-1. In response to the addressed cell being on the right, the remaining signal on path 94 (e.g., besides the resolved bits of the address) can be passed to path 98-2. The location of the address cell is narrowed down by the decoding circuit 96 using the information in the (most significant) bits of the address on the corresponding address data path in path 94, which no longer needs to be routed through the decoding circuit 96 to identify the addressed cell. Therefore, a set of paths 98-1 and a set of paths 98-2 can each have a width of (N-1) bits, where the address data path has bits resolved by the decoding circuit 96 that are not present in either set of paths.

[0063] Path 98-1 may be coupled between decoding circuit 96 and decoding circuit 100. Address decoding circuit 100 may process (e.g., parse, perform decoding, etc.) the second bit (e.g., the second most significant bit) of the original address data bits on address data path 72 in path 94 (or the most significant bit of the address data bits on address data path 72 in path 98-1). Specifically, decoding circuit 100 may determine, based on this (second most significant) bit of the original address, whether the addressed cell is a cell in set 54-5 (e.g., located in the right branch of that cell from the perspective of circuit 100) or a cell in set 54-7 (e.g., located in the right branch of that cell from the perspective of circuit 100).

[0064] In response to the addressed cell being in set 54-5, the remaining signal on path 98-1 (e.g., besides the bits of the address resolved by circuit 100) can be passed to path 102-1. In response to the addressed cell being in set 54-7, the remaining signal on path 98-1 (e.g., besides the bits of the address resolved by circuit 100) can be passed to path 102-2. The location of the address cell is narrowed down by the decoding circuit 100 using information from the (second most significant) bits of the original address on the corresponding address data path in path 98-1, which no longer needs to be routed through the decoding circuit 100 to identify the addressed cell. Therefore, set 102-1 and set 10-2 can each have a width of (N-2) bits, wherein the address data path has additional (second most significant) bits of the original address resolved by the decoding circuit 100, which are not present in either set of paths.

[0065] Similar to the description above for the left side of section 52-2 and decoding circuit 100, the corresponding data received on path 98-2 can be processed similarly by decoding circuit 104 (e.g., by decoding the second most significant bit of the original address). Therefore, a set of paths 106-1 and a set of paths 106-2 can each have a width of (N-2) bits, lacking the two address data paths 72 in path 94 that contain the address bits (e.g., the most significant bit and the second most significant bit) decoded by decoding circuits 96 and 104.

[0066] If necessary, this type of shared decoding scheme can continue until the last two sets of paths branch off from the last shared address decoding circuit (shared only between two units). These last two sets of paths may lack any address data paths because all address bits in that address have been decoded by all upstream shared address decoding circuits. This situation can be illustrated by path 94 having only two address bits on its two corresponding address data paths 72. Therefore, path 102-1 (and similarly, paths 102-2, 106-1, and 106-2) may lack any address data path 72 (but include other data paths such as write data path 70, strobe signal path 74, read flag data path 76, and read data path 78). If necessary, when using a fully shared address decoding scheme (e.g., using...), Figure 5 The local address decoding circuit implemented by circuit 80 can omit the comparison circuit 82, AND logic gate 84 and AND logic gate 88. The strobe signal path 74 can be connected to the clock input of latch 86, and the read flag data path 78 can be connected to the control input of buffer 90.

[0067] Figure 8 This is a diagram illustrating an exemplary shared address decoding circuit 108 (e.g., a corresponding instance of which may be implemented at each branch of the routing path). As a combination Figure 7 For example, instances of circuit 108 can be implemented at paths 98-1 and 98-2 (as decoding circuit 96) by branching path 94, instances of circuit 108 can be implemented at paths 102-1 and 102-2 by branching path 98-1 (as decoding circuit 100), instances of circuit 108 can be implemented at paths 106-1 and 106-2 by branching path 98-2 (as decoding circuit 104), and so on.

[0068] exist Figure 8The example illustrates two exemplary types of decoding circuits 108-1 and 108-2. Decoding circuit 108-1 can be used to decode a given address (e.g., the most significant bit of the received address bits) to route write data, other (e.g., remaining) address bits, strobe signals, and read flags through decoding circuit 108. Specifically, path 110 providing the address bits to be decoded can be coupled to the first input of AND gate 114-1 and via intermediate inverter 116 to the first input of AND gate 114-2. Inverter 116 can provide bit ADDRB, which is the inverted version of the address bits on path 110, to the first input of AND gate 114-2. Another data bit (e.g., a write data bit, another address bit, a strobe bit, a read flag bit) may be provided on path 112, which is coupled to the second input of AND gate 114-1 and to the second input of AND gate 114-2.

[0069] Therefore, based on the value of the parsed address bit, another data bit on path 112 will be output by either AND gate 114-1 or AND gate 114-2, and the other of AND gate 114-1 or AND gate 114-2 will output a fixed binary value (e.g., "0"). Figure 8 In the example, AND gate 114-1 outputs (e.g., passes) the value on path 112, and AND gate 114-2 outputs (e.g., passes) a fixed binary value.

[0070] exist Figure 8 In the example, paths 110 and 112 may be coupled to these paths before the branch or may be part of these paths, while the outputs of logic gates 114-1 and 114-2 may be coupled to the branch path.

[0071] If needed, multiple instances of the decoding circuit 108-1 can be provided to properly process each of the other bits that should pass through circuit 108 (e.g., all bits for writing data, all unresolved address bits, strobe bits, read flag bits). If needed, inverter 116 can be shared among multiple instances of circuit 108-1.

[0072] If needed, a single instance of the decoding circuit 108-1 can be used to determine the output or pass-through path, and the remaining bits can be passed along a path parallel to the determined output or pass-through path (e.g., in the same direction as the determined output or pass-through path), without being directly gated by logic gates 114-1, 114-2, and 116.

[0073] Decoding circuit 108-2 can be used to decode a given address bit (e.g., the most significant bit of the received address bits) for routing read data from the unit cell to programming circuit 58. Specifically, path 110 providing the address bit to be decoded can be coupled to the first input of AND gate 118-1. Path 110' providing the inverted version of the address bit to be decoded (e.g., bit ADDRB provided by inverter 116) can be coupled to the first input of AND gate 118-2. Path 120-1 from the first branch path (e.g., for providing read data from the first set of cells) can be coupled to the second input of AND gate 118-1. Path 120-2 from the second branch path (e.g., for providing read data from the second set of cells) can be coupled to the second input of AND gate 118-2. The outputs of gates 118-1 and 118-2 can be coupled to the corresponding inputs of OR gate 122. In this configuration, when the appropriate AND gate 118-1 or 118-2 (e.g., located on the side containing the addressed cell) outputs or passes a read data bit (RDATA1 or RDATA2), the read data bit is passed through the OR logic gate 122 and provided at the output of the OR gate logic 122 (e.g., as RDATA).

[0074] exist Figure 8 In the example, path 110 and the output of OR gate 122 can be coupled to these paths before the branch, while paths 120-1 and 120-2 can be coupled to the branch path.

[0075] Combination Figure 6 In the described example, address decoding can occur entirely (e.g., for all address bits) within the local address decoding circuitry (e.g., Figure 5 At point 80 in the circuit. Combined with... Figure 7 In the described example, address decoding can occur entirely (e.g., for all address bits) within a shared address decoding circuit (e.g., Figure 8 The circuit is located at 108. If needed, a combination of these two address decoding schemes (e.g., a hybrid approach) can be used.

[0076] like Figure 9As illustrated in the exemplary flowchart, the exemplary DAC 50 may include one or more instances of shared address decoding circuitry (e.g., an instance of decoding circuitry 108) that perform shared decoding at a corresponding number (e.g., "X") of bifurcations at block 124 to decode a set of most significant bits of the address for other data pairs (e.g., bits written to data, unresolved address bits, strobe bits, read flag bits, and read data bits). The exemplary DAC 50 may also include local address decoding circuitry at each cell 54 (e.g., an instance of decoding circuitry 80) that performs local decoding at block 126 (e.g., at the cell level) to decode the remaining bits of the address (e.g., least significant bits) to appropriately process other data (e.g., bits written to data, unresolved address bits, strobe bits, read flag bits, and read data bits).

[0077] The above text combined Figure 1 to Figure 9 The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) that stores one or more components of device 10 (e.g., Figure 1 The software code is stored on the storage device circuitry 16 and / or the wireless communication circuitry 24. This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of the device 10 (e.g., processing circuitry in the wireless circuitry 24, ...). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0078] According to one embodiment, a wireless communication circuit includes: a digital-to-analog converter (DAC) having a plurality of unit cells; a programming circuit configured to program the plurality of unit cells; and a plurality of data paths coupled to the programming circuit and the DAC and including an address data path, wherein the programming circuit is configured to transmit address bits to the DAC via the address data path, the address bits collectively forming an address identifying a given unit cell among the plurality of unit cells.

[0079] According to another embodiment, the plurality of data paths optionally include a programming data path, and the programming circuit is configured to transmit programming data to be stored at the given unit cell to the plurality of unit cells via the programming data path.

[0080] According to another embodiment, the plurality of data paths optionally include strobe signal paths, and the programming circuit is configured to transmit strobe signals to the plurality of unit cells via the strobe signal paths, the strobe signals causing the programming data to be stored at the given unit cell when asserted.

[0081] According to another embodiment, the given unit cell optionally has configurable circuitry, and the programming data, when stored at the given unit cell, causes the configurable circuitry to be in a state.

[0082] According to another embodiment, the plurality of data paths optionally includes a read flag data path, and the programming circuit is configured to transmit a read flag to the plurality of unit cells via the read flag data path, the read flag, when set, causing data to be read from the given unit cell.

[0083] According to another embodiment, the plurality of data paths optionally includes a read data path, and the programming circuit is configured to receive the data read from the given unit cell via the read data path when the read flag is set.

[0084] According to another embodiment, the given unit optionally includes a local address decoding circuit configured to receive and decode at least one address bit among the address bits.

[0085] According to another embodiment, the local address decoding circuit is optionally configured to receive and decode each address bit in the address bits.

[0086] According to another embodiment, the digital-to-analog converter optionally includes a shared address decoding circuit coupled to a first set of unit cells and a second set of unit cells in the plurality of unit cells, and the shared address decoding circuit is configured to receive and decode at least one address bit in the address bits.

[0087] According to another embodiment, the given unit optionally includes a local address decoding circuit configured to receive and decode at least one address bit among the address bits.

[0088] According to another embodiment, the shared address decoding circuit is optionally configured to receive and decode at least the most significant bit of the address, and the local address decoding circuit is configured to receive and decode at least the least significant bit of the address.

[0089] According to another embodiment, the wireless communication circuit optionally further includes a transmitter, which includes the digital-to-analog converter.

[0090] According to one embodiment, a digital-to-analog converter includes: a plurality of unit cells, a given unit cell having programmable features and storage circuitry configured to store programming data for the programmable features; a plurality of address data paths coupled to the plurality of unit cells and configured to transmit an address of the given unit cell; a strobe signal path coupled to the plurality of unit cells and configured to transmit a strobe signal; and a write data path coupled to the plurality of unit cells and configured to provide the programming data to the storage circuitry based on the address and the strobe signal.

[0091] According to another embodiment, the digital-to-analog converter optionally further includes: a read flag data path coupled to the plurality of unit cells and configured to transmit read flags; and a read data path coupled to the plurality of unit cells and configured to provide data from the given unit cell based on the address and the read flags.

[0092] According to another embodiment, the given unit optionally has a local address and includes a comparison circuit configured to perform a comparison between the address transmitted by the plurality of address data paths and the local address, and the write data path is configured to provide the programming data to the storage circuit based on the comparison.

[0093] According to another embodiment, the digital-to-analog converter optionally further includes a shared address decoding circuit coupled between the plurality of address data paths and the plurality of unit cells, wherein the shared address decoding circuit is configured to decode the address bits transmitted on the address data paths of the plurality of address data paths.

[0094] According to another embodiment, the digital-to-analog converter optionally further includes an additional shared address decoding circuit coupled between the plurality of address data paths and the plurality of unit cells, wherein the additional shared address decoding circuit is configured to decode additional address bits of the address transmitted on an additional address data path in the plurality of address data paths.

[0095] According to another embodiment, the digital-to-analog converter optionally further includes: an input terminal configured to receive digital data; and an output terminal configured to use the plurality of unit cells to provide an analog voltage corresponding to the digital data.

[0096] According to one embodiment, a digital-to-analog converter includes: a plurality of unit cells, each of the plurality of unit cells having configurable circuitry; an input terminal coupled to the plurality of unit cells and configured to receive digital data; an output terminal coupled to the plurality of unit cells and configured to use the plurality of unit cells to provide an analog voltage corresponding to the digital data; and a plurality of programming input terminals coupled to the plurality of unit cells and configured to receive an address and programming data, the programming data being used to control the configurable circuitry of a unit cell identified by the address among the plurality of unit cells.

[0097] According to another embodiment, the digital-to-analog converter optionally further includes a first address decoding circuit coupled between a first group of unit units and a second group of unit units in the plurality of unit units, and configured to provide address decoding for a first portion of the address and for the first group of unit units and the second group of unit units, wherein the unit unit identified by the address includes a second address decoding circuit configured to provide address decoding for a second portion of the address and for the unit unit.

[0098] The foregoing is merely illustrative and various modifications can be made to the described implementation scheme. The foregoing implementation scheme can be implemented individually or in any combination.

[0099] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. A wireless communication circuit, the wireless communication circuit comprising: a digital-to-analog converter having a plurality of unit cells; a programming circuit configured to program the plurality of unit cells; and a plurality of data paths coupled to the programming circuit and the digital-to-analog converter and including an address data path, wherein the programming circuit is configured to convey address bits through the address data path to the digital-to-analog converter, the address bits collectively forming an address identifying a given unit cell of the plurality of unit cells.

2. The wireless communication circuit of claim 1, wherein the plurality of data paths includes a programming data path, and wherein the programming circuit is configured to convey programming data to be stored at the given unit cell through the programming data path to the plurality of unit cells.

3. The wireless communication circuit of claim 2, wherein the plurality of data paths includes a strobe signal path, and wherein the programming circuit is configured to convey a strobe signal through the strobe signal path to the plurality of unit cells, the strobe signal when asserted causing the programming data to be stored at the given unit cell.

4. The wireless communication circuit of claim 2, wherein the given unit cell has a configurable circuit, and wherein the programming data when stored at the given unit cell causes the configurable circuit to assume a state.

5. The wireless communication circuit of claim 1, wherein the plurality of data paths includes a read flag data path, and wherein the programming circuit is configured to convey a read flag through the read flag data path to the plurality of unit cells, the read flag when set causing data to be read from the given unit cell.

6. The wireless communication circuit of claim 5, wherein the plurality of data paths includes a read data path, and wherein the programming circuit is configured to receive the data read when the read flag is set from the given unit cell through the read data path.

7. The wireless communication circuit of claim 1, wherein the given unit cell includes a local address decode circuit configured to receive and decode at least one of the address bits.

8. The wireless communication circuit of claim 7, wherein the local address decode circuit is configured to receive and decode each of the address bits.

9. The wireless communication circuit of claim 1, wherein the digital-to-analog converter includes a shared address decode circuit coupled to a first set of unit cells of the plurality of unit cells and coupled to a second set of unit cells of the plurality of unit cells, and wherein the shared address decode circuit is configured to receive and decode at least one of the address bits.

10. The wireless communication circuit of claim 9, wherein the given unit cell includes a local address decode circuit configured to receive and decode at least one of the address bits. ​ 11. The wireless communication circuit of claim 10, wherein the shared address decode circuit is configured to receive and decode at least the most significant bits of the address, and wherein the local address decode circuit is configured to receive and decode at least the least significant bits of the address.

12. The wireless communication circuit of claim 1, further comprising a transmitter including the digital-to-analog converter.

13. A digital-to-analog converter, the digital-to-analog converter comprising: a plurality of unit cells, a given unit cell of the plurality of unit cells having a programmable feature and a storage circuit configured to store programming data for the programmable feature; a plurality of address data paths coupled to the plurality of unit cells and configured to convey an address of the given unit cell; a strobe signal path coupled to the plurality of unit cells and configured to convey a strobe signal; and a write data path coupled to the plurality of unit cells and configured to provide the programming data to the storage circuit based on the address and the strobe signal.

14. The digital-to-analog converter of claim 13, further comprising: a read flag data path coupled to the plurality of unit cells and configured to convey a read flag; and a read data path coupled to the plurality of unit cells and configured to provide data from the given unit cell based on the address and the read flag.

15. The digital-to-analog converter of claim 13, wherein the given unit cell has a local address and includes a comparison circuit configured to perform a comparison of the address conveyed by the plurality of address data paths and the local address, and wherein the write data path is configured to provide the programming data to the storage circuit based on the comparison.

16. The digital-to-analog converter of claim 13, further comprising: a shared address decode circuit coupled between the plurality of address data paths and the plurality of unit cells, wherein the shared address decode circuit is configured to decode address bits of the address conveyed on an address data path of the plurality of address data paths.

17. The digital-to-analog converter of claim 16, further comprising: an additional shared address decode circuit coupled between the plurality of address data paths and the plurality of unit cells, wherein the additional shared address decode circuit is configured to decode additional address bits of the address conveyed on an additional address data path of the plurality of address data paths.

18. The digital-to-analog converter of claim 13, further comprising: an input configured to receive digital data; and an output configured to provide an analog voltage corresponding to the digital data using the plurality of unit cells.

19. A digital-to-analog converter, the digital-to-analog converter comprising: a plurality of unit cells each having a configurable circuit; an input coupled to the plurality of unit cells and configured to receive digital data; an output coupled to the plurality of unit cells and configured to provide, using the plurality of unit cells, an analog voltage corresponding to the digital data; and a plurality of programming inputs coupled to the plurality of unit cells and configured to receive an address and programming data for controlling the configurable circuit of a unit cell of the plurality of unit cells identified by the address.

20. The digital-to-analog converter of claim 19, the digital-to-analog converter further comprising: a first address decode circuit coupled between a first group of unit cells and a second group of unit cells of the plurality of unit cells and configured to provide address decoding for a first portion of the address and for the first group of unit cells and the second group of unit cells, wherein the unit cell identified by the address includes a second address decode circuit configured to provide address decoding for a second portion of the address and for the unit cell. ​

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