Time synchronization method and device based on precise network time protocol

Abstract

The invention discloses a time synchronization method and device based on a precise network time protocol, and belongs to the field of computer networks. The time synchronization method comprises the following steps: determining a time synchronization control parameter; the parameters comprise a phase modulation time deviation stable value, a first target frequency deviation value and a second target frequency deviation value; acquiring a first time deviation between the first clock signal of the slave device and the second clock signal of the master device; entering a frequency modulation stage under the condition that the first time deviation is smaller than or equal to a phase modulation time deviation stable value, and adjusting the frequency of the first clock signal based on a first target frequency deviation value for the first frequency modulation; and after the first frequency modulation, adjusting the frequency of the first clock signal according to the target control method based on the second target frequency offset value. According to the time synchronization method and device based on the precise network time protocol disclosed by the invention, the convergence time of time synchronization can be shortened by entering the frequency modulation stage under the condition that the time deviation is smaller than or equal to the target threshold value.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer networks, and particularly relates to a time synchronization method and device based on a precision network time protocol. BACKGROUND

[0002] In related technologies, the precision network time protocol (PTP) is a network clock synchronization protocol defined by the IEEE Std 1588-2008 / IEC 61588 standard. The protocol adopts a master-slave architecture and realizes clock calibration and time synchronization between distributed systems through message types such as Sync and Delay_Req, and can achieve sub-microsecond synchronization accuracy in a local area network, and is widely used in power systems, communication networks and industrial automation fields.

[0003] For time synchronization based on the precision network time protocol, a proportional-integral-derivative (PID) control algorithm is generally used to control the clock signal of the slave device to adjust the time of the slave device, so as to realize time synchronization between the master device and the slave device. However, the convergence time of time synchronization is relatively long, that is, a long time is needed to complete the time synchronization between the master device and the slave device. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides a time synchronization method and device based on a precision network time protocol, which can shorten the convergence time of time synchronization.

[0005] In a first aspect, the present application provides a time synchronization method based on a precision network time protocol, the method comprising: determining a time synchronization control parameter; the time synchronization control parameter comprises a phase adjustment time deviation stable value, a first target frequency deviation value and a second target frequency deviation value; obtaining a first time deviation between a first clock signal of a slave device and a second clock signal of a master device; in the case where the first time deviation is less than or equal to the phase adjustment time deviation stable value, entering a frequency adjustment phase, and for the first frequency adjustment, adjusting the frequency of the first clock signal based on the first target frequency deviation value; and after the first frequency adjustment, adjusting the frequency of the first clock signal according to a target control method based on the second target frequency deviation value; The phase adjustment time deviation stable value is a minimum value of the first time deviation that can be reached by adjusting the phase of the first clock signal; and the first target frequency deviation value is a frequency deviation between the first clock signal and the second clock signal when the first time deviation converges by adjusting the frequency of the first clock signal.

[0006] According to the time synchronization method based on the precise network time protocol, the time synchronization can be shortened by entering the frequency adjustment stage when the time deviation between the first clock signal of the slave device and the second clock signal of the master device is less than or equal to the phase adjustment time deviation stable value, and adjusting the frequency of the first clock signal based on the first target frequency deviation value in the first frequency adjustment.

[0007] According to an embodiment of the present application, after the first time deviation between the first clock signal of the slave device and the second clock signal of the master device is obtained, the method further comprises: When the first time deviation is greater than the phase adjustment time deviation stable value, adjusting the phase of the first clock signal based on the first time deviation.

[0008] According to an embodiment of the present application, the second target frequency deviation value is half of the first target frequency deviation value; and / or, the target control method comprises an integral control method.

[0009] According to an embodiment of the present application, the determination of the time synchronization control parameter comprises: adjusting the phase of the third clock signal of the sample device multiple times based on the second time deviation between the third clock signal of the sample device and the second clock signal, with the phase of the second clock signal as a target, and obtaining a target fluctuation range until the second time deviation converges and lasts for a target number of times; the sample device and the slave device use the same type of crystal oscillator; and the target fluctuation range is a fluctuation range of the second time deviation during the second time deviation converges and lasts for the target number of times. determining an upper limit of the target fluctuation range as the phase adjustment time deviation stable value.

[0010] According to an embodiment of the present application, the determination of the time synchronization control parameter further comprises: When the second time deviation obtained this time belongs to the target fluctuation range, adjusting the frequency of the third clock signal of the sample device based on a target frequency deviation according to a target control method until the second time deviation converges and lasts for a target time length; and the target frequency deviation is a frequency deviation between the third clock signal and the second clock signal. determine the target frequency deviation in the case that the second time deviation converges as the first target frequency deviation value.

[0011] According to one embodiment of the present application, the adjusting the frequency of the third clock signal of the sample device according to the target control method based on the target frequency deviation comprises: In the case that the second time deviation does not satisfy the convergence and lasts for the target duration, updating the target frequency deviation based on the second time deviation obtained this time and the second time deviation obtained last time; adjusting the frequency of the third clock signal according to the target control method based on the target frequency deviation.

[0012] According to one embodiment of the present application, the updating the target frequency deviation based on the second time deviation obtained this time and the second time deviation obtained last time comprises: in the case that the second time deviation obtained this time is greater than or equal to the second time deviation obtained last time, decreasing the target frequency deviation by 1.

[0013] According to one embodiment of the present application, the updating the target frequency deviation based on the second time deviation obtained this time and the second time deviation obtained last time comprises: in the case that the second time deviation obtained this time is less than the second time deviation obtained last time, increasing the target frequency deviation by 1.

[0014] In a second aspect, the present application provides a time synchronization device based on a precise network time protocol, comprising: a determining module configured to determine time synchronization control parameters; the time synchronization control parameters comprise: a phase modulation time deviation stable value, a first target frequency deviation value and a second target frequency deviation value; an obtaining module configured to obtain a first time deviation between a first clock signal of a slave device and a second clock signal of a master device; an adjusting module configured to, in the case that the first time deviation is less than or equal to the phase modulation time deviation stable value, enter a frequency modulation stage, and for the first time frequency modulation, adjust the frequency of the first clock signal based on the first target frequency deviation value; and after the first time frequency modulation, adjust the frequency of the first clock signal according to a target control method based on the second target frequency deviation value; wherein the phase modulation time deviation stable value is the minimum value of the first time deviation that can be reached by adjusting the phase of the first clock signal; and the first target frequency deviation value is the frequency deviation between the first clock signal and the second clock signal in the case that the first time deviation converges by adjusting the frequency of the first clock signal.

[0015] According to the time synchronization method based on the precise network time protocol, the time synchronization convergence time is shortened by entering the frequency adjustment phase when the time deviation between the first clock signal of the slave device and the second clock signal of the master device is less than or equal to the phase adjustment time deviation stability value, and adjusting the frequency of the first clock signal based on the first target frequency deviation value in the first frequency adjustment.

[0016] In a third aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the time synchronization method based on the precise network time protocol according to the first aspect.

[0017] In a fourth aspect, the present application provides a non-volatile computer readable storage medium, which stores a computer program, and the computer program is executable on a processor to implement the time synchronization method based on the precise network time protocol according to the first aspect.

[0018] In a fifth aspect, the present application provides a chip, comprising a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run a program or an instruction to implement the time synchronization method based on the precise network time protocol according to the first aspect.

[0019] In a sixth aspect, the present application provides a computer program product, comprising a computer program, and the computer program is executable on a processor to implement the time synchronization method based on the precise network time protocol according to the first aspect.

[0020] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings. Figure 1 is a flowchart of the time synchronization method based on the precise network time protocol provided by the embodiments of the present application; Figure 2 is a comparison diagram of the time synchronization convergence time of the time synchronization method based on the precise network time protocol provided by the embodiments of the present application; Figure 3 is a flowchart of obtaining the phase adjustment time deviation stability value in the time synchronization method based on the precise network time protocol provided by the embodiments of the present application; Figure 4is a flowchart of acquiring a first target frequency offset value in a time synchronization method based on a precise network time protocol provided by an embodiment of the present application. Figure 5 is a diagram of a use timing of a parameter in a time synchronization method based on a precise network time protocol provided by an embodiment of the present application. Figure 6 is a structural diagram of a time synchronization device based on a precise network time protocol provided by an embodiment of the present application. Figure 7 is a structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0023] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a category and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in an "or" relationship.

[0024] In related technologies, time synchronization based on a precise network time protocol realizes high-precision time synchronization, generally including two stages of phase adjustment and frequency adjustment. In the case that the time deviation offset between the time of a slave device and the time of a master device is too large (generally, greater than a phase adjustment threshold step_threshold is taken as a condition), the phase adjustment stage is entered; in the case that the time deviation offset between the time of the slave device and the time of the master device is small (generally, less than or equal to the phase adjustment threshold step_threshold is taken as a condition), the frequency adjustment stage is entered.

[0025] In the phase adjustment stage, the time deviation offset between the time of the slave device and the time of the master device is directly used as an adjustment parameter to adjust the clock signal of the slave device. In the frequency adjustment stage, the frequency difference ppb (i.e., the frequency offset) between the clock signal of the slave device and the clock signal of the master device is used as an adjustment parameter to adjust the clock signal of the slave device.

[0026] The following description, in conjunction with the accompanying drawings, details the time synchronization method, device, electronic device, and readable storage medium based on the Precision Network Time Protocol (PRTP) provided in this application, through specific embodiments and application scenarios.

[0027] Among them, the time synchronization method based on the Precise Network Time Protocol can be applied to the terminal, specifically executed by the hardware or software in the terminal.

[0028] The time synchronization method based on the Precise Network Time Protocol provided in this application embodiment can be executed by an electronic device or a functional module or entity in an electronic device that can implement the time synchronization method based on the Precise Network Time Protocol. The electronic devices mentioned in this application embodiment include, but are not limited to, mobile phones, tablets, computers, cameras, and wearable devices. The following uses an electronic device as the execution subject to illustrate the time synchronization method based on the Precise Network Time Protocol provided in this application embodiment.

[0029] like Figure 1 As shown, the time synchronization method based on the Precise Network Time Protocol includes steps 110, 120 and 130.

[0030] Step 110: Determine the time synchronization control parameters; the time synchronization control parameters include: the stable value of phase modulation time deviation, the first target frequency deviation value, and the second target frequency deviation value; the stable value of phase modulation time deviation is the minimum value of the first time deviation that can be achieved by adjusting the phase of the first clock signal; the first target frequency deviation value is the frequency deviation between the first clock signal and the second clock signal when the first time deviation is converged by adjusting the frequency of the first clock signal.

[0031] In actual implementation, in order to achieve faster convergence, time synchronization control parameters such as the stable value of phase modulation time deviation, the first target frequency deviation value, and the second target frequency deviation value can be determined first.

[0032] It should be noted that the stable value of the phase modulation time deviation, step_time_offset, is the minimum value of the first time deviation offset1 achievable by adjusting the phase of the first clock signal; that is, the stable value of the phase modulation time deviation. It can be understood that if the first time deviation offset1 is greater than the stable value of the phase modulation time deviation, step_time_offset, adjusting the phase of the first clock signal can reduce the first time deviation offset1, but it cannot make the first time deviation offset1 less than the stable value of the phase modulation time deviation, step_time_offset.

[0033] In some embodiments, the phase adjustment time offset stable value step_time_offset can be obtained by training and / or experiment, etc. The minimum value of the first time offset that can be achieved by adjusting the phase of the first clock signal can be determined by training and / or experiment, etc., as the phase adjustment time offset stable value step_time_offset.

[0034] In some embodiments, the first target frequency offset value freq_ppb_first is the frequency offset ppb between the first clock signal and the second clock signal in the case where the first time offset converges by adjusting the frequency of the first clock signal.

[0035] In some embodiments, the first target frequency offset value freq_ppb_first can be obtained by training and / or experiment, etc. The frequency offset between the first clock signal and the second clock signal when the first time offset converges by adjusting the frequency of the first clock signal can be obtained by training and / or experiment, etc., as the first target frequency offset value freq_ppb_first.

[0036] In some embodiments, the second target frequency offset value freq_ppb can be used as the initial value of the target control method, to prevent the burst from being ineffective due to the incorrect initial value of the target control method.

[0037] In some embodiments, the second target frequency offset value freq_ppb can be determined according to the first target frequency offset value freq_ppb_first. Alternatively, the second target frequency offset value freq_ppb can be obtained separately by training and / or experiment, etc.

[0038] Step 120, obtaining a first time offset between a first clock signal of the slave device and a second clock signal of the master device.

[0039] It should be noted that the precise network time protocol-based time synchronization method provided by the embodiments of the present application can be applied to the slave device in the master-slave architecture based on the precise network time protocol, to synchronize the clock signal of the slave device with the clock signal of the master device.

[0040] It should be noted that the clock signal of the slave device can be denoted as the first clock signal, and the clock signal of the master device can be denoted as the second clock signal.

[0041] In actual execution, after the slave device is powered on, the time offset between the first clock signal and the second clock signal can be obtained, denoted as the first time offset offset1.

[0042] In step 130, in a case where the first time offset is less than or equal to the phase modulation time offset stable value, entering a frequency modulation stage, and for the first time frequency modulation, adjusting the frequency of the first clock signal based on the first target frequency offset value; and after the first time frequency modulation, adjusting the frequency of the first clock signal according to a target control method based on the second target frequency offset value.

[0043] In actual implementation, the size of the first time offset offset1 and the phase modulation time offset stable value step_time_offset can be compared to determine whether to enter the frequency modulation stage. The first time offset offset1 is less than or equal to the phase modulation time offset stable value step_time_offset, and the frequency modulation stage can be entered. The frequency modulation stage refers to a stage of achieving synchronization of the first clock signal and the second clock signal (i.e., synchronization of the clock signal of the slave device and the clock signal of the master device) by adjusting the frequency of the first clock signal.

[0044] It should be noted that the condition for entering the frequency modulation stage in the related art is that the time offset offset between the time of the slave device and the time of the master device is less than the phase modulation threshold step_threshold. However, the phase modulation threshold step_threshold is usually set artificially according to experience. If the value of step_threshold is too large, it will lead to early entry into the frequency modulation stage. Frequency modulation is to adjust the speed of time change to achieve time adjustment, which belongs to fine adjustment, and the larger the time offset offset is, the longer the convergence time of time synchronization is. If the value of step_threshold is too small, it will lead to failure to enter the frequency modulation stage, and the slave device is always in the phase modulation stage (i.e., always in the phase modulation stage), and the convergence of time synchronization cannot be achieved, i.e., the time synchronization of the slave device and the master device cannot be achieved.

[0045] It can be understood that by entering the frequency modulation stage in a case where the first time offset offset1 is less than or equal to the phase modulation time offset stable value step_time_offset, both the longer convergence time of time synchronization caused by early entry into the frequency modulation stage and the failure to achieve the convergence of time synchronization by always being in the phase modulation stage can be avoided.

[0046] After entering the frequency modulation stage, for the first time frequency modulation (i.e., the first time adjustment of the frequency of the first clock signal), the first target frequency offset value freq_ppb_first can be used as an adjustment parameter to adjust the frequency of the first clock signal.

[0047] In some embodiments, adjusting the frequency of the first clock signal based on the first target frequency offset value freq_ppb_first can include using the first target frequency offset value freq_ppb_first as an adjustment parameter to adjust the frequency of the first clock signal.

[0048] In some embodiments, the frequency of the first clock signal can be adjusted in a manner that the frequency of the first clock signal is reduced by a first target frequency offset value freq_ppb_first (the first target frequency offset value freq_ppb_first has a negative sign in a case that the frequency of the first clock signal is less than the frequency of the second clock signal, and the first target frequency offset value freq_ppb_first has a positive sign in a case that the frequency of the first clock signal is greater than the frequency of the second clock signal).

[0049] It should be noted that in the related art, a control algorithm based on proportional-integral-derivative (PID) control is used throughout the frequency adjustment stage. Based on the frequency difference between the first clock signal and the second clock signal (i.e., the frequency offset between the first clock signal and the second clock signal), the adjustment amount of the frequency of the first clock signal is calculated, and then the frequency of the first clock signal is adjusted based on the adjustment amount. For the first frequency adjustment, if the current first time offset offset1 is relatively large, the frequency offset between the first clock signal and the second clock signal calculated by the above control algorithm is also relatively large, and multiple PTP cycles are required to gradually adjust the frequency to successfully synchronize. If the current first time offset offset1 is relatively small, the frequency offset between the first clock signal and the second clock signal calculated by the above control algorithm is also relatively small, resulting in that the frequency adjustment is not in place, and the first time offset offset1 of the next PTP cycle becomes large, and multiple PTP cycles are required to gradually adjust the frequency to successfully synchronize. Therefore, the convergence time of time synchronization in the related art is longer.

[0050] In the embodiments of the present application, a frequency offset parameter, a first target frequency freq_ppb_first (the first frequency offset ppb, i.e., the frequency offset ppb between the first clock signal and the second clock signal when the first frequency adjustment is performed for the first time in the frequency adjustment stage) is added, and the current first time offset offset1 can be successfully synchronized after one frequency adjustment. Since the PID-based control algorithm is not required to be gradually calculated, the preset parameter first target frequency freq_ppb_first is directly used to adjust in one step, and the convergence time of time synchronization is greatly shortened.

[0051] In actual implementation, for each frequency adjustment after the first frequency adjustment, a target control algorithm based on PID control can be used to adjust the frequency of the first clock signal based on a second target frequency offset value freq_ppb.

[0052] In some embodiments, the target control algorithm can be any PID control based control algorithm, such as a proportional-integral (PI) control algorithm, an integral (I) control algorithm, a proportional-derivative (PD) control algorithm, or a PID control algorithm, etc.

[0053] In some embodiments, adjusting the frequency of the first clock signal according to the target control method based on the second target frequency offset value freq_ppb can include adjusting the frequency of the first clock signal according to the target control method with the second target frequency offset value freq_ppb as an adjustment parameter.

[0054] In some embodiments, an adjustment amount of the frequency of the first clock signal can be calculated based on the second target frequency offset value freq_ppb and the frequency offset between the first clock signal and the second clock signal according to the target control method, and then the frequency of the first clock signal can be adjusted based on the adjustment amount.

[0055] In some embodiments, an adjustment amount of the frequency of the first clock signal can be calculated based on the second target frequency offset value freq_ppb and the frequency offset between the first clock signal and the second clock signal according to the target control method, and then the frequency of the first clock signal can be adjusted based on the adjustment amount.

[0056] It should be noted that by adjusting the frequency of the first clock signal according to the target control method based on the second target frequency offset value in the second frequency adjustment and subsequent frequency adjustments, the second target frequency offset value is used as the initial value of the target control method, which can prevent burst convergence failure caused by incorrect initial value of the target control method, thereby shortening the convergence time of time synchronization.

[0057] It should be noted that by applying the time synchronization method provided in the embodiments of the present application, frequency adjustment and phase adjustment are performed based on the three parameters of the phase adjustment time offset stable value step_time_offset, the first target frequency offset value freq_ppb_first, and the second target frequency offset value freq_ppb according to the PTP protocol to achieve time synchronization, which can achieve fast convergence. The schematic diagram of the above fast convergence effect can be as shown in Figure 2 . The left half of Figure 2 shows the convergence process of the related art time synchronization, Figure 2 The right half of Figure 2It can be known from the left half and the right half in the figure that the number of PTP cycles required for convergence of time synchronization by using the time synchronization method provided in the embodiments of the present application is obviously less than that of related technologies, that is, the time synchronization method provided in the embodiments of the present application can greatly shorten the convergence time of time synchronization.

[0058] According to the time synchronization method based on the precise network time protocol provided in the embodiments of the present application, by entering the frequency adjustment stage in the case that the time deviation between the first clock signal of the slave device and the second clock signal of the master device is less than or equal to the phase adjustment time deviation stability value, and adjusting the frequency of the first clock signal based on the first target frequency deviation value in the first frequency adjustment, and adjusting the frequency of the first clock signal based on the second target frequency deviation according to the target control method after the first frequency adjustment, time synchronization is performed, which can shorten the convergence time of time synchronization.

[0059] In some embodiments of the present application, after obtaining the first time deviation between the first clock signal of the slave device and the second clock signal of the master device, the method further comprises: in the case that the first time deviation is greater than the phase adjustment time deviation stability value, adjusting the phase of the first clock signal based on the first time deviation.

[0060] In actual implementation, the size of the first time deviation offset1 and the phase adjustment time deviation stability value step_time_offset can be compared to determine whether to enter the frequency adjustment stage. The first time deviation offset1 is greater than the phase adjustment time deviation stability value step_time_offset, which indicates that it is in the phase adjustment stage. The phase adjustment stage refers to a stage of realizing synchronization of the first clock signal and the second clock signal (i.e., synchronization of the clock signal of the slave device and the clock signal of the master device) by adjusting the phase of the first clock signal. In time synchronization, frequency adjustment belongs to fine adjustment, and phase adjustment belongs to larger adjustment. Phase adjustment is to realize time adjustment by directly adjusting time.

[0061] In some embodiments, adjusting the phase of the first clock signal based on the first time deviation offset1 can include: taking the first time deviation offset1 as an adjustment parameter to adjust the phase of the first clock signal.

[0062] In some embodiments, the phase of the first clock signal can be adjusted by subtracting the first time deviation offset1 (the first time deviation offset1 is signed, in the case that the time represented by the first clock signal is less than the time represented by the second clock signal, the sign of the first time deviation offset1 is negative, and in the case that the time represented by the first clock signal is greater than the time represented by the second clock signal, the sign of the first time deviation offset1 is positive) from the phase of the first clock signal.

[0063] In some embodiments, after the slave device is first enabled or after the first PTP cycle (hereinafter referred to as the "first PTP cycle", "second PTP cycle", and the like can be analogously referred to) after the crystal oscillator of the slave device is powered on, the first time offset offset1 and the phase modulation time offset stable value step_time_offset can be compared in size, and in the case that the first time offset offset1 is greater than the phase modulation time offset stable value step_time_offset, the phase of the first clock signal is adjusted based on the first time offset.

[0064] According to the time synchronization method based on the precise network time protocol provided in the embodiments of the present application, in the case that the time offset between the first clock signal of the slave device and the second clock signal of the master device is greater than the phase modulation time offset stable value, the phase modulation stage is entered or maintained, which can not only avoid the situation that the convergence time of the time synchronization is longer due to the early entry into the frequency modulation stage, thereby shortening the convergence time of the time synchronization, but also avoid the situation that the convergence of the time synchronization cannot be achieved due to the constant presence in the phase modulation stage.

[0065] In some embodiments of the present application, the second target frequency offset value is half of the first target frequency offset value; and / or, the target control method comprises an integral control method.

[0066] In some embodiments, the second target frequency offset value freq_ppb can be half of the first target frequency offset value freq_ppb_first, i.e., half of the stable frequency offset ppb after the convergence of the time synchronization of the slave device.

[0067] In some embodiments, the target control algorithm can be any PID control-based control algorithm containing an integral control method, such as a proportional-integral (PI) control algorithm, an integral (I) control algorithm, a proportional-derivative (PD) control algorithm, or a PID control algorithm, etc.

[0068] According to the time synchronization method based on the precise network time protocol provided in the embodiments of the present application, by using half of the first target frequency offset value as the second target frequency offset value, and / or using a target control method containing an integral control method, the frequency of the first clock signal can be adjusted based on the second target frequency offset value according to the target control method in the second frequency modulation and subsequent frequency modulations, and the second target frequency offset value can be used as the initial value of the target control method, which can prevent the sudden convergence failure caused by the incorrect initial value of the target control method, thereby shortening the convergence time of the time synchronization.

[0069] In some embodiments of the present application, the time synchronization control parameter is determined, including: based on a second time deviation between the third clock signal of the sample device and the second clock signal, adjusting the phase of the third clock signal of the sample device multiple times with the phase of the second clock signal as the target, and obtaining a target fluctuation range until the second time deviation converges and lasts for a target number of times; the sample device and the slave device use the same type of crystal oscillator; the target fluctuation range is the fluctuation range of the second time deviation during the second time deviation converges and lasts for the target number of times; and the upper limit of the target fluctuation range is determined as the phase-adjusted time deviation stable value.

[0070] In actual implementation, it is relatively difficult to determine a reasonable value of the phase-adjusted time deviation stable value step_time_offset. Embodiments of the present application provide a mechanism for automatically determining or obtaining a reasonable value of the phase-adjusted time deviation stable value step_time_offset through training.

[0071] In some embodiments, the phase-adjusted time deviation stable value step_time_offset can be obtained through training by performing time synchronization between the sample device and the master device using the same type of crystal oscillator.

[0072] In some embodiments, the training process of the phase-adjusted time deviation stable value step_time_offset can include: during the time synchronization between the sample device and the master device, adjusting the clock signal (which can be referred to as the "third clock signal") of the sample device multiple times, and updating the fluctuation range [offset_min, offset_max] (i.e., the target fluctuation range) of the time deviation offset (which can be referred to as the "second time deviation offset2") between the third clock signal of the sample device and the second clock signal after each adjustment, until the second time deviation offset2 stabilizes and the target number of times CNT_MAX of stable adjustment is reached, and the value of offset_max at this time is determined as the phase-adjusted time deviation stable value step_time_offset.

[0073] In some embodiments, the target number of times CNT_MAX can be pre-set or configured according to actual conditions. The specific value of the target number of times CNT_MAX is not limited in the embodiments of the present application. For example, the default value of the target number of times CNT_MAX can be 15 times or 10 times, etc.

[0074] In some embodiments, the phase-adjusted time deviation stable value step_time_offset and other parameters obtained through training can be saved or fixed.

[0075] In some embodiments, reference is made to Figure 3A training procedure of a phase modulation time offset stable value step_time_offset can include the following steps.

[0076] Step 310, calculate a second time offset offset2 based on the PTP protocol.

[0077] According to the PTP protocol, calculate the time offset offset between the third clock signal of the update sample device and the second clock signal, denoted as the second time offset offset2.

[0078] Step 320, determine whether offset2 is stable.

[0079] Determine whether the second time offset offset2 is stable, which can include whether the difference between the second time offset offset2 calculated this time and the second time offset offset2 calculated last time (or N times, N is an integer greater than 1) is less than a threshold value, and whether the second time offset offset2 calculated this time belongs to a certain range.

[0080] If yes, step 330 can be executed; if no, step 350 can be executed.

[0081] Step 330, update the maximum value offset_max and the minimum value offset_min.

[0082] According to the second time offset offset2 calculated this time, update the maximum value offset_max and the minimum value offset_min of the second time offset offset2 during the second time offset offset2 converges and lasts for a target number of times, so as to update the target fluctuation range. The maximum value offset_max and the minimum value offset_min are respectively the upper limit and the lower limit of the target fluctuation range.

[0083] Step 340, determine whether the stable number of times < CNT_MAX.

[0084] If yes, step 350 can be executed; if no, step 360 can be executed.

[0085] Count the number of times (i.e. "stable number of times") that the second time offset offset2 is stable, and determine whether the stable number of times is less than the target number of times CNT_MAX.

[0086] Step 350, phase modulation according to offset2.

[0087] According to the second time offset offset2, phase modulate the third clock signal to adjust the phase of the third clock signal.

[0088] Step 360, the training ends, and step_time_offset = offset_max.

[0089] If the second time offset offset2 is stable for more than or equal to the target number of times CNT_MAX, the training ends, and offset_max at this time is determined as the phase adjustment time offset stable value step_time_offset.

[0090] According to the time synchronization method based on the precise network time protocol provided in the embodiments of the present application, by taking the phase of the second clock signal as the target, based on the second time offset between the third clock signal of the sample device and the second clock signal of the slave device using the same type of crystal oscillator, the phase of the third clock signal of the sample device is adjusted multiple times, and the fluctuation range of the second time offset during which the second time offset converges and lasts for the target number of times is obtained, until the second time offset converges and lasts for the target number of times, the upper limit of the fluctuation range is determined as the phase adjustment time offset stable value, which can realize more accurate determination of whether to enter the frequency adjustment phase based on the phase adjustment time offset stable value, thereby avoiding the situation that the convergence time of time synchronization is longer due to early entering of the frequency adjustment phase, thereby shortening the convergence time of time synchronization, and avoiding the situation that the phase adjustment phase is always in the phase adjustment phase and the convergence of time synchronization cannot be realized.

[0091] In some embodiments of the present application, determining the time synchronization control parameter further includes: in the case that the second time offset obtained this time belongs to the target fluctuation range, adjusting the frequency of the third clock signal of the sample device based on the target frequency offset according to the target control method until the second time offset converges and lasts for the target time length; the target frequency offset is the frequency offset between the third clock signal and the second clock signal; and the target frequency offset in the case that the second time offset converges is determined as the first target frequency offset value.

[0092] In actual implementation, it is relatively difficult to determine the reasonable value of the first target frequency offset value freq_ppb_first, and the embodiments of the present application provide a mechanism for automatically determining or obtaining the reasonable value of the first target frequency offset value freq_ppb_first.

[0093] It can be understood that the reasonable value of the first target frequency offset value freq_ppb_first is automatically determined or obtained, that is, the reasonable value of the second target frequency offset value freq_ppb is automatically determined or obtained according to the multiplication relationship between the first target frequency offset value freq_ppb_first and the second target frequency offset value freq_ppb.

[0094] In some embodiments, the training process of the first target frequency offset value freq_ppb_first can include: if the current second time offset offset2 reaches the stable time difference (i.e., offset_min < offset2 < offset_max), the frequency adjustment is performed once, if the current frequency adjustment can reach the convergence value V of the duration of the convergence of the second time offset offset2, the current target frequency offset between the third clock signal and the second clock signal (i.e., the target frequency offset) ppb_t is determined as freq_ppb_first, the training is successful and ends; otherwise, the value of ppb is adjusted for the next training until the duration of the convergence of the second time offset offset2 reaches the convergence value V. The value of the second target frequency offset value freq_ppb is freq_ppb_first / 2.

[0095] In some embodiments, the convergence value V is a target duration. The target duration can be pre-set or configured according to actual conditions. The specific value of the target duration is not limited in the embodiments of the present application. For example, the default value of the target duration can be 10 ns or 5 ns, etc.

[0096] In some embodiments, the first target frequency offset value freq_ppb_first and / or the second target frequency offset value freq_ppb obtained by training can be saved or solidified.

[0097] According to the time synchronization method based on the precise network time protocol provided in the embodiments of the present application, if the current obtained second time offset belongs to the target fluctuation range, the frequency of the third clock signal of the sample device is adjusted based on the frequency offset between the third clock signal and the second clock signal according to the target control method until the second time offset converges and lasts for a target duration, and the target frequency offset in the case of the convergence of the second time offset is determined as the first target frequency offset value. The value of the first target frequency offset value is more reasonable, and the frequency of the first clock signal can be adjusted for the first time based on the first target frequency offset value, which is adjusted to the right in one step, greatly shortening the convergence time of time synchronization.

[0098] In some embodiments of the present application, based on the target frequency offset, the frequency of the third clock signal of the sample device is adjusted multiple times according to the target control method, including: if the second time offset does not satisfy the convergence and lasts for a target duration, the target frequency offset is updated based on the current obtained second time offset and the last obtained second time offset.

[0099] In actual implementation, in a case where the duration of the second time offset offset2 not reaching the convergence value V after the last frequency adjustment, the target frequency offset ppb_t can be updated according to a size relationship between the second time offset offset2 obtained this time (i.e., the second time offset offset2 after the last frequency adjustment) and the second time offset offset2 obtained last time.

[0100] For a specific method of updating the target frequency offset ppb_t according to the size relationship between the second time offset offset2 obtained this time and the second time offset offset2 obtained last time, embodiments of the present application are not limited.

[0101] For example, in a case where the second time offset obtained this time is greater than or equal to the second time offset obtained last time, the target frequency offset can be reduced by the first frequency. Alternatively, in a case where the second time offset obtained this time is less than the second time offset obtained last time, the target frequency offset can be increased by the second frequency. For specific values of the first frequency and the second frequency, embodiments of the present application are not limited.

[0102] Based on the target frequency offset, the frequency of the third clock signal is adjusted according to a target control method.

[0103] In actual implementation, after the target frequency offset ppb_t is updated, the frequency of the third clock signal can be adjusted according to the target control method, and a new round of training is performed.

[0104] According to the time synchronization method based on the precise network time protocol provided in embodiments of the present application, in a case where the second time offset does not satisfy the convergence and lasts for a target duration, the target frequency offset is updated based on the second time offset obtained this time and the second time offset obtained last time, the value of the target frequency offset is more reasonable, the value of the first target frequency offset is more reasonable, and thus the frequency of the first clock signal can be adjusted for the first time based on the first target frequency offset, which is adjusted to the target value at one step, and the convergence time of the time synchronization is greatly shortened.

[0105] In some embodiments of the present application, updating the target frequency offset based on the second time offset obtained this time and the second time offset obtained last time includes: in a case where the second time offset obtained this time is greater than or equal to the second time offset obtained last time, the target frequency offset is reduced by 1.

[0106] In actual implementation, the value of the first frequency can be 1 (unit: Hz).

[0107] According to the time synchronization method based on the precise network time protocol provided in the embodiments of the present application, in the case that the second time offset obtained this time is greater than or equal to the second time offset obtained last time, the target frequency offset is reduced by 1, the value of the target frequency offset is more reasonable, the value of the first target frequency offset is more reasonable, so that the frequency of the first clock signal is adjusted for the first time based on the first target frequency offset, and the adjustment is completed in one step, and the convergence time of time synchronization is greatly shortened.

[0108] In some embodiments of the present application, the target frequency offset is updated based on the second time offset obtained this time and the second time offset obtained last time, and the updating includes: in the case that the second time offset obtained this time is less than the second time offset obtained last time, the target frequency offset is increased by 1.

[0109] In actual implementation, the value of the second frequency can be 1 (unit: Hz).

[0110] In some embodiments, the reference Figure 4 The training process of the first target frequency offset freq_ppb_first can include the following steps.

[0111] Step 410: calculate the second time offset offset2 based on the PTP protocol.

[0112] According to the PTP protocol, the time offset offset between the third clock signal of the sample device and the second clock signal is calculated, which is recorded as the second time offset offset2.

[0113] Step 420: determine whether offset2 converges and the duration of the convergence reaches V.

[0114] If yes, step 480 can be performed; if no, step 430 can be performed.

[0115] According to the PTP protocol, it is determined whether offset2 converges. In the case that offset2 converges, it is further determined whether the duration of the convergence of the second time offset offset2 reaches the convergence value V.

[0116] Step 430: determine whether offset_min<offset2<offset_max is satisfied.

[0117] It is determined whether offset2 falls within the target fluctuation range [offset_min, offset_max].

[0118] If yes, step 440 can be performed; if no, step 490 can be performed.

[0119] Step 440, judging whether offset2 >= offset2_pre is satisfied.

[0120] Judging whether the current acquired offset2 is greater than or equal to the last acquired offset2 (denoted as offset2_pre).

[0121] If yes, step 450 can be executed; if no, step 460 can be executed.

[0122] Step 450, ppb_t = ppb_t - 1.

[0123] In the case that the current acquired second time offset offset2 is greater than the last acquired second time offset (i.e., offset2_pre), the target frequency offset ppb_t can be updated by reducing 1 from the target frequency offset ppb_t.

[0124] Step 460, ppb_t = ppb_t + 1.

[0125] In the case that the current acquired second time offset offset2 is less than the last acquired second time offset (i.e., offset2_pre), the target frequency offset ppb_t can be updated by increasing 1 from the target frequency offset ppb_t.

[0126] Step 470, frequency tuning according to ppb_t.

[0127] The third clock signal is frequency tuned according to the updated ppb_t, so as to adjust the frequency of the third clock signal.

[0128] Step 480, training ends, freq_ppb_first = ppb_t, freq_ppb = ppb_t / 2.

[0129] When the second time offset offset2 converges and the duration reaches V, the training ends, the target frequency offset ppb_t at this time is determined as the first target frequency offset value freq_ppb_first, and half of the target frequency offset ppb_t is determined as the second target frequency offset value freq_ppb.

[0130] Step 490, phase tuning according to offset2.

[0131] The third clock signal is phase tuned according to the second time offset offset2, so as to adjust the phase of the third clock signal.

[0132] According to the time synchronization method based on the precise network time protocol provided in the embodiments of the present application, in the case that the second time deviation obtained this time is less than the second time deviation obtained last time, the target frequency deviation is increased by 1, and the value of the target frequency deviation is more reasonable, so that the value of the first target frequency deviation is more reasonable, thereby enabling the frequency of the first clock signal to be adjusted for the first time based on the first target frequency deviation, one-step adjustment, and greatly shortened convergence time of time synchronization.

[0133] In order to facilitate the understanding of the foregoing embodiments of the present application, the following describes the process of integrating the three parameters of the phase modulation time deviation stable value step_time_offset, the first target frequency deviation value freq_ppb_first and the second target frequency deviation value freq_ppb into the PI algorithm and performing time synchronization, taking the target control algorithm as the PI algorithm as an example.

[0134] The PTP-based time synchronization process based on the PI algorithm can be divided into three stages: s0, s1 and s2, and three states: unlock state, jump state and lock state are generated, and the frequency deviation (i.e., "frequency deviation") ppb between the first clock signal and the second clock signal is calculated.

[0135] In the s0 stage (referring to the first PTP period), the unlock state is returned, and the next PTP period is set to the s1 stage. In the related art, according to the precise network time protocol, no frequency modulation and phase modulation operation is performed in the unlock state, that is, the frequency modulation and phase modulation operation is performed from the second PTP period. According to the embodiments of the present application, in the s0 stage, that is, in the first PTP period, phase modulation operation is also performed, which avoids the case that no operation is performed in the unlock state in the related art, resulting in waste of one PTP period, thereby shortening the convergence time of time synchronization.

[0136] The example code is as follows: case SERVO_UNLOCKED: kd_ptp_clockadj_step_set(0,c->clkid,-tmv_to_nanoseconds(c->master_offset),1); / / new phase modulation operation.

[0137] break.

[0138] In the s1 stage, based on the PI algorithm, according to the current first time deviation offset1, if it is greater than the threshold value, the returned state is the jump state; otherwise, it is the locked state. Calculate the frequency deviation ppb between the first clock signal and the second clock signal, and set the next PTP cycle as the s2 stage. In the case where the PI algorithm returns the jump state, based on the Precision Network Time Protocol, perform a phase modulation operation according to the first time deviation offset1; in the case where the PI algorithm returns the locked state, based on the Precision Network Time Protocol, perform a frequency modulation operation according to the frequency deviation ppb between the first clock signal and the second clock signal.

[0139] In the s1 stage, in the related art, the aforementioned threshold value uses step_threshold. Since the unreasonable threshold value step_threshold may cause premature entry into the locked state or failure to enter the locked state, that is, the aforementioned situation of premature entry into the frequency modulation stage or inability to enter the frequency modulation stage will occur. In the above embodiments of the present application, the aforementioned threshold value is changed to the phase modulation time deviation stable value step_time_offset obtained through training. If the first time deviation offset1 is greater than the phase modulation time deviation stable value step_time_offset, enter the jump state; otherwise, enter the locked state.

[0140] The example code is as follows: case 1: …… if(servo->time_offset&&abs(servo->time_offset)<llabs(offset)) / / New addition to incorporate step_time_offset into the algorithm.

[0141] { *state = SERVO_JUMP; break; } else { *state = SERVO_LOCKED; } …… In the s1 stage, the adjustment amount of the frequency of the first clock signal is determined by using integration when calculating the PI. The initial value is 0 by default when the frequency offset is calculated for the first time, and the adjustment amount calculated is too small, which leads to poor effect of frequency adjustment for the first time, and the convergence of time synchronization can be achieved only after multiple PTP cycles of integration calculation and frequency adjustment. The first target frequency offset value freq_ppb_first trained is used for the first frequency adjustment, which can immediately achieve the convergence effect and avoid multiple cycle calculations, thereby greatly reducing the convergence time. Moreover, the initial value of the frequency offset for entering the s2 stage is set as the second target frequency offset value freq_ppb trained, which can prevent the incorrect calculation of the frequency offset ppb due to incorrect initial value, thereby preventing convergence failure.

[0142] The example code is as follows: case 1: … ppb = s->drift; / / original ppb value acquisition if(*state == SERVO_LOCKED) / / newly added, when the state is switched to lock, new processing is performed, otherwise the original value is maintained.

[0143] { s->drift= servo->freq_ppb; / / the trained freq_ppb is assigned to the initial value of the PI, to prevent jumping.

[0144] ppb = servo->freq_ppb_first; / / the trained freq_ppb_first is assigned to the first frequency adjustment PPB, to achieve the effect of adjusting to the position once.

[0145] } … It should be noted that the use time of the three parameters, the phase time offset stable value step_time_offset, the first target frequency offset value freq_ppb_first and the second target frequency offset value freq_ppb, can be as shown in Figure 5 .

[0146] The execution subject of the time synchronization method based on the precise network time protocol can be a time synchronization device based on the precise network time protocol. In the present application, the time synchronization device based on the precise network time protocol is taken as an example to execute the time synchronization method based on the precise network time protocol, and the time synchronization device based on the precise network time protocol provided in the present application is described.

[0147] The present application also provides a time synchronization device based on the precise network time protocol. As Figure 6As shown, the time synchronization apparatus based on the precise network time protocol comprises an acquisition module 620 and an adjustment module 630.

[0148] The determination module 610 is configured to determine a time synchronization control parameter, wherein the time synchronization control parameter comprises a phase adjustment time deviation stable value, a first target frequency deviation value and a second target frequency deviation value. The acquisition module 620 is configured to acquire a first time deviation between a first clock signal of a slave device and a second clock signal of a master device. The adjustment module 630 is configured to, in a case where the first time deviation is less than or equal to the phase adjustment time deviation stable value, enter a frequency adjustment phase, and based on the first target frequency deviation value, adjust the frequency of the first clock signal for a first time of frequency adjustment; and after the first time of frequency adjustment, based on the second target frequency deviation value, adjust the frequency of the first clock signal according to a target control method. The phase adjustment time deviation stable value is a minimum value of the first time deviation that can be reached by adjusting the phase of the first clock signal; and the first target frequency deviation value is a frequency deviation between the first clock signal and the second clock signal in a case where the first time deviation converges by adjusting the frequency of the first clock signal.

[0149] According to the time synchronization apparatus based on the precise network time protocol provided in the embodiments of the present application, by entering the frequency adjustment phase in a case where the time deviation between the first clock signal of the slave device and the second clock signal of the master device is less than or equal to the phase adjustment time deviation stable value, and by adjusting the frequency of the first clock signal based on the first target frequency deviation value for the first time of frequency adjustment, the time synchronization can be performed, and the convergence time of the time synchronization can be shortened.

[0150] In some embodiments, the adjustment module 630 can also be configured to, in a case where the first time deviation is greater than the phase adjustment time deviation stable value, adjust the phase of the first clock signal based on the first time deviation.

[0151] In some embodiments, the second target frequency deviation value is half of the first target frequency deviation value; and / or the target control method comprises an integral control method.

[0152] In some embodiments, the time synchronization apparatus based on the precise network time protocol can further comprise: The first training module is configured to, based on a second time deviation between a third clock signal of a sample device and the second clock signal, adjust the phase of the third clock signal of the sample device multiple times with the phase of the second clock signal as a target, and acquire a target fluctuation range until the second time deviation converges and lasts for a target number of times; the sample device and the slave device use the same type of crystal oscillator; an upper limit of the target fluctuation range is determined as the phase adjustment time deviation stable value; and the target fluctuation range is a fluctuation range of the second time deviation during the second time deviation converges and lasts for the target number of times.

[0153] In some embodiments, the time synchronization device based on the precise network time protocol can further comprise: The second training module is configured to, in a case where the second time deviation obtained this time belongs to the target fluctuation range, adjust the frequency of the third clock signal of the sample device according to a target control method based on a target frequency deviation until the second time deviation converges and lasts for a target duration; the target frequency deviation is a frequency deviation between the third clock signal and the second clock signal; and the target frequency deviation in the case where the second time deviation converges is determined as a first target frequency deviation value.

[0154] In some embodiments, the second training module can comprise: The updating unit is configured to, in a case where the second time deviation does not satisfy the condition of converging and lasting for the target duration, update the target frequency deviation based on the second time deviation obtained this time and the second time deviation obtained last time; The frequency adjusting unit is configured to adjust the frequency of the third clock signal according to the target control method based on the target frequency deviation.

[0155] In some embodiments, the updating unit can be specifically configured to, in a case where the second time deviation obtained this time is greater than or equal to the second time deviation obtained last time, decrease the target frequency deviation by 1.

[0156] In some embodiments, the updating unit can be specifically configured to, in a case where the second time deviation obtained this time is less than the second time deviation obtained last time, increase the target frequency deviation by 1.

[0157] The time synchronization apparatus based on the precise network time protocol in the embodiments of the present application can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other device than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a Mobile Internet Device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), and can also be a server, a Network Attached Storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, and the like, and the embodiments of the present application are not limited in this regard.

[0158] The time synchronization apparatus based on the precise network time protocol in the embodiments of the present application can be a device with an operating system. The operating system can be a Windows operating system, an Android operating system, an iOS operating system, or other possible operating system, and the embodiments of the present application are not limited in this regard.

[0159] The time synchronization apparatus based on the precise network time protocol provided in the embodiments of the present application can implement the method embodiments Figures 1 to 5 , and each process of the method embodiments is not repeated here to avoid repetition.

[0160] In some embodiments, as shown in Figure 7 , the present application further provides an electronic device 700, which includes a processor 701, a memory 702, and a computer program stored in the memory 702 and executable on the processor 701. When the computer program is executed by the processor 701, each process of the above-mentioned time synchronization method based on the precise network time protocol is implemented, and the same technical effects can be achieved, and each process is not repeated here to avoid repetition.

[0161] It should be noted that the electronic device in the embodiments of the present application includes the mobile electronic device and the non-mobile electronic device described above.

[0162] The embodiment of the present application further provides a nonvolatile computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement each process of the above-mentioned time synchronization method based on the precise network time protocol, and the same technical effects can be achieved. To avoid repetition, details are not described herein.

[0163] The processor is the processor in the electronic device in the above-mentioned embodiment. The readable storage medium includes a computer readable storage medium, such as a computer readable only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0164] The embodiment of the present application further provides a computer program product, which includes a computer program. The computer program is executed by a processor to implement the above-mentioned time synchronization method based on the precise network time protocol.

[0165] The processor is the processor in the electronic device in the above-mentioned embodiment. The readable storage medium includes a computer readable storage medium, such as a computer readable only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0166] The embodiment of the present application further provides a chip, which includes a processor and a communication interface. The communication interface is coupled with the processor. The processor is used to run a program or an instruction to implement each process of the above-mentioned time synchronization method based on the precise network time protocol, and the same technical effects can be achieved. To avoid repetition, details are not described herein.

[0167] It should be understood that the chip mentioned in the embodiment of the present application can also be referred to as a system level chip, a system chip, a chip system or a system on chip, etc.

[0168] It should be noted that, in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the present application is not limited to the order of performing the functions shown or discussed, but can also include performing the functions in a substantially simultaneous manner or in reverse order, for example, the described method can be performed in an order different from that described, and various steps can be added, omitted or combined. In addition, the features described with reference to some examples can be combined in other examples.

[0169] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned example methods can be realized by means of software and necessary general hardware platforms, and of course, they can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a computer software product in essence or in the form of a computer software product that contributes to the related art. The computer software product is stored in a storage medium (such as a ROM / RAM, a magnetic disc, an optical disc), and includes a plurality of instructions for causing a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application.

[0170] The embodiments of the present application are described above in combination with the accompanying drawings, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative and not restrictive. Those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope of protection of the claims.

[0171] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an illustrative embodiment", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0172] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A time synchronization method based on Precise Network Time Protocol, characterized in that, include: Determine the time synchronization control parameters; The time synchronization control parameters include: a stable value for phase modulation time deviation, a first target frequency deviation value, and a second target frequency deviation value; Obtain the first time deviation between the first clock signal of the slave device and the second clock signal of the master device; If the first time deviation is less than or equal to the stable value of the phase modulation time deviation, the frequency modulation stage is entered, and for the first frequency modulation, the frequency of the first clock signal is adjusted based on the first target frequency deviation value. Furthermore, after the first frequency modulation, based on the second target frequency offset value, the frequency of the first clock signal is adjusted according to the target control method. Wherein, the stable value of the phase modulation time deviation is the minimum value of the first time deviation that can be achieved by adjusting the phase of the first clock signal; the first target frequency deviation value is the frequency deviation between the first clock signal and the second clock signal when the first time deviation is converged by adjusting the frequency of the first clock signal.

2. The time synchronization method based on Precise Network Time Protocol according to claim 1, characterized in that, After acquiring the first time deviation between the first clock signal of the slave device and the second clock signal of the master device, the method further includes: If the first time deviation is greater than the stable value of the phase adjustment time deviation, the phase of the first clock signal is adjusted based on the first time deviation.

3. The time synchronization method based on Precise Network Time Protocol according to claim 1, characterized in that, The second target frequency offset value is half of the first target frequency offset value; and / or, the target control method includes an integral control method.

4. The time synchronization method based on Precise Network Time Protocol according to claim 2, characterized in that, The determination of time synchronization control parameters includes: With the phase of the second clock signal as the target, based on the second time deviation between the third clock signal of the sample device and the second clock signal, the phase of the third clock signal of the sample device is adjusted multiple times, and the target fluctuation range is obtained until the second time deviation converges and continues for the target number of times. The sample device and the slave device use the same type of crystal oscillator; The target fluctuation range is the fluctuation range of the second time deviation during the period when the second time deviation converges and continues for the target number of times; The upper limit of the target fluctuation range is determined as the stable value of the phase adjustment time deviation.

5. The time synchronization method based on Precise Network Time Protocol according to claim 4, characterized in that, The determination of time synchronization control parameters also includes: If the second time deviation obtained in this study falls within the target fluctuation range, the frequency of the third clock signal of the sample device is adjusted according to the target frequency deviation and the target control method until the second time deviation converges and lasts for the target duration. The target frequency deviation is the frequency offset between the third clock signal and the second clock signal; The target frequency deviation when the second time deviation converges is determined as the first target frequency deviation value.

6. The time synchronization method based on Precise Network Time Protocol according to claim 5, characterized in that, The step of adjusting the frequency of the third clock signal of the sample device multiple times based on the target frequency deviation and according to the target control method includes: If the second time deviation does not meet the convergence requirement and continues for the target duration, the target frequency deviation is updated based on the second time deviation obtained this time and the second time deviation obtained last time. Based on the target frequency deviation, the frequency of the third clock signal is adjusted according to the target control method.

7. The time synchronization method based on Precise Network Time Protocol according to claim 6, characterized in that, The step of updating the target frequency deviation based on the second time deviation obtained this time and the second time deviation obtained previously includes: If the second time deviation obtained this time is greater than or equal to the second time deviation obtained in the previous time, the target frequency deviation is reduced by 1; If the second time deviation obtained this time is less than the second time deviation obtained in the previous time, the target frequency deviation is incremented by 1.

8. A time synchronization device based on a precise network time protocol, characterized in that, include: The determination module is used to determine the time synchronization control parameters; The time synchronization control parameters include: a stable value for phase modulation time deviation, a first target frequency deviation value, and a second target frequency deviation value; The acquisition module is used to acquire the first time deviation between the first clock signal of the slave device and the second clock signal of the master device; The adjustment module is configured to enter the frequency modulation stage when the first time deviation is less than or equal to the stable value of the phase modulation time deviation, and adjust the frequency of the first clock signal based on the first target frequency deviation value for the first frequency modulation; and after the first frequency modulation, adjust the frequency of the first clock signal based on the second target frequency deviation value and according to the target control method. Wherein, the stable value of the phase modulation time deviation is the minimum value of the first time deviation that can be achieved by adjusting the phase of the first clock signal; the first target frequency deviation value is the frequency deviation between the first clock signal and the second clock signal when the first time deviation is converged by adjusting the frequency of the first clock signal.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the time synchronization method based on the Precise Network Time Protocol as described in any one of claims 1-7.

10. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the time synchronization method based on the Precise Network Time Protocol as described in any one of claims 1-7.

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