Semiconductor memory device

Abstract

A semiconductor memory device may include a molding structure including a plurality of molding stacks each including a plurality of gate electrodes stacked in a first direction, a first surface of the molding structure being opposite to a second surface of the molding structure in the first direction; a capacitor structure penetrating at least one of the molded stacks in a first direction from a first surface of the molded structure; a cap filling insulating film penetrating at least one of the molding stacks in the first direction from the second surface of the molding structure, and connected to the capacitor structure in the first direction; and a channel structure penetrating the molding structure in the first direction. The capacitor structure and the cap filling insulating film may not overlap in a direction crossing the first direction.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0129415, filed with the Korean Intellectual Property Office on September 24, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor storage device. Background Technology

[0004] Since electronic systems may require semiconductor memory devices to store large amounts of data, methods for increasing the data storage capacity of semiconductor memory devices can be investigated. As one method for increasing the data storage capacity of semiconductor memory devices, a semiconductor memory device comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells is proposed.

[0005] As the input / output speeds of semiconductor memory devices increase, precise control of noise in the signal may become necessary. Input / output speeds can be improved by using high-capacity capacitors to remove noise from the signal. Summary of the Invention

[0006] On the one hand, a semiconductor memory device with improved input / output signal quality is provided.

[0007] However, the aspects of the exemplary embodiments of this disclosure are not limited to those described above, and those skilled in the art will clearly understand other aspects based on the following exemplary embodiments.

[0008] According to an embodiment, a semiconductor memory device may include: a molded structure including a plurality of gate electrodes stacked in a first direction, the molded structure including a first molded portion and a second molded portion disposed in the first direction, the molded structure including a capacitor aperture penetrating the molded structure in the first direction; a capacitor structure in the capacitor aperture and penetrating a portion of the molded structure in the first direction, the capacitor structure including a dielectric film and an electrode film; and a cap-filled insulating film in the capacitor aperture, the cap-filled insulating film penetrating at least a portion of the molded structure in the first direction and overlapping the capacitor structure in the first direction. The capacitor aperture may include a first aperture portion in the first molded portion and a second aperture portion in the second molded portion. The first aperture portion may not penetrate the second molded portion. The second aperture portion may be connected to the first aperture portion and may not penetrate the first molded portion. The dielectric film may extend along the first aperture portion and may not extend along the second aperture portion.

[0009] According to an embodiment, a semiconductor memory device may include: a molded structure comprising a plurality of molded stacks, each of the plurality of molded stacks including a plurality of gate electrodes stacked in a first direction, a first surface of the molded structure opposite to a second surface of the molded structure in the first direction; a capacitor structure penetrating at least one of the plurality of molded stacks from the first surface of the molded structure in the first direction; a cap-filled insulating film penetrating at least one of the plurality of molded stacks from the second surface of the molded structure in the first direction, and the cap-filled insulating film being connected to the capacitor structure in the first direction; and a channel structure penetrating the molded structure in the first direction. The capacitor structure and the cap-filled insulating film may not overlap in a direction intersecting the first direction.

[0010] According to an embodiment, a semiconductor memory device may include: a molded structure including a plurality of gate electrodes stacked in a first direction, the molded structure including a first molded portion and a second molded portion disposed in the first direction; an interlayer insulating film covering the molded structure; a capacitor structure penetrating the first molded portion in the first direction, the capacitor structure including a dielectric film and an electrode film; a cap-filled insulating film penetrating the second molded portion in the first direction and overlapping the capacitor structure in the first direction; a contact plug penetrating the interlayer insulating film, the contact plug being electrically connected to the capacitor structure; and input / output pads on the interlayer insulating film and connected to the contact plug. The capacitor structure may not overlap with the second molded portion in a direction intersecting the first direction. The cap-filled insulating film may not overlap with the first molded portion in a direction intersecting the first direction.

[0011] Additional aspects of the exemplary embodiments will be set forth in part in the following description and accompanying drawings.

[0012] According to the example embodiments, the quality of input / output signals of semiconductor memory devices can be improved. Attached Figure Description

[0013] These and / or other aspects, features, and advantages of the present invention will become clear and more readily understood from the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0014] Figure 1 These are example block diagrams used to describe semiconductor memory devices according to some example embodiments;

[0015] Figure 2 These are example circuit diagrams used to describe semiconductor memory devices according to some example embodiments;

[0016] Figure 3 It is a schematic layout diagram used to describe a semiconductor memory device according to some example embodiments;

[0017] Figure 4 It shows along Figure 3 Example diagram of the cross section intercepted by line A-A';

[0018] Figure 5 It shows Figure 4 An enlarged example diagram of part of R1;

[0019] Figure 6 It shows Figure 4 A magnified example diagram of part of R2;

[0020] Figure 7 It shows Figure 4 Another example diagram with an enlarged portion of R2;

[0021] Figure 8 It shows along Figure 3 Example diagram of the cross section intercepted by line B-B';

[0022] Figure 9 It shows along Figure 3 Another example diagram of a cross-section taken by line A-A' is used to describe a semiconductor memory device according to some other example embodiments;

[0023] Figure 10 It shows along Figure 3 Another example diagram of a cross section taken by line A-A' is used to describe a semiconductor memory device according to yet another example embodiment;

[0024] Figure 11 It shows along Figure 3 Another example diagram of a cross section taken by line A-A' is used to describe a semiconductor memory device according to yet another example embodiment;

[0025] Figures 12 to 28 This is a diagram illustrating the operation of a method for manufacturing a semiconductor memory device according to some example embodiments;

[0026] Figure 29 These are example diagrams used to describe electronic systems including semiconductor memory devices according to some example embodiments;

[0027] Figure 30 These are example perspective views used to describe electronic systems including semiconductor memory devices according to some example embodiments; and

[0028] Figure 31 It shows along Figure 30 Example diagram of the cross section taken by line II. Detailed Implementation

[0029] Before describing the exemplary embodiments, the terms or words used in this disclosure and the appended claims are not limited to their general or dictionary definitions. The terms and words should be interpreted in accordance with the principle that the inventor can appropriately define the concepts of the terms in order to best describe the inventive concept. Therefore, since the exemplary embodiments described in this disclosure and the configurations shown in the accompanying drawings are merely the most ideal exemplary embodiments and do not represent the full technical spirit of this disclosure, it should be understood that various equivalents and modifications may exist to replace the exemplary embodiments and configurations when this application is filed.

[0030] In the following description, unless there is an obvious conflict in the context, singular terms include plural terms. Terms such as “comprising” or “including” indicate the presence of features, numbers, operations, actions, elements, components, or combinations thereof. It should be understood that these terms do not preclude the possibility that one or more other features, numbers, operations, actions, elements, components, or combinations thereof may be present or added.

[0031] In the following description, terms including ordinal numbers (e.g., "first" or "second") used in this specification may be used to describe various elements. However, elements may not be limited to terms including ordinal numbers. These terms may be used to distinguish one element from another in a part of the specification. Within the scope of the technical spirit of this disclosure, a first element may be referred to as a second element in another part of the specification, and vice versa. Furthermore, in the accompanying drawings, the shape, size, etc., of the elements may be exaggerated for clarity.

[0032] Furthermore, it should be noted beforehand that expressions such as upper side, upper part, lower side, lower part, side surface, front surface, or rear surface are based on the orientation shown in the figures, and the expressions may change when the orientation of the corresponding object changes. For clarity, the shape, size, etc., of elements in the figures may be exaggerated. Although the term "identical" is used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is described as "identical" to another element, it should be understood that the element or value may be "identical" to the other element within the expected manufacturing or operational tolerances (e.g., ±10%).

[0033] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0034] Figure 1 This is an example block diagram used to describe a semiconductor memory device according to some example embodiments.

[0035] Reference Figure 1According to some example embodiments, the semiconductor memory device 10 may include a memory cell array 20 and peripheral circuitry 30.

[0036] According to some example embodiments, the memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 can be connected to the peripheral circuitry 30 via bit line BL, word line WL, at least one serial select line SSL, and at least one ground select line GSL. Specifically, the memory cell blocks BLK1 to BLKn can be connected to the row decoder 33 via word line WL, serial select line SSL, and ground select line GSL. In addition, the memory cell blocks BLK1 to BLKn can be connected to the page buffer 35 via bit line BL.

[0037] According to some example embodiments, peripheral circuitry 30 can receive address ADDR, command CMD, and control signal CTRL from outside the semiconductor memory device 10, and can send data DATA to and receive data DATA from devices outside the semiconductor memory device 10. Peripheral circuitry 30 may include control logic 37, a row decoder 33, and a page buffer 35. Although not shown, peripheral circuitry 30 may also include various sub-circuits, such as voltage generation circuitry for generating various voltages required for the operation of the semiconductor memory device 10, and error correction circuitry for correcting errors in the data DATA read from the memory cell array 20.

[0038] According to some example embodiments, control logic 37 can be connected to line decoder 33, input / output circuitry, and voltage generation circuitry. Control logic 37 can control the overall operation of semiconductor memory device 10. Control logic 37 can generate various internal control signals used in semiconductor memory device 10 in response to control signal CTRL. For example, when performing memory operations such as programming or erasing operations, control logic 37 can adjust the voltage levels provided via word line WL and bit line BL.

[0039] According to some example embodiments, the row decoder 33 can select at least one memory cell block from a plurality of memory cell blocks BLK1 to BLKn in response to address ADDR, and can select the word line WL, serial select line SSL, and ground select line GSL of the at least one memory cell block selected from the plurality of memory cell blocks BLK1 to BLKn. Furthermore, the row decoder 33 can transmit voltage for performing memory operations to the word line WL of the selected memory cell block BLK1 to BLKn.

[0040] According to some example embodiments, page buffer 35 can be connected to memory cell array 20 via bit line BL. Page buffer 35 can operate as a write driver or a sense amplifier. Specifically, when performing a programming operation, page buffer 35 can operate as a write driver to apply a voltage according to the data DATA to be stored in memory cell array 20 to bit line BL. Simultaneously, when performing a read operation, page buffer 35 can operate as a sense amplifier to read the data DATA stored in memory cell array 20.

[0041] Figure 2 These are example circuit diagrams used to describe semiconductor memory devices according to some example embodiments.

[0042] Reference Figure 2 Array of memory cells of semiconductor memory devices according to some example embodiments (e.g., Figure 1 The storage cell array 20 may include a common source line CSL, multiple bit lines BL and multiple cell strings CSTR.

[0043] According to some example embodiments, multiple bit lines BL can be arranged two-dimensionally on a plane including a second direction D2 and a third direction D3. For example, each of the bit lines BL can extend in the third direction D3, and the bit lines BL can be spaced apart from each other to be arranged in the second direction D2. Multiple cell strings CSTR can be connected in parallel to each bit line BL. The cell strings CSTR can be collectively connected to a common source line CSL. In other words, multiple cell strings CSTR can be disposed between the bit line BL and the common source line CSL. The multiple cell strings CSTR can extend in the first direction D1.

[0044] According to some example embodiments, each of the plurality of cell strings CSTRs may include a ground select transistor GST connected to a common source line CSL, a string select transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCTs disposed between the ground select transistor GST and the string select transistor SST. Each of the memory cell transistors MCTs may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistors MCTs may be connected in series.

[0045] According to some example embodiments, the common source line CSL can be commonly connected to the source of the ground select transistor GST. Furthermore, the ground select line GSL, multiple word lines WL, and serial select line SSL can be disposed between the common source line GSL and the bit line BL. The ground select line GSL can be used as the gate electrode of the ground select transistor GST. The multiple word lines WL can be used as the gate electrode of the memory cell transistor MCT. The serial select line SSL can be used as the gate electrode of the serial select transistor SST.

[0046] Figure 3 It is a schematic layout diagram used to describe a semiconductor memory device according to some example embodiments. Figure 4 It shows along Figure 3 Example diagram of the cross section taken by line A-A'. Figure 5 It shows Figure 4 A magnified example diagram of part R1. Figure 6 It shows Figure 4 A magnified example diagram of part of R2. Figure 7 It shows Figure 4 Another example diagram of a magnified portion of R2. Figure 8 It shows along Figure 3 Example diagram of the cross section taken by line B-B'.

[0047] Reference Figures 3 to 8 According to some example embodiments, a semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (PERI).

[0048] According to some example embodiments, the cell structure CELL may include a cell substrate 100, an insulating substrate 101, a molded structure MS, a first interlayer insulating film 140a, a second interlayer insulating film 140b, a gate electrode dicing pattern WLC, a channel structure CH, a bit line BL, a capacitor structure CAP, a cap-filled insulating film 193, a cell contact portion 162, a cell wiring structure 180, and input / output pads 320.

[0049] According to some example embodiments, the unit substrate 100 may include, for example, a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the unit substrate 100 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

[0050] According to some example embodiments, the cell substrate 100 may include impurities. For example, the cell substrate 100 may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.). However, this is merely an example. For example, the cell substrate 100 may also include p-type impurities. The cell substrate 100 may include polycrystalline silicon (poly-Si) doped with n-type impurities. According to some example embodiments, the cell substrate 100 may be configured as a common source line of a semiconductor memory device (e.g., Figure 2 The common source line (CSL).

[0051] According to some example embodiments, the cell substrate 100 may include a cell array region CAR and an extension region EXT.

[0052] According to some example embodiments, a storage cell array comprising multiple storage cells can be formed in the cell array region (CAR) (e.g., Figure 1The memory cell array 20. For example, the channel structure CH, bit line BL, multiple gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL, etc., which will be described below, can be set in the cell array region CAR. In the following description, the surface of the cell substrate 100 on which the memory cell array is disposed can be referred to as the first surface 100a of the cell substrate. The first surface 100a of the cell substrate can be the front side of the cell substrate 100. Conversely, the surface of the cell substrate 100 opposite to the first surface 100a of the cell substrate can be referred to as the second surface 100b of the cell substrate. The second surface 100b of the cell substrate can be the back side of the cell substrate 100.

[0053] According to some example embodiments, the gate electrode dicing pattern WLC can extend in a first direction D1. The gate electrode dicing pattern WLC can penetrate the molding structure MS in the first direction D1. Specifically, the gate electrode dicing pattern WLC can extend along a plane including the first direction D1 and the second direction D2. The gate electrode dicing pattern WLC can extend from the cell substrate 100 in the first direction D1 to dicing a plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL. The gate electrode dicing pattern WLC can dicing a plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL along a plane including the first direction D1 and the second direction D2. For example, the gate electrode dicing pattern WLC can divide the molding structure MS into a first block BLK1 and a second block BLK2 by penetrating the molding structure MS. The gate electrode dicing pattern WLC may include an insulating material (e.g., at least one of silicon oxide, silicon nitride, and silicon oxynitride), but this is just an example.

[0054] According to some example embodiments, the gate electrode dicing pattern WLC can extend in the second direction D2. The gate electrode dicing pattern WLC can extend across the cell array region CAR and the extension region EXT. For example, the gate electrode dicing pattern WLC can extend across the cell array region CAR and the extension region EXT configured to be adjacent to the cell array region CAR in the second direction D2.

[0055] According to some example embodiments, the gate electrode cutting patterns WLC can be spaced apart from each other on the third direction D3. The gate electrode cutting patterns WLC can divide the molded structure MS into multiple blocks on the third direction D3. Multiple blocks can be arranged on the third direction D3. The multiple blocks may include a first block BLK1 and a second block BLK2. The gate electrode cutting patterns WLC can be arranged between the first block BLK1 and the second block BLK2. The gate electrode cutting patterns WLC can be arranged between two adjacent blocks. Each of the first block BLK1 and the second block BLK2 can be arranged between two adjacent gate electrode cutting patterns WLC along the third direction D3.

[0056] According to some example embodiments, the molded structure MS may include a first BLK1 and a second BLK2. The first BLK1 and the second BLK2 may be disposed on a third-party D3. On the third-party D3, the first BLK1 may be disposed outside the second BLK2.

[0057] According to some example embodiments, the extended region EXT can be disposed around the cell array region CAR. For example, when viewed in a plan view, the extended region EXT can surround the cell array region CAR. The plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL, which will be described below, can be stacked in a stepped manner within the extended region EXT. However, this is merely an example. For example, in the extended region EXT, the plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL can be stacked without a stepped manner, and each gate electrode can be stacked on a plane including the second direction D2 and the third direction D3, while having equal areas to each other.

[0058] According to some example embodiments, an insulating substrate 101 may be formed around the unit substrate 100. The insulating substrate 101 may form an insulating region around the unit substrate 100. The insulating substrate 101 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, but these are merely examples.

[0059] According to some example embodiments, the lower surface of the insulating substrate 101 is shown only as being disposed on a plane common to the first surface 100a of the unit substrate, but this is merely an example. As another example, the lower surface of the insulating substrate 101 may be lower than the first surface 100a of the unit substrate.

[0060] According to some example embodiments, the cell substrate 100 and the insulating substrate 101 may further include an outer region OR. The outer region OR may be disposed outside the cell array region CAR and the extension region EXT. For example, when viewed in a plan view, the outer region OR may surround the cell array region CAR and the extension region EXT. The contact plug 166, which will be described below, may be disposed in the outer region OR.

[0061] According to some example embodiments, a molded structure MS can be formed on a first surface 100a of a unit substrate. The molded structure MS may include a plurality of molded insulating films 111, 112, 113, and 114, and a plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL stacked on the unit substrate 100. The plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL, as well as the plurality of molded insulating films 111, 112, 113, and 114, may be a layered structure extending parallel to the first surface 100a of the unit substrate. Multiple gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL may be spaced apart from each other by multiple molded insulating films 111, 112, 113, and 114 and stacked on the first surface 100a of the cell substrate. The multiple gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL are shown as including only one ground select line GSL and one string select line SSL, but this is merely an example. The multiple gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL may also include two or more ground select lines and two or more string select lines.

[0062] According to some example embodiments, the molded structure MS may include a plurality of molded stacks MS1, MS2, MS3 and MS4 stacked sequentially on a first surface 100a of the cell substrate. For example, the molded structure MS may include a first molded stack MS1, a second molded stack MS2, a third molded stack MS3 and a fourth molded stack MS4.

[0063] According to some example embodiments, a first molded stack MS1 may include a first gate electrode GSL and WL1 to WL1n alternately stacked on a cell substrate 100, and a plurality of first molded insulating films 111. In some example embodiments, the first gate electrode GSL and WL1 to WL1n may include a ground select line GSL and first word lines WL1 to WL1n stacked sequentially on a cell substrate 100. A second molded stack MS2 may include a second gate electrode WL21 to WL2n alternately stacked on a first molded stack MS1, and a plurality of second molded insulating films 112. In some example embodiments, the second gate electrodes WL21 to WL2n may include second word lines WL21 to WL2n stacked sequentially on a first molded stack MS1. A third molded stack MS3 may include a third gate electrode WL31 to WL3n alternately stacked on a second molded stack MS2, and a plurality of third molded insulating films 113. In some example embodiments, the third gate electrodes WL31 to WL3n may include third word lines WL31 to WL3n stacked sequentially on the second molding stack MS2. The fourth molding stack MS4 may include fourth gate electrodes WL41 to WL4n and SSL alternately stacked on the third molding stack MS3, as well as a plurality of fourth molding insulating films 114. In some example embodiments, the fourth gate electrodes WL41 to WL4n and SSL may include fourth word lines WL41 to WL4n and a string select line SSL stacked sequentially on the third molding stack MS3.

[0064] According to some example embodiments, each of the plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n and SSL may include a conductive material (e.g., a semiconductor material, such as a metal including tungsten (W), cobalt (Co), nickel (Ni) or silicon), but this is merely an example.

[0065] According to some example embodiments, each of the plurality of molded insulating films 111, 112, 113, and 114 may include an insulating material. For example, the plurality of molded insulating films 111, 112, 113, and 114 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, but this is merely an example.

[0066] According to some example embodiments, the molded structure MS may include a first molded portion MP1 and a second molded portion MP2. The first molded portion MP1 and the second molded portion MP2 may be disposed in a first direction D1. The first molded portion MP1 may be a portion of the molded structure MS penetrated by the capacitor structure CAP. For example, the first molded portion MP1 may include a third molded stack MS3 and a fourth molded stack MS4. The second molded portion MP2 may be a portion of the molded structure MS penetrated by the cap-filled insulating film 193. For example, the second molded portion MP2 may include the first molded stack MS1 and the second molded stack MS2.

[0067] According to some example embodiments, the molded structure MS may include a first surface MS_S1 and a second surface MS_S2 disposed opposite to each other in a first direction D1. The first surface MS_S1 may face the peripheral circuit structure PERI. The second surface MS_S2 may be disposed opposite to the first surface MS_S1 in the first direction D1. However, this is merely an example. For instance, the second surface MS_S2 may face the peripheral circuit structure PERI, and the first surface MS_S1 may be a surface disposed opposite to the second surface MS_S2 in the first direction D1.

[0068] According to some example embodiments, a first interlayer insulating film 140a may be formed on the insulating substrate 101 and / or the first surface 100a of the unit substrate to cover at least a portion of the molded structure MS. For example, the first interlayer insulating film 140a may cover a first molded stack MS1 and a second molded stack MS2. The first interlayer insulating film 140a may include at least one of, for example, silicon oxide, silicon oxynitride, and a low-k material with a dielectric constant lower than that of silicon oxide, but this is merely an example.

[0069] According to some example embodiments, the second interlayer insulating film 140b may cover at least a portion of the molded structure MS beneath the first surface 100a of the insulating substrate 101 and / or the unit substrate. For example, the second interlayer insulating film 140b may cover the third molded stack MS3 and the fourth molded stack MS4. The second interlayer insulating film 140b may include at least one of, for example, silicon oxide, silicon oxynitride, and a low-k material with a dielectric constant lower than that of silicon oxide, but this is merely an example.

[0070] According to some example embodiments, a channel structure CH can be formed in a molded structure MS within a cell array region CAR. The channel structure CH can extend in a first direction D1 perpendicular to a first surface 100a of the cell substrate to penetrate the molded structure MS. The channel structure CH can be disposed in a second block BLK2. The channel structure CH can penetrate the molded structure MS in the second block BLK2 in the first direction D1. For example, the channel structure CH can have a cylindrical shape (e.g., a cylindrical shape) extending in the first direction D1. Accordingly, the channel structure CH can intersect each of the plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL.

[0071] According to some example embodiments, the channel structure CH may have a curved portion in the molding structure MS. The channel structure CH may have a curved portion between the first molding stack MS1, the second molding stack MS2, the third molding stack MS3, and the fourth molding stack MS4. The channel structure CH may have a curved portion at the boundary between the first molding stack MS1 and the second molding stack MS2. The channel structure CH may have a step at the boundary between the first molding stack MS1 and the second molding stack MS2. The channel structure CH may have a curved portion at the boundary between the second molding stack MS2 and the third molding stack MS3. The channel structure CH may have a step at the boundary between the second molding stack MS2 and the third molding stack MS3. The channel structure CH may have a curved portion at the boundary between the third molding stack MS3 and the fourth molding stack MS4. The channel structure CH may have a step at the boundary between the third molding stack MS3 and the fourth molding stack MS4.

[0072] According to some example embodiments, the channel structures CH can be arranged in a zigzag pattern. For example, the channel structures CH can be staggered in a second direction D2 and a third direction D3 parallel to the first surface 100a of the cell substrate. Multiple channel structures CH arranged in a zigzag pattern can further improve the integration density of the semiconductor memory device. According to some example embodiments, multiple channel structures CH can be arranged in a honeycomb pattern.

[0073] According to some example embodiments, the channel structure CH may include a semiconductor pattern 130 and an information storage film 132.

[0074] According to some example embodiments, the semiconductor pattern 130 may extend in a first direction D1 to intersect with a plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL. Only a cup-shaped semiconductor pattern 130 is shown, but this is merely an example. For example, the semiconductor pattern 130 may have various shapes, such as cylindrical, quadrilateral container-shaped, or filler-shaped. The semiconductor pattern 130 may include, for example, semiconductor materials such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures, but this is merely an example.

[0075] According to some example embodiments, the semiconductor pattern 130 may be attached to the cell substrate 100. For example, an end (e.g., an upper end) of the semiconductor pattern 130 may be exposed from the information storage film 132 to attach to the cell substrate 100. According to some example embodiments, the semiconductor pattern 130 may penetrate a first surface 100a of the cell substrate 100. For example, an end (e.g., an upper end) of the semiconductor pattern 130 may protrude further into the cell substrate 100 than the information storage film 132. The semiconductor pattern 130 can improve contact resistance by increasing the area of ​​contact with the cell substrate 100.

[0076] According to some example embodiments, the information storage film 132 may be situated between the semiconductor pattern 130 and each of the plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL. For example, the information storage film 132 may extend along the outer surface of the semiconductor pattern 130. The information storage film 132 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant materials with a dielectric constant higher than that of silicon oxide. High dielectric constant materials may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0077] According to some example embodiments, the information storage film 132 can be formed as a multilayer film. For example, such as Figure 5 As shown, the information storage film 132 may include a tunnel insulating film 132a, a charge storage film 132b, and a barrier insulating film 132c stacked sequentially on the outer surface of the semiconductor pattern 130.

[0078] According to some example embodiments, the tunnel insulating film 132a may include, for example, silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). The charge storage film 132b may include, for example, silicon nitride. According to some example embodiments, the barrier insulating film 132c may include, for example, silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)).

[0079] According to some example embodiments, the channel structure CH may also include a filling insulating film 134. The filling insulating film 134 may be formed to fill the interior of a semiconductor pattern 130 having a cup shape. The filling insulating film 134 may include an insulating material (e.g., silicon oxide), but this is merely an example.

[0080] According to some example embodiments, the channel structure CH may also include a channel pad 136. The channel pad 136 may be formed to connect to the other end (e.g., the lower end) of the semiconductor pattern 130. The channel pad 136 may include a conductive material (e.g., doped polysilicon, metal, etc.), but this is merely an example.

[0081] According to some example embodiments, a bit line BL can be formed beneath the molded structure MS. The bit line BL can extend in the third direction D3 to intersect the gate electrode dicing pattern WLC. Furthermore, the bit line BL can extend in the third direction D3 to connect to multiple channel structures CH arranged in the third direction D3. For example, a bit line contact 182 connecting to the upper portion of each channel structure CH can be formed in the second interlayer insulating film 140b. The bit line BL can be electrically connected to the channel structures CH through the bit line contact 182.

[0082] According to some example embodiments, the bit line BL can be disposed below the first surface MS_S1 of the molded structure. In the first direction D1, the bit line BL can be disposed below the fourth molded stack MS4. However, this is merely an example. According to some example embodiments, the bit line BL can be disposed on the second surface MS_S2 of the molded structure. In the first direction D1, the bit line BL can be disposed on the first molded stack MS1.

[0083] According to some example embodiments, a capacitor structure CAP can be set in the first BLK1. Multiple capacitor structures CAP can be set.

[0084] According to some example embodiments, the capacitor structure CAP can penetrate a portion of the molded structure MS in the first BLK1. The capacitor structure CAP can penetrate a portion of the molded structure MS from the first surface MS_S1 of the molded structure in the first direction D1. The capacitor structure CAP can penetrate the first surface MS_S1 of the molded structure. For example, the capacitor structure CAP can penetrate the third molded stack MS3 and the fourth molded stack MS4, but can not penetrate the first molded stack MS1 and the second molded stack MS2.

[0085] According to some example embodiments, the capacitor structure CAP may penetrate the first molded portion MP1. The capacitor structure CAP may overlap the first molded portion MP1 in a direction intersecting the first direction D1 (e.g., a second direction D2 or a third direction D3). For example, the direction intersecting the first direction D1 may include a direction parallel to the cell substrate 100. The capacitor structure CAP may not penetrate the second molded portion MP2. The capacitor structure CAP may not overlap the second molded portion MP2 in a direction intersecting the first direction D1.

[0086] According to some example embodiments, a capacitor structure CAP can be disposed in a capacitor hole CAP_H. The capacitor hole CAP_H can penetrate the molding structure MS in a first direction D1. The capacitor hole CAP_H can include a first hole portion CAP_H_P1 and a second hole portion CAP_H_P2. The first hole portion CAP_H_P1 and the second hole portion CAP_H_P2 can be disposed in the first direction D1. The first hole portion CAP_H_P1 and the second hole portion CAP_H_P2 can be connected in the first direction D1.

[0087] According to some example embodiments, the first hole portion CAP_H_P1 can penetrate the first molded portion MP1. The first hole portion CAP_H_P1 can not penetrate the second molded portion MP2. The second hole portion CAP_H_P2 can penetrate the second molded portion MP2. The second hole portion CAP_H_P2 can not penetrate the first molded portion MP1.

[0088] According to some example embodiments, the capacitor structure CAP can be disposed along the first hole portion CAP_H_P1. For example, the dielectric film 191 of the capacitor structure CAP can extend along the first hole portion CAP_H_P1. The dielectric film 191 may not extend along the second hole portion CAP_H_P2. The electrode film 192 can be disposed on the dielectric film 191 in the first hole portion CAP_H_P1. The electrode film 192 may not be disposed in the second hole portion CAP_H_P2.

[0089] According to some example embodiments, the capacitor structure CAP can be connected to the cap-filled insulating film 193 in a first direction D1. The capacitor structure CAP can overlap with the cap-filled insulating film 193 in the first direction D1. The capacitor structure CAP and the cap-filled insulating film 193 can not overlap in a direction intersecting the first direction D1. The capacitor structure CAP can be connected to the cap-filled insulating film 193 at one of the boundaries between the plurality of molded stacks MS1, MS2, MS3, and MS4. The capacitor structure CAP and the cap-filled insulating film 193 can be in direct contact with each other to be connected at one of the boundaries between the plurality of molded stacks MS1, MS2, MS3, and MS4. For example, the capacitor structure CAP can contact the cap-filled insulating film 193 at the boundary between the second molded stack MS2 and the third molded stack MS3.

[0090] According to some example embodiments, the capacitor structure CAP may include a dielectric film 191 and an electrode film 192.

[0091] According to some example embodiments, the dielectric film 191 may extend along a side surface of the electrode film 192. The dielectric film 191 may contact the molded structure MS. The dielectric film 191 may surround the electrode film 192.

[0092] According to some example embodiments, dielectric film 191 may comprise silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant materials including metals. Dielectric film 191 is shown as a monolayer film, but this is merely for ease of description and is only an example.

[0093] According to some example embodiments, dielectric film 191 may include a stacked structure in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in a sequential order. Dielectric film 191 may include a dielectric film containing hafnium (Hf). Dielectric film 191 may have a stacked structure of ferroelectric material film and paraelectric material film.

[0094] According to some example embodiments, the electrode film 192 may be disposed on the dielectric film 191. The electrode film 192 may be surrounded by the dielectric film 191. The electrode film 192 may include, for example, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc.), metals (e.g., ruthenium, iridium, titanium, tantalum, etc.), conductive metal oxides (e.g., iridium oxide, niobium oxide, etc.), etc., but these are merely examples.

[0095] According to some example embodiments, a capacitor may be formed from an electrode film 192, a dielectric film 191, a plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL. For example, each capacitor structure CAP may have an equivalent circuit in which a plurality of capacitors formed by a plurality of word lines WL, an electrode film 192, and a dielectric film 191 between the plurality of word lines WL and the electrode film 192 are connected in parallel.

[0096] According to some example embodiments, the capacitor structure CAP can be arranged in the same shape as the channel structure CH. For example, the capacitor structure CAP can be arranged in a zigzag pattern. The capacitor structure CAP can be staggered in the second direction D2 and the third direction D3. The capacitor structure CAP can be arranged in a honeycomb pattern.

[0097] According to some example embodiments, the maximum width of the capacitor structure CAP and the maximum width of the channel structure CH can be equal. The maximum width of the capacitor structure CAP can be the diameter of the capacitor structure CAP at the boundary between the molded stacks MS1, MS2, MS3, and MS4. The maximum width of the channel structure CH can be the diameter of the channel structure CH at the boundary between the molded stacks MS1, MS2, MS3, and MS4. For example, the width of the capacitor structure CAP can be equal to the width of the cap-filled insulating film 193 at the boundary between the first molded stack MS1 and the second molded stack MS2. However, this is merely an example. The maximum width of the capacitor structure CAP and the maximum width of the channel structure CH can be different.

[0098] Reference Figure 6 The electrode film 192 of the capacitor structure CAP can contact the cap-filled insulating film 193. The electrode film 192 and the cap-filled insulating film 193 can contact each other at the boundary between the molded stacks MS1, MS2, MS3, and MS4, where the capacitor structure CAP and the cap-filled insulating film 193 are connected. For example, the upper surface 192b of the electrode film can directly contact the lower surface 193a of the cap-filled insulating film at the boundary between the second molded stack MS2 and the third molded stack MS3.

[0099] According to some example embodiments, the dielectric film 191 may not cover the upper surface 192b of the electrode film. The dielectric film 191 and the electrode film 192 may not overlap each other in the first direction D1. The dielectric film 191 may extend along the side surface of the electrode film 192. The upper surface 191b of the dielectric film and the upper surface 192b of the electrode film may be disposed in the same plane. The upper surface 191b of the dielectric film may contact the lower surface 193a of the cap-filled insulating film.

[0100] Reference Figure 7The electrode film 192 of the capacitor structure CAP may not be in contact with the cap-filled insulating film 193. The electrode film 192 and the cap-filled insulating film 193 may be spaced apart at the boundary between multiple molded stacks MS1, MS2, MS3, and MS4, where the capacitor structure CAP and the cap-filled insulating film 193 are connected. For example, the upper surface 192b of the electrode film may be spaced apart from the lower surface 193a of the cap-filled insulating film at the boundary between the second molded stack MS2 and the third molded stack MS3, with the dielectric film 191 between the upper surface 192b of the electrode film and the lower surface 193a of the cap-filled insulating film.

[0101] According to some example embodiments, in a first direction D1, a dielectric film 191 may be disposed between an electrode film 192 and a cap-filled insulating film 193. The dielectric film 191 may cover the upper surface 192b of the electrode film. The dielectric film 191 and the electrode film 192 may overlap each other in the first direction D1. The dielectric film 191 may extend along the upper surface 192b of the electrode film. The upper surface 191b of the dielectric film may be disposed at a different height level than the upper surface 192b of the electrode film. The upper surface 191b of the dielectric film may be disposed above the upper surface 192b of the electrode film and facing the cap-filled insulating film 193. The upper surface 191b of the dielectric film may contact the lower surface 193a of the cap-filled insulating film.

[0102] According to some example embodiments, a cap-filled insulating film 193 may be disposed in the first BLK1. Multiple cap-filled insulating films 193 may be disposed.

[0103] According to some example embodiments, the cap-filled insulating film 193 can penetrate a portion of the molded structure MS in the first BLK1. The cap-filled insulating film 193 can penetrate a portion of the molded structure MS from the second surface MS_S2 of the molded structure. The cap-filled insulating film 193 can penetrate the second surface MS_S2 of the molded structure. The cap-filled insulating film 193 can be attached to the second surface MS_S2 of the molded structure. For example, the cap-filled insulating film 193 can penetrate the first molded stack MS1 and the second molded stack MS2, but can not penetrate the third molded stack MS3 and the fourth molded stack MS4.

[0104] According to some example embodiments, the cap-filled insulating film 193 may be attached to the capacitor structure CAP in a first direction D1. The cap-filled insulating film 193 may overlap with the capacitor structure CAP in the first direction D1. The cap-filled insulating film 193 may be attached to the capacitor structure CAP at one of the boundaries between the plurality of molded stacks MS1, MS2, MS3, and MS4. For example, the cap-filled insulating film 193 may contact the capacitor structure CAP at the boundary between the second molded stack MS2 and the third molded stack MS3.

[0105] According to some example embodiments, the cap-filled insulating film 193 may include at least one of silicon oxide, silicon oxynitride, and a low-k material with a dielectric constant lower than that of silicon oxide, but this is merely an example.

[0106] According to some example embodiments, the cap-filled insulating film 193 may penetrate the second molded portion MP2. The cap-filled insulating film 193 may overlap with the second molded portion MP2 in a direction intersecting the first direction D1. The cap-filled insulating film 193 may not penetrate the first molded portion MP1. The cap-filled insulating film 193 may not overlap with the first molded portion MP1 in a direction intersecting the first direction D1.

[0107] According to some example embodiments, the cap-filled insulating film 193 may be disposed in the capacitor hole CAP_H. The cap-filled insulating film 193 may be disposed along the second hole portion CAP_H_P2. The cap-filled insulating film 193 may fill the second hole portion CAP_H_P2. The cap-filled insulating film 193 may not extend along the first hole portion CAP_H_P1.

[0108] According to some example embodiments, the capacitor structure CAP and the cap-filled insulating film 193 may have steps at their contacting boundary surfaces. For example, the capacitor structure CAP and the cap-filled insulating film 193 may have a step at the boundary between the second molded stack MS2 and the third molded stack MS3, which are among the boundaries between the plurality of molded stacks MS1, MS2, MS3 and MS4, and the capacitor structure CAP and the cap-filled insulating film 193 are in contact with and connected to each other at the boundary between the second molded stack MS2 and the third molded stack MS3.

[0109] According to some example embodiments, in a direction intersecting the first direction D1 (e.g., the second direction D2 or the third direction D3), the width of the first bonding surface of the capacitor structure CAP that contacts the cap-filled insulating film 193 and the width of the second bonding surface of the cap-filled insulating film 193 that contacts the capacitor structure CAP may be different from each other.

[0110] As an example, refer to Figure 6The first bonding surface of the capacitor structure CAP that contacts the cap-filled insulating film 193 may include the upper surface 191b of the dielectric film and the upper surface 192b of the electrode film. The second bonding surface of the cap-filled insulating film 193 that contacts the capacitor structure CAP may be the lower surface 193a of the cap-filled insulating film. In the second direction D2 or the third direction D3 intersecting the first direction D1, the width of the first bonding surface of the capacitor structure CAP, including the upper surface 191b of the dielectric film and the upper surface 192b of the electrode film, may be different from the width of the second bonding surface of the cap-filled insulating film 193, including the lower surface 193a of the cap-filled insulating film. In the second direction D2, the width of the first bonding surface of the capacitor structure CAP may be smaller than the width of the second bonding surface of the cap-filled insulating film 193. However, this is merely an example. The width of the first bonding surface of the capacitor structure CAP may also be greater than the width of the second bonding surface of the cap-filled insulating film 193.

[0111] As another example, see Figure 7 The first bonding surface of the capacitor structure CAP that contacts the cap-filled insulating film 193 can be the upper surface 191b of the dielectric film. The second bonding surface of the cap-filled insulating film 193 that contacts the capacitor structure CAP can be the lower surface 193a of the cap-filled insulating film. In the second direction D2 or the third direction D3 intersecting the first direction D1, the width of the first bonding surface of the capacitor structure CAP, including the upper surface 191b of the dielectric film, can be different from the width of the second bonding surface of the cap-filled insulating film 193, including the lower surface 193a of the cap-filled insulating film. In the second direction D2, the width of the first bonding surface of the capacitor structure CAP can be smaller than the width of the second bonding surface of the cap-filled insulating film 193.

[0112] According to some example embodiments, in the first direction D1, the height of the capacitor structure CAP and the height of the cap-filled insulating film 193 can be equal. The height of the cap-filled insulating film 193 penetrating the first molded stack MS1 and the second molded stack MS2 and the height of the capacitor structure CAP penetrating the third molded stack MS3 and the fourth molded stack MS4 can be equal. However, this is merely an example. For instance, when the heights of the first molded stack MS1 and the second molded stack MS2 in the first direction D1 are different from the heights of the third molded stack MS3 and the fourth molded stack MS4, the height of the capacitor structure CAP and the height of the cap-filled insulating film 193 in the first direction D1 can be different from each other.

[0113] According to some example embodiments, in the first direction D1, the capacitor structure CAP can be positioned closer to the bit line BL than the cap-filled insulating film 193. Since the bit line BL is located below the fourth molded stack MS4, the capacitor structure CAP penetrating the third molded stack MS3 and the fourth molded stack MS4 can be positioned closer to the bit line BL than the cap-filled insulating film 193 penetrating the first molded stack MS1 and the second molded stack MS2.

[0114] According to some example embodiments, the capacitor structure CAP can be connected to the cap connection wiring 170 via the cap connection contact 184. The cap connection wiring 170 can be electrically connected to the electrode film 192 of the capacitor structure CAP.

[0115] According to some example embodiments, in the first direction D1, the cap connection wiring 170 may be disposed at the same height level as the bit line BL. The cap connection wiring 170 may be formed below the molded structure MS. The cap connection wiring 170 may be disposed below the first surface MS_S1 of the molded structure. In the first direction D1, the cap connection wiring 170 may be disposed below the fourth molded stack MS4. The cap connection wiring 170 may be spaced apart from the bit line BL. For example, the cap connection wiring 170 may be spaced apart from the bit line BL in the third direction D3.

[0116] According to some example embodiments, the capacitor structure CAP can reduce noise in the input / output signals applied to the semiconductor memory device through the input / output pads 320. As the height of the molded structure MS increases in the first direction D1, the resistance appearing in the molded structure MS may increase. Therefore, since the capacitor structure CAP does not penetrate the entire molded structure MS in the first direction D1 but only penetrates a portion of the molded structure MS, the impact on the resistance of the capacitor structure CAP due to the increase in the height of the molded structure MS can be reduced, and a more efficient capacitor capacity of the capacitor structure CAP can be achieved.

[0117] According to some example embodiments, the electrode connection structure TAP can penetrate the molded structure MS in the first BLK1 in the first direction D1. Therefore, the electrode connection structure TAP can connect to multiple gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL through the penetration of the molded structure MS.

[0118] According to some example embodiments, the electrode connection structure TAP may be spaced apart from the capacitor structure CAP in the second direction D2. For example, the electrode connection structure TAP may be disposed between multiple capacitor structures CAP in the second direction D2. The electrode connection structure TAP may include conductive materials (e.g., metals such as tungsten (W), cobalt (Co), or nickel (Ni) or semiconductor materials such as silicon), but this is merely an example.

[0119] According to some example embodiments, the cell wiring structure 180 can be formed on the molded structure MS. The cell wiring structure 180 can be disposed on the first surface MS_S1 of the molded structure. For example, a first inter-wiring insulating film 145 can be formed on the second inter-layer insulating film 140b, and the cell wiring structure 180 can be formed in the first inter-wiring insulating film 145. The cell wiring structure 180 can be electrically connected to the bit line BL, the cell contact 162, the source contact 164, and the contact plug 166. Thus, the cell wiring structure 180 can be electrically connected to the channel structure CH, the plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n and SSL, and the cell substrate 100. The number of layers, arrangement, etc. of the illustrated cell wiring structure 180 are merely examples.

[0120] According to some example embodiments, the cell wiring structure 180 can be electrically connected to a plurality of memory cells formed in the cell array region CAR. For example, the cell wiring structure 180 can be electrically connected to the bit line BL. Thus, the cell wiring structure 180 can be electrically connected to the channel structure CH. Furthermore, since the cell wiring structure 180 is electrically connected to the cell contact portion 162, the cell wiring structure 180 can be electrically connected to a plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL.

[0121] According to some example embodiments, the cell contact 162 can be connected to a plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL. For example, the cell contact 162 can extend in a first interlayer insulating film 140a and a second interlayer insulating film 140b in a first direction D1 to connect to the plurality of gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL. In some example embodiments, the cell contact 162 can have a curved portion at the boundary between the second molded stack MS2 and the third molded stack MS3. However, this is merely an example. For example, similar to the channel structure CH, the cell contact portion 162 may have a curved portion between the first molded stack MS1 and the second molded stack MS2, between the second molded stack MS2 and the third molded stack MS3, and between the third molded stack MS3 and the fourth molded stack MS4.

[0122] According to some example embodiments, the source contact 164 can be connected to the cell substrate 100. For example, the source contact 164 can extend in the first interlayer insulating film 140a and the second interlayer insulating film 140b in the first direction D1 to connect to the cell substrate 100. The source contact 164 can electrically connect the cell substrate 100 and the cell wiring structure 180.

[0123] According to some example embodiments, each of the cell contact portion 162 and the source contact portion 164 can be connected to the cell wiring structure 180 through the contact via 186.

[0124] According to some example embodiments, the peripheral circuit structure PERI may include a peripheral circuit substrate 200, a peripheral circuit element PT, and a peripheral circuit wiring structure 260.

[0125] According to some example embodiments, the peripheral circuit substrate 200 may be disposed below the unit substrate 100. For example, the peripheral circuit substrate 200 may be opposite to the first surface 100a of the unit substrate. According to some example embodiments, the peripheral circuit substrate 200 may include, for example, a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the peripheral circuit substrate 200 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

[0126] According to some example embodiments, peripheral circuit elements PT can be formed on the peripheral circuit substrate 200. The peripheral circuit elements PT can form peripheral circuitry for controlling the operation of semiconductor memory devices (e.g., Figure 1 The peripheral circuit 30). For example, the peripheral circuit element PT may include control logic (e.g., Figure 1Control logic 37), line decoder (e.g., Figure 1 The line decoder 33), page buffer (e.g., Figure 1 (e.g., page buffer 35). In the following description, the surface of the peripheral circuit substrate 200 on which peripheral circuit elements are disposed may be referred to as the first surface 200a of the peripheral circuit substrate. The first surface 200a of the peripheral circuit substrate may be the front side of the peripheral circuit substrate 200. Conversely, the surface of the peripheral circuit substrate 200 opposite to the first surface 200a of the peripheral circuit substrate may be referred to as the second surface 200b of the peripheral circuit substrate. The second surface 200b of the peripheral circuit substrate may be the back side of the peripheral circuit substrate.

[0127] According to some example embodiments, the peripheral circuit element PT may include, for example, a transistor, but this is merely an example. For example, the peripheral circuit element PT may include not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, or inductors.

[0128] According to some example embodiments, the cell structure can be stacked on the peripheral circuit structure PERI. For example, the cell structure can be stacked on the first surface 200a of the peripheral circuit substrate.

[0129] According to some example embodiments, the first surface 100a of the unit substrate may be opposite to the peripheral circuit structure PERI. For example, the first surface 100a of the unit substrate may be opposite to the first surface 200a of the peripheral circuit substrate.

[0130] According to some example embodiments, semiconductor memory devices may have a chip-to-chip (C2C) structure. A C2C structure may be a structure in which an upper chip including a cell structure CELL is fabricated on a first wafer (e.g., cell substrate 100), and a lower chip including a peripheral circuit structure PERI is fabricated on a second wafer (e.g., peripheral circuit substrate 200), which is different from the first wafer, and then the upper chip and the lower chip are connected to each other using a bonding scheme.

[0131] As an example, a bonding scheme could be one in which a first bonding metal 195 formed in the uppermost metal layer of the upper chip is electrically connected to a second bonding metal 295 formed in the uppermost metal layer of the lower chip. For example, when the first bonding metal 195 and the second bonding metal 295 are formed of copper (Cu), the bonding scheme could be a Cu-Cu bonding scheme. However, this is merely an example. The first bonding metal 195 and the second bonding metal 295 could also be formed of various other metals, such as aluminum (Al) or tungsten (W).

[0132] According to some example embodiments, since the first bonding metal 195 and the second bonding metal 295 are bonded, the cell wiring structure 180 can be connected to the peripheral circuit wiring structure 260. Thus, the bit line BL, each gate electrode GSL, WL or SSL, and / or the cell substrate 100 can be connected to the peripheral circuit element PT.

[0133] According to some example embodiments, input / output pads 320 may be disposed above the second surface 100b of the cell substrate 100. For example, a third interlayer insulating film 310 covering the cell substrate 100 and the insulating substrate 101 may be formed on the second surface 100b of the cell substrate 100. Input / output pads 320 may be formed on the third interlayer insulating film 310. The third interlayer insulating film 310 may include at least one of, for example, silicon oxide, silicon oxynitride, and a low-k material with a dielectric constant lower than that of silicon oxide, but this is merely an example.

[0134] According to some example embodiments, the input / output pads 320 can be electrically connected to the cell structure (CELL) and / or the peripheral circuit structure (PERI). For example, contact plugs 166 can be formed to connect the cell wiring structure 180 and the input / output pads 320. Contact plugs 166 can penetrate interlayer insulating films 140a, 140b, and 310. Interlayer insulating films 140a, 140b, and 310 can cover the molded structure MS. Contact plugs 166 can extend, for example, in a first direction D1 to penetrate the third interlayer insulating film 310, the insulating substrate 101, the first interlayer insulating film 140a, and the second interlayer insulating film 140b. The input / output pads 320 can be electrically connected to the cell wiring structure 180 via contact plugs 166.

[0135] According to some example embodiments, the contact plug 166 can be electrically connected to the capacitor structure CAP via the unit wiring structure 180 and the cap connection wiring 170. The capacitor structure CAP can receive signals input and output through the input / output pads 320 and the contact plug 166 via the unit wiring structure 180 and the cap connection wiring 170, and can reduce noise in the signals by utilizing the capacitance of the capacitor structure CAP.

[0136] According to some example embodiments, the width of the contact plug 166 may decrease as it approaches the cell wiring structure 180. This may be due to the characteristics of the etching process used to form the contact plug 166.

[0137] According to some example embodiments, a capping insulating film 330 may be provided on the input / output pads 320. The capping insulating film 330 may include a pad opening OP that exposes at least a portion of the input / output pads 320. The input / output pads 320 may be electrically connected to external devices, etc., through the pad opening OP.

[0138] Figure 9 It shows along Figure 3 Another example diagram of a cross-section taken by line A-A' is provided to illustrate a semiconductor memory device according to some other example embodiments. In order to describe the semiconductor memory device according to some other example embodiments, the description will focus primarily on the one referenced above. Figures 3 to 8 Different aspects described.

[0139] Reference Figure 9 The capacitor structure CAP can penetrate the fourth molded stack MS4, but can not penetrate the first molded stack MS1, the second molded stack MS2, and the third molded stack MS3. In the second direction D2 and the third direction D3, the capacitor structure CAP can overlap with the fourth molded stack MS4, but can not overlap with the first molded stack MS1, the second molded stack MS2, and the third molded stack MS3.

[0140] According to some example embodiments, the cap-filled insulating film 193 may penetrate the first molded stack MS1, the second molded stack MS2, and the third molded stack MS3, but may not penetrate the fourth molded stack MS4. In the second direction D2 and the third direction D3, the cap-filled insulating film 193 may overlap with the first molded stack MS1, the second molded stack MS2, and the third molded stack MS3, but may not overlap with the fourth molded stack MS4.

[0141] According to some example embodiments, the first molding portion MP1 may include a fourth molding stack MS4, and the second molding portion MP2 may include a first molding stack MS1, a second molding stack MS2, and a third molding stack MS3.

[0142] According to some example embodiments, the capacitor structure CAP and the cap-filled insulating film 193 can be connected at the boundary between the third molded stack MS3 and the fourth molded stack MS4. The capacitor structure CAP and the cap-filled insulating film 193 can also be connected to each other at the boundary between the third molded stack MS3 and the fourth molded stack MS4 using steps.

[0143] According to some example embodiments, the height of the capacitor structure CAP and the height of the cap-filled insulating film 193 may be different in the first direction D1. In the first direction D1, the height of the capacitor structure CAP penetrating the fourth molded stack MS4 may be less than the height of the cap-filled insulating film 193 penetrating the first molded stack MS1, the second molded stack MS2, and the third molded stack MS3.

[0144] Figure 10 It shows along Figure 3 Another example diagram of a cross-section taken by line A-A' is provided to illustrate a semiconductor memory device according to yet another example embodiment. In order to describe the semiconductor memory device according to yet another example embodiment, the description will focus primarily on the references above. Figures 3 to 8 Different aspects described.

[0145] Reference Figure 10 The capacitor structure CAP can penetrate the second molded stack MS2, the third molded stack MS3, and the fourth molded stack MS4, but can not penetrate the first molded stack MS1. In the second direction D2 and the third direction D3, the capacitor structure CAP can overlap with the second molded stack MS2, the third molded stack MS3, and the fourth molded stack MS4, but can not overlap with the first molded stack MS1.

[0146] According to some example embodiments, the cap-filled insulating film 193 may penetrate the first molded stack MS1, but may not penetrate the second molded stack MS2, the third molded stack MS3, and the fourth molded stack MS4. In the second direction D2 and the third direction D3, the cap-filled insulating film 193 may overlap with the first molded stack MS1, but may not overlap with the second molded stack MS2, the third molded stack MS3, and the fourth molded stack MS4.

[0147] According to some example embodiments, the first molding portion MP1 may include a second molding stack MS2, a third molding stack MS3 and a fourth molding stack MS4, and the second molding portion MP2 may include the first molding stack MS1.

[0148] According to some example embodiments, the capacitor structure CAP and the cap-filled insulating film 193 can be connected at the boundary between the first molded stack MS1 and the second molded stack MS2. The capacitor structure CAP and the cap-filled insulating film 193 can also be connected to each other at the boundary between the first molded stack MS1 and the second molded stack MS2 using steps.

[0149] According to some example embodiments, the height of the capacitor structure CAP and the height of the cap-filled insulating film 193 may be different in the first direction D1. In the first direction D1, the height of the capacitor structure CAP penetrating the second molded stack MS2, the third molded stack MS3, and the fourth molded stack MS4 may be greater than the height of the cap-filled insulating film 193 penetrating the first molded stack MS1.

[0150] Figure 11 It shows along Figure 3 Another example diagram of a cross-section taken by line A-A' is provided to illustrate a semiconductor memory device according to yet another example embodiment. In order to describe the semiconductor memory device according to yet another example embodiment, the description will focus primarily on the references above. Figures 3 to 8 Different aspects described.

[0151] Reference Figure 11 The capacitor structure CAP can penetrate a portion of the molded structure MS from the second surface MS_S2 of the molded structure. The capacitor structure CAP can be connected to the second surface MS_S2 of the molded structure. The capacitor structure CAP can penetrate the second surface MS_S2 of the molded structure. The capacitor structure CAP can penetrate the first molded stack MS1 and the second molded stack MS2.

[0152] According to some example embodiments, the cap-filled insulating film 193 can penetrate a portion of the molded structure MS from the first surface MS_S1 of the molded structure. The cap-filled insulating film 193 can penetrate the first surface MS_S1 of the molded structure. The cap-filled insulating film 193 can penetrate the third molded stack MS3 and the fourth molded stack MS4.

[0153] According to some example embodiments, the first molding portion MP1 may include a first molding stack MS1 and a second molding stack MS2, and the second molding portion MP2 may include a third molding stack MS3 and a fourth molding stack MS4.

[0154] According to some example embodiments, the cap connection wiring 170 connected to the capacitor structure CAP can be disposed on the second surface MS_S2 of the molded structure. In the first direction D1, the cap connection wiring 170 and the bit line BL can be disposed opposite each other, with the molded structure MS located between the cap connection wiring 170 and the bit line BL. The cap connection wiring 170 can be disposed within the capping insulating film 330. As an example, the cap connection wiring 170 can be electrically connected to the input / output pads 320 via a wiring structure. As another example, when a pad opening OP is formed on the cap connection wiring 170, the cap connection wiring 170 can be used as an input / output pad.

[0155] According to some example embodiments, in the first direction D1, the cap-filled insulating film 193 can be positioned closer to the bit line BL than the capacitor structure CAP. Since the bit line BL is disposed on the fourth molding stack MS4, the cap-filled insulating film 193, which penetrates the third molding stack MS3 and the fourth molding stack MS4, can be positioned closer to the bit line BL than the capacitor structure CAP, which penetrates the first molding stack MS1 and the second molding stack MS2.

[0156] Figures 12 to 28 This is a diagram illustrating the operation of a method for manufacturing a semiconductor memory device according to some example embodiments.

[0157] Reference Figure 12 A pre-first molded stack MS1p and a first interlayer insulating film 140a can be formed on the unit substrate 100 and the insulating substrate 101. The pre-first molded stack MS1p may include alternately stacked molding sacrificial films 120 and first molding insulating films 111. The molding sacrificial film 120 may include a material that is etch-selective to the first molding insulating film 111. For example, the first molding insulating film 111 may include a silicon oxide film, and the molding sacrificial film 120 may include a silicon nitride film.

[0158] Then, capacitor vias CAP_H and channel vias CH_H can be formed that penetrate the pre-first molded stack MS1p and the first interlayer insulating film 140a.

[0159] Reference Figure 13 It can form a filler ( Figure 12 The capacitor hole CAP_H, the capacitor sacrificial film CAP_S, and the filler ( Figure 12 The channel sacrificial film CH_S consists of a channel hole CH_H. The capacitor sacrificial film CAP_S and the channel sacrificial film CH_S may include, for example, carbon.

[0160] Reference Figure 14 A pre-second molded stack MS2p can be formed on the pre-first molded stack MS1p. The pre-second molded stack MS2p may include alternately stacked molded sacrificial films 120 and second molded insulating films 112. An interlayer insulating film 140a can be formed on the pre-second molded stack MS2p.

[0161] Then, it can be formed in a manner similar to Figure 12The capacitor vias and channel vias penetrate the pre-second molded stack MS2p in a manner described in the diagram. The capacitor vias and channel vias penetrating the pre-first molded stack MS1p can be formed on the capacitor sacrificial film CAP_S and channel sacrificial film CH_S, respectively. These vias expose the surfaces of the capacitor sacrificial film CAP_S and channel sacrificial film CH_S, respectively.

[0162] Then, a capacitor sacrificial film CAP_S and a channel sacrificial film CH_S can be formed in the capacitor vias and channel vias penetrating the pre-second molded stack MS2p, respectively. The capacitor sacrificial film CAP_S and the channel sacrificial film CH_S penetrating the pre-second molded stack MS2p can be connected to the capacitor sacrificial film CAP_S and the channel sacrificial film CH_S penetrating the pre-first molded stack MS1p, respectively. Therefore, each of the capacitor sacrificial film CAP_S and the channel sacrificial film CH_S can be formed to penetrate both the pre-first molded stack MS1p and the pre-second molded stack MS2p.

[0163] Reference Figure 15 It can remove penetrations through the pre-first molded stack MS1p and the pre-second molded stack MS2p. Figure 14 The capacitor sacrificial film CAP_S can be retained without removal, penetrating the pre-first molded stack MS1p and the pre-second molded stack MS2p. The molded sacrificial film 120, the first molded insulating film 111, and the second molded insulating film 112 can be exposed by penetrating the capacitor aperture CAP_H of the pre-second molded stack MS2p.

[0164] Reference Figure 16 , can be ( Figure 15 A cap-filled insulating film 193 is formed in the capacitor aperture CAP_H. The cap-filled insulating film 193 can fill ( Figure 15 (The capacitor hole CAP_H)

[0165] Reference Figure 17 It can form a first portion 162a of the unit contact portion and a first portion 164a of the source contact portion that penetrate the first interlayer insulating film 140a.

[0166] Reference Figure 18 and Figure 19 It can be done by repeating Figures 12 to 17The same operation is used to form the capacitor sacrificial film CAP_S and the channel sacrificial film CH_S penetrating the pre-third molded stack MS3p and the pre-fourth molded stack MS4p. The capacitor sacrificial film CAP_S penetrating the pre-third molded stack MS3p and the pre-fourth molded stack MS4p can be formed to connect to the cap-filled insulating film 193 penetrating the pre-first molded stack MS1p and the pre-second molded stack MS2p.

[0167] Then, a second portion 162b of the cell contact portion and a second portion 164b of the source contact portion can be formed, penetrating the second interlayer insulating film 140b. The second portion 162b of the cell contact portion can be formed to connect to the first portion 162a of the cell contact portion. The first portion 164a of the source contact portion can be formed to connect to the second portion 164b of the source contact portion.

[0168] Reference Figure 20 It can remove ( Figure 19 The sacrificial membrane CH_S in the channel can be used to form channel pores CH_H. When removing ( Figure 19 When the channel sacrificial membrane CH_S is used, the capacitor sacrificial membrane CAP_S can be left unremoved.

[0169] Reference Figure 21 , can be ( Figure 20 The channel structure CH is formed in the channel hole CH_H. It can be formed in ( Figure 20 The channel holes CH_H are formed in sequence. Figure 5 (of) information storage film 132, ( Figure 5 Semiconductor pattern 130 and ( Figure 5 ) Filled insulating film 134.

[0170] Reference Figure 22 A gate-cut patterned hole WLC_H can be formed penetrating the pre-first molded stack MS1p, pre-second molded stack MS2p, pre-third molded stack MS3p, and pre-fourth molded stack MS4p. The gate-cut patterned hole WLC_H can be formed between the capacitor sacrificial film CAP_H and the channel structure CH. (Refer to...) Figure 22 The molded sacrificial film 120 and molded insulating films 111, 112, 113 and 114 of the pre-first molded stack MS1p, pre-second molded stack MS2p, pre-third molded stack MS3p and pre-fourth molded stack MS4p can be exposed in the gate cut pattern hole WLC_H.

[0171] Reference Figure 23 It can remove ( Figure 22 (of) pre-molded stacked MS1p, ( Figure 22 (of) pre-second molded stacked MS2p, ( Figure 22 (of) pre-third molded stacked MS3p and ( Figure 22 (of) pre-fourth molded stacked MS4p ( Figure 22 A molded sacrificial film 120 can be formed, and multiple gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n, and SSL can be formed. (The sacrificial film 120 can be removed.) Figure 22 The molded sacrificial film 120 is exposed in the gate-cut patterned hole WLC_H, and is replaced by multiple gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n and SSL.

[0172] Then, a filling can be formed ( Figure 22 The gate cut pattern of the hole WLC_H is WLC.

[0173] Reference Figure 24 It can remove those that penetrate the third-mold stack MS3 and the fourth-mold stack MS4. Figure 23 The capacitor sacrificial film CAP_S is formed, thereby creating the capacitor aperture CAP_H. The cap-filled insulating film 193 penetrating the first molded stack MS1 and the second molded stack MS2 can be exposed in the capacitor aperture CAP_H.

[0174] Reference Figure 25 and Figure 26 , can be ( Figure 24 The capacitor structure CAP is formed in the capacitor hole CAP_H. It can be formed sequentially in (…). Figure 24 A dielectric film 191 and an electrode film 192 are formed in the capacitor hole CAP_H.

[0175] According to some example embodiments, it is possible to form Figure 13 and Figure 14 The capacitor sacrificial film CAP_S penetrates the pre-first molded stack MS1p and the pre-second molded stack MS2p. Figure 18 While the capacitor sacrificial film CAP_S penetrates the pre-third molded stack MS3p and the pre-fourth molded stack MS4p, an electrode connection sacrificial film TAP_S is formed that is spaced apart from the cap-filled insulating film 193 and the capacitor structure CAP.

[0176] Reference Figure 27 It can remove ( Figure 26 The electrode is connected to the sacrificial film TAP_S, thereby forming an electrode connection hole TAP_H. Multiple gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n and SSL of the first molding stack MS1 to the fourth molding stack MS4 can be exposed in the electrode connection hole TAP_H.

[0177] Reference Figure 28 , can be ( Figure 27 An electrode connection structure TAP is formed in the electrode connection hole TAP_H. The electrode connection structure TAP can be connected to multiple gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, WL31 to WL3n, WL41 to WL4n and SSL of the first molding stack MS1 to the fourth molding stack MS4.

[0178] Then, refer to Figure 4 and Figure 8 Above the fourth molding stack MS4, bit line contacts 182 and bit lines BL connected to the channel structure CH can be formed, and cap connection contacts 184 and cap connection wiring 170 connected to the capacitor structure CAP can be formed. Contact vias 186 and cell wiring structures 180 connected to cell contacts 162 and source contacts 164 can be formed. A first bonding metal 195 connected to the bit lines BL, cap connection wiring 170, and cell wiring structures 180 can be formed in the first inter-wiring insulating film 145, thereby forming a cell structure CELL.

[0179] Then, the cell structure (CELL) can be bonded to the peripheral circuit structure (PERI), which includes the peripheral circuit element (PT) and the peripheral circuit wiring structure (260). The cell structure (CELL) can be bonded to the peripheral circuit structure (PERI) such that the first bonding metal (195) and the second bonding metal (295) are bonded.

[0180] Then, a third interlayer insulating film 310 can be formed on the cell substrate 100, and a contact plug 166 penetrating the first interlayer insulating film 140a, the second interlayer insulating film 140b, and the third interlayer insulating film 310 can be formed. Input / output pads 320 and capping insulating film 330 connected to the contact plug 166 can be formed. Unlike the cell contact portion 162 and the source contact portion 164, the contact plug 166 is shown to simultaneously penetrate the first interlayer insulating film 140a, the second interlayer insulating film 140b, and the third interlayer insulating film 310, but this is merely an example. For example, when the first portion 162a of the cell contact portion and the first portion 164a of the source contact portion are formed, a portion of the contact plug 166 penetrating the first interlayer insulating film 140a can be formed, and when the second portion 162b of the cell contact portion and the second portion 164b of the source contact portion are formed, a portion of the contact plug 166 penetrating the second interlayer insulating film 140b can be formed.

[0181] Figure 29 These are example diagrams used to describe electronic systems including semiconductor memory devices according to some example embodiments.

[0182] Reference Figure 29According to some example embodiments, the electronic system 1000 may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor memory devices 1100.

[0183] According to some example embodiments, the semiconductor memory device 1100 may be a non-volatile memory device (e.g., a NOT (NAND) flash memory device), and may be, for example, the one described above. Figures 1 to 28 The semiconductor memory device described. The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0184] According to some example embodiments, the first structure 1100F may be a peripheral circuit structure, which includes a decoder circuit 1110 (e.g., Figure 1 The line decoder 33), page buffer 1120 (e.g., Figure 1 Page buffer 35) and logic circuit 1130 (e.g., Figure 1 Control logic 37). The first structure 1100F can correspond to, for example, reference... Figures 1 to 28 The described peripheral circuit structure is PERI.

[0185] According to some example embodiments, the second structure 1100S may include the above-mentioned reference. Figure 2 The description includes a common source line CSL, multiple bit lines BL, and multiple cell strings CSTR. The cell strings CSTR can be connected to the decoder circuit 1110 via a word line WL, at least one string select line SSL, and at least one ground select line GSL. Furthermore, the cell strings CSTR can be connected to the page buffer 1120 via the bit line BL. The second structure 1100S can correspond to, for example, reference [reference missing]. Figures 1 to 28 The described cell structure.

[0186] According to some example embodiments, the common source line CSL and cell string CSTR can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S.

[0187] According to some example embodiments, the semiconductor memory device 1100 can be electrically connected to the logic circuit 1130 (e.g., Figure 1 The input / output pads 1101 of the control logic 37) communicate with the controller 1200. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection wiring 1135 extending from inside the first structure 1100F to the second structure 1100S. The input / output pads 1101 can correspond to the above reference. Figures 1 to 28 The input / output pads 320 are described. Input / output connection wiring 1135 can correspond to, for example, the above reference. Figures 1 to 28 The described contact plug 166.

[0188] According to some example embodiments, controller 1200 may include processor 1210, NAND controller 1220, and host interface 1230. In some example embodiments, electronic system 1000 may include multiple semiconductor memory devices 1100, and in this case, controller 1200 may control multiple semiconductor memory devices 1100.

[0189] According to some example embodiments, processor 1210 can control the operation of the entire electronic system 1000, including controller 1200. Processor 1210 can operate according to desired and / or alternatively predetermined firmware and access semiconductor memory device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor memory device 1100. Control commands for controlling semiconductor memory device 1100, data recorded in memory cell transistors (MCTs) of semiconductor memory device 1100, data read from memory cell transistors (MCTs) of semiconductor memory device 1100, etc., can be transmitted. Host interface 1230 can provide functionality for communication between electronic system 1000 and an external host. When a control command is received from an external host via host interface 1230, processor 1210 can control semiconductor memory device 1100 in response to the control command.

[0190] Figure 30 This is an example perspective view used to describe an electronic system including a semiconductor memory device according to some example embodiments. Figure 31 It shows along Figure 30 Example diagram of the cross section taken by line II.

[0191] Reference Figure 30 and Figure 31An electronic system according to some example embodiments may include a main substrate 2001, a main controller 2002 mounted to the main substrate 2001, one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and DRAM 2004 may be connected to the main controller 2002 via wiring patterns 2005 formed to the main substrate 2001.

[0192] According to some example embodiments, the main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The arrangement and number of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host via one of the following interfaces: Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-PHY for Universal Flash Memory (UFS). In some example embodiments, the electronic system 2000 may operate via power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied by the external host to the main controller 2002 and the semiconductor package 2003.

[0193] According to some example embodiments, the main controller 2002 can record data in or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0194] According to some example embodiments, DRAM 2004 can be a buffer memory used to reduce the speed difference between an external host and the semiconductor package 2003, which serves as data storage space. DRAM 2004 included in the electronic system 2000 can also operate as a cache memory and provide temporary data storage space during control operations on the semiconductor package 2003. When DRAM 2004 is included in the electronic system 2000, the main controller 2002 may include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003.

[0195] According to some example embodiments, semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b disposed spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a corresponding lower surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0196] According to some example embodiments, the package substrate 2100 may be a printed circuit board including on-package pads 2130. Each of the semiconductor chips 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 29 Input / output pad 1101.

[0197] According to some example embodiments, the connection structure 2400 may be a bonding wiring that electrically connects the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a bonding wiring scheme and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of the connection structure 2400 in the bonding wiring scheme.

[0198] According to some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the main substrate 2001, and the main controller 2002 and the semiconductor chip 2200 may be interconnected by wiring formed to the interposer substrate.

[0199] According to some example embodiments, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include: a package substrate body portion 2120; an upper package pad 2130 disposed on the upper surface of the package substrate body portion 2120; a lower package pad 2125 disposed on or exposed through the lower surface of the package substrate body portion 2120; and internal wiring 2135 electrically connecting the upper package pad 2130 and the lower package pad 2125 in the package substrate body portion 2120. The upper package pad 2130 may be electrically connected to the connection structure 2400. The lower package pad 2125 may be connected to the wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 via a conductive connection portion 2800, such as... Figure 30 As shown.

[0200] In an electronic system 2000 according to some example embodiments, each semiconductor chip 2200 may include the above-mentioned references. Figures 1 to 28 The semiconductor memory device described. For example, semiconductor chip 2200 may include a capacitor structure CAP and a cap-filled insulating film 193. The capacitor structure CAP and the cap-filled insulating film 193 may vertically overlap each other.

[0201] In an electronic system 2000 according to some example embodiments, when a signal is input to or output from a semiconductor memory device of a semiconductor chip 2200, noise in the input or output signal can be reduced by using a capacitor structure CAP.

[0202] One or more elements disclosed above may include or be implemented in processing circuitry, such as hardware including logic circuitry; a hardware / software combination such as a processor executing software; or a combination of both. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0203] Various exemplary embodiments of the present disclosure have been described in detail above, but the scope of the disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications are permissible within the spirit of the present disclosure. Furthermore, the above exemplary embodiments can be implemented without some of their components, and the various exemplary embodiments can be combined with each other.

Claims

1. A semiconductor memory device, comprising: A molded structure includes a plurality of gate electrodes stacked in a first direction, the molded structure including a first molded portion and a second molded portion disposed in the first direction, and the molded structure including a capacitor hole penetrating the molded structure in the first direction; A capacitor structure, comprising a dielectric film and an electrode film, is disposed in the capacitor hole and penetrates a portion of the molded structure in the first direction; as well as The capacitor aperture is filled with an insulating film, the insulating film penetrating at least a portion of the molded structure in the first direction and overlapping the capacitor structure in the first direction, wherein... The capacitor hole includes a first hole portion in the first molding portion and a second hole portion in the second molding portion. The first hole does not penetrate the second molded portion. The second hole portion is connected to the first hole portion, and the second hole portion does not penetrate the first molded portion. The dielectric film extends along the first hole portion but not along the second hole portion.

2. The semiconductor memory device according to claim 1, wherein, The first surface of the molded structure is opposite to the second surface of the molded structure. The capacitor structure penetrates the first surface of the molded structure, and The cap-filled insulating film penetrates the second surface of the molded structure.

3. The semiconductor memory device according to claim 1, wherein, The plurality of gate electrodes includes a plurality of first gate electrodes stacked in the first direction and a plurality of second gate electrodes stacked on the plurality of first gate electrodes in the first direction. The first molding portion includes a first molding stack, and the first molding stack includes the plurality of first gate electrodes. The second molding portion includes a second molding stack disposed together with the first molding stack in the first direction, and the second molding stack includes the plurality of second gate electrodes. The capacitor structure penetrates the first molded stack, and The cap-filled insulating film penetrates the second molded stack.

4. The semiconductor memory device according to claim 3, wherein, The capacitor structure and the cap-filled insulating film have a step at the boundary between the first molded stack and the second molded stack.

5. The semiconductor memory device according to claim 3, wherein, The electrode film contacts the cap-filled insulating film at the boundary between the first molded stack and the second molded stack.

6. The semiconductor memory device according to claim 3, wherein, The dielectric film is located in the first direction between the electrode film and the cap-filled insulating film at the boundary between the first molded stack and the second molded stack, and The electrode film is spaced apart from the cap-filled insulating film.

7. The semiconductor memory device according to claim 1, further comprising: A gate dicing pattern penetrates the molding structure in the first direction and divides the molding structure into a first block and a second block; as well as A channel structure, in the second block, penetrates the molded structure in the first direction, wherein... The capacitor structure and the cap-filled insulating film penetrate the molded structure in the first block.

8. The semiconductor memory device according to claim 7, further comprising: Bit lines are located on the molding structure in the first direction and connected to the channel structure. Compared to the capacitor structure, the cap-filled insulating film is closer to the bit line in the first direction.

9. The semiconductor memory device according to claim 8, further comprising: The cap connects to the wiring, which is then connected to the capacitor structure. The cap connecting wire and the bit line are located on opposite sides of the molded structure in the first direction.

10. The semiconductor memory device according to claim 7, wherein, In the direction intersecting the first direction, the maximum width of the channel structure is equal to the maximum width of the capacitor structure.

11. The semiconductor memory device according to claim 1, wherein, In the first direction, the height of the capacitor structure is different from the height of the cap-filled insulating film.

12. The semiconductor memory device according to claim 1, further comprising: An electrode connection structure penetrates the molding structure in the first direction, wherein the electrode connection structure is connected to the plurality of gate electrodes.

13. A semiconductor memory device, comprising: A molded structure includes multiple molded stacks, each of the multiple molded stacks including multiple gate electrodes stacked in a first direction, and a first surface of the molded structure being opposite to a second surface of the molded structure in the first direction; A capacitor structure that penetrates at least one of the plurality of molded stacks in the first direction from the first surface of the molded structure; A cap-filled insulating film penetrates at least one of the plurality of molded stacks from the second surface of the molded structure in the first direction, and the cap-filled insulating film is connected to the capacitor structure in the first direction; as well as The channel structure penetrates the molded structure in the first direction. The capacitor structure and the cap-filled insulating film do not overlap in a direction intersecting the first direction.

14. The semiconductor memory device of claim 13, further comprising: The gate dicing pattern is configured to penetrate the molded structure in the first direction, wherein... The gate dicing pattern is located between the capacitor structure and the channel structure.

15. The semiconductor memory device of claim 13, further comprising: Bit lines are located on the first surface of the molded structure and connected to the channel structure; as well as The cap connection wiring is at the same height level as the bit line in the first direction, and the cap connection wiring is connected to the capacitor structure.

16. The semiconductor memory device according to claim 13, wherein, The capacitor structure includes an electrode film and a dielectric film. The electrode film extends in the first direction, and The dielectric film surrounds the electrode film.

17. The semiconductor memory device according to claim 13, wherein, In a direction intersecting the first direction, the width of the first bonding surface of the capacitor structure that contacts the cap-filled insulating film and the width of the second bonding surface of the cap-filled insulating film that contacts the capacitor structure are different.

18. The semiconductor memory device according to claim 13, wherein, In the first direction, the height of the capacitor structure is equal to the height of the cap-filled insulating film.

19. The semiconductor memory device according to claim 13, wherein, The channel structure has steps at the boundaries between the plurality of molded stacks.

20. A semiconductor memory device, comprising: A molded structure includes a plurality of gate electrodes stacked in a first direction, the molded structure including a first molded portion and a second molded portion disposed in the first direction; An interlayer insulating film covers the molded structure; A capacitor structure that penetrates the first molded portion in the first direction, the capacitor structure comprising a dielectric film and an electrode film; The cap is filled with an insulating film that penetrates the second molded portion in the first direction and overlaps with the capacitor structure in the first direction; A contact plug penetrates the interlayer insulating film and is electrically connected to the capacitor structure. as well as Input / output pads are located on the interlayer insulating film and connected to the contact plugs. Wherein, the capacitor structure does not overlap with the second molded portion in the direction intersecting the first direction, and The cap-filled insulating film does not overlap with the first molded portion in a direction intersecting the first direction.

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