Replacement metal gate priority method for manufacturing ferroelectric memory device

Abstract

The present disclosure relates to a method of manufacturing a memory device, such as a ferroelectric memory device. In addition, the present disclosure relates to a structure suitable for building a memory device. A method of the present disclosure includes a replacement metal gate (RMG) process in which a sacrificial layer of a stack is replaced by a metal layer. An RMG process is performed prior to a process of forming a memory structure in a memory hole extending through a stack. In this manner, a memory structure with a low thermal budget may be formed, for example, at temperatures below 400 DEG C, which is particularly advantageous for the ferroelectric layer of the memory structure of a ferroelectric memory device.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a memory device (e.g., a ferroelectric memory device). This disclosure also relates to a structure suitable for constructing such a memory device. The method includes one or more alternative metal gate (RMG) or alternative metal electrode (RME) process steps performed prior to one or more process steps forming the memory structure (e.g., a ferroelectric memory structure) of the memory device. Therefore, this disclosure relates to an RMG-preferred method for manufacturing memory devices. Background Technology

[0002] Three-dimensional (3D) non-volatile semiconductor memory devices, such as 3D NAND flash memory devices, are typically manufactured using a manufacturing method known in this disclosure as RMG hysteresis. In this conventional manufacturing method, the memory structure (also referred to as a memory element) is first formed, particularly in the vertical memory vias, before the final RMG process step of forming metal word lines.

[0003] However, this conventional manufacturing method, particularly the processing sequence, is unsuitable for manufacturing many other memory devices, especially ferroelectric-based non-volatile memory devices. For example, the conventional manufacturing method is unsuitable for manufacturing 3D ferroelectric field-effect transistors (FeFETs), 3D ferroelectric flash memory, or 3D ferroelectric random access memory (FeRAM). This is because the final RMG process step performed in the conventional manufacturing method may, for example, generate undesirable stresses in the channel layers(s) and ferroelectric layers(s) of the memory element disposed near the RMG layer in the previously manufactured process. These undesirable stresses can, for example, alter the phase ratio in the ferroelectric layers(s), thereby affecting properties such as remanent polarization and coercive field, and can negatively impact the performance of ferroelectric memory devices, such as memory window, durability, and retention force. Generally, for many types of memory devices, the conventional manufacturing method employing the RMG hysteresis approach can negatively affect the performance of the memory device. Summary of the Invention

[0004] In view of the foregoing, the object of this disclosure is to provide an alternative manufacturing method applicable to the manufacture of a wider variety of memory devices, particularly ferroelectric memory devices. A particular object is to avoid or at least significantly reduce undesirable stresses on the memory structure of the memory device, especially undesirable stresses on the ferroelectric layer that may be used.

[0005] These and other objectives are achieved by the various embodiments of this disclosure as described in the independent claims. Advantageous embodiments are described in the dependent claims.

[0006] This disclosure proposes a manufacturing method with either an RMG-first or RME-first approach. That is, using one or more RMG or RME process steps, metal gates or metal electrodes are constructed respectively before forming the memory structure of the memory device. Specifically, the RMG or RME process steps are performed before the deposition of the ferroelectric layer used in the memory structure.

[0007] A first aspect of this disclosure provides a method for manufacturing a memory device, particularly a ferroelectric memory device, the method comprising: depositing a stack of a plurality of dielectric layers and sacrificial layers arranged alternately to each other along a stacking direction, wherein the sacrificial layers are made of a first sacrificial material; forming a plurality of memory apertures in the stack, wherein each memory aperture extends through each layer of the stack; filling each memory aperture with a second sacrificial material; shaping the stack to have a stepped structure on opposite outer sides, wherein the stepped structure is formed by a shaped stack of a plurality of concentric layer pairs having a dielectric layer and a sacrificial layer, wherein the respective widths of the layer pairs continuously decrease along the stacking direction; after forming the memory apertures, replacing each sacrificial layer of the stack with a corresponding metal layer; and after replacing the sacrificial layer, replacing the second sacrificial material in each memory aperture with a corresponding memory structure; wherein each memory structure is combined with the plurality of metal layers to form a plurality of memory cells.

[0008] It is worth noting that, unless explicitly stated otherwise, the order of the above method steps should not be inferred from their described order. In particular, while the formation of the stack preferably occurs after filling the memory vias, it can also be formed before forming and filling the memory vias. At least after forming the memory vias, preferably after filling the memory vias, and more preferably after filling the memory vias and forming the stack, the sacrificial layer is replaced to avoid, for example, etching of the metal.

[0009] In the manufacturing method of the first aspect, one or more RMG or RME process steps are performed before forming the memory structure for the memory portion of the memory cell—depending on the type of memory device, replacing the sacrificial layer with a metal layer to form a metal gate or metal electrode. It is worth noting that this disclosure may refer to the RMG process step in some places, even if a metal electrode is formed from the metal layer instead of a metal gate. In such cases, it is more accurate to say one or more RME process steps rather than one or more RMG process steps. However, the distinction between RMG and RME is beyond the scope of this disclosure. Therefore, the manufacturing method of the first aspect is applicable to manufacturing more memory devices than conventional manufacturing methods, including ferroelectric memory devices. For example, the manufacturing method of the first aspect is applicable to manufacturing FeRAM, FeFET, or ferroelectric flash memory devices. However, this manufacturing method is also applicable to manufacturing any other memory devices that can be manufactured using RMG or RME process steps, such as memory devices without any ferroelectric functionality.

[0010] Furthermore, forming the stack into a stepped structure offers additional advantages in terms of contacting memory cells, which include memory structures and metal layers, particularly contact metal layers, to enable addressing of individual memory cells within the memory device. In this regard, dielectric filling and planarization steps may be beneficial after forming the stepped structure and before performing RMG or RME process steps, to provide a better support structure when removing the first sacrificial material of the sacrificial layer to replace the removed layer with a metal layer. A stepped structure means that the formed stack has a stepped shape on each of two opposite sides, where these sides can be opposite each other relative to the direction in which the width of each layer is measured. This direction of width measurement can be perpendicular to the stacking direction, i.e., the in-plane direction of the layers. Therefore, the stack will become narrower towards its top, for example, becoming narrower with increasing distance from the substrate on which the stack is formed. The stepped structure has steps, where each step is formed by one of the layer pairs. The height and width of the steps can be the same or different.

[0011] In one embodiment, the storage structure is formed in the storage hole at a temperature below 400°C, and / or the storage structure is formed in the storage hole and subsequently not exposed to temperatures above 400°C.

[0012] In other words, the memory structure experiences only a low thermal budget (TB), which further helps to avoid or at least significantly reduce unwanted stress and damage. The memory structure, and the memory cells in the final memory device, can exhibit better performance and can have better defined characteristics achievable with conventional manufacturing methods. For example, when ferroelectric layers are included in the memory structure, the associated properties of these ferroelectric layers, such as remanent polarization and coercive field, and the resulting memory performance characteristics, such as memory window, durability, and retention force, are unaffected or at least minimally affected compared to conventional manufacturing methods. Furthermore, other structures present on the memory device prior to the formation of the memory structure, such as peripheral logic structures and metallization layers, also experience only a low TB, which allows for the use of lower-resistance metals, such as copper, and temperature-sensitive logic devices.

[0013] The RMG or RME process steps, namely the steps of replacing the sacrificial layer with a metal layer, occur before the formation of the memory structure, and the memory structure formation steps may also involve temperatures significantly above 400°C.

[0014] In one implementation, the memory structure is formed in the memory hole and is not subsequently exposed to mechanical stress due to the removal of material adjacent to the memory structure.

[0015] This can further improve the clarity and performance of the storage structure, and thus also improve the clarity and performance of the storage cells of the storage device.

[0016] In one implementation, the storage structure comprises an oxide semiconductor material.

[0017] The use of oxide semiconductor materials allows skipping high-temperature channel activation annealing, which can benefit the performance of memory devices.

[0018] In one implementation, the storage structure includes a ferroelectric material, such as hafnium zirconium oxide (HZO).

[0019] HZO offers a low-temperature option with a crystallization temperature below 400°C, which can benefit the performance of storage devices.

[0020] In one implementation, the storage cell includes a ferroelectric capacitor or a ferroelectric field-effect transistor, or a flash memory cell or a ferroelectric flash memory cell.

[0021] In other words, ferroelectric storage devices can be manufactured using the first method without the performance degradation seen in the traditional RMG hysteresis method.

[0022] In one implementation, the ferroelectric material includes HZO, such as lanthanum-doped HZO.

[0023] In one implementation, the method further includes: forming one of a plurality of trenches in the stack after filling the memory vias and before replacing the sacrificial layer, wherein each trench extends through each layer of the stack and is disposed between two or more memory vias; and filling one or more trenches with a dielectric, semiconductor, or conductive material after replacing the sacrificial layer.

[0024] In one implementation, a portion of the stack is arranged between each trench and two or more storage holes, the trench being arranged between the two or more storage holes.

[0025] These grooves help remove the first sacrificial material, thereby improving the efficiency of the method.

[0026] In one implementation, the method further includes: after forming the stepped structure, depositing a planarization material, such as silicon oxide, on the top of the stepped structure; wherein the thickness of the deposited planarization material exceeds the step height difference between the top and bottom step levels; and after depositing the planarization material, planarizing the surface of the structure by, for example, chemical mechanical planarization.

[0027] Planarizing materials (compared to the absence of planarizing materials) help stabilize the resulting intermediate structure, which is beneficial for the one or more RMG or RME process steps or other process steps, such as contact formation or patterning steps outside of RMG or RME process steps.

[0028] In one implementation, the method further includes: forming a plurality of contact holes to a plurality of metal layers before replacing the second sacrificial material in each storage hole; and filling the plurality of contact holes with a conductive or semiconductive material.

[0029] Therefore, it can be advantageous to manufacture the contact holes early in the manufacturing process of the first aspect, i.e., before the storage structure is formed.

[0030] In one implementation, the first sacrificial material includes silicon nitride or another nitride.

[0031] In one implementation, replacing the sacrificial layer with a metal layer involves selectively etching the first sacrificial material and / or depositing a metallic material to form the metal layer.

[0032] The etching of the first sacrificial material can be performed using etching chemicals that do not affect the second sacrificial material.

[0033] In one implementation, the method further includes: forming one or more memory structures, for example by atomic layer deposition or region selective deposition, within the cavity created by the etching between selective etching of a first sacrificial material and deposition of a metallic material to form a metallic layer; wherein the one or more memory layers comprise a metal, semiconductor, ferroelectric, or dielectric material.

[0034] It is important to note that cavities (or cavities) created by etching are different from memory vias. Instead, they refer to additional spaces between the layers of the stack after the sacrificial layer has been removed. In this way, for example, a buffer layer can be formed, which may help reduce the size of the memory via (a smaller thickness deposited on the sidewalls) and improve stack properties (the boundary between the metal gate and the memory layer, such as a clear barrier layer).

[0035] In one implementation, the second sacrificial material includes amorphous silicon.

[0036] In one implementation, replacing the second sacrificial material involves selectively etching the second sacrificial material, for example, selectively etching amorphous silicon with phosphoric acid and / or tetramethylammonium hydroxide.

[0037] In one implementation, the metal layer comprises one or more of the following: molybdenum; a composition comprising molybdenum and molybdenum oxide; titanium nitride; a composition comprising ruthenium and titanium nitride; or tungsten.

[0038] A second aspect of this disclosure provides a structure suitable for constructing memory devices, particularly ferroelectric memory devices, the structure comprising: a stack of multiple metal layers and dielectric layers arranged alternately to each other along a stacking direction, wherein the stack has a stepped structure shape on opposite outer sides of the stack, wherein the stepped structure shape is formed by a stack of multiple concentric pairs of dielectric layers and sacrificial layers, wherein the respective widths of the layer pairs decrease continuously along the stacking direction; and a plurality of memory vias in the stack, wherein each memory via extends through each layer of the stack, and wherein each memory via is filled with a sacrificial material, such as amorphous silicon.

[0039] In one implementation, the structure of the second aspect further includes a plurality of vertical contact holes formed through the stack and filled with a conductive or semiconductive material.

[0040] Verticality can be related to the stacking direction, meaning the stacking direction can be vertical. The width of each layer in the stack can be horizontal.

[0041] The structure of the second aspect can have various implementations corresponding to the manufacturing method of the first aspect. The structure of the second aspect is suitable for the proposed RMG-preferred method of the manufacturing method of the first aspect. Therefore, this structure is applicable to ferroelectric storage devices. The structure of the second aspect and its implementation can provide the effects and advantages described above regarding the method and its implementation of the first aspect.

[0042] Based on the above aspects and implementations, a method for fabricating stress-sensitive 3D non-volatile memories, such as FeFETs and FeRAMs, is proposed. Such memory devices can benefit from forming metal layers (e.g., used as metal gates or metal electrodes) prior to depositing a memory structure comprising one or more ferroelectric layers.

[0043] The method proposed in this disclosure is particularly suitable for fabricating 3D ferroelectric memory devices because it involves using an RMG-first approach, for example, with a back-to-office (BEOL) thermal budget, and therefore employing a memory structure (e.g., ferroelectric) hysteresis approach. Forming a metal layer in the presence of a dummy memory via plug, the dummy memory via plug being made of or comprising a second sacrificial material, is also proposed. The sacrificial memory via plug is subsequently replaced with a (low TB) memory structure, for example comprising a ferroelectric and / or oxide semiconductor layer.

[0044] The proposed manufacturing method ensures that any high-stress-induced RMG process steps are completed before the deposition of the storage structure, especially its ferroelectric layer, so that, for example, the ferroelectric properties of these ferroelectric layers are not affected by the mechanical stress induced by the RMG process. Attached Figure Description

[0045] The above aspects and implementations are explained in the following specific embodiments with reference to the accompanying drawings:

[0046] Figure 1 A flowchart of a method for manufacturing a storage device, such as a ferroelectric storage device, according to the present disclosure is shown.

[0047] Figure 2-14 The steps of the manufacturing method according to this disclosure are shown, and in particular the resulting structure.

[0048] Figure 15-17 Additional steps that can be used for contact formation in the manufacturing method according to this disclosure are shown. Detailed Implementation

[0049] Figure 1 A flowchart of a manufacturing method 10 according to this disclosure is shown, wherein method 10 is suitable for manufacturing memory devices. Method 10 can be used to manufacture ferroelectric memory devices. The steps of method 10 can be performed before and / or after additional steps for completing the manufacturing of the memory device. These additional steps can depend on the type of memory device. Method 10 can be performed as a process flow of consecutive process steps in a semiconductor production line, etc.

[0050] Method 10 includes the step 11 of depositing a stack of dielectric and sacrificial layers, which are arranged alternately to each other along a stacking direction. These layers may be deposited one after another on top of each other to form a stack. Each dielectric layer may be followed by a sacrificial layer deposited thereon. Preferably, the first and last layers are dielectric layers, but this is not mandatory. The layer-by-layer deposition of the stack, such as by atomic layer deposition (ALD) or chemical vapor deposition (CVD), also defines the stacking direction. The stacking direction is typically perpendicular to the plane of each layer and may be parallel to the vertical axis (or the z-axis in a coordinate system). The sacrificial layer is made of a first sacrificial material, which may be or may include a nitride, such as silicon nitride. The dielectric layer may be or may include an oxide, such as silicon oxide.

[0051] Method 10 also includes step 12 of forming a plurality of storage holes in the stack. Each storage hole extends through each layer of the stack. For example, the storage holes may extend parallel to the stacking direction and thus are typically perpendicular to the plane of each layer. Therefore, they may be referred to as perpendicular storage holes. However, it is also possible that the storage holes extend at a corresponding angle relative to the stacking direction (i.e., tilted to the plane of each layer of the stack).

[0052] Method 10 also includes the step 13 of filling each storage hole with a second sacrificial material, for example, the second sacrificial material includes amorphous silicon.

[0053] Before or after steps 12 and 13 of forming and filling the storage holes, method 10 further includes step 14 of shaping the stack into a stepped structure on opposite outer sides. Specifically, the stepped structure is formed from a shaped stack having multiple concentric layer pairs, wherein each layer pair includes one dielectric layer and one sacrificial layer. Furthermore, the respective widths of the layer pairs continuously decrease along the stacking direction. In this disclosure, the width of each layer is understood as its extension perpendicular to the stacking direction, which may be parallel to the horizontal axis (or the x-axis in a coordinate system). The thickness of each layer will be along the stacking direction (or the z-axis). That is, the width of the stack as a whole also decreases along the stacking direction from one outer side to the other outer side relative to that width. Therefore, when viewed in cross-section, the stack can resemble a triangular structure, or when viewed in perspective, the stack can resemble a pyramid structure.

[0054] For example, after steps 12 and 13 of forming and filling the memory via 31, method 10 includes step 15 of replacing each sacrificial layer of the stack with a corresponding metal layer. This step 15 can be implemented by one or more RMG process steps. The metal layer replacing the sacrificial layer may be referred to as a substitute metal gate, used as the gate of a memory cell in a memory device, or a substitute metal electrode, used as the capacitor metal plate of a memory cell in a memory device.

[0055] Following step 15, which replaces the sacrificial layer, the method includes step 16, which replaces the second sacrificial material in each memory aperture with a corresponding memory structure. Each memory structure incorporates multiple metal layers to form multiple memory cells. The memory structure may be or includes functional storage (memory) elements for the memory cells, and the metal layers may be metal gates or metal electrodes. Memory structures for various memory devices, such as 3D FeFETs or FeRAMs, are known to those skilled in the art.

[0056] As can be seen from the steps of Method 10, the memory structure (also referred to as a memory element) is formed after the RMG or RME process steps performed to replace the sacrificial layer with a metal layer. This sequence brings the aforementioned advantages and makes Method 10 particularly suitable for manufacturing ferroelectric memory devices without degrading the ferroelectric layer. However, Method 10 can also be used to manufacture other non-ferroelectric memory devices, such as NAND flash memory devices or DRAM memory devices.

[0057] exist Figure 2-14 It shows Figure 1 Illustrative examples of each step of method 10 are shown, along with additional optional steps. Figure 2-14 At least a portion of an exemplary process flow for manufacturing storage devices is shown.

[0058] Figure 2 It shows Figure 1 The result of step 11 in method 10. That is to say, Figure 2 A stack of multiple dielectric layers 21 and sacrificial layers 22 is shown, which are arranged along the stacking direction (in... Figure 2 The layers are arranged vertically and alternately. Layers 21 and 22 have been deposited one on top of another, in particular one after another. Figure 2 It is also shown that a stack can be deposited on substrate 23, and a layer 24 including a CMOS periphery for a memory device can be disposed between the stack and substrate 23. Substrate 23 can be a substrate layer or a wafer. In one example, dielectric layer 21 is a (silicon) oxide layer, and sacrificial layer 22 is a (silicon) nitride layer.

[0059] Figure 3 It shows Figure 1 The result of step 12 in method 10 shown. That is, Figure 3 Multiple memory vias 31 are shown, each extending through all dielectric layers 21 and all sacrificial layers 22 of the stack. As shown, the memory vias 31 can extend parallel to the stack direction. As shown, the memory vias 31 can terminate / land on the CMOS peripheral layer 24 or on the substrate 23.

[0060] Figure 4 and Figure 5 The result of step 13 of method 10 is shown. That is, Figure 4 and Figure 5 Each storage hole 31 is shown to be filled with a second sacrificial material 41. (See diagram.) Figure 4 As shown, sacrificial material 41 can be deposited first, thereby forming a virtual storage hole plug. Chemical mechanical polishing (CMP) can be performed to planarize the top surface of the second sacrificial material 41. Figure 5 The isolated storage hole plug of the second sacrificial material 41 is shown after back etch (i.e., removal of all second sacrificial material 41 on top of the stack).

[0061] Figure 6 It shows Figure 1 The result of step 14 of method 10 shown. That is, Figure 6 The stack has been formed on its two outer sides ( Figure 6 The left and right sides of the image show a stepped structure 61. It can be seen that the stepped structure 61 consists of multiple pairs of shaped layers. Each layer pair consists of a dielectric layer 21 and a sacrificial layer 22. The dielectric layer 21 can be disposed on the sacrificial layer 22 in each layer pair; that is, the sacrificial layer 22 can be the lower layer (closer to the substrate 23) of each layer pair. The layer pairs are concentrically arranged on another layer, but with different widths (i.e., different extensions perpendicular to the stacking direction, as described above); in Figure 6 (In the diagram, the width is horizontal). As shown, the corresponding width of the layer pair continuously decreases along the stacking direction (towards the top of the stack, i.e., away from the substrate 23). Therefore, the stack narrows along the stacking direction, i.e., towards its top, i.e., away from the substrate 23. The result is a triangular or pyramidal shape for the stack.

[0062] Figure 7 The results of optional dielectric filling and planarization steps that can be performed next are shown (where planarization may include CMP and etch-back). In this step, step 61 can be covered with a dielectric, such as an oxide. Preferably, the dielectric material used for filling corresponds to the dielectric material of dielectric layer 21. Dielectric filling and planarization may be beneficial in providing a support structure before the first sacrificial material of sacrificial layer 22 (part of step 16 of method 10) is removed later.

[0063] Figure 8 The result of an optional step of forming one or more trenches 71 in the stack is shown. Each trench 71 is formed such that it extends through each layer 21, 22 of the stack. For example, the trench 71 extends parallel to the stacking direction, but it is not necessary to resemble a storage hole 31. Each trench 71 is arranged between two or more storage holes 31. The trench 71 can facilitate the removal and replacement of the first sacrificial material.

[0064] Figure 9, 10 Figures 11 and 11 show the result of step 15 of method 10. Therefore, Figure 10 It is optional. Figure 11 yes Figure 9 It is a direct continuation, but it can also continue. Figure 10 The intermediate structure shown.

[0065] Figure 9 The first sacrificial material of sacrificial layer 22 is shown to be removed. This can be accomplished by selectively etching the first sacrificial material. The dummy memory hole plug of the second sacrificial material 41 should be selectively etched by the etching chemical. That is, the first sacrificial material should be etched by the etching chemical, but the second sacrificial material 41 should not be etched. As an example, the second sacrificial material 41 can be amorphous silicon (a-Si), and the etching chemical can be thermal H3PO4. Advantageously, the dummy memory hole plug can also act as an anchor in the memory array region, i.e., in the region where memory cells will be formed. The stepped structure 61 can be achieved by referencing... Figure 7 The filling medium material in the described steps remains stable.

[0066] Figure 10 Optionally, in Figure 9 Subsequently, a step can be performed to form one or more layers 101 of a memory structure within at least one cavity obtained by etching. The one or more layers 101 can be formed, for example, by atomic layer deposition (ALD) or region-selective deposition (ASD). Figure 10 In the example provided, one or more layers 101 of the memory structure are selectively deposited via ASD onto the surface of a second sacrificial material 41 exposed within the cavity. For example, the one or more memory layers 101 may comprise a metal, semiconductor, ferroelectric, or dielectric material, or a high-k pad. The cavity is distinct from the memory via 31 itself and may be the space between layers of a stack, for example, adjacent to a blocked memory via and / or adjacent to a trench 71, as shown.

[0067] Figure 11 The diagram illustrates that after step 15 is completed, step 15 may further include depositing a metallic material to form a metal layer 111, which has replaced the sacrificial layer 22 in the stack. The deposition of the metallic material can be performed using ALD or ASD. As previously described, Figure 11 The structure in can additionally include Figure 10 One or more layers 101 are shown.

[0068] Figure 12The step of refilling trench 71 is illustrated, which may include depositing material followed by planarization, such as CMP. A first refill option may be to deposit only a dielectric material, such as an oxide. A second refill option (not shown) may be to deposit a dielectric material and additionally deposit metal (e.g., for BEOL contact with the CMOS periphery in layer 24). Notably, Figure 12 Structure 20 according to this disclosure is shown, which is suitable for constructing storage devices, particularly ferroelectric storage devices.

[0069] Figure 13 The steps for removing the second sacrificial material 41 are illustrated, namely, removing the dummy storage hole plug from the storage hole 31. For example, if the dummy storage hole plugs are made of a-Si, they can be removed with tetramethylammonium hydroxide (TMAH), which is selective for oxides and metals. Specifically, removing the second sacrificial material 41 includes selectively etching the second sacrificial material 41, for example, selectively etching a-Si with TMAH and / or phosphoric acid. Phosphoric acid can be used to remove the top layer of a-Si, which is expected to be oxidized in the preceding process steps. Generally, phosphoric acid may not be selective for oxide material 22; therefore, the etching time should be limited, and sufficient thickness margin of oxide material 22 should be provided to allow for slight consumption during the removal of the second sacrificial material 41.

[0070] Figure 14 The steps of forming a corresponding memory structure 141 in each memory hole 31 are illustrated. Subsequently, the second sacrificial material 41 in each memory hole 31 has been effectively replaced by the corresponding memory structure 141. Each memory structure 141 may include an oxide semiconductor material. Each memory structure 141 may additionally or optionally include a ferroelectric material, such as HZO.

[0071] Figure 15-17 Additional options for the manufacturing method 10 of this disclosure to form metal contacts are shown. Figure 15 Involving Figure 7 It is shown that a plurality of contact holes 151 may be formed before replacing the second sacrificial material 41 in each storage hole 31, wherein the contact holes 151 reach a plurality of metal layers 111. The contact holes 151 may be formed parallel to the stacking direction, but this is not required. Figure 16 Multiple contact holes 151 are also shown filled with, for example, a conductive or semi-conductive material 161. For example, they may be filled with the same material as the metal layer 111. It is worth noting that... Figure 16 The groove 71 is not shown because, preferably, the contact hole 151 and the storage hole 31, as well as the groove 71, are on different planes. However, the contact hole 151 and the groove 71 can also be arranged in the same plane, in which case the groove 71 is in... Figure 16 The lieutenant general is visible. Finally, Figure 17 It shows that the second sacrificial material 41, namely the virtual storage hole plug, has been removed, which is consistent with... Figure 13 Related. Can be embedded into Figure 2-14 The benefit of this additional option in the process flow is that it allows for the manufacture of memory cells with fewer processing steps, which can potentially lead to higher performance and stability of the memory devices.

[0072] Based on the description of the foregoing figures, the present invention proposes an RMG-first method, and correspondingly, a method for hysteresis of (ferroelectric) memory structures. This method constructs a metal layer 111 (gate or electrode) prior to the deposition of the memory structure 141, particularly any ferroelectric material used.

[0073] As an example summary of the manufacturing method: alternating layers of interlayer dielectric (e.g., silicon oxide) and first sacrificial material (e.g., silicon nitride) are deposited. A memory via 31 is then etched into the stack and plugged with a dummy second sacrificial material 41, which is selective to the RMG process etching step (e.g., amorphous silicon). A stepped structure 61 is formed to facilitate future metal interconnection. The RMG process step is then applied by replacing the second sacrificial material 41 with a suitable work function metal (e.g., TiN) or a metal combination (e.g., TiN pad + W) and pulling back the deposited metal to form a separate metal layer 111 (used as a gate and / or word line). The dummy second sacrificial material 41 is selective to the first sacrificial material removal and metal pull-back etching steps. It can also be used for anchoring purposes during the first sacrificial material replacement by the metal layer 111. The dummy second sacrificial material 41 is then selectively removed, for example, by wet chemical etching. A memory structure, preferably with a low thermal budget (TB), is formed within the memory via 31. Alternatively, additional peripheral circuitry (e.g., a vertical bit line selector for an oxide semiconductor-based transistor) can be formed within the storage via 31. The process can end with a standard BEOL module (contact etching, metallization, end-of-line (EOL) processing).

[0074] Suitable low-TB memory structures could be, for example, oxide semiconductor (OSC) based FeFETs, where the OSC is used as the channel and the replaced metal layer 111 acts as the gate. Alternatively, FeRAM devices could be used, where a ferroelectric layer (combined with the OSC layer if desired) is deposited on the sidewalls of the corresponding memory via 31, where the RMG metal layer 111 acts as the plate line electrode, and the fill metal in the center of the memory via 31 can act as the bit line electrode. The use of OSC allows skipping high-temperature channel activation annealing, and the HfZrO4-based ferroelectric material provides a low-temperature option with a crystallization temperature below 400°C.

[0075] The downstream process steps that can proceed with method 10 to form the desired memory device may depend on the type of memory device. Possible memory device implementations to which method 10 is applicable include 1T-nC 3D FeRAM (where “1T” represents a transistor, “nC” represents a vertical string of n ferroelectric capacitors, and “n” represents the number of capacitors, which may be one or more), which uses, for example, metal-ferroelectric-metal (MFM), metal-ferroelectric-semiconductor-metal (MFSM), or metal-ferroelectric-insulator-semiconductor-metal (MFISM) structures to take advantage of the ferroelectric properties of non-volatile memory. Method 10 is also applicable to 3D NAND based on vertical oxide semiconductor channel FeFETs, as well as ferroelectric back-end process (BEOL) compatible 3D NAND flash memory, which allows for advanced integration and scalability in memory technology.

[0076] The advantages of method 10 presented in this disclosure are numerous. For example, any stress-sensitive 3D device (e.g., memory devices with air gaps) can potentially benefit from the proposed RMG-preferred method. Additional process damage caused by performing RMG process steps near the memory element can be eliminated. Furthermore, the active memory layer can be fabricated with fewer processing steps, thus avoiding material property degradation due to exposure to high thermal budgets (>400°C), which can ultimately lead to less variability and higher performance.

[0077] In the claims and in the description herein, the word "a" does not exclude other elements or steps, and the indefinite article "a" ("a" or "an") does not exclude the plural. A single element may perform the function of several entities or items recited in the claims. The mere fact that certain measures are stated in mutually different dependent claims does not imply that combinations of these measures cannot be used in an advantageous implementation.

Claims

1. A method (10) for manufacturing a storage device, particularly a ferroelectric storage device, said method (10) comprising: A stack of multiple dielectric layers (21) and sacrificial layers (22) is deposited (11), the dielectric layers and sacrificial layers being arranged alternately to each other along the stacking direction, wherein the sacrificial layer (22) is made of a first sacrificial material; A plurality of storage holes (31) are formed (12) in the stack, wherein each storage hole (31) extends through each layer (21, 22) of the stack; Each storage hole (31) is filled (13) with a second sacrificial material (41); The stack is shaped (14) to have a stepped structure (61) on opposite outer sides, wherein the stepped structure (61) is formed by a shaped stack of multiple concentric layer pairs having a dielectric layer (21) and a sacrificial layer (22), wherein the width of the respective layer pairs decreases continuously along the stacking direction. After forming the storage hole (31) described in (12), each sacrificial layer (22) of the stack described in (15) is replaced with a corresponding metal layer (111); and After replacing the sacrificial layer (22) described in (15), the second sacrificial material (41) in each storage hole (31) of (16) is replaced with the corresponding storage structure (141); Each storage structure (141) combines with the multiple metal layers (111) to form multiple storage cells.

2. The method (10) according to claim 1, characterized in that, The storage structure (141) is formed in the storage hole (31) at a temperature below 400°C, and / or the storage structure (141) is formed in the storage hole (31) and is subsequently not exposed to a temperature above 400°C.

3. The method according to claim 1 or 2, characterized in that, The storage structure (141) therein comprises an oxide semiconductor material.

4. The method (10) according to any one of claims 1 to 3, characterized in that, The storage structure (141) described therein includes ferroelectric materials, such as hafnium zirconium oxide, HZO.

5. The method (10) according to any one of claims 1 to 4, characterized in that, The storage units include ferroelectric capacitors or ferroelectric field-effect transistors, or flash memory units or ferroelectric flash memory units.

6. The method (10) according to any one of claims 1 to 5, characterized in that, Further includes: After filling (13) the storage hole (31) and before replacing (15) the sacrificial layer (22), one of a plurality of trenches (71) is formed in the stack, wherein each trench (71) extends through each layer (21, 22) of the stack and is arranged between two or more of the storage holes (31); and After replacing the sacrificial layer (22) (15), the one or more trenches (71) are filled with a dielectric, semiconductor or conductive material.

7. The method (10) according to claim 6, characterized in that, in, A portion of the stack is disposed between each trench (71) and the two or more storage holes (31), the trench (71) being disposed between the two or more storage holes.

8. The method (10) according to any one of claims 1 to 7, characterized in that, Further includes: Before replacing the second sacrificial material (41) in each storage hole (31), a plurality of contact holes (151) are formed to the plurality of metal layers (111); and The plurality of contact holes (151) are filled with a conductive or semi-conductive material (161).

9. The method (10) according to any one of claims 1 to 8, characterized in that, The first sacrificial material includes silicon nitride or another nitride.

10. The method (10) according to any one of claims 1 to 9, characterized in that, Replacing the sacrificial layer (22) (15) with the metal layer (111) includes selectively etching the first sacrificial material and / or depositing a metallic material to form the metal layer (111).

11. The method (10) according to claim 10, characterized in that, Also includes: Between selective etching of the first sacrificial material and deposition of metallic material to form the metal layer (111), one or more layers (101) of the storage structure (141) are formed within the cavity obtained by etching, for example by atomic layer deposition or region selective deposition. The one or more storage layers (101) therein include metals, semiconductors, ferroelectrics or dielectric materials.

12. The method (10) according to any one of claims 1 to 11, characterized in that, The second sacrificial material (41) includes amorphous silicon.

13. The method (10) according to claim 12, characterized in that, The replacement of the second sacrificial material (41) includes selectively etching the second sacrificial material (41), for example, selectively etching the amorphous silicon with phosphoric acid and / or tetramethylammonium hydroxide.

14. A structure (20) suitable for constructing storage devices, particularly ferroelectric storage devices, said structure (20) comprising: A stack of multiple metal layers (111) and dielectric layers (21) arranged alternately along the stacking direction. The stack has a stepped structure (61) shape on the opposite outer side of the stack, wherein the stepped structure (61) shape is formed by a stack of multiple concentric pairs of layers having a dielectric layer (21) and a metal layer (111), wherein the width of the respective pairs of layers continuously decreases along the stacking direction; and The stack has a plurality of storage vias (31), each storage via (31) extending through each layer (111, 21) of the stack, and each storage via (31) is filled with a sacrificial material (41), such as amorphous silicon.

15. The structure (20) according to claim 14, characterized in that, It also includes a plurality of vertical contact holes (151) formed through the stack and filled with a conductive or semi-conductive material (161).

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