High-linearity enhanced GaN-based HEMT device and preparation method thereof

Abstract

The invention discloses a high-linearity enhanced GaN-based HEMT (High Electron Mobility Transistor) device and a preparation method thereof, and the preparation method comprises the steps: carrying out the etching of a P-GaN cap layer outside a gate region, and obtaining a P-GaN gate; preparing a source electrode and a drain electrode on the barrier layer; preparing a SiNx hard mask layer on the source electrode, the drain electrode, the barrier layer and the P-GaN grid electrode; selectively etching the SiNx mask layer on the P-GaN grid in a partitioned manner, and sequentially carrying out O2 plasma treatment and annealing to form a plurality of plasma treatment regions; removing the residual SiNx mask layer on the P-GaN grid electrode, and preparing grid electrode metal on the P-GaN grid electrode and the plasma processing region; and removing the SiNx mask layer in the region where the source electrode and the drain electrode are located to form a contact hole. The grid bias voltage corresponding to the threshold voltage and the transconductance peak value of the device formed in the area, subjected to O2 plasma processing, of the grid is improved, the transconductance peak of the grid is coupled with the transconductance peak of the device formed in the unprocessed area, the transconductance of the device is increased, the stable input voltage swing is kept, and the nonlinear distortion of signals is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a high linearity enhancement-mode GaN-based HEMT device and its fabrication method. Background Technology

[0002] With the widespread adoption of 5G and the development of 6G communication, signal frequencies are increasing daily, making traditional Si-based transistors inadequate. GaN devices, due to their wide bandgap, high voltage withstand capability, and high electron mobility, are well-suited for high-frequency, high-power applications. AlGaN / GaN heterostructures, due to their polarization effect, can form a high-concentration two-dimensional electron gas. Based on this principle, AlGaN / GaN high electron mobility transistors (HEMTs) exhibit excellent high-frequency, high-power characteristics, leading to their widespread application in wireless communication.

[0003] In wireless communication systems, power amplifiers (PAs) are crucial components. GaN-based HEMT devices are well-suited for use as the core components of power amplifiers, significantly improving high-frequency and high-power performance compared to traditional silicon-based transistors. Traditional HEMTs are typically depletion-mode transistors, requiring bipolar power supply designs; in contrast, P-GaN gate HEMT transistors with positive threshold voltages are a better choice. PAs with enhancement-mode HEMTs can be biased using a unipolar power supply, simplifying circuit design and saving space.

[0004] However, for P-GaN gate AlGaN / GaN HEMTs, as the gate bias voltage Vg increases, the transconductance Gm of the device gradually increases to reach a peak and then drops rapidly. When the input signal swing is large, it is easy to cause nonlinear distortion of the output signal. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a high linearity enhancement-type GaN-based HEMT device and its fabrication method.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for fabricating a high linearity enhancement-mode GaN-based HEMT device, the method comprising: The substrate layer, nucleation layer, buffer layer, channel layer, intermediate layer, barrier layer and P-GaN cap layer are stacked sequentially from bottom to top. The P-GaN cap layer outside the gate region is etched, and the remaining P-GaN cap layer in the gate region is used as the P-GaN gate. Source and drain electrodes with ohmic contacts are fabricated on the barrier layer on both sides of the P-GaN gate. A continuous SiN layer is fabricated on the source, drain, barrier layer, and P-GaN gate. x Hard mask layer; Selective partitioning etching removes the SiN on the P-GaN gate. x A mask layer was applied, and the region containing the P-GaN gate was sequentially subjected to O2 plasma treatment and annealing to etch away the SiN. x Multiple plasma processing regions are formed on the P-GaN gate of the mask layer at intervals along the width direction; Remove the remaining SiN on the P-GaN gate x A mask layer is used to prepare a Schottky contact gate metal on the P-GaN gate and the plasma processing region; Remove the SiN from the regions where the source and drain are located. x A mask layer is used to form contact holes, completing the fabrication of the HEMT device.

[0007] In one embodiment of the present invention, the preparation of a substrate layer, a nucleation layer, a buffer layer, a channel layer, an intermediate layer, a barrier layer, and a P-GaN cap layer, which are stacked sequentially from bottom to top, includes: Select the substrate layer; The nucleation layer, the buffer layer, the channel layer, the intermediate layer, the barrier layer, and the P-GaN cap layer are sequentially grown on the substrate layer from bottom to top using a metal-organic chemical vapor deposition method.

[0008] In one embodiment of the present invention, etching is performed on the P-GaN cap layer outside the gate region, and the remaining P-GaN cap layer in the gate region is used as the P-GaN gate, including: The P-GaN cap layer outside the gate region is etched using an inductively coupled plasma etching method, and the remaining P-GaN cap layer in the gate region is used as the P-GaN gate. In one embodiment of the present invention, before fabricating the source and drain electrodes on both sides of the P-GaN gate on the barrier layer, the method further includes: The barrier layer, the intermediate layer, and a portion of the channel layer outside the active region are etched away using inductively coupled plasma etching to form a mesa isolation. In one embodiment of the present invention, a source and a drain with ohmic contacts are fabricated on the barrier layer on both sides of the P-GaN gate, including: Electron materials are deposited in the source and drain regions of the barrier layer using an electron beam evaporation method, followed by annealing in a nitrogen atmosphere to form source and drain electrodes with ohmic contacts. In one embodiment of the present invention, a continuous SiN layer is fabricated on the source, the drain, the barrier layer, and the P-GaN gate. x Hard mask layer, including: A continuous SiN layer was deposited on the source, drain, barrier layer, and P-GaN gate using inductively coupled plasma-enhanced chemical vapor deposition (ICP-CVD). x Hard mask layer.

[0009] In one embodiment of the present invention, selective partition etching is performed to remove the SiN on the P-GaN gate. x A mask layer was applied, and the region containing the P-GaN gate was sequentially subjected to O2 plasma treatment and annealing to etch away the SiN. x Multiple plasma processing regions are formed on the P-GaN gate of the mask layer, spaced apart along the width direction, including: The SiN on the P-GaN gate was selectively etched away along the width direction using reactive ion etching. x Mask layer; The region containing the P-GaN gate is treated with O2 plasma using an inductively coupled plasma etching machine, a reactive ion etching machine, or a high-current ion implanter, followed by annealing in an oxygen atmosphere, so that a GaON thin film is formed on the exposed P-GaN gate, forming multiple plasma-treated regions with GaON thin films spaced apart along the width direction. In one embodiment of the present invention, the remaining SiN on the P-GaN gate is removed. x A mask layer is applied, and a Schottky contact gate metal is fabricated on the P-GaN gate, comprising: The remaining SiN on the P-GaN gate was removed using reactive ion etching. x Mask layer; Schottky contact gate metal is prepared on the exposed P-GaN gate and the plasma-processed region using an electron beam evaporation method.

[0010] In one embodiment of the present invention, the SiN in the regions where the source and drain are located is removed. x The mask layer, forming contact holes, includes: The SiN in the source and drain regions was removed using reactive ion etching. x A mask layer is used to form contact holes.

[0011] Secondly, the present invention provides a high linearity enhancement-mode GaN-based HEMT device, fabricated by the fabrication method described in any of the above embodiments, wherein the HEMT device comprises: The substrate layer, nucleation layer, buffer layer, channel layer, intermediate layer, and barrier layer are stacked sequentially from bottom to top. A P-GaN gate is disposed on the barrier layer; Multiple plasma processing regions are arranged at intervals along the width direction on the P-GaN gate; The source and drain are located on opposite sides of the P-GaN gate, and the source and drain are in ohmic contact with the barrier layer. A gate metal is disposed on the P-GaN gate and the plurality of plasma processing regions; SiN x A mask layer is disposed on the barrier layer between the source and the P-GaN gate and on the barrier layer between the drain and the P-GaN gate.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention performs O2 plasma treatment and annealing on the region containing the P-GaN gate of a P-GaN HEMT, thereby increasing the threshold voltage and gate bias corresponding to the transconductance peak value. Therefore, after selectively partitioning the P-GaN gate of the P-GaN HEMT device with O2 plasma treatment, two HEMTs with different threshold voltages and transconductance peak values ​​will be integrated in the gate width direction, forming a composite device. The threshold voltage and gate bias corresponding to the transconductance peak value of the device formed by the O2 plasma-treated region are increased, and its transconductance peak is coupled with the transconductance peak of the device formed by the untreated region, increasing the transconductance and maintaining a stable input voltage swing. This helps reduce signal nonlinear distortion and greatly improves the linearity of the device. Furthermore, when applied to power amplifier circuits, it can reduce circuit design costs and promote the application of third-generation semiconductors in the communication field.

[0013] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0014] Figure 1 A schematic flowchart illustrating the fabrication method of a high linearity enhancement-mode GaN-based HEMT device provided by this invention; Figures 2a-2k A schematic diagram illustrating the process of fabricating a high linearity enhancement-mode GaN-based HEMT device provided by the present invention; Figure 3 This is a schematic diagram of a high linearity enhancement-type GaN-based HEMT device provided by the present invention. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0016] Example 1 Power amplifiers (PAs) typically use GaN-based HEMT devices to replace silicon-based devices to improve the frequency characteristics of PAs. To address the nonlinearity issues of GaN-based HEMT devices, several technical approaches have been proposed, such as nanochannel gate Fin structure HEMT devices. These devices integrate different HEMTs along the gate width direction through selective etching, forming a composite device. Because the threshold voltage varies with the etching depth, the composite device is equivalent to paralleling a group of field-effect transistors with slightly offset threshold voltages, thereby improving the device's linearity. Other techniques include HEMT devices with heavily doped source regions and HEMT devices with graded-component barrier layers. These techniques significantly improve PA performance.

[0017] These high-linearity HEMTs are all depletion-type HEMTs. Their use in power amplifiers (PAs) introduces bipolar power supplies, increasing circuit design costs and area. Traditional enhancement-type P-GaN HEMTs also suffer from nonlinearity issues, leading to signal nonlinear distortion.

[0018] Therefore, this invention provides a method for fabricating a high linearity enhancement-mode GaN-based HEMT device. Please refer to [link to relevant documentation]. Figure 1 , Figures 2a-2k , Figure 1 This is a schematic flowchart illustrating a method for fabricating a high linearity enhancement-mode GaN-based HEMT device provided by the present invention. Figures 2a-2k This is a schematic diagram illustrating the fabrication process of a high linearity enhancement-mode GaN-based HEMT device provided by the present invention. The fabrication method of the high linearity enhancement-mode GaN-based HEMT device includes: Step 1, please refer to Figure 2a The substrate layer 1, nucleation layer 2, buffer layer 3, channel layer 4, intermediate layer 5, barrier layer 6, and P-GaN cap layer 7 are prepared and stacked sequentially from bottom to top.

[0019] Step 1.1: Select substrate layer 1.

[0020] Optionally, the substrate 1 may be made of Si, SiC, or sapphire.

[0021] Optionally, the thickness of substrate 1 is 1 mm.

[0022] Step 1.2: Using the Metal-organic Chemical Vapor Deposition (MOCVD) method, the nucleation layer 2, buffer layer 3, channel layer 4, intermediate layer 5, barrier layer 6, and P-GaN cap layer 7 are sequentially grown on the substrate from bottom to top.

[0023] Optionally, the nucleation layer 2 may be made of AlN with a thickness of 0.20 μm.

[0024] Optionally, the buffer layer 3 consists of AlN(doped with C) / AlGaN(doped with C) / GaN(doped with C) stacked sequentially from bottom to top, with thicknesses of 0.47 μm / 1 μm / 2.75 μm from bottom to top, and the C doping concentration is 2*10⁻⁶. 17 ~6*10 17 cm -3 .

[0025] Optionally, the channel layer 4 may be made of GaN and have a thickness of 0.32 μm.

[0026] Optionally, the material of the intermediate layer 5 includes AlN with a thickness of 1 nm.

[0027] Optionally, the material of the barrier layer 6 includes AlGaN (Al composition of 20%-25%), with a thickness of 20 nm.

[0028] Optionally, the material of the P-GaN cap layer 7 includes GaN (doped with Mg, at a concentration of 10). 17 cm -3 -10 20 cm -3 The thickness is 80-100nm.

[0029] Step 2, please refer to Figure 2b The P-GaN cap layer 7 outside the gate region is etched, and the remaining P-GaN cap layer 7 in the gate region is used as the P-GaN gate 8.

[0030] Specifically, the P-GaN cap layer 7 outside the gate region is etched using an inductively coupled plasma (ICP) etching method, and the remaining P-GaN cap layer 7 in the gate region is used as the P-GaN gate 8.

[0031] Step 3, please refer to Figure 2c The barrier layer 6, intermediate layer 5, and channel layer 4 of a certain thickness outside the active region are etched away using inductively coupled plasma etching to form mesa isolation between devices.

[0032] Step 4, please refer to Figure 2dSource 9 and drain 10 with ohmic contacts are fabricated on both sides of P-GaN gate 8 on barrier layer 6.

[0033] Specifically, electrode materials are deposited in the source and drain regions of the barrier layer 6 using an electron beam evaporation method, followed by annealing in a nitrogen atmosphere to form a source 9 and a drain 10 with ohmic contacts.

[0034] In other words, an electron beam evaporation stage is used to deposit electrode materials in the source and drain regions of the device, and a rapid annealing furnace is used to anneal the device in a nitrogen atmosphere, so that the electrodes form ohmic contacts with the material surface, forming source 9 and drain 10 with ohmic contacts.

[0035] Optionally, the source 9 and drain 10 are made of Ti / Al / Ni / Au stacked sequentially from bottom to top, with thicknesses of 20nm / 130nm / 50nm / 45nm respectively.

[0036] Step 5, please refer to Figure 2e Continuous SiN was fabricated on the source 9, drain 10, barrier layer 6, and P-GaN gate 8. x Hard mask layer 11.

[0037] Specifically, an inductively coupled plasma enhanced chemical vapor deposition (ICPECVD) method was used to deposit a continuous SiN layer on the source 9, drain 10, barrier layer 6, and P-GaN gate 8. x Hard mask layer 11.

[0038] Step 6, please refer to Figure 2f , Figure 2g Selective partitioning etching removes the SiN on the P-GaN gate 8 x Mask layer 11 is applied, and the region containing the P-GaN gate 8 is sequentially subjected to O2 plasma treatment and annealing to etch away the SiN. x A plurality of plasma processing regions 12 are formed on the P-GaN gate 8 of the mask layer 11 at intervals along the width direction, wherein the width direction is shown in Figure 11. Figure 2g .

[0039] Step 6.1: Selectively etch away the SiN on the P-GaN gate 8 along the width direction using reactive ion etching (RIE). x Mask layer 11.

[0040] Step 6.2: Use an inductively coupled plasma etching machine, a reactive ion etching machine, or a high-current ion implanter to perform O2 plasma treatment on the region where the P-GaN gate 8 is located, and then perform annealing treatment in an oxygen atmosphere to form a GaON thin film on the exposed P-GaN gate 8, forming multiple plasma treatment regions 12 with GaON thin films spaced apart along the width direction.

[0041] Specifically, the region where the P-GaN gate 8 is located can be treated with O2 plasma using an inductively coupled plasma etching machine, a reactive ion etching machine, or a high-current ion implanter, followed by annealing in an oxygen atmosphere, thereby forming a GaON thin film on the exposed P-GaN gate 8.

[0042] Step 7, please refer to Figure 2h , Figure 2i and Figure 2j Remove the remaining SiN on the P-GaN gate 8 x A mask layer 11 is used, and a Schottky contact gate metal 13 is prepared on the P-GaN gate 8 and the plasma processing region 12.

[0043] Step 7.1, please refer to Figure 2h Reactive ion etching was used to remove the remaining SiN on the P-GaN gate 8. x A top view of the gate region of mask layer 11 is shown below. Figure 2i .

[0044] Step 7.2, please refer to Figure 2j Schottky contact gate metal 13 was prepared on the exposed P-GaN gate 8 and the plasma-processed region 12 using electron beam evaporation (EBE).

[0045] Optionally, the gate metal material includes Ni / Au stacked sequentially from bottom to top.

[0046] Step 8, please refer to Figure 2k Remove the SiN in the regions where source 9 and drain 10 are located. x Mask layer 11 forms contact holes, completing the fabrication of HEMT devices.

[0047] Specifically, reactive ion etching is used to remove the SiN in the regions where the source electrode 9 and drain electrode 10 are located. x Mask layer 11 is used to form contact holes.

[0048] This invention proposes a method for fabricating a GaN-based high-linearity enhancement-mode HEMT device for power amplifiers. This method involves selectively partitioning the P-GaN gate region using O2 plasma treatment and annealing in an O2 atmosphere to form multiple plasma-treated regions with GaON thin films spaced apart along the width direction. Since the GaON thin film possesses functions similar to a gate dielectric, it can transform the original Schottky junction into a MIS junction. The GaON thin film also possesses voltage-dividing functions similar to a gate dielectric, thus increasing the device's threshold voltage. This increased threshold voltage consequently leads to a corresponding increase in the voltage corresponding to the device's transconductance peak value. After selectively partitioning O2 plasma treatment and annealing in an O2 atmosphere, the threshold voltage and gate bias corresponding to the peak transconductance in certain regions of the device are improved. This is equivalent to forming a new device in a certain region along the gate width direction of the original device. This new device is a device with a GaON thin film on its surface. Therefore, the device in this embodiment is a composite device, consisting of a parallel connection of the new device and the original device. In the transconductance characteristic curve, as the gate voltage increases, the transconductance of the original device first reaches its peak and then decreases. As the gate voltage continues to increase, the transconductance of the new device reaches its peak. Therefore, the transconductance peaks of the two devices are coupled to each other. The transconductance curve of the composite device increases again after reaching its peak and then decreases, reaching a second peak. Thus, the transconductance of the device remains stable over a large bias range, the linearity is improved, and the nonlinear distortion of the power amplifier is greatly reduced.

[0049] This invention pertains to enhancement-mode HEMT devices used in power amplifiers. They can be driven by a unipolar power supply, simplifying circuit design. This invention improves the linearity of P-GaN HEMTs, significantly reducing input signal nonlinear distortion when used in power amplifiers. The process is simpler and the material cost is lower. The fabrication methods provided by this invention, such as electron beam evaporation, ICP dry etching, and RIE dry etching, are common processes in Si-based semiconductor fabrication and can be effectively integrated with existing Si-based CMOS processes.

[0050] This invention relates to core components of power amplifiers (PAs) in communication systems. Based on the principle of transconductance compensation, the transconductance remains stable over a wide range, which can improve the swing of the PA input signal and reduce the nonlinear distortion of the output signal. Furthermore, this invention is an enhanced HEMT device, which can be directly driven by a unipolar power supply in PA circuit design, simplifying the circuit design.

[0051] Example 2 Based on Embodiment 1, this invention also provides an example of a method for fabricating a high linearity enhancement-mode GaN-based HEMT device for power amplifiers, the method comprising: 1) Preparation of GaN-based epitaxial wafers.

[0052] Specifically, prepare a 6-inch single-crystal silicon substrate with a thickness of 1 mm. Using MOCVD, sequentially deposit a 0.2 μm AlN nucleation layer, a 4 μm C-doped GaN buffer layer, a 300 nm GaN channel layer, a 1 nm AlN interlayer, and a 20 nm AlGaN barrier layer (Al composition 23%, i.e., Al...) on the Si substrate. 0.23 Ga 0.77 N) and a 100 nm Mg-doped P-GaN cap layer (Mg doping concentration of 2*10) 19 cm -3 Its structure is as follows: Figure 2a .

[0053] 2) Fabrication of P-GaN gate.

[0054] Specifically, photolithography is used to cover and protect the P-GaN gate region of the device with photoresist. ICP etching is then used to remove the P-GaN cap layer outside the P-GaN gate region, achieving an etching depth of 100nm to ensure that excess P-GaN cap layer is fully etched. The ICP process parameters are: ICP power 100W, RF power 10W, Cl2 flux 10sccm, BCl3 flux 10sccm, chamber pressure 0.18Pa, chamber temperature 10℃, etching rate accurate to 5nm / min, and etching time 1200s, ensuring precise anisotropic etching of 100nm. The structure is as follows: Figure 2b .

[0055] 3) Physical isolation of devices.

[0056] Specifically, photolithography is used to cover and protect the active region of the device with photoresist. ICP etching is then used to remove GaN and AlGaN outside the active region, achieving an etching depth of 190nm to form a 190nm mesa, ensuring isolation between devices. The ICP process parameters are: ICP power 115W, RF power 25W, Cl2 flux 25sccm, BCl3 flux 10sccm, chamber pressure 0.2Pa, chamber temperature 10℃, etching rate accurate to 95nm / min, and etching time 120s, ensuring precise anisotropic etching of 190nm. The structure is as follows: Figure 2c .

[0057] 4) Deposition of metal in the source and drain regions.

[0058] Specifically, photolithography is used to expose the areas of the device where source and drain metal need to be deposited, while other areas are covered with photoresist. The sample is then placed inside the cavity of an electron beam evaporation (EBE) stage, and a vacuum is drawn to bring the pressure inside the cavity to 1*10. -5Pa was used to sequentially evaporate the metals Ti / Al / Ni / Au from bottom to top in the source / drain region using an electron beam evaporation stage, with thicknesses of 30 nm / 120 nm / 50 nm / 45 nm. The sample was then immersed in NMP solution at 60 °C for 30 min to remove excess metal. Its structure is shown below. Figure 2d .

[0059] 5) Formation of ohmic contacts in the source-drain region.

[0060] Specifically, the sample was placed in a rapid annealing furnace and rapidly annealed at 850°C for 30 seconds to ensure good ohmic contact between the metal and the material surface. The process parameters were: nitrogen flow rate of 2000 sccm in the rapid annealing furnace, temperature raised to 850°C and held for 30 seconds, followed by rapid cooling to room temperature at a rate of 15°C per second.

[0061] 6) SiN x Deposition of hard mask layer.

[0062] Specifically, an 150 nm layer of SiN was deposited on the sample surface using inductively coupled plasma enhanced chemical vapor deposition (ICPECVD). x Hard mask layer. ICPECVD process parameters were: ICP power 450W, NH3 flux 9.7 sccm, Ar flux 140 sccm, 5% SiH4 (He solvent) flux 145 sccm, deposition at 10 Pa and 150℃ chamber environment for 530 s. The dielectric deposition rate was ensured to be accurate to 17 nm / min to obtain 150 nm SiN. x Hard mask layer, its structure is as follows Figure 2e .

[0063] 7) Selected area O2 plasma treatment.

[0064] Specifically, photolithography is used to selectively process the SiN in the region of the device gate that requires processing. x The hard mask layer is exposed, while other areas are protected by photoresist. The exposed SiN is then etched away using a reactive ion etching (RIE) machine. x The hard mask layer was processed using the following RIE equipment parameters: RF power 200W, He flux 10 sccm, CF4 flux 80 sccm, O2 flux 6 sccm, and CHF3 flux 25 sccm. The etching rate was accurate to 140 nm / min, and the etching time was 64 s, which precisely removed the exposed SiNx hard mask layer. The sample was then immersed in acetone solution for 10 min to remove the photoresist. The selected area etching effect and the top view of the resulting device gate region are shown below. Figure 2gAs shown. The sample was subjected to O2 plasma treatment for 2 minutes using ICP. The process parameters of the ICP equipment were: ICP power 300W, RF power 60W, O2 flux 60sccm, chamber pressure 0.2Pa, chamber temperature 10℃, and plasma treatment time 2 minutes. The treated sample was then placed in a rapid annealing furnace and annealed at 500℃ for 5 minutes in an oxygen atmosphere. Its structure is shown below. Figure 2f .

[0065] 8) Etch away excess SiN in the gate region x .

[0066] Specifically, photolithography is used to remove excess SiN in the gate region of the device. x The hard mask layer is exposed, while other areas, including those treated with O2 plasma, are protected by photoresist. Excess SiN is etched away using a reactive ion etching (RIE) machine. x The hard mask layer, RIE equipment process parameters are: RF power 200W, He flux 10 sccm, CF4 flux 80 sccm, O2 flux 6 sccm, CHF3 flux 25 sccm. Etching rate accurate to 140 nm / min, etching time 64 s, which precisely removes excess SiN. x The hard mask layer was etched away. The sample was then immersed in acetone solution for 10 minutes to wash away the photoresist, revealing its structure as follows: Figure 2h The top view of the obtained device gate region is as follows Figure 2i .

[0067] 9) Deposition of gate metal.

[0068] Specifically, photolithography is used to expose the areas of the device where gate metal needs to be deposited while covering other areas with photoresist. The sample is then placed inside the cavity of an electron beam evaporation (EBE) stage, and a vacuum is drawn to bring the pressure inside the cavity to 1*10. -5 Pa, using an electron beam evaporation stage, Ti / Au metals were sequentially evaporated from bottom to top in the source / drain region, with thicknesses of 30 nm / 150 nm. The sample was then immersed in NMP solution at 60 °C for 30 min to remove excess metal. Its structure is shown below. Figure 2j .

[0069] 10) Open the contact hole in the source / drain area.

[0070] Specifically, photolithography is used to expose the areas of the device where contact holes need to be opened, while other areas are covered with photoresist. RIE is then used to etch away the SiN in the exposed areas. xHard mask layer. The RIE equipment process parameters are: RF power 200W, He flux 10 sccm, CF4 flux 80 sccm, O2 flux 6 sccm, CHF3 flux 25 sccm. The etching rate is accurate to 140 nm / min, and the etching time is 64 s, which precisely exposes the SiN in the region. x The hard mask layer is etched away, thus opening the contact hole, and its structure is as follows: Figure 2k .

[0071] Example 3 This embodiment, based on the above embodiments, also provides a high linearity enhancement-mode GaN-based HEMT device, such as... Figure 3 As shown, Figure 3 This is a schematic diagram of a high linearity enhancement-mode GaN-based HEMT device provided by the present invention. The HEMT device is fabricated using the method described in the above embodiments, and includes: The substrate layer 1, nucleation layer 2, buffer layer 3, channel layer 4, intermediate layer 5, and barrier layer 6 are stacked sequentially from bottom to top. P-GaN gate 8 is disposed on barrier layer 6; Multiple plasma processing regions 12 are arranged at intervals along the width direction on the P-GaN gate 8; The source 9 and drain 10 are located on both sides of the P-GaN gate 8, and the source 9 and drain 10 are in ohmic contact with the barrier layer 6. Gate metal 13 is disposed on the P-GaN gate 8 and multiple plasma processing regions 12; SiN x A mask layer 11 is disposed on a barrier layer 6 between the source 9 and the P-GaN gate 8 and on a barrier layer 6 between the drain 10 and the P-GaN gate 8.

[0072] The HEMT device provided in this embodiment of the invention is prepared by the preparation method of the above embodiment, and its principle and beneficial effects are similar, so they will not be repeated here.

[0073] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0074] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0075] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0076] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0077] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0078] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a high linearity enhancement-mode GaN-based HEMT device, characterized in that, The preparation method includes: The substrate layer, nucleation layer, buffer layer, channel layer, intermediate layer, barrier layer and P-GaN cap layer are stacked sequentially from bottom to top. The P-GaN cap layer outside the gate region is etched, and the remaining P-GaN cap layer in the gate region is used as the P-GaN gate. Source and drain electrodes with ohmic contacts are fabricated on the barrier layer on both sides of the P-GaN gate. A continuous SiN layer is fabricated on the source, drain, barrier layer, and P-GaN gate. x Hard mask layer; Selective partitioning etching removes the SiN on the P-GaN gate. x A mask layer was applied, and the region containing the P-GaN gate was sequentially subjected to O2 plasma treatment and annealing to etch away the SiN. x Multiple plasma processing regions are formed on the P-GaN gate of the mask layer at intervals along the width direction; Remove the remaining SiN on the P-GaN gate x A mask layer is used to prepare a Schottky contact gate metal on the P-GaN gate and the plasma processing region; Remove the SiN from the regions where the source and drain are located. x A mask layer is used to form contact holes, completing the fabrication of the HEMT device.

2. The method for fabricating a high linearity enhancement-mode GaN-based HEMT device according to claim 1, characterized in that, The fabrication process involves layering a substrate layer, a nucleation layer, a buffer layer, a channel layer, an intermediate layer, a barrier layer, and a P-GaN cap layer sequentially from bottom to top, including: Select the substrate layer; The nucleation layer, the buffer layer, the channel layer, the intermediate layer, the barrier layer, and the P-GaN cap layer are sequentially grown on the substrate layer from bottom to top using a metal-organic chemical vapor deposition method.

3. The method for fabricating a high linearity enhancement-mode GaN-based HEMT device according to claim 1, characterized in that, Etching the P-GaN cap layer outside the gate region and using the remaining P-GaN cap layer in the gate region as the P-GaN gate includes: The P-GaN cap layer outside the gate region is etched using an inductively coupled plasma etching method, and the remaining P-GaN cap layer in the gate region is used as the P-GaN gate.

4. The method for fabricating a high linearity enhancement-mode GaN-based HEMT device according to claim 1, characterized in that, Before fabricating the source and drain electrodes on both sides of the P-GaN gate on the barrier layer, the process further includes: The barrier layer, the intermediate layer, and a portion of the channel layer outside the active region are etched away using inductively coupled plasma etching to form a mesa isolation.

5. The method for fabricating a high linearity enhancement-mode GaN-based HEMT device according to claim 1, characterized in that, Fabricating source and drain electrodes with ohmic contacts on both sides of the P-GaN gate on the barrier layer includes: Electron materials are deposited in the source and drain regions of the barrier layer using an electron beam evaporation method, followed by annealing in a nitrogen atmosphere to form source and drain electrodes with ohmic contacts.

6. The method for fabricating a high linearity enhancement-mode GaN-based HEMT device according to claim 1, characterized in that, A continuous SiN layer is fabricated on the source, drain, barrier layer, and P-GaN gate. x Hard mask layer, including: A continuous SiN layer was deposited on the source, drain, barrier layer, and P-GaN gate using inductively coupled plasma-enhanced chemical vapor deposition (ICP-CVD). x Hard mask layer.

7. The method for fabricating a high linearity enhancement-mode GaN-based HEMT device according to claim 1, characterized in that, Selective partitioning etching removes the SiN on the P-GaN gate. x A mask layer was applied, and the region containing the P-GaN gate was sequentially subjected to O2 plasma treatment and annealing to etch away the SiN. x Multiple plasma processing regions are formed on the P-GaN gate of the mask layer, spaced apart along the width direction, including: The SiN on the P-GaN gate was selectively etched away along the width direction using reactive ion etching. x Mask layer; The region containing the P-GaN gate is treated with O2 plasma using an inductively coupled plasma etching machine, a reactive ion etching machine, or a high-current ion implanter, followed by annealing in an oxygen atmosphere, so that a GaON thin film is formed on the exposed P-GaN gate, forming multiple plasma-treated regions with GaON thin films spaced apart along the width direction.

8. The method for fabricating a high linearity enhancement-mode GaN-based HEMT device according to claim 1, characterized in that, Remove the remaining SiN on the P-GaN gate x A mask layer is applied, and a Schottky contact gate metal is fabricated on the P-GaN gate, comprising: The remaining SiN on the P-GaN gate was removed using reactive ion etching. x Mask layer; Schottky contact gate metal is prepared on the exposed P-GaN gate and the plasma-processed region using an electron beam evaporation method.

9. The method for fabricating a high linearity enhancement-mode GaN-based HEMT device according to claim 1, characterized in that, Remove the SiN from the regions where the source and drain are located. x The mask layer, forming contact holes, includes: The SiN in the source and drain regions was removed using reactive ion etching. x A mask layer is used to form contact holes.

10. A high linearity enhancement-mode GaN-based HEMT device, characterized in that, The HEMT device is prepared by the preparation method according to any one of claims 1 to 9, and comprises: The substrate layer, nucleation layer, buffer layer, channel layer, intermediate layer, and barrier layer are stacked sequentially from bottom to top. A P-GaN gate is disposed on the barrier layer; Multiple plasma processing regions are arranged at intervals along the width direction on the P-GaN gate; The source and drain are located on opposite sides of the P-GaN gate, and the source and drain are in ohmic contact with the barrier layer. A gate metal is disposed on the P-GaN gate and the plurality of plasma processing regions; SiN x A mask layer is disposed on the barrier layer between the source and the P-GaN gate and on the barrier layer between the drain and the P-GaN gate.

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