Vertical channel transistor capable of improving conductivity and preparation method thereof
By designing convex or concave trench sidewalls in vertical channel transistors and filling them with an insulating layer to form a control gate, the problem of insufficient channel conductivity is solved, achieving the effect of improving conductivity and reducing power consumption without increasing chip area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-18
- Publication Date
- 2026-03-27
AI Technical Summary
Existing vertical channel transistors have insufficient channel conductivity within a limited chip area, resulting in high conduction losses and making it difficult to improve device performance without increasing chip area.
The trench sidewalls are designed to be convex or concave towards the device layer. By filling the trench with an insulating layer and forming a control gate, the channel structure is optimized, and the effective conductive area of the channel layer is increased.
Without increasing chip area, it significantly improves channel conductivity, reduces gate resistance, lowers overall power consumption, and enhances device performance.
Smart Images
Figure CN121751689A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor device manufacturing, and in particular to a vertical channel transistor capable of improving conduction capability and a preparation method thereof. BACKGROUND
[0002] In the prior art vertical channel transistor (such as power MOSFET), the channel conduction capability is directly related to the chip area. With the development of electronic devices towards miniaturization and high power density, how to improve the channel conduction capability and reduce the on-state loss in the limited chip area has become a key technical problem. The prior art transistor with a planar trench structure has problems such as insufficient effective conduction area of the channel and high gate resistance, which limits the further improvement of the device performance. Therefore, there is an urgent need for a new transistor design capable of optimizing the channel structure and improving the conduction capability without increasing the chip area. SUMMARY
[0003] The technical problem to be solved by the present application is to provide a vertical channel transistor capable of improving conduction capability and a preparation method thereof, which can optimize the channel structure and improve the conduction capability without increasing the chip area.
[0004] To solve the above problems, the present application provides a vertical channel transistor capable of improving conduction capability, comprising: a substrate and a device layer on the surface of the substrate; the surface of the device layer comprises a trench, and the trench comprises a control gate, which is insulated from the device layer by an insulating layer; at least one set of opposite side walls of the trench is outwardly convex or inwardly concave towards the device layer.
[0005] Optionally, all side walls of the trench are outwardly convex or inwardly concave towards the device layer.
[0006] Optionally, the device layer comprises a surface source layer, a channel layer below the source layer, and a drain layer below the channel layer.
[0007] Optionally, the device layer is an epitaxial layer.
[0008] Optionally, the material of the control gate is polysilicon, and the material of the insulating layer is silicon oxide.
[0009] To solve the above problems, the present application provides a preparation method of a vertical channel transistor capable of improving conduction capability, comprising: providing a substrate, the surface of the substrate comprising a device layer; forming a trench in the device layer, at least one set of opposite side walls of the trench being outwardly convex or inwardly concave towards the device layer; filling an insulating layer in the trench; and forming a control gate in the insulating layer.
[0010] Optionally, the morphology of all sidewalls of the trench facing the device layer is selected from either an outwardly convex or inwardly concave morphology.
[0011] Optionally, it may also include: implanting a channel layer within the device layer, and simultaneously separating the source layer defining the surface and the drain layer below the channel layer.
[0012] Optionally, the device layer is formed using an epitaxial process.
[0013] Optionally, the control gate is made of polycrystalline silicon, and the insulating layer is made of silicon oxide.
[0014] In the above technical solution, the sidewalls of the trench facing the device layer are designed with an outward or inward convex shape, which can increase the effective conductive area of the subsequently formed channel layer and improve the conductivity of the channel without increasing the chip area. Attached Figure Description
[0015] Appendix Figure 1 The diagram shows the steps of a method for fabricating a vertical channel transistor that can improve conductivity, according to a specific embodiment of the present invention.
[0016] Reference Appendix Figure 2A To be continued Figure 2E The diagram shown is a process flow chart of a method for fabricating a vertical channel transistor that can improve conductivity according to a specific embodiment of the present invention.
[0017] Appendix Figure 3 The diagram shows two optional trench topography schematics of a vertical channel transistor that can improve conductivity according to a specific embodiment of the present invention. Detailed Implementation
[0018] The following detailed description, with reference to the accompanying drawings, illustrates specific embodiments of the vertical channel transistor and its fabrication method that enhance conductivity provided by the present invention.
[0019] Appendix Figure 1 The diagram illustrates the steps of a method for fabricating a vertical channel transistor (VCT) with improved conductivity according to a specific embodiment of the present invention, including: step S10, providing a substrate, the surface of which includes a device layer; step S11, forming a trench within the device layer, wherein at least one set of opposing sidewalls of the trench has an outwardly convex or inwardly concave shape facing the device layer; step S12, filling the trench with an insulating layer; step S13, forming a control gate within the insulating layer; and step S14, implanting a channel layer within the device layer, simultaneously separating a source layer defining the surface and a drain layer below the channel layer.
[0020] Reference Appendix Figure 2A To be continued Figure 2EThe diagram shown is a process flow chart of a method for fabricating a vertical channel transistor according to a specific embodiment of the present invention.
[0021] Reference Appendix Figure 2A As shown, referring to step S10, a substrate 10 is provided, the surface of which includes a device layer 11. The substrate 10 can be an N-type silicon substrate, a P-type silicon substrate, an N-type silicon carbide (SiC) substrate, a P-type silicon carbide substrate, an N-type gallium nitride (GaN) substrate, a P-type gallium nitride substrate, an N-type gallium arsenide (GaAs) substrate, a P-type gallium arsenide substrate, etc. An epitaxial layer is prepared on the substrate surface as the device layer 11 by epitaxial growth, providing a basic conductive structure for the subsequent implantation of the channel layer and source layer.
[0022] Reference Appendix Figure 2B As shown, referring to step S11, a trench 12 is formed in the device layer 11. At least one set of opposing sidewalls of the trench 12 has a convex or concave shape facing the device layer 11. Preferably, the shape of all sidewalls of the trench facing the device layer is selected from either a convex or concave shape. A convex or concave sidewall shape facing the device layer 11 can increase the effective conductive area of the subsequently formed trench layer, improving the conductivity of the trench without increasing the chip area. Preferably, all sidewalls have a concave shape facing the device layer, as shown in the attached figure. Figure 2B Therefore, increasing the effective width of the trench and increasing the cross-sectional area of the gate to reduce the gate resistance is beneficial to reducing overall power consumption.
[0023] Specifically, when forming trenches 12 within device layer 11, precise control of the etching process ensures that at least one set of opposing sidewalls of trench 12 exhibits either an outward or inward convex shape facing device layer 11. For example, in the outward convex shape, the middle of the sidewall protrudes outward from the device layer, forming a bulge-like contour. This allows for a larger spacing between adjacent trenches, reducing parasitic capacitance while increasing the effective conductive area of the channel by increasing the perimeter of the wavy contour of the sidewall. Conversely, in the inward convex shape, the middle of the sidewall recesses inward from the device layer, forming a bowl-shaped structure. This design also significantly increases the effective perimeter of the trench sidewalls compared to traditional vertical planar structures, thereby substantially increasing the effective conductive area of the channel layer without increasing the chip area. This structural design is not only applicable to vertical channel MOSFETs but can also be extended to power devices such as IGBTs and JFETs, as well as RF transistors. Through geometric optimization, while maintaining the same chip area, it achieves a comprehensive improvement in key performance aspects such as channel conductivity, gate resistance, and breakdown voltage, providing an innovative solution for the development of high-power-density semiconductor devices.
[0024] Reference Appendix Figure 2CAs shown, referring to step S12, an insulating layer 13 is filled into the trench 12. The insulating layer 13 is preferably made of silicon oxide and can be formed using a thermal oxidation process. The wafer can be placed in a high-temperature oxidation furnace at 1000-1100°C, preferably using a wet oxide furnace with a faster growth rate. A dense silicon oxide layer is grown on the inner wall of the trench through a chemical reaction between silicon and oxygen, with a thickness typically controlled between 100-600 nm. This process achieves atomic-level bonding between the insulating layer and the device layer, effectively improving insulation reliability. The oxide layer uniformly covers the entire surface of the trench 12, maintaining consistent thickness, especially in the concave sidewall region, avoiding electric field concentration problems caused by uneven thickness and ensuring stable operation of the subsequent control gate.
[0025] Reference Appendix Figure 2D As shown, referring to step S13, a control gate 14 is formed within the insulating layer 13. The material of the control gate 14 is preferably polysilicon. A continuous polysilicon layer can be formed on the surface of the device layer 11 using an epitaxial process. The exposed polysilicon on the surface is then removed by etching or polishing processes to form the control gate 14 within the trench. Polysilicon is preferably used as the gate material. First, a continuous polysilicon layer with a thickness of 300-800 nm is deposited on the surface of the device layer 11 and within the trench 12 using low-pressure chemical vapor deposition at a deposition temperature of 550-620°C. SiH4 is used as the silicon source gas, and phosphorus (N-type) or boron (P-type) impurities are incorporated to control the conductivity type. After deposition, the exposed polysilicon on the surface of the device layer 11 is removed using a chemical mechanical polishing process or a dry etching process, leaving only the polysilicon filling the inner side of the insulating layer 13 within the trench 12 as the control gate 14.
[0026] Reference Appendix Figure 2E As shown, referring to step S14, a channel layer 112 is formed by implantation within the device layer 11, simultaneously separating the source layer 111 defining the surface and the drain layer 113 beneath the channel layer. This step is a conventional step in forming a vertical channel transistor. The channel layer 112 is preferably a P-type semiconductor, and the source layer 111 and drain layer 113 are N-type semiconductors. Alternatively, additional N-type implantation can be performed on the source layer 111 to form a heavily doped N-type semiconductor. + Layer. For example, the channel layer 112 can be p-type doped first, preferably using boron ions (B). + ) or BF2 + This forms a P-type region with a depth of 1-3 μm, serving as the basis for channel conductivity. Subsequently, a supplementary implantation process can be performed to form heavily doped N-type ions on the surface using low-energy, high-dose N-type ions. + Layers reduce contact resistance.
[0027] After the above steps are completed, as shown in the attached document. Figure 2B and 2EAs shown, a specific embodiment of a vertical channel transistor capable of improving conductivity is formed, comprising: a substrate 10, and a device layer 11 on the surface of the substrate; the surface of the device layer 11 includes a trench 12, the trench 12 includes a control gate 14, the control gate 14 being insulated from the device layer 11 by an insulating layer 13; at least one set of opposing sidewalls of the trench 12 are convex or concave in shape facing the device layer. Preferably, the shape of all sidewalls of the trench facing the device layer is selected from either convex or concave. The convex or concave shape of the sidewalls facing the device layer 11 can increase the effective conductive area of the subsequently formed channel layer, improving the conductivity of the channel without increasing the chip area. Preferably, all sidewalls exhibit a concave shape facing the device layer, as shown in the attached figure. Figure 2B Therefore, increasing the effective width of the trench and increasing the cross-sectional area of the gate to reduce the gate resistance is beneficial to reducing overall power consumption.
[0028] Appendix Figure 3 The diagram shows two other optional trench topologies: a trench topology combining concave and planar elements, and a trench topology combining concave and convex elements. These can also achieve the technical effect of improving the conductivity of the channel without increasing the chip area.
[0029] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A vertical channel transistor capable of improving conductivity, comprising: Substrate, and the device layer on the substrate surface; The surface of the device layer includes a trench, and the trench includes a control gate, which is insulated from the device layer by an insulating layer. Its features are, At least one set of opposing sidewalls of the trench has a convex or concave shape facing the device layer.
2. The transistor according to claim 1, characterized in that, The morphology of all sidewalls of the trench facing the device layer is selected from either an outward convex or an inward concave morphology.
3. The transistor according to claim 1, characterized in that, The device layer includes a source layer on the surface, a channel layer below the source layer, and a drain layer below the channel layer.
4. The transistor according to claim 1, characterized in that, The device layer is an epitaxial layer.
5. The transistor according to claim 1, characterized in that, The control gate is made of polycrystalline silicon, and the insulating layer is made of silicon oxide.
6. A method for fabricating a vertical channel transistor capable of improving conductivity, characterized in that, include: A substrate is provided, the surface of which includes a device layer; A trench is formed within the device layer, and at least one set of opposing sidewalls of the trench are convex or concave in shape facing the device layer. Fill the groove with an insulating layer; A control gate is formed within the insulating layer.
7. The method according to claim 6, characterized in that, The morphology of all sidewalls of the trench facing the device layer is selected from either an outward convex or an inward concave morphology.
8. The method according to claim 6, characterized in that, Also includes: A channel layer is formed within the device layer, simultaneously separating and defining the source layer on the surface and the drain layer below the channel layer.
9. The method according to claim 6, characterized in that, The device layer is formed using an epitaxial process.
10. The method according to claim 6, characterized in that, The control gate is made of polycrystalline silicon, and the insulating layer is made of silicon oxide.