Silicon carbide MOSFET device and preparation method thereof

Abstract

The invention provides a silicon carbide MOSFET device and a preparation method thereof. The silicon carbide MOSFET device comprises a substrate, one side surface of which is provided with a first groove, and the substrate has a first doping type; the first doping region is located in the substrate at the bottom of the first groove and has a second doping type; the gate structure is located on the side wall of the first groove, and the bottom of the gate structure is in contact with the first doped region; the interlayer dielectric layer is located on the surface, away from the first doped region, of the gate structure and the surface, away from the side wall of the first groove, of the gate structure; the source region is located in the substrate, and one side is in contact with the gate structure; the source electrode conducting layer is located in the first groove, on the surface, away from the substrate, of the interlayer dielectric layer and on part of the surface of the substrate so as to be in contact with the first doping region and the source region. According to the invention, the performance of the first groove type silicon carbide MOSFET device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a silicon carbide MOSFET device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), a third-generation semiconductor, is a new generation of power semiconductor material. Due to its unique physical properties, it exhibits significant advantages in high-voltage, high-temperature, and high-frequency applications, gradually becoming a core direction for replacing traditional silicon-based power devices. Silicon carbide has a bandgap (3.2 eV) three times that of silicon (1.1 eV), a breakdown field strength (3 MV / cm) ten times that of silicon, and a thermal conductivity (4.9 W / cm·K) three times that of silicon. These characteristics allow it to withstand higher operating voltages (>1200V), higher switching frequencies (MHz level), and higher junction temperatures (>200℃), significantly reducing system heat dissipation requirements. For example, at the same 1200V voltage level, silicon carbide devices with the same resistance specifications have losses more than 50% lower than silicon-based IGBTs, and their volume is reduced to less than 1 / 5, making them suitable for high power density designs.

[0003] Currently, in trench silicon carbide MOS devices, the current is concentrated in the channel region of the device during reverse recovery or short-circuit overshoot. This not only exacerbates the bipolar degradation of the device, but also limits the overcurrent capability of the device. Summary of the Invention

[0004] The main objective of this application is to provide a silicon carbide MOSFET device and its fabrication method, so as to at least solve the problem that the performance of trench-type silicon carbide MOSFET devices in the prior art needs to be further improved.

[0005] To achieve the above objectives, according to one aspect of this application, a silicon carbide MOSFET device is provided, comprising: a substrate having a first trench on one side surface, the substrate having a first doping type; a first doped region located in the substrate at the bottom of the first trench and having a second doping type; a gate structure located on the sidewall of the first trench and having its bottom in contact with the first doped region; an interlayer dielectric layer located on the surface of the gate structure away from the first doped region and on the surface of the gate structure away from the sidewall of the first trench; a source region located in the substrate and having one side in contact with the gate structure; and a source conductive layer located in the first trench, on the surface of the interlayer dielectric layer away from the substrate, and on a portion of the surface of the substrate, for contacting the first doped region and the source region, respectively.

[0006] Optionally, the first doped region includes: a first sub-doped region located at the bottom of the first trench and in contact with at least the gate structure; and a second sub-doped region located within the first sub-doped region and in contact with at least the source conductive layer, wherein the doping concentration of the second sub-doped region is greater than the doping concentration of the first sub-doped region.

[0007] Optionally, the contact surface between the source conductive layer and the second sub-doped region is an ohmic contact surface or a Schottky contact surface.

[0008] Optionally, the second sub-doped region satisfies at least one of the following: the junction depth of the second sub-doped region is 1 μm to 1.5 μm; and the doping concentration of the second sub-doped region first increases and then decreases along the direction from the substrate to the source conductive layer.

[0009] Optionally, the first trench includes a first sub-trench and a second sub-trench arranged sequentially and connected along a predetermined direction, the predetermined direction being the direction from the source conductive layer to the substrate, the width of the first sub-trench being greater than the width of the second sub-trench, the source conductive layer being located in the first sub-trench and the second sub-trench, and the second sub-doped region wrapping around the bottom corner of the second sub-trench and contacting the interlayer dielectric layer.

[0010] Optionally, the gate structure includes: a first oxide layer located between a portion of the sidewall of the first trench and the interlayer dielectric layer, the thickness of the first oxide layer being greater than or equal to 2000 angstroms; a second oxide layer located on the remaining portion of the sidewall of the first trench, in contact with a portion of the surface of the first oxide layer away from the first doped region and the source region, respectively; and a gate layer located between the second oxide layer and the interlayer dielectric layer.

[0011] Optionally, the interlayer dielectric layer includes: a first dielectric layer located on the surface of the gate structure away from the first doped region and on a portion of the surface of the source region, the first dielectric layer being made of silicon nitride; a second dielectric layer located on the surface of the first dielectric layer away from the substrate, the second dielectric layer being made of silicon oxide; and a third dielectric layer located on the surface of the second dielectric layer away from the first dielectric layer and between the gate structure and the source conductive layer, the third dielectric layer being made of silicon nitride.

[0012] Optionally, the source region includes: a body region located in the substrate and in contact with the gate structure, having the second doping type; a second doped region located in the body region and in contact with the gate structure, having the first doping type, wherein the surface of the second doped region near the source conductive layer is a portion of the surface of the substrate, and the interlayer dielectric layer is also located on the surface of the second doped region near the source conductive layer; and a third doped region located in the body region and on the side of the second doped region away from the gate structure, wherein the portion of the surface of the third doped region near the source conductive layer is in contact with the portion of the surface of the second doped region away from the source conductive layer, the third doped region has the second doping type, the doping concentration of the third doped region is greater than the doping concentration of the body region, and the source conductive layer is in contact with both the second doped region and the third doped region.

[0013] According to another aspect of this application, a method for fabricating the silicon carbide MOSFET device is provided, comprising: providing an initial device, the initial device including an initial substrate, an initial trench, and a first mask layer, the first mask layer being located on the surface of the initial substrate, the initial trench extending from the first mask layer into the initial substrate, the initial substrate having a first doping type; forming a first doped region having a second doping type in the initial substrate at the bottom of the initial trench by at least stepwise ion implantation; removing the first mask layer and forming a gate structure, an interlayer dielectric layer, a source region, and a source conductive layer, the remaining initial substrate forming a substrate, the initial trench after removing the first mask layer forming a first trench, the gate structure being located on the sidewall of the first trench and in contact with the first doped region, the interlayer dielectric layer being located on the surface of the gate structure away from the first doped region and on the surface of the gate structure away from the sidewall of the first trench, the source region being located in the substrate and in contact with the gate structure, and the source conductive layer being located in the first trench, on the surface of the interlayer dielectric layer away from the substrate, and on a portion of the surface of the substrate, to contact the first doped region and the source region, respectively.

[0014] Optionally, forming a first doped region having a second doping type in the initial substrate at the bottom of the initial trench via at least stepwise ion implantation includes: ion implanting the initial device to form a first initial doped region in the initial substrate at the bottom of the initial trench, the first initial doped region having the second doping type; forming a first initial dielectric layer on the sidewall of the initial trench where the first initial doped region is formed and on the surface of the first mask layer away from the initial substrate, and ion implanting the exposed bottom of the initial trench to form a second initial doped region having the second doping type in the first initial doped region, the remaining first initial doped region forming a first sub-doped region; forming a second initial dielectric layer on the exposed surface of the first initial dielectric layer, and etching the exposed second initial doped region to form a second sub-trench in the second initial doped region, the remaining second initial doped region forming a second sub-doped region, the first sub-doped region and the second sub-doped region constituting the first doped region.

[0015] By applying the technical solution of this application, a first doped region is formed at the bottom of the first trench, and the source conductive layer extends into the first trench of the substrate to contact the first doped region, forming a freewheeling channel during reverse recovery or short-circuit overshoot. During reverse recovery or short-circuit overshoot, the current is collected and extracted from the bottom of the first trench, avoiding excessive concentration in the channel region and reducing the current density in the channel region. This helps to reduce the negative impact of bipolar degradation on device performance. This design introduces an additional diode in the first trench to optimize the current path inside the device, making the current distribution more uniform, reducing local overheating, and contributing to the stable operation of the device under high current, thus improving the device's overcurrent capability. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic diagram of the structure of a silicon carbide MOSFET device provided according to a first embodiment of this application is shown;

[0018] Figure 2 A schematic diagram of the structure of a silicon carbide MOSFET device provided according to a second embodiment of this application is shown;

[0019] Figure 3 It shows Figure 1 A schematic diagram of the reverse freewheeling path of a silicon carbide MOSFET device;

[0020] Figure 4 It shows Figure 2 A schematic diagram of the reverse freewheeling path of a silicon carbide MOSFET device;

[0021] Figure 5 A schematic flowchart of a method for fabricating a silicon carbide MOSFET device according to an embodiment of this application is shown;

[0022] Figures 6 to 16 The diagrams show the structural schematics obtained after each process step of the fabrication method of the silicon carbide MOSFET device provided according to the embodiments of this application.

[0023] The accompanying drawings include the following reference numerals:

[0024] 10. Substrate; 11. First trench; 12. First doped region; 13. Gate structure; 14. Interlayer dielectric layer; 15. Source region; 16. Source conductive layer; 111. First sub-trench; 112. Second sub-trench; 121. First sub-doped region; 122. Second sub-doped region; 131. First oxide layer; 132. Second oxide layer; 133. Gate layer; 141. First dielectric layer; 142. Second dielectric layer; 143. Third dielectric layer; 144. First partial dielectric layer; 145. Second preparatory dielectric layer; 146. Second partial dielectric layer; 151. Body region; 152. Second doped region; 153. Third doped region; 20. Initial substrate; 21. Initial trench; 22. First mask layer; 2 3. First initial doped region; 24. First initial dielectric layer; 25. Second initial doped region; 26. Second initial dielectric layer; 27. Intermediate mask layer; 28. Fourth initial dielectric layer; 29. ​​Fifth initial dielectric layer; 30. Third intermediate dielectric layer; 31. Sixth initial dielectric layer; 32. Sixth intermediate dielectric layer; 33. First intermediate dielectric layer; 34. Second intermediate dielectric layer; 35. Third initial doped region; 36. Fourth initial doped region; 37. First contact hole; 38. Second contact hole; 40. First source portion; 50. Preparative substrate; 51. Second well region; 52. First well region; 53. Second photoresist layer; 341. First sub-dielectric layer; 342. Second sub-dielectric layer; 343. Third sub-dielectric layer. Detailed Implementation

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be used interchangeably where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] As described in the background section, in the prior art, the current of trench silicon carbide MOSFET devices is concentrated in the channel region of the device during reverse recovery or short-circuit overshoot. This not only exacerbates the bipolar degradation of the device, but also limits the overcurrent capability of the device. Therefore, the performance of trench silicon carbide MOSFET devices needs to be further improved. To solve this technical problem, the embodiments of this application provide a silicon carbide MOSFET device and its fabrication method.

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0030] This application provides a silicon carbide MOSFET device. Figure 1 A schematic diagram of the structure of a silicon carbide MOSFET device according to an embodiment of this application is shown as an example. Figure 2 A schematic diagram of the structure of a silicon carbide MOSFET device according to another embodiment of this application is shown as an example. Figure 1 and Figure 2 As shown, the silicon carbide MOSFET device includes:

[0031] The substrate 10 has a first trench 11 on one side surface, and the substrate 10 has a first doping type;

[0032] Specifically, the substrate 10 provides a conductive path and supports the entire device structure. The substrate 10 may include stacked silicon carbide substrates and silicon carbide epitaxial layers, with the first trench 11 located within the silicon carbide epitaxial layer. Specifically, the first doping type may be P-type doping or N-type doping. The first trench 11 may be a cuboid trench, a cylindrical trench, or a trench of other shapes.

[0033] The first doped region 12 is located in the substrate 10 at the bottom of the first trench 11 and has a second doping type;

[0034] Specifically, the second doping type is different from the first doping type. That is, the first doped region 12 has a different doping type than the substrate 10, thereby integrating an additional diode at the bottom of the first trench 11.

[0035] The gate structure 13 is located on the sidewall of the first trench 11 and its bottom is in contact with the first doped region 12;

[0036] Interlayer dielectric layer 14 is located on the surface of the gate structure 13 away from the first doped region 12 and on the surface of the gate structure 13 away from the sidewall of the first trench 11.

[0037] Specifically, the interlayer dielectric layer 14 is used to isolate the gate and the source to prevent them from short-circuiting.

[0038] Source region 15 is located in the substrate 10 and is in contact with the gate structure 13 on one side;

[0039] The source conductive layer 16 is located in the first trench 11, on the surface of the interlayer dielectric layer 14 away from the substrate 10, and on a portion of the surface of the substrate 10, to contact the first doped region 12 and the source region 15, respectively.

[0040] Specifically, the source conductive layer 16 enables current to flow into or out of the device efficiently. The contact between the source conductive layer 16 and the source region 15 can be an ohmic contact. Optionally, the contact between the source conductive layer 16 and the first doped region 12 can be an ohmic contact or a Schottky contact.

[0041] In the described embodiment, by setting a first doped region at the bottom of the first trench, the source conductive layer extends into the first trench of the substrate and contacts the first doped region, forming a freewheeling channel during reverse recovery or short-circuit overshoot. During reverse recovery or short-circuit overshoot, the current is collected and extracted from the bottom of the first trench, avoiding excessive concentration in the channel region and reducing the current density in the channel region. This helps to reduce the negative impact of bipolar degradation on device performance. This design introduces an additional diode in the first trench to optimize the current path inside the device, making the current distribution more uniform, reducing local overheating, and contributing to the stable operation of the device under high current, thus improving the device's overcurrent capability.

[0042] According to some optional embodiments of this application, such as Figure 1 and Figure 2 As shown, the first doped region 12 includes: a first sub-doped region 121, located at the bottom of the first trench 11 and in contact with at least the gate structure 13; and a second sub-doped region 122, located in the first sub-doped region 121 and in contact with at least the source conductive layer 16, wherein the doping concentration of the second sub-doped region 122 is greater than the doping concentration of the first sub-doped region 121. In this embodiment, the first doped region 12 for the freewheeling channel is designed to include two sub-doped regions with different concentrations. The second sub-doped region 122 is in direct contact with the source conductive layer 16 and has a higher doping concentration. On the one hand, this can effectively enhance the carrier extraction capability. On the other hand, it can act as a freewheeling path inside the device when the device is subjected to reverse recovery or short-circuit overshoot with a large current, further preventing excessive current concentration in a specific area, reducing the formation of local hot spots, and reducing the risk of damage and degradation of the device due to overheating. Compared with the second sub-doped region 122, the first sub-doped region 121 has a lower doping concentration. This design helps to extract more carriers during the freewheeling process, reducing the charge remaining in the first sub-doped region 121 at the moment of device turn-off, thereby reducing the tail current and charge storage at the time of device turn-off, improving the switching speed and efficiency of the device, and thus improving its electrical performance.

[0043] In other exemplary solutions, such as Figure 1 and Figure 2 As shown, the contact surface between the source conductive layer 16 and the second sub-doped region 122 is an ohmic contact surface or a Schottky contact surface. In this embodiment, by using an ohmic contact or a Schottky contact, an additional body diode or Schottky diode is integrated at the bottom of the first trench 11 of the device. This can further enhance the freewheeling capability of the device under the extreme conditions and effectively mitigate the negative impact of bipolar degradation on device performance.

[0044] Specifically, such as Figure 1As shown, the contact surface between the source conductive layer 16 and the second sub-doped region 122 is an ohmic contact surface, and the diode additionally integrated at the bottom of the first trench 11 is a body diode. Figure 2 As shown, the contact surface between the source conductive layer 16 and the second sub-doped region 122 is a Schottky contact surface, and the diode additionally integrated at the bottom of the first trench 11 is a Schottky diode.

[0045] Figure 3 It shows Figure 1 The reverse freewheeling path of the silicon carbide MOSFET device in the middle. Figure 4 It shows Figure 2 The reverse freewheeling path of a silicon carbide MOSFET device. For example... Figure 3 and Figure 4 As shown, the silicon carbide MOSFET device of this application introduces a body diode or Schottky diode for freewheeling in the first trench, which makes the current distribution more uniform, effectively alleviates the SiC bipolar degradation phenomenon, and extends the service life of the silicon carbide MOSFET device.

[0046] In some embodiments, the junction depth of the second sub-doped region 122 is 1 μm to 1.5 μm. For example, the junction depth of the first and second sub-doped regions can be 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, or 1.5 μm, etc. In silicon carbide MOSFETs, the thickness and doping concentration of the substrate directly affect the breakdown voltage of the device. If the junction depth of the second sub-doped region is too deep, approaching or exceeding the effective blocking layer of the substrate, the electric field will directly penetrate this layer when the device is subjected to high voltage, leading to a decrease in breakdown voltage or even device failure. A junction depth of less than or equal to 1.5 μm ensures sufficient distance between the second sub-doped region and the substrate, avoiding electric field punch-through and thus maintaining a high breakdown voltage of the device. On the other hand, if the junction depth of the second sub-doped region is too shallow, the distance between it and the metal contact layer above will be shortened. Under high electric field conditions, this close proximity may lead to electric field punch-through, which will also cause a sharp drop in breakdown voltage. Setting the junction depth to be greater than or equal to 1μm ensures a sufficient insulation distance between the second sub-doped region and the metal contact, avoiding this phenomenon. Furthermore, to ensure high-efficiency operation of the MOSFET, the on-resistance of the device needs to be minimized, which typically depends on the thickness of the epitaxial layer. The thinner the epitaxial layer, the lower the on-resistance, but this also reduces the device's breakdown voltage. At rated voltage, by precisely controlling the junction depth of the epitaxial layer and the second sub-doped region, it is possible to achieve a thin epitaxial layer while maintaining breakdown voltage, thereby reducing on-resistance and conduction losses. A junction depth of 1μm to 1.5μm combined with a thin epitaxial layer perfectly meets this requirement, achieving an optimal balance between conduction losses and breakdown voltage.

[0047] In other embodiments, the doping concentration of the second sub-doped region first increases and then decreases along the direction from the substrate to the source conductive layer. In this embodiment, the doping concentration distribution of the second sub-doped region exhibits a characteristic of first increasing and then decreasing. That is, near the bottom of the first trench, the doping concentration gradually increases to reach a peak value, and then gradually decreases as it approaches the source conductive layer. This controls the peak value of the implanted concentration in the second sub-doped region to be in the middle position of the second sub-doped region. On the one hand, this can effectively enhance the breakdown voltage performance of the second sub-doped region and avoid premature breakdown; on the other hand, it can enhance the carrier extraction capability and protect the gate structure.

[0048] According to one specific implementation of this application, such as Figure 1 and Figure 2 As shown, the first trench 11 includes a first sub-trench 111 and a second sub-trench 112 arranged sequentially and connected along a predetermined direction. The predetermined direction is from the source conductive layer 16 to the substrate 10. The width of the first sub-trench 111 is greater than the width of the second sub-trench 112. The source conductive layer 16 is located in the first sub-trench 111 and the second sub-trench 112. The second sub-doped region 122 wraps around the bottom corner of the second sub-trench 112 and contacts the interlayer dielectric layer 14.

[0049] In the embodiment, the first sub-trench 111 and the second sub-trench 112 contact each other to form a stepped first trench 11 structure. By introducing the stepped first trench 11 structure, a large contact area can be formed between the second sub-doped region 122 at the bottom of the first trench 11 and the source conductive layer 16, thereby making the contact area of ​​the body diode or Schottky diode larger, and thus making the device have a stronger freewheeling capability.

[0050] In specific applications, the junction depth refers to the doping depth of the doped region. The predetermined direction is parallel to the thickness direction of the device. The direction of the trench width is perpendicular to the thickness direction of the device.

[0051] Of course, in addition to the embodiments described above, in some other exemplary embodiments, the first trench may also consist only of the first sub-trench, which contacts a portion of the upper surface of the second sub-doped region.

[0052] In one of the alternative solutions, such as Figure 1 and Figure 2As shown, the gate structure 13 includes: a first oxide layer 131 located between a portion of the sidewall of the first trench 11 and the interlayer dielectric layer 14, the thickness of the first oxide layer 131 being greater than or equal to 2000 angstroms; a second oxide layer 132 located on the remaining portion of the sidewall of the first trench 11, in contact with a portion of the surface of the first oxide layer 131 away from the first doped region 12 and the source region 15, respectively; and a gate layer 133 located between the second oxide layer 132 and the interlayer dielectric layer 14. In this embodiment, the first oxide layer 131 is disposed between a portion of the sidewalls of the first trench 11 and the interlayer dielectric layer 14, and its thickness is set to be more than 2000 Å. This can enhance the electric field management at the edge of the gate structure 13 and improve the stability and reliability of the device. The second oxide layer 132 is adjacent to the first oxide layer 131 and covers the remaining sidewalls of the first trench 11. It directly contacts the surface of the first oxide layer 131 away from the first doped region 12 and the source region 15, forming an electrical insulation barrier between the gate and the source, while ensuring effective control of the gate. The gate layer 133 is located between the second oxide layer 132 and the interlayer dielectric layer 14, constituting the core control component of the first trench 11 type silicon carbide MOSFET device.

[0053] In this application, the introduction of a thicker first oxide layer 131 and a first doped region 12 both serve to shield the electric field of the device gate oxide, thereby improving device reliability. Simultaneously, the thick oxide layer and the first doped region 12 can reduce the device gate-drain capacitance, lower switching losses, and further enhance the device's electrical performance.

[0054] Optionally, the thickness of the first oxide layer 131 is greater than or equal to 2000 angstroms and less than or equal to 3000 angstroms.

[0055] According to another alternative embodiment of this application, such as Figure 1 and Figure 2 As shown, the interlayer dielectric layer 14 includes: a first dielectric layer 141, located on the surface of the gate structure 13 away from the first doped region 12 and on the surface of the source region 15, wherein the material of the first dielectric layer 141 is silicon nitride; a second dielectric layer 142, located on the surface of the first dielectric layer 141 away from the substrate 10, wherein the material of the second dielectric layer 142 is silicon oxide; and a third dielectric layer 143, located on the surface of the second dielectric layer 142 away from the first dielectric layer 141 and between the gate structure 13 and the source conductive layer 16, wherein the material of the third dielectric layer 143 is silicon nitride. This embodiment provides a composite dielectric layer design, which not only improves the reliability of the device but also optimizes its electrical performance. The combination of silicon nitride and silicon oxide utilizes the high dielectric constant of silicon nitride and the low dielectric constant of silicon oxide to form effective isolation between the gate and source, reducing Miller capacitance and improving the switching speed of the device.

[0056] Optionally, the second dielectric layer 142 may specifically include stacked USG (Undoped Silicate Glass) and BPSG (Boron Phosphorous Silicate Glass).

[0057] In one embodiment, such as Figure 1 and Figure 2 As shown, the silicon carbide MOSFET device further includes a second trench located in the source region, and the source conductive layer is located in the second trench to contact the source region.

[0058] In some embodiments, such as Figure 1 and Figure 2 As shown, the source region 15 includes: a body region 151, located in the substrate 10 and in contact with the gate structure 13, having the second doping type; a second doped region 152, located in the body region 151 and in contact with the gate structure 13, having the first doping type, wherein the surface of the second doped region 152 near the source conductive layer 16 is a portion of the surface of the substrate 10, that is, the surface of the second doped region 152 near the source conductive layer 16 is flush with a portion of the surface of the substrate 10, and the interlayer dielectric layer 14 is also located on the surface of the second doped region 152 near the source conductive layer 16; and a third doped region 153, located in... In the body region 151, and located on the side of the second doped region 152 away from the gate structure 13, a portion of the surface of the third doped region 153 near the source conductive layer 16 is in contact with a portion of the surface of the second doped region 152 away from the source conductive layer 16 (i.e., a portion of the upper surface of the third doped region 153 is in contact with a portion of the lower surface of the second doped region 152). The third doped region 153 has the second doping type, and the doping concentration of the third doped region 153 is greater than the doping concentration of the body region 151. The source conductive layer 16 is in contact with both the second doped region 152 and the third doped region 153.

[0059] In the embodiment, the source region 15 includes a body region 151, a second doped region 152, and a first doped region 12. This doping design, combined with the body diode in the first trench 11, optimizes the current path, promotes the effective pumping and recombination of carriers, further alleviates the thermal effect, increases the freewheeling path, and manages the current density, thereby further effectively solving the bipolar degradation problem of silicon carbide trench MOSFETs and significantly improving the overcurrent capability of the device.

[0060] In one specific embodiment, the second doped region and the third doped region may be arranged and in contact along a direction perpendicular to the thickness direction of the device (not shown in the figure).

[0061] In another specific embodiment, the second doped region 152 can also be as follows: Figure 1 and Figure 2 As shown, they are arranged in a direction that intersects with but is not perpendicular to the thickness direction of the device, and are in contact.

[0062] like Figure 1 As shown, the first dielectric layer 141 may be located only on a portion of the upper surface of the second doped region 152. The source conductive layer 16 may contact the surface of the second doped region 152 away from the gate structure 13 (i.e., the side of the second doped region 152) and the portion of the surface of the second doped region 152 near the first dielectric layer 141 (i.e., a portion of the upper surface of the second doped region 152).

[0063] like Figure 2 As shown, the first dielectric layer 141 may also cover the entire upper surface of the second doped region 152. The source conductive layer 16 is in contact with the surface of the second doped region 152 away from the gate structure 13 (i.e., the side surface of the second doped region 152).

[0064] Specifically, such as Figure 1 and Figure 2 As shown, the first oxide layer 131 is located between the sidewall of the first sub-trench 111 and the third dielectric layer 143, and the gate layer 133 is located between the second oxide layer 132 and the third dielectric layer 143.

[0065] In this application, such as Figure 1 As shown, the plane of the third dielectric layer 143 away from the first sub-doped region 121 can be flush with the plane of the second dielectric layer 142 away from the first sub-doped region 121. Figure 2 As shown, the plane of the third dielectric layer 143 away from the first sub-doped region 121 may also be higher than the plane of the second dielectric layer 142 away from the first sub-doped region 121.

[0066] Furthermore, the silicon carbide MOSFET device of this application further includes a drain conductive layer located on the surface of the substrate away from the source conductive layer. The contact surface between the source conductive layer and the substrate is an ohmic contact surface.

[0067] In this application, the source conductive layer and the drain conductive layer can each be a single-layer conductive film or a multi-layer conductive film. The materials of the source conductive layer and the drain conductive layer are independently selected from at least one or more of aluminum, copper, nickel, titanium, tungsten, molybdenum, gold, and silver. The materials of the first oxide layer and the second oxide layer can be independently selected from one or more of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and titanium oxide. The material of the gate layer can be polycrystalline silicon, a metal gate, amorphous silicon, or microcrystalline silicon, etc.

[0068] In one embodiment, the silicon carbide MOSFET device of this application is an NMOS, wherein the substrate is an N-type silicon carbide substrate, the first sub-doped region is a P+ doped region, the second sub-doped region is a P- doped region, the body region is a P- doped region, the second doped region is an N+ doped region, the third doped region is a P+ doped region, the first oxide layer and the second oxide layer are both silicon oxide layers, the gate layer is a polysilicon layer, the first dielectric layer is a silicon nitride layer, the second dielectric layer is a silicon oxide layer, and the third dielectric layer is a silicon nitride layer. The source conductive layer is a multi-layer structure, including a nickel layer and an aluminum-copper alloy layer sequentially stacked along the direction away from the substrate.

[0069] Of course, in other embodiments, the silicon carbide MOSFET device of this application can also be a PMOS. The materials of each film layer in the silicon carbide MOSFET device are not limited to the materials mentioned in the embodiments. Those skilled in the art can flexibly select appropriate materials as the film layer materials in the device according to the actual situation.

[0070] This application also provides a method for fabricating the silicon carbide MOSFET device described above. Figure 5 This is a flowchart of a method for fabricating a silicon carbide MOSFET device according to an embodiment of this application. Figures 6 to 15 as well as Figure 1 This is a schematic diagram of the structure obtained after each process step in one embodiment of the method. Figures 6 to 14 , Figure 16 as well as Figure 2 This is a schematic diagram of the structure obtained after each process step in another embodiment of the method. For example... Figures 5 to 16 , Figure 1 and Figure 2 As shown, the method includes the following steps:

[0071] Step S201: Provide an initial device, the initial device including an initial substrate 20, an initial trench 21 and a first mask layer 22, the first mask layer 22 being located on the surface of the initial substrate 20, the initial trench 21 penetrating from the first mask layer 22 into the initial substrate 20, the initial substrate 20 having a first doping type;

[0072] Step S202, at least by step ion implantation, a first doped region 12 having a second doping type is formed in the initial substrate 20 at the bottom of the initial trench 21;

[0073] Specifically, the stepwise ion implantation method refers to decomposing the ion implantation process into multiple steps, and achieving fine doping control by controlling the implantation energy, implantation dose, and ion type of each step.

[0074] In step S203, the first mask layer 22 is removed to form a gate structure 13, an interlayer dielectric layer 14, a source region 15, and a source conductive layer 16. The remaining initial substrate 20 forms a substrate 10. The initial trench 21 after removing the first mask layer 22 forms a first trench. The gate structure 13 is located on the sidewall of the first trench and is in contact with the first doped region 12. The interlayer dielectric layer 14 is located on the surface of the gate structure 13 away from the first doped region 12 and on the surface of the gate structure 13 away from the sidewall of the first trench. The source region 15 is located in the substrate and is in contact with the gate structure 13. The source conductive layer 16 is located in the first trench, on the surface of the interlayer dielectric layer 14 away from the substrate, and on a portion of the surface of the substrate, so as to contact the first doped region 12 and the source region 15, respectively.

[0075] The embodiments described above first provide an initial device comprising an initial substrate, an initial trench, and a first mask layer. A first doped region with a second doping type is formed at the bottom of the initial trench of the initial device, at least through stepwise ion implantation. The formation of the first doped region optimizes the distribution of charge carriers, reducing bipolar degradation during reverse recovery or short-circuit overshoot, thereby improving the device's reliability and lifespan. The stepwise ion implantation method effectively controls the depth and concentration of the first doped region, ensuring relatively stable diode characteristics within the device. Finally, the first mask layer is removed, and a gate structure, an interlayer dielectric layer, a source region, and a source conductive layer are formed to obtain the final silicon carbide MOSFET device. This method introduces an additional diode in the first trench of the device to optimize the internal current path, resulting in a more uniform current distribution, reducing local overheating, and contributing to stable operation of the device under high current, thus improving the device's overcurrent capability.

[0076] Optionally, at least through stepwise ion implantation, such as Figures 8 to 10 As shown, a first doped region 12 having a second doping type is formed in the initial substrate 20 at the bottom of the initial trench 21, including: Figure 8As shown, the initial device is ion implanted to form a first initial doped region 23 in the initial substrate 20 at the bottom of the initial trench 21, the first initial doped region 23 having the aforementioned dual doping type; as Figure 8 and Figure 9 As shown, a first initial dielectric layer 24 is formed on the sidewall of the initial trench 21 where the first initial doped region 23 is formed and on the surface of the first mask layer 22 away from the initial substrate 20. Ion implantation is performed on the exposed bottom of the initial trench 21 to form a second initial doped region 25 with the second doping type in the first initial doped region 23. The remaining first initial doped region 23 forms a first sub-doped region 121. Figure 9 and Figure 10 As shown, a second initial dielectric layer 26 is formed on the exposed surface of the first initial dielectric layer 24, and the exposed second initial doped region 25 is etched to form a second sub-trench 112 in the second initial doped region 25. The remaining second initial doped region 25 forms a second sub-doped region 122. The first sub-doped region 121 and the second sub-doped region 122 constitute the first doped region 12.

[0077] The embodiment described provides a scheme for forming a first doped region 12 comprising two sub-doped regions with different concentrations through step-by-step implantation and etching techniques. The second sub-doped region 122 is in direct contact with the source conductive layer 16 and has a higher doping concentration. This implantation region design allows it to withstand higher breakdown voltages and, when the device experiences large current overcurrents such as reverse recovery or short-circuit overshoot, it can act as a freewheeling path, further preventing excessive current concentration in specific areas, reducing the formation of local hot spots, and lowering the risk of damage and degradation due to overheating. It also provides electric field shielding protection for the gate structure 13. Compared to the second sub-doped region 122, the first sub-doped region 121 has a lower doping concentration. This design helps to remove more carriers during freewheeling, reducing the charge remaining in the first sub-doped region 121 at the moment of device turn-off. This reduces the tail current and charge storage during device turn-off, improving the switching speed and efficiency of the device, thereby enhancing its electrical performance. In addition, a stepped trench design was introduced, which expands the contact area between the diode and the P-injection region, further improving the freewheeling capability and carrier extraction efficiency.

[0078] In some embodiments, ion implantation is performed on the initial device to form a first initial doped region 23 at the bottom of the initial trench 21 in the initial substrate 20, including: Figure 7 and Figure 8As shown, the initial device is subjected to multiple ion implantation operations sequentially. During these operations, the ion implantation dose is controlled to first increase and then decrease, while maintaining a dose of 1E14~3E15 ions / cm². 2 The dosage range and the controlled ion implantation energy are sequentially increased and satisfy the energy range of 50 keV to 500 keV to form the first initial doped region 23 with a junction depth of 1 μm to 1.5 μm.

[0079] In the embodiment described above, by performing multiple implantations with increasing energy and decreasing dosage, the depth of the first initial doped region 23 can be made to 1~1.5μm, and the peak implantation concentration is controlled at the middle depth of the P-implantation region, thus better protecting the gate oxide layer.

[0080] Optionally, the first initial doped region 23 is a P-region, and the implanted element can be aluminum ions.

[0081] In other embodiments, forming a first initial dielectric layer 24 on the sidewall of the initial trench 21 where the first initial doped region 23 is formed and on the surface of the first mask layer 22 away from the initial substrate 20 may include: Figure 8 A silicon oxide layer with a thickness of 4000 Å to 6000 Å is deposited on the exposed surface of the device shown. This silicon oxide layer is then etched to expose a portion of the initial substrate 20 at the bottom of the initial trench 21, with the remaining silicon oxide layer forming as shown. Figure 9 The first initial dielectric layer 24 is shown.

[0082] In other embodiments, ion implantation is performed on the exposed bottom of the initial trench 21 to form a second initial doped region 25 having the second doping type in the first initial doped region 23, including: such as Figure 8 and Figure 9 As shown, a self-aligned method is used to sequentially perform multiple ion implantation operations on the exposed bottom of the initial trench 21. During the multiple ion implantation operations, the ion implantation dose is controlled to be 1E16~3E16 ions / cm. 2 And control the ion implantation energy to increase sequentially in the range of 50 keV to 200 keV to form the second initial doped region 25.

[0083] In the embodiment described above, a second initial doped region 25 with a high doping concentration is formed in a first initial doped region 23 with a low doping concentration, making the forward and reverse characteristics of the introduced diode controllable. When the introduced diode is a body diode, this injection step can reduce the risk of premature breakdown of the body diode. If a Schottky diode is introduced, this step can reduce the forward voltage drop (VF) of the Schottky diode.

[0084] Optionally, the second initial doped region 25 is a P+ region, and the implanted element can be aluminum ions.

[0085] In the aforementioned embodiment, the self-aligned ion implantation process not only enhances the tolerance of the manufacturing process and allows for smaller cell sizes, but also simplifies the process flow and reduces production costs. Furthermore, by controlling the implantation process of the second sub-doped region 122, the doping concentration distribution exhibits a characteristic of first increasing and then decreasing. That is, near the bottom of the first trench, the doping concentration gradually increases to a peak value, and then gradually decreases as it approaches the source conductive layer 16. This controls the peak value of the implanted concentration in the second sub-doped region 122 to be located in the middle of the second sub-doped region 122. This effectively enhances the carrier extraction capability and the breakdown voltage performance of the second sub-doped region 122, preventing premature breakdown. Simultaneously, the implanted region forms an electric field shielding effect on the gate structure 13, better protecting the gate oxide layer of the gate structure 13. Furthermore, by controlling the implantation process of the first sub-doped region 121, different concentrations of doping are introduced at different depths to form a concentration gradient from high to low. This design ensures that the source region 15 and the trench region can work together to effectively extract carriers throughout the entire operating cycle of the device. In particular, when the device is subjected to reverse recovery or short-circuit overshoot, it can quickly remove carriers, reduce bipolar degradation, and extend the device's lifespan.

[0086] Exemplarily, a second initial dielectric layer 26 is formed on the exposed surface of the first initial dielectric layer 24, and the exposed second initial doped region 25 is etched to form a second sub-trench 112 in the second initial doped region 25, including: Figure 9 and Figure 10 As shown, in Figure 9 A silicon nitride layer with a thickness of 2000~4000 Å is deposited on the exposed surface of the device shown; the silicon nitride layer is etched to expose a portion of the second initial doped region 25 at the bottom of the initial trench 21, forming a structure as shown. Figure 10 The second initial dielectric layer 26 is shown; as Figure 9 and Figure 10 As shown, a self-aligned method is used to etch the exposed second initial doped region 25 to form a second sub-trench 112 with a depth of 0.3~0.5μm in the second initial doped region 25. In this embodiment, by forming a stepped trench in the initial substrate 20, the contact area of ​​the subsequently introduced diode can be increased, thereby improving the freewheeling capability and carrier extraction capability of the subsequently introduced diode during switching.

[0087] According to other embodiments of this application, such as Figure 7As shown, the initial device further includes a third initial doped region 35 and a fourth initial doped region 36. The third initial doped region 35 is located on both sides of the initial trench 21 in the initial substrate 20 and is in contact with the first mask layer 22. The fourth initial doped region 36 is located in the initial substrate 20 and is in contact with the surface of the third initial doped region 35 away from the first mask layer 22. Figures 10 to 15 as well as Figure 1 As shown, or as Figures 10 to 14 , Figure 16 as well as Figure 2 As shown, removing the first mask layer 22 and forming the gate structure 13, interlayer dielectric layer 14, source region 15, and source conductive layer 16 includes: forming a third initial dielectric layer on the exposed surface of the second initial dielectric layer 26, the third initial dielectric layer filling the second sub-trench 112 and the remaining initial trench 21, and performing chemical mechanical polishing on the device with the third initial dielectric layer formed, so that the first mask layer 22 is exposed or partially removed, the remaining first mask layer 22 forms an intermediate mask layer 27, the remaining first initial dielectric layer 24 forms a fourth initial dielectric layer 28, the remaining second initial dielectric layer 26 forms a fifth initial dielectric layer 29, and the remaining third initial dielectric layer forms a third intermediate dielectric layer 30; as Figure 11 As shown, a sixth initial dielectric layer 31 is formed on the exposed intermediate mask layer 27, the exposed fourth initial dielectric layer 28, the exposed fifth initial dielectric layer 29, and the exposed third intermediate dielectric layer 30. The device with the sixth initial dielectric layer 31 is selectively etched to remove the intermediate mask layer 27, the fourth initial dielectric layer 28, and a portion of the sixth initial dielectric layer 31, exposing the third initial doped region 35 and the first sub-doped region 121. The sixth initial dielectric layer 31 located on the surfaces of the third intermediate dielectric layer 30 and the fifth initial dielectric layer 29 away from the second sub-doped region 122 is retained, forming a sixth intermediate dielectric layer 32. The fifth initial dielectric layer 29 and the sixth intermediate dielectric layer 32 located on the sidewall of the third intermediate dielectric layer 30 form a first intermediate dielectric layer 33. Figure 12 and Figure 13As shown, a gate structure 13 is formed between the sidewall of the first trench and the first intermediate dielectric layer 33, contacting the first sub-doped region 121. A second intermediate dielectric layer 34 is formed on the gate structure 13 and the portion of the third initial doped region 35 away from the first sub-doped region 121. The exposed third initial doped region 35 and a portion of the fourth initial doped region 36 are sequentially removed to form a first contact hole 37 (corresponding to the second trench in a silicon carbide MOSFET device). The remaining third initial doped region 35 forms a second doped region 152. Ion implantation is performed on the bottom of the first contact hole 37 to form a third doped region 153 located in the remaining fourth initial doped region 36. A body region 151 is formed, the third doped region 153 is in contact with the second doped region 152, the doping concentration of the third doped region 153 is greater than the doping concentration of the body region 151, and the body region 151, the second doped region 152 and the third doped region 153 form the source region 15; the third intermediate dielectric layer 30 and part of the first intermediate dielectric layer 33 are removed, so that the second sub-doped region 122 is exposed, forming a second contact hole 38, and conductive materials are filled in the first contact hole 37 and the second contact hole 38 on the surface of the interlayer dielectric layer 14 away from the substrate, respectively, to form the source conductive layer 16, and the remaining first intermediate dielectric layer 33 and the remaining second intermediate dielectric layer 34 form the interlayer dielectric layer 14.

[0088] The embodiment described above forms and fills third, fourth, fifth, and sixth initial dielectric layers 31, followed by chemical mechanical polishing and selective etching to form first and second intermediate dielectric layers 34. These steps ensure precise alignment and thickness control of the dielectric layers, reducing alignment errors in the process and improving device manufacturing accuracy and yield. The thickened oxide and shielding layers effectively protect the gate structure 13, reduce premature gate oxide degradation, and extend device lifetime. The first intermediate dielectric layer 33 and the second intermediate dielectric layer 34 not only provide insulation between the gate and source regions 15 but also optimize the electric field distribution inside the device, reduce Miller capacitance, and improve the switching speed and efficiency of the device. Simultaneously, the multilayer dielectric design allows the device to withstand higher operating voltages and currents, increasing device reliability and robustness.

[0089] Optionally, a third initial dielectric layer is formed on the exposed surface of the second initial dielectric layer 26, the third initial dielectric layer filling the second sub-trench 112 and the remaining initial trench 21, and the device with the third initial dielectric layer formed is subjected to chemical mechanical planarization (CMP) to expose the first mask layer 22, including: using HDP-CVD (High Density Plasma Chemical Vapor Deposition) process on... Figure 8 A silicon oxide layer is deposited on the exposed surface of the device to fill the initial trench 21 and the second sub-trench 112, resulting in the third initial dielectric layer. The device surface with the third initial dielectric layer is subjected to chemical mechanical polishing (CMP) to make the remaining film thickness on the surface of the initial substrate 20 reach 2000 Å to 3000 Å. This CMP process removes part of the third initial dielectric layer, part of the second initial dielectric layer 26, part of the first initial dielectric layer 24, and part of the first mask layer 22.

[0090] Optionally, such as Figure 11 As shown, a sixth initial dielectric layer 31 is formed on the exposed intermediate mask layer 27, the exposed fourth initial dielectric layer 28, the exposed fifth initial dielectric layer 29, and the exposed third intermediate dielectric layer 30, including: depositing a silicon nitride layer with a thickness of 2000Å to 3000Å ​​on the exposed intermediate mask layer 27, the exposed fourth initial dielectric layer 28, the exposed fifth initial dielectric layer 29, and the exposed third intermediate dielectric layer 30 to form the sixth initial dielectric layer 31.

[0091] In a specific implementation, such as Figure 11 and Figure 12As shown, selective etching is performed on the device on which the sixth initial dielectric layer 31 is formed to remove the intermediate mask layer 27, the fourth initial dielectric layer 28, and a portion of the sixth initial dielectric layer 31, exposing the third initial doped region 35 and the first sub-doped region 121. This includes forming a first photoresist layer on the surface of the sixth initial dielectric layer 31 away from the initial substrate 20, wherein the orthographic projection of the first photoresist layer on the initial substrate 20 covers the fifth initial dielectric layer 29 and the third intermediate dielectric layer 30 respectively. The first initial photoresist layer is projected onto the initial substrate 20. Using the first photoresist layer as a mask, the device with the first photoresist layer is wet-etched with phosphoric acid to remove the exposed sixth initial dielectric layer 31, thus exposing the intermediate mask layer 27 and the fourth initial dielectric layer 28. The exposed fourth initial dielectric layer 28 and the intermediate mask layer 27 are etched away using a wet etching process, thus exposing the first intermediate dielectric layer 33, the third initial doped region 35, and the first sub-doped region 121. The first photoresist layer is then removed. In this embodiment, firstly, a first photoresist layer is formed on a portion of the upper surface of the sixth initial dielectric layer 31. The orthogonal projection of the first photoresist layer onto the initial substrate 20 covers the orthogonal projections of the fifth initial dielectric layer 29 and the third intermediate dielectric layer 30, ensuring the accuracy and controllability of subsequent etching processes. Next, using the first photoresist layer as a mask, wet etching with phosphoric acid is performed to precisely remove a portion of the sixth initial dielectric layer 31 until the intermediate mask layer 27 and the fourth initial dielectric layer 28 are exposed. This process utilizes the selectivity and uniformity of wet etching. Subsequently, the exposed fourth initial dielectric layer 28 and intermediate mask layer 27 are removed by wet etching. The precise control of the etching process achieves complete exposure of the third initial doped region 35 and the first sub-doped region 121.

[0092] Optionally, the width of the first photoresist layer can be 1.0~1.2μm. The midpoint of the first photoresist layer can be located on the central axis of the third intermediate dielectric layer 30.

[0093] In addition, after removing the first photoresist layer, the method may further include forming an oxide layer of 200-300 Å on the exposed surface of the initial substrate 20, thereby repairing the silicon carbide surface.

[0094] In some embodiments, such as Figures 12 to 13 As shown, a gate structure 13 is formed between the sidewall of the first trench and the first intermediate dielectric layer 33, contacting the first sub-doped region 121. This includes forming a first oxide layer 131 with a thickness of 2000-3000 Å on the exposed surface of the first sub-doped region 121. Figure 13The thickness value in the vertical direction is such that one side of the first oxide layer 131 contacts the sidewall of the first sub-trench 111, and the other side of the first oxide layer 131 contacts the fifth initial dielectric layer 29; a second oxide layer 132 with a thickness of 300 Å to 400 Å is formed on the remaining sidewall of the first sub-trench 111, where the thickness is... Figure 13 The thickness value in the horizontal direction; a gate layer 133 is formed between the second oxide layer 132 and the fifth initial dielectric layer 29 in the first sub-trench 111, to obtain the gate structure 13 including the first oxide layer 131, the second oxide layer 132 and the gate layer 133.

[0095] In the embodiment described, the first oxide layer 131 with a thickness of 2000~3000 Å can keep the subsequent second oxide layer 132 (i.e., the gate oxide layer of the device) away from the high electric field at the bottom, effectively reducing the electric field peak at the corner of the second oxide layer 132 and protecting the second oxide layer 132. The thickness of the second oxide layer 132 is not limited to 300 Å~400 Å, and this thickness can be adjusted according to the required threshold voltage and the required operating conditions of the device.

[0096] For example, such as Figure 13 and Figure 14 As shown, a second intermediate dielectric layer 34 is formed on the surface of the gate structure 13 and the third initial doped region 35 away from the first sub-doped region 121, including: sequentially depositing a first sub-dielectric layer 341, a second sub-dielectric layer 342, and a third sub-dielectric layer 343 on the surface of the gate structure 13 and the third initial doped region 35 away from the first sub-doped region 121, to obtain the following: Figure 13 The structure shown is as follows: the third sub-dielectric layer 343, the second sub-dielectric layer 342, and the first sub-dielectric layer 341 are sequentially photolithographically etched to remove a portion of the third sub-dielectric layer 343, a portion of the second sub-dielectric layer 342, and a portion of the first sub-dielectric layer 341, thereby exposing a portion of the third initial doped region 35 to form the second intermediate dielectric layer 34. The remaining first sub-dielectric layer 341 forms the first dielectric layer 141, the remaining second sub-dielectric layer 342 forms the second dielectric layer 142, and the remaining third sub-dielectric layer 343 forms the first partial dielectric layer 144.

[0097] Optionally, a first sub-dielectric layer 341, a second sub-dielectric layer 342, and a third sub-dielectric layer 343 are sequentially deposited on the surfaces of the gate structure 13 and the third initial doped region 35 away from the first sub-doped region 121, including: depositing a silicon nitride layer with a thickness of 200-300 Å on the surfaces of the gate structure 13 and the third initial doped region 35 away from the first sub-doped region 121; depositing an ILD layer on the surface of the silicon nitride layer, wherein the ILD can be a silicon oxide layer composed of USG and BPSG, wherein the thickness of USG is 1800-2200 Å and the thickness of BPSG is 3000-4000 Å; and depositing a silicon nitride layer with a thickness of 500-800 Å on the surface of the ILD layer.

[0098] For example, such as Figure 13 and Figure 14 As shown, the exposed third initial doped region 35 and a portion of the fourth initial doped region 36 are sequentially removed to form a first contact hole 37. This includes: etching the exposed third initial doped region 35 to expose a portion of the fourth initial doped region 36, and etching the exposed fourth initial doped region 36 to form the first contact hole 37 with an etching depth of 0.3~0.4μm. The initial substrate 20 after forming the first contact hole 37 forms the substrate 10.

[0099] like Figure 14 As shown, ion implantation is performed on the bottom of the first contact hole 37 to form a third doped region 153 located in the remaining fourth initial doped region 36. This includes: performing ion implantation on the bottom of the first contact hole 37, controlling the ion implantation energy to be 30~60 keV and the implantation dose to be 3E15~5E15 ions / cm. 2 The implanted ions were aluminum ions, and the doping depth after ion implantation was 0.1~0.15μm.

[0100] In some other alternatives to this application, such as Figure 13 , Figure 14 , Figure 15 as well as Figure 1As shown, removing the third intermediate dielectric layer 30 and a portion of the first intermediate dielectric layer 33 exposes the second sub-doped region 122, forming a second contact hole 38. Conductive material is then filled into the surface of the interlayer dielectric layer 14 away from the substrate, and into the first contact hole 37 and the second contact hole 38, respectively, to form the source conductive layer 16. This process includes: removing the third intermediate dielectric layer 30 and a portion of the first intermediate dielectric layer 33, exposing the second sub-doped region 122, forming the second contact hole 38; the second intermediate dielectric layer 34 and the remaining first intermediate dielectric layer 33 forming the interlayer dielectric layer 14; annealing the device after removing the third initial dielectric layer, controlling the annealing temperature to be greater than 1650°C; and filling the surface of the interlayer dielectric layer 14 away from the substrate 10, and into the first contact hole 37 and the second contact hole 38, to form the source conductive layer 16.

[0101] In the aforementioned embodiment, by controlling the annealing temperature to exceed 1650°C, effective activation of doped ions was achieved, improving the quality of the composite dielectric layer on the silicon carbide surface and reducing the interface state density. A continuous source conductive layer 16 was formed by filling the surface of the interlayer dielectric layer 14, the first contact hole 37, and the second contact hole 38 with conductive material in a single step. This one-step filling process avoids process errors that may be introduced by multiple depositions and etchings, ensuring close contact and good electrical connectivity between the source conductive layer 16 and each doped region, reducing contact resistance, and improving device efficiency.

[0102] Based on this, such as Figure 13 , Figure 14 , Figure 15 as well as Figure 1 As shown, removing the third intermediate dielectric layer 30 and a portion of the first intermediate dielectric layer 33 to expose the second sub-doped region 122 may include: performing chemical mechanical polishing on the device to remove a portion of the first intermediate dielectric layer 33, exposing the third intermediate dielectric layer 30, with the remaining first intermediate dielectric layer 33 forming a second preparatory dielectric layer 145; removing the third intermediate dielectric layer 30 by a wet etching process; removing a portion of the second preparatory dielectric layer 145, such that the surface of the remaining second preparatory dielectric layer 145 away from the substrate 10 is flush with the surface of the second intermediate dielectric layer 34 away from the substrate 10, with the remaining second preparatory dielectric layer 145 forming a second dielectric layer 146.

[0103] like Figure 15 As shown, the first portion of the dielectric layer 144 and the second portion of the dielectric layer 146 constitute the third dielectric layer 143.

[0104] During the removal of a portion of the second preparatory portion of the dielectric layer 145, the method further includes: as follows Figure 14 and Figure 15 As shown, a portion of the first dielectric layer 144, a portion of the second dielectric layer 142, and a portion of the first dielectric layer 141 are removed, exposing a portion of the upper surface of the second doped region 152.

[0105] According to another alternative of this application, such as Figure 14 , Figure 16 as well as Figure 2 As shown, removing the third intermediate dielectric layer 30 and a portion of the first intermediate dielectric layer 33 exposes the second sub-doped region 122, forming a second contact hole 38. Conductive material is then filled into the interlayer dielectric layer 14 on the surface away from the substrate, and into the first contact hole 37 and the second contact hole 38, respectively, to form the source conductive layer 16. This process includes: annealing the device forming the source region 15 at a temperature greater than 1650°C; filling the first contact hole 37 with conductive material to obtain a first source portion 40; removing the third intermediate dielectric layer 30 and a portion of the first intermediate dielectric layer 33 exposes the second sub-doped region 122, forming the second contact hole 38; the second intermediate dielectric layer 34 and the remaining first intermediate dielectric layer 33 form the interlayer dielectric layer 14; filling the second contact hole 38 and the surface of the interlayer dielectric layer 14 away from the substrate 10 with the conductive material to form a second source portion; and the second source portion contacts the first source portion 40 to form the source conductive layer 16.

[0106] In this embodiment, a first sub-conductive layer is formed by filling the first contact hole 37 with conductive material, establishing an electrical connection with the second sub-implantation region, thereby enhancing the conductivity between the source and the bottom of the trench. Subsequently, a portion of the first intermediate dielectric layer 33 and all of the third intermediate dielectric layer 30 are removed using precise etching techniques, exposing the second sub-doped region 122 located deep in the trench. This operation creates the second contact hole 38, ensuring independence from the first contact hole 37 and increasing the area in direct contact with the source conductive layer 16. The remaining first intermediate dielectric layer 33 and second intermediate dielectric layer 34 together constitute the interlayer dielectric layer 14, effectively isolating the gate and source and reducing unnecessary capacitance effects. Finally, conductive material is filled in the second contact hole 38 and the surface of the interlayer dielectric layer 14 away from the substrate 10 to form a complete source conductive layer 16, ensuring good ohmic contact and achieving electrical connectivity with the first sub-conductive layer. This series of process designs not only improves the conductivity of the device's source region but also optimizes reverse recovery characteristics through self-aligned diode integration, significantly enhancing the device's freewheeling capability and short-circuit withstand capability.

[0107] Furthermore, the high-temperature annealing process ensures the effective distribution of dopants in the SiC matrix, enhancing the electrical conductivity of the doped region. Simultaneously, high-temperature annealing helps reduce the interface state density, improving device reliability and minimizing the impact of defects and stresses introduced during manufacturing on device performance.

[0108] Based on this, such as Figure 14 , Figure 16 as well as Figure 2 As shown, removing the third intermediate dielectric layer 30 and a portion of the first intermediate dielectric layer 33 to expose the second sub-doped region 122 may include: performing chemical mechanical polishing on the device to remove a portion of the first intermediate dielectric layer 33, exposing the third intermediate dielectric layer 30, wherein the surface of the remaining first intermediate dielectric layer 33 away from the substrate 10 is higher than the surface of the second intermediate dielectric layer 34 away from the substrate 10, and the remaining first intermediate dielectric layer 33 constitutes the second portion of the dielectric layer 146; and removing the third intermediate dielectric layer 30 by a wet etching process.

[0109] like Figure 16 As shown, the first portion of the dielectric layer 144 and the second portion of the dielectric layer 146 constitute the third dielectric layer 143.

[0110] Specifically, filling with conductive material to form the source conductive layer 16 includes: first depositing nickel to form an ohmic contact, and then depositing a metal layer AlCu to form the source conductive layer 16.

[0111] In some exemplary embodiments, such as Figure 6 and Figure 7 As shown, an initial device is provided, including: a preparatory substrate 50 and a hard mask stacked on the preparatory substrate 50, the thickness of the hard mask being 500~1000 Å; using the hard mask as a mask, the preparatory substrate 50 is subjected to second-type doping ion implantation and first-type doping ion implantation, thereby forming a stacked first well region 52 and a second well region 51 in the preparatory substrate 50, wherein the ion implantation depth of the second well region 51 of the first-type doping is 0.2~0.3 μm, and the first well region 51 of the second-type doping is... The ion implantation depth of region 52 is 0.6~0.8μm; hard mask material is further deposited on the surface of the hard mask layer away from the pre-substrate 50 to increase the thickness of the hard mask; a second pre-photoresist layer is formed on the surface of the hard mask away from the pre-substrate 50 after the thickness is increased, and a second photoresist layer 53 is obtained after exposure and development; using the second photoresist layer 53 as a mask, the hard mask with increased thickness is etched to the surface of the pre-substrate 50, and the etched hard mask forms a first mask layer 22, resulting in... Figure 6 The structure shown; as Figure 7 As shown, the exposed pre-substrate 50 is etched to form the initial trench 21, the remaining pre-substrate 50 forms the initial substrate 20, the remaining first well region 52 forms the fourth initial doped region 36, and the remaining second well region 51 forms the third initial doped region 35.

[0112] In the embodiment described, the thickness of the hard mask after the thickness increase can be 10000Å~20000Å. Its thickness cannot be too thin, otherwise high-energy ion implantation will penetrate the hard mask, affecting epitaxial doping; nor can it be too thick, otherwise the aspect ratio of the trench etching will be too high, increasing the difficulty of the silicon carbide etching process. The width of the etched hard mask can be 1.5~2.5μm. The depth of the etched-removed pre-substrate 50 can be 1~2μm, which can be determined according to the designed breakdown voltage, capacitance, and other dynamic and static parameters.

[0113] This application discloses a silicon carbide MOSFET device and its fabrication method. The SiN layer is used as the dielectric layer in the self-aligned process, reducing photolithography layers and successfully isolating the metal layer from the polysilicon layer, thus preventing gate-source short circuits. A deeper trench is introduced into the trench-gate MOSFET, and through a series of self-aligned processes, the source metal is inserted deep into the SiC substrate beneath the trench, short-circuiting with the P+ region at the bottom of the trench. This forms a freewheeling channel during reverse recovery or short-circuit overshoot, resulting in better overcurrent capability. This application introduces a 2000-3000 Å thick oxide layer at the bottom of the trench and a P-type implantation region at the bottom of the trench. Both of these layers shield the gate oxide field, improving device reliability. Simultaneously, the thick oxide layer and P-type implantation reduce the gate-drain capacitance and lower switching losses. This application uses a two-step implantation process within the trench to introduce P+ and P- regions at the bottom of the trench, allowing for flexible adjustment of the P-type implantation concentration gradient according to the design.

[0114] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the silicon carbide MOSFET device fabrication method of this application will be described in detail below with reference to specific embodiments.

[0115] Example 1

[0116] This embodiment relates to a specific method for fabricating a silicon carbide MOSFET device, such as... Figures 6 to 15 as well as Figure 1 As shown, it includes the following steps:

[0117] Step S1: First, a hard mask (HM) with a thickness of 500–1000 Å is deposited. Then, N-type and P-type high-energy ion implantation is performed to form N+ and P-well regions with depths of 0.2–0.3 Å, respectively. m and 0.6~0.8 Following this, silicon oxide is deposited to increase the hard mask thickness to 10,000 Å~20,000 Å. It cannot be too thin, otherwise high-energy ion implantation will penetrate the hard mask, affecting epitaxial doping; nor can it be too thick, otherwise the aspect ratio of the trench etching will be too high, increasing the difficulty of the silicon carbide etching process. Next, a layer of photoresist is applied, followed by exposure, and then the hard mask is etched onto the silicon carbide surface, with a dimension of 1.5~2.5 m. m;

[0118] Step S2: Etch silicon carbide to form a depth of 1~2 The specific depth of the trench (m) can be determined based on the dynamic and static parameters such as the breakdown voltage and capacitance designed.

[0119] Step S3: Perform high-energy ion implantation using aluminum ions. Implantation can be performed in multiple stages, with energies increasing from 50 keV to 500 keV and doses ranging from 1E14 to 3E15 ions / cm³. 2 The range increases and then decreases layer by layer, with the goal of achieving a depth of 1 in the P-injection zone beneath the trench. m~1.5 m, and the peak of the implantation concentration is controlled at the middle depth of the P-implantation region, which better protects the gate oxide layer;

[0120] Step S4: Deposit a layer of silicon oxide with a thickness of 4000 Å~6000 Å, and etch the silicon oxide to expose the silicon carbide epitaxial layer at the bottom of the trench. Then, perform high-energy ion implantation using a self-aligned method, implanting aluminum ions. Implantation can be performed in multiple stages, with energy increasing from 50 keV to 200 keV, and a dose of 1E16~3E16 ions / cm. 2 This creates a P+ region within the P- region under the trench, making the forward and reverse characteristics of the introduced diode controllable. This injection step can reduce the risk of premature breakdown of the body diode. If a Schottky diode is introduced, the VF of the Schottky diode can be reduced.

[0121] Step S5: Deposit a silicon nitride layer with a thickness of 2000~4000 Å, and etch the silicon nitride to expose the silicon carbide epitaxial layer at the bottom of the trench. Then continue etching the silicon carbide using a self-aligned method to form a trench with a depth of 0.3 Å. m~0.5 The stepped trench of m increases the contact area of ​​the subsequently introduced diode, thereby improving the freewheeling capability of the subsequently introduced diode and the carrier extraction capability during the switching process.

[0122] Step S6: Deposit silicon oxide using HDP-CVD and perform CMP to grind the wafer surface film to 2000Å~3000Å. Then deposit a 500~1000Å nitride layer on the surface to prepare for the subsequent self-alignment scheme.

[0123] Step S7: Apply a layer of photoresist as a barrier layer in the middle of the trench, with a width of 1.0~1.2 mm. First, phosphoric acid etching is performed to remove some of the surface silicon nitride. Then, wet etching is performed to over-etch the silicon oxide to ensure that all the surface oxide layer is removed, leaving only the oxide pillars in the trenches, which are wrapped with a layer of silicon nitride. During this process, the photoresist is removed, and a thin oxide layer of 200~300Å is grown to repair the silicon carbide surface. Next, HDP-CVD is performed to fill the silicon oxide above the surface, and wet etching is performed to etch the silicon oxide into the trenches, leaving a thickness of 2000~3000Å. This thick oxide layer can keep the subsequent gate oxide layer away from the high electric field at the bottom, effectively reducing the electric field peak at the corner of the gate oxide layer and protecting the gate oxide.

[0124] Step S8: Generate and clean off a sacrificial oxide layer, grow a gate oxide layer with a thickness of 300 Å to 400 Å. This thickness can be adjusted according to the required threshold voltage and the operating conditions required by the device. Deposit polysilicon and perform dry etching to below the silicon carbide epitaxial surface. Continue to deposit a silicon nitride layer with a thickness of 200 to 300 Å, and an ILD layer. The ILD layer is a silicon oxide layer composed of USG and BPSG. The thickness of USG is 1800 to 2200 Å, and the thickness of BPSG is 3000 to 4000 Å. Then deposit a silicon nitride layer with a thickness of 500 to 800 Å to form an interlayer composite dielectric layer.

[0125] Step S9: Perform photolithography on the source contact hole, with a size of 0.3~0.5 mm. m, dry etching of the interlayer composite dielectric layer to remove the photoresist, followed by etching of the exposed silicon carbide epitaxial layer to form a depth 0.3~0.4 cm below the silicon carbide surface. A trench of m in diameter was simultaneously implanted with ions to form a high-concentration P+ region. The ion implantation energy was 30-60 keV, and the implantation dose was 3E15-5E15 ions / cm². 2 The ion type is aluminum ions, and the doping depth after ion implantation is 0.1~0.15. m, perform CMP on the device to remove the silicon nitride layer on top of the "silicon oxide pillar" and expose the "silicon oxide pillar";

[0126] Step S10: Wet etching completely removes the "silicon oxide pillars", and phosphoric acid wet etching removes part of the silicon nitride, aligning the silicon oxide and silicon nitride in the interlayer composite dielectric layer on the surface of the source contact hole. Then, high-temperature annealing above 1650℃ is performed to activate the doped ions. Next, a C film (carbon-based thin film) is made and removed to repair the etched silicon carbide surface and reduce the interface state density.

[0127] Step S100: Ni is deposited and annealed to form ohmic contacts, and finally a metal layer AlCu is deposited to form the final complete device structure.

[0128] This embodiment first integrates an additional body diode at the bottom of the trench in the trench silicon carbide device. During reverse recovery or short-circuit overshoot, current is collected from the bottom of the trench, away from the channel region, reducing the impact of bipolar degradation on device performance. Simultaneously, the introduction of the stepped trench increases the contact area between the diode and the P-injection region, resulting in stronger freewheeling capability. This process employs a self-aligned method, effectively reducing the alignment difficulty of the diode, gate, and various injection regions, allowing for further reduction in device cell size. It also achieves thick oxide at the bottom of the trench, improving gate oxide reliability and ensuring a thick dielectric layer separating the source metal and the gate polysilicon, reducing Miller capacitance and increasing device switching speed.

[0129] Example 2

[0130] This embodiment relates to a specific method for fabricating a silicon carbide MOSFET device, such as... Figures 6 to 14 , Figure 16 as well as Figure 2 As shown, it includes the following steps:

[0131] Step S11: First, deposit a hard mask (HM) with a thickness of 500–1000 Å, then perform N-type and P-type high-energy ion implantation to form N+ and P-well regions with depths of 0.2–0.3 Å, respectively. m and 0.6~0.8 Following this, silicon oxide is deposited to increase the hard mask thickness to 10,000 Å~20,000 Å. It cannot be too thin, otherwise high-energy ion implantation will penetrate the hard mask, affecting epitaxial doping; nor can it be too thick, otherwise the aspect ratio of the trench etching will be too high, increasing the difficulty of the silicon carbide etching process. Next, a layer of photoresist is applied, followed by exposure, and then the hard mask is etched onto the silicon carbide surface, with a dimension of 1.5~2.5 m. m;

[0132] Step S21: Etch silicon carbide to form a depth of 1~2 The specific depth of the trench (m) can be determined based on the dynamic and static parameters such as the breakdown voltage and capacitance designed.

[0133] Step S31: Perform high-energy ion implantation using aluminum ions. Implantation can be performed in multiple stages, with energies increasing from 50 keV to 500 keV and doses ranging from 1E14 to 3E15 ions / cm³. 2 The range increases and then decreases layer by layer, with the goal of achieving a depth of 1 in the P-injection zone beneath the trench. m~1.5 m, and the peak of the implantation concentration is controlled at the middle depth of the P-implantation region, which better protects the gate oxide layer;

[0134] Step S41: Deposit a layer of silicon oxide with a thickness of 4000 Å to 6000 Å, and etch the silicon oxide to expose the silicon carbide epitaxial layer at the bottom of the trench. Then, perform high-energy ion implantation using a self-aligned method, implanting aluminum ions. Implantation can be performed in multiple stages, with energy increasing from 50 keV to 200 keV, and a dose of 1E16 to 3E16 ions / cm. 2 This creates a P+ region within the P- region under the trench, making the forward and reverse characteristics of the introduced diode controllable. This injection step can reduce the risk of premature breakdown of the body diode. If a Schottky diode is introduced, the VF of the Schottky diode can be reduced.

[0135] Step S51: Deposit a silicon nitride layer with a thickness of 2000~4000 Å, and etch the silicon nitride to expose the silicon carbide epitaxial layer at the bottom of the trench. Then continue etching the silicon carbide using a self-aligned method to form a trench with a depth of 0.3 Å. m~0.5 The stepped trench of m increases the contact area of ​​the subsequently introduced diode, thereby improving the freewheeling capability of the subsequently introduced diode and the carrier extraction capability during the switching process.

[0136] Step S61: Deposit silicon oxide using HDP-CVD and perform CMP to grind the wafer surface film to 2000Å~3000Å. Then deposit a 500~1000Å nitride layer on the surface to prepare for the subsequent self-alignment scheme.

[0137] Step S71: Apply a layer of photoresist as a barrier layer in the middle of the trench, with a width of 1.0~1.2 mm. First, phosphoric acid etching is performed to remove some of the surface silicon nitride. Then, wet etching is performed to over-etch the silicon oxide to ensure that all the surface oxide layer is removed, leaving only the oxide pillars in the trenches, which are wrapped with a layer of silicon nitride. During this process, the photoresist is removed, and a thin oxide layer of 200~300Å is grown to repair the silicon carbide surface. Next, HDP-CVD is performed to fill the silicon oxide above the surface, and wet etching is performed to etch the silicon oxide into the trenches, leaving a thickness of 2000~3000Å. This thick oxide layer can keep the subsequent gate oxide layer away from the high electric field at the bottom, effectively reducing the electric field peak at the corner of the gate oxide layer and protecting the gate oxide.

[0138] Step S81: Generate and clean off a sacrificial oxide layer, grow a gate oxide layer with a thickness of 300 Å to 400 Å. This thickness can be adjusted according to the required threshold voltage and the operating conditions required by the device. Deposit polysilicon and perform dry etching to below the silicon carbide epitaxial surface. Continue to deposit a silicon nitride layer with a thickness of 200 to 300 Å, and an ILD layer. The ILD layer is a silicon oxide layer composed of USG and BPSG. The thickness of USG is 1800 to 2200 Å, and the thickness of BPSG is 3000 to 4000 Å. Then deposit a silicon nitride layer with a thickness of 500 to 800 Å to form an interlayer composite dielectric layer.

[0139] Step S91: Perform photolithography on the source contact hole, with a size of 0.3~0.5 mm. m, dry etching of the interlayer composite dielectric layer to remove the photoresist, followed by etching of the exposed silicon carbide epitaxial layer to form a depth 0.3~0.4 cm below the silicon carbide surface. A trench of m is simultaneously implanted with ions to form a high-concentration P+ region. The ion implantation energy should not be too high, approximately 30~60 keV, and the implantation dose should be 3E15~5E15 ions / cm². 2 The ion type is aluminum ions, and the doping depth after ion implantation is approximately 0.1~0.15. m. Perform CMP on the device to remove the silicon nitride layer on top of the "silicon oxide pillar" to expose the "silicon oxide pillar". Then perform high-temperature annealing above 1650℃ to activate the doped ions. Next, apply a C film and remove it to repair the etched silicon carbide surface. Reduce the interface state density, deposit Ni and anneal to form ohmic contacts. Deposit the metal layer AlCu and etch it back to the wafer surface, retaining the metal in the source contact hole.

[0140] Step S101: Perform wet etching on the device to remove the "silicon oxide pillars", and then deposit Ti and AlCu to form a complete device structure. A Schottky contact diode is formed in the stepped trench.

[0141] Compared to Example 1, this example replaces the ohmic contacts in the stepped trench with Schottky contacts. Schottky contacts do not involve the recombination of hole-electron carriers. When the device experiences reverse recovery or short-circuit overshoot, the Schottky diode can collect and extract carriers, effectively reducing the risk of bipolar degradation of the device. This invention can select between integrating a Schottky diode or a body diode according to the device's operating scenario, and the process has strong compatibility.

[0142] Furthermore, the two embodiments can be freely switched between integrated diodes or Schottky diodes without introducing new processes, making them highly adaptable to various processes.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0145] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A silicon carbide MOSFET device, characterized in that, include: A substrate having a first trench on one side surface, the substrate having a first doping type; A first doped region is located in the substrate at the bottom of the first trench and has a second doping type; The gate structure is located on the sidewall of the first trench and its bottom is in contact with the first doped region; An interlayer dielectric layer is located on the surface of the gate structure away from the first doped region and on the surface of the gate structure away from the first trench sidewall; The source region is located in the substrate and is in contact with the gate structure on one side. A source conductive layer is located in the first trench, on the surface of the interlayer dielectric layer away from the substrate, and on a portion of the surface of the substrate, to contact the first doped region and the source region, respectively.

2. The silicon carbide MOSFET device according to claim 1, characterized in that, The first doped region includes: The first sub-doped region is located at the bottom of the first trench and is in contact with at least the gate structure; The second sub-doped region is located within the first sub-doped region and is in contact with at least the source conductive layer. The doping concentration of the second sub-doped region is greater than that of the first sub-doped region.

3. The silicon carbide MOSFET device according to claim 2, characterized in that, The contact surface between the source conductive layer and the second sub-doped region is an ohmic contact surface or a Schottky contact surface.

4. The silicon carbide MOSFET device according to claim 2, characterized in that, The second sub-doped region satisfies at least one of the following: The junction depth of the second sub-doped region is 1 μm to 1.5 μm; Along the direction from the substrate to the source conductive layer, the doping concentration of the second sub-doped region first increases and then decreases.

5. The silicon carbide MOSFET device according to claim 2, characterized in that, The first trench includes a first sub-trench and a second sub-trench arranged sequentially and connected along a predetermined direction, the predetermined direction being the direction from the source conductive layer to the substrate. The width of the first sub-trench is greater than the width of the second sub-trench. The source conductive layer is located in the first sub-trench and the second sub-trench. The second sub-doped region surrounds the bottom corner of the second sub-trench and contacts the interlayer dielectric layer.

6. The silicon carbide MOSFET device according to claim 1, characterized in that, The gate structure includes: A first oxide layer is located between a portion of the sidewall of the first trench and the interlayer dielectric layer, and the thickness of the first oxide layer is greater than or equal to 2000 angstroms. The second oxide layer is located on the remaining sidewall of the first trench and is in contact with the portion of the first oxide layer away from the first doped region and the source region, respectively. A gate layer is located between the second oxide layer and the interlayer dielectric layer.

7. The silicon carbide MOSFET device according to claim 6, characterized in that, The interlayer dielectric layer includes: A first dielectric layer is located on the surface of the gate structure away from the first doped region and on a portion of the surface of the source region, wherein the material of the first dielectric layer comprises silicon nitride. A second dielectric layer is located on the surface of the first dielectric layer away from the substrate, and the material of the second dielectric layer includes silicon oxide; A third dielectric layer is located on the surface of the second dielectric layer away from the first dielectric layer and between the gate structure and the source conductive layer, wherein the material of the third dielectric layer includes silicon nitride.

8. The silicon carbide MOSFET device according to claim 1, characterized in that, The source region includes: The body region, located in the substrate and in contact with the gate structure, has the second doping type; The second doped region is located in the body region and is in contact with the gate structure. It has the first doping type. The surface of the second doped region near the source conductive layer is a part of the surface of the substrate. The interlayer dielectric layer is also located on the surface of the second doped region near the source conductive layer. The third doped region is located in the body region and on the side of the second doped region away from the gate structure. A portion of the surface of the third doped region near the source conductive layer is in contact with a portion of the surface of the second doped region away from the source conductive layer. The third doped region has the second doping type. The doping concentration of the third doped region is greater than the doping concentration of the body region. The source conductive layer is in contact with both the second doped region and the third doped region.

9. A method for fabricating a silicon carbide MOSFET device according to any one of claims 1 to 8, characterized in that, include: An initial device is provided, the initial device including an initial substrate, an initial trench and a first mask layer, the first mask layer being located on the surface of the initial substrate, the initial trench extending from the first mask layer into the initial substrate, the initial substrate having a first doping type; A first doped region having a second doping type is formed in the initial substrate at the bottom of the initial trench, at least by stepwise ion implantation. The first mask layer is removed to form a gate structure, an interlayer dielectric layer, a source region, and a source conductive layer. The remaining initial substrate forms a substrate. The initial trench after removing the first mask layer forms a first trench. The gate structure is located on the sidewall of the first trench and is in contact with the first doped region. The interlayer dielectric layer is located on the surface of the gate structure away from the first doped region and on the surface of the gate structure away from the sidewall of the first trench. The source region is located in the substrate and is in contact with the gate structure. The source conductive layer is located in the first trench, on the surface of the interlayer dielectric layer away from the substrate, and on a portion of the surface of the substrate, so as to contact the first doped region and the source region, respectively.

10. The method according to claim 9, characterized in that, At least through stepwise ion implantation, a first doped region having a second doping type is formed in the initial substrate at the bottom of the initial trench, including: Ion implantation is performed on the initial device to form a first initial doped region in the initial substrate at the bottom of the initial trench, the first initial doped region having the second doping type; A first initial dielectric layer is formed on the sidewall of the initial trench where the first initial doped region is formed and on the surface of the first mask layer away from the initial substrate, and ion implantation is performed on the exposed bottom of the initial trench to form a second initial doped region having the second doping type in the first initial doped region, and the remaining first initial doped region forms a first sub-doped region. A second initial dielectric layer is formed on the exposed surface of the first initial dielectric layer, and the exposed second initial doped region is etched to form a second sub-trench in the second initial doped region. The remaining second initial doped region forms a second sub-doped region, and the first sub-doped region and the second sub-doped region constitute the first doped region.

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