Semiconductor layout pattern and radio frequency circuit layout pattern

Abstract

A semiconductor layout pattern includes a substrate on which an active region is defined, a plurality of gate structures located in the active region, a plurality of doped regions located in the active region, and a plurality of gate structures located in the doped regions. Wherein a plurality of gate structures and a plurality of doped regions included in the active region form a first amplifier and a second amplifier, the first amplifier and the second amplifier are connected in series, and a drain doped region of the first amplifier and a source doped region of the second amplifier share the same doped region. The invention has the advantages of saving element space and improving the efficiency of the amplifier.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor layout pattern suitable for power amplifiers, which has the advantages of reducing space and improving performance. Background Technology

[0002] A power amplifier is an important component in radio frequency (RF) transmitter circuits. Its main function is to amplify and output signals. It is usually designed at the front end of the antenna radiator and is also the most power-consuming component in the entire RF front-end circuit.

[0003] Power amplifiers are mainly used in electronic products or devices that require bandwidth, such as mobile phones, tablets, WiMAX, Wi-Fi, Bluetooth, RFID readers, satellite communication and other network communication products.

[0004] A two-stage amplifier is a type of power amplifier that consists of two amplifiers connected in series. Its main purpose is to achieve higher overall gain through multi-stage amplification, while also improving the frequency response and distortion problems that may exist in single-stage amplifiers.

[0005] A cascaded power amplifier (or cascode amplifier) ​​is a two-stage amplifier consisting of a common-source (or common-emitter) transistor connected in series with a common-gate (or common-base) transistor. Compared to a single-stage amplifier, the cascode combination achieves the following characteristics: better input / output shielding, higher input impedance, higher output impedance, and wider bandwidth. In modern circuits, cascode amplifiers may be composed of two different types of transistors (i.e., bipolar junction transistors and field-effect transistors). Because the cascode amplifier has better input / output isolation characteristics and less direct coupling between the input and output points, it can reduce the effects of the Miller effect and thus achieve a wider bandwidth.

[0006] There is still room for improvement in current power amplifiers. For example, their layout patterns occupy a large area, which is not conducive to miniaturization. Summary of the Invention

[0007] This invention provides a semiconductor layout pattern comprising a substrate, an active region defined on the substrate, a plurality of gate structures located within the active region, wherein the gate structures are arranged parallel to each other along a first direction, and a plurality of doped regions located within the active region, with each doped region situated on either side of the gate structure in the substrate. The plurality of gate structures within the active region include a first gate structure and a second gate structure. The plurality of doped regions within the active region include a first source doped region, a first drain doped region, a second source doped region, and a second drain doped region. The first gate structure, the first source doped region, and the first drain doped region constitute a first amplifier, and the second gate structure, the second source doped region, and the second drain doped region constitute a second amplifier. The first drain doped region and the second source doped region include the same doped region among the plurality of doped regions, and the same doped region is defined as a common doped region.

[0008] The present invention also provides a radio frequency circuit layout pattern, comprising a substrate, an active region defined on the substrate, a plurality of gate structures located within the active region, wherein each gate structure is arranged parallel to each other along a first direction, and a plurality of doped regions located within the active region, wherein each doped region is located in the substrate on both sides of each gate structure, wherein the plurality of gate structures and the plurality of doped regions included in the active region constitute a first amplifier and a second amplifier, wherein a drain of the first amplifier and a source of the second amplifier are connected to each other, and the drain of the first amplifier and the source of the second amplifier are both located on a common doped region.

[0009] The present invention is characterized in that, in order to save component space and reduce the influence of wire impedance when fabricating the layout pattern of the two-stage amplifier, the two amplifiers are fabricated in the same active region. This allows the two amplifiers within the two-stage amplifier to share a portion of the doped region; that is, there is no shallow trench separating the two amplifier regions. Under the concept of the present invention, component size can be effectively reduced, and due to the reduction in the influence of wire impedance, amplifier performance can also be improved. Attached Figure Description

[0010] To facilitate understanding of the following text, reference should be made to the accompanying drawings and their detailed description while reading this invention. The specific embodiments described herein, with reference to the corresponding accompanying drawings, are used to explain in detail the specific embodiments of the invention and to illustrate the working principles of these embodiments. Furthermore, for clarity, the features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0011] Figure 1 This is a circuit diagram of a stacked power amplifier.

[0012] Figure 2 This is a schematic diagram showing the arrangement of the first and second amplifiers in two different embodiments of a stacked power amplifier;

[0013] Figure 3 This is a schematic diagram illustrating the arrangement of the first amplifier and the second amplifier in the active region, representing some different embodiments of the present invention. Figure 3 Figures (a), (b), (c), (d), and (e) illustrate five different arrangements.

[0014] Figure 4 , Figure 5 and Figure 6 These are schematic diagrams showing the layout of several secondary amplifiers according to different embodiments of the present invention;

[0015] Figure 7 This is a schematic diagram of the layout of a radio frequency circuit pattern according to an embodiment of the present invention;

[0016] Figure 8 This is a circuit diagram of a stacked MOSFET.

[0017] Figure 9 This is a schematic diagram of the layout of a stacked field-effect transistor according to an embodiment of the present invention.

[0018] Symbol Explanation

[0019] AA: Active Zone

[0020] AA1: Active Zone

[0021] AA2: Active Zone

[0022] CT: Contact Structure

[0023] CS: First Amplifier

[0024] CS-D: Drain of the first amplifier

[0025] CS-G: Gate of the first amplifier

[0026] CS-S: Source of the first amplifier

[0027] CG: Second Amplifier

[0028] CG-D: Drain of the second amplifier

[0029] CG-G: Gate of the second amplifier

[0030] CG-S: Source of the second amplifier

[0031] CTM: Contact Metal Layer

[0032] D: Drain electrode

[0033] D1: First drain doped region

[0034] D2: Second drain doped region

[0035] G: Gate structure

[0036] G1: First gate structure

[0037] G2: Second gate structure

[0038] M1: Metallic conductor layer

[0039] M2: Metallic conductor layer

[0040] R: Resistance

[0041] S: Source

[0042] S1: First source doped region

[0043] S2: Second source doped region

[0044] Sub: Base

[0045] SD: Source / Drain Doped Region

[0046] SD3: Common doped region

[0047] STI: Shallow Trench Isolation

[0048] T1: First amplifier

[0049] T2: Second amplifier

[0050] V+: Voltage source

[0051] V-: Voltage source

[0052] Vin: Input signal

[0053] Vout: Output signal

[0054] VG: Voltage source

[0055] VG1: Voltage source

[0056] VG2: Voltage source Detailed Implementation

[0057] To enable those skilled in the art to further understand the present invention, preferred embodiments of the invention are described below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings.

[0058] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0059] Although the present invention uses terms such as first, second, third, etc., to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0060] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, such as within 10%, 5%, 3%, 2%, 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate, meaning that the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0061] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0062] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0063] As described in the prior art section, a secondary amplifier is a type of power amplifier. Depending on the application, various types of secondary amplifiers exist, such as the aforementioned cascode amplifier. Other common secondary amplifiers include stacked MOSFETs, Gilbert mixers, RF switches, and active inductors. To clearly illustrate the features of this invention, the following paragraphs primarily focus on cascode amplifiers; however, those skilled in the art will understand that the scope of this invention also includes other types of secondary amplifiers besides cascode amplifiers, which will be described here first.

[0064] Figure 1 Draw a circuit diagram of a stacked power amplifier. Figure 2 A schematic diagram illustrating the arrangement of the first and second amplifiers in a stacked power amplifier according to two different embodiments is shown. Figure 1 As shown, a stacked power amplifier includes a first amplifier CS and a second amplifier CG. The first amplifier CS is, for example, a common-source amplifier, and the second amplifier CG is, for example, a common-gate amplifier. The first amplifier CS and the second amplifier CG are connected in series. More specifically, the gate terminal CS-G of the first amplifier CS is connected to an input signal VG1 (or input signal Vin), and the source terminal CS-S of the first amplifier CS is connected to a potential V- or ground. The gate terminal CG-G of the second amplifier CG is connected to a voltage source VG2, and the drain terminal CG-D of the second amplifier CG is connected to an output signal Vout. The drain terminal CS-D of the first amplifier CS is connected to the source terminal CG-S of the second amplifier CG. Furthermore, in... Figure 1 The circuit diagram also includes a resistor R connected to a voltage source V+. These elements pertain to existing stacked power amplifier circuit techniques and are not key features of this invention; therefore, they will not be repeated here.

[0065] It is worth noting that, such as Figure 1 As shown, the drain terminal CS-D of the first amplifier CS is connected to the source terminal CG-S of the second amplifier CG. Therefore, when the first amplifier CS and the second amplifier CG are jointly formed on a substrate (not shown), as... Figure 2 As shown in the left-hand embodiment, Figure 2The left side of the diagram illustrates a schematic of a first amplifier CS and a second amplifier CG formed side-by-side on a substrate according to one embodiment. The first amplifier CS and the second amplifier CG are formed within two active regions AA1 and AA2, respectively, and these two active regions AA1 and AA2 are separated by a shallow trench isolation (STI). Subsequently, after the first amplifier CS and the second amplifier CG are formed in active regions AA1 and AA2, respectively, the two amplifiers are connected in series by components such as wires, for example, connecting the drain terminal CS-D of the first amplifier CS to the source terminal CG-S of the second amplifier CG. For the sake of simplicity in the diagram, [the diagram is omitted here]. Figure 2 The layout structure within the first amplifier CS and the second amplifier CG is not shown, including components such as gate structures, source / drain doped regions, contact structures, and wires. However, those skilled in the art should understand that... Figure 2 The layout structure should be included within the range of the first amplifier CS and the second amplifier CG shown.

[0066] However, in Figure 2 In the embodiment shown on the left, even though the two active regions AA1 and AA2, where the first amplifier CS and the second amplifier CG are respectively formed, are brought as close as possible, a shallow trench isolation (STI) of a certain width still exists between active regions AA1 and AA2 due to manufacturing limitations. This creates two problems. First, active regions AA1 and AA2 each occupy a certain area, and their adjacent side-by-side arrangement hinders component miniaturization. Second, the first amplifier CS and the second amplifier CG need to be connected to each other via wires or other components. Since wires themselves have impedance, when the distance between active regions AA1 and AA2 is large, the wire length increases, raising the overall component impedance and negatively impacting amplifier performance.

[0067] Therefore, based on the above problems, the applicant of this invention proposes another layout and arrangement pattern suitable for power amplifiers. For example... Figure 2 The embodiment illustrated in the right half of the diagram is different from the one shown in the diagram. Figure 2 In the embodiment illustrated in the left half, the first amplifier CS and the second amplifier CG are jointly formed within the same active region AA, and a shallow trench isolation STI surrounds the active region AA. However, since the first amplifier CS and the second amplifier CG share the same active region AA, and there is no shallow trench isolation STI between the first amplifier CS and the second amplifier CG, the overall component area can be reduced (because they share the same active region AA). Furthermore, since the distance between the first amplifier CS and the second amplifier CG is shortened, the influence of wire impedance after the two amplifiers are connected to each other is smaller, which is beneficial to improving the efficiency of the amplifier.

[0068] In summary, the concept of this invention is to integrate two previously separate amplifiers, CS and CG, into a single active region AA, thereby achieving the advantages of reduced component space and improved performance. Under this concept, various different embodiments of the invention can be formed depending on the arrangement of the first amplifier CS and the second amplifier CG within the active region AA. Some embodiments will be described in the following paragraphs.

[0069] Figure 3 The illustrations depict the arrangement of the first amplifier and the second amplifier in the active region according to various embodiments of the present invention, wherein... Figure 3 Figures (a), (b), (c), (d), and (e) illustrate five different arrangements. For the sake of brevity, the figures are shown in [the original text]. Figure 3 The layout of the first amplifier CS and the second amplifier CG is not shown in the figure, but those skilled in the art should know that... Figure 3 The layout structure should be included within the range of the first amplifier CS and the second amplifier CG. As shown in (a), the first amplifier CS and the second amplifier CG are arranged side by side in the active region AA. As shown in (b), a second amplifier CG is located between two first amplifier CSs in the active region AA. As shown in (c), from left to right, there are first amplifier CS, second amplifier CG, first amplifier CS and second amplifier CG. As shown in (d), from left to right, there are multiple sets of first amplifier CS and second amplifier CG arranged repeatedly (that is, arranged repeatedly in the order of first amplifier CS, second amplifier CG, first amplifier CS, second amplifier CG...). As shown in (e), this embodiment also includes a contact metal layer CTM located on the periphery of the amplifier. The contact metal layer CTM can connect multiple gates (not shown) in the amplifier to each other, or connect multiple sources / drains in the amplifier to each other. The contact metal layer CTM can be located on at least one side of the amplifier, for example... Figure 3 In (e), the contact metal layer CTM is located on the upper, lower, and left and right sides of the first amplifier CS, while another part of the contact metal layer CTM is located on the upper side of the second amplifier CG, but not on the lower side of the second amplifier CG.

[0070] It is worth noting that, in Figure 3 Several possible arrangements of the first and second amplifiers are illustrated, but the invention is not limited thereto. For example, the above... Figure 3In the various embodiments shown, the positions of the first amplifier CS and the second amplifier CG may be interchanged. For example, in (a), the first amplifier CS is on the left and the second amplifier CG is on the right, but in practice, their positions can also be interchanged (i.e., the first amplifier CS is on the right and the second amplifier CG is on the left), which is also within the scope of this invention. Furthermore, the arrangement of the contact metal layer CTM shown in (e) can also be changed according to actual needs, for example, by adding or removing contact metal layers CTM around the first amplifier CS and the second amplifier CG. All of the above variations are within the scope of this invention.

[0071] Figure 4 , Figure 5 and Figure 6 Schematic diagrams of the layouts of several two-stage amplifiers according to different embodiments of the present invention are shown. Figure 4 , Figure 5 and Figure 6 The two-stage amplifier shown is an example of a cascaded amplifier. First, as... Figure 4 As shown, after defining an active region AA and a shallow trench isolation STI surrounding the active region AA on a substrate Sub, a first amplifier CS and a second amplifier CG are formed within the active region AA. Depending on the arrangement of the first amplifier CS and the second amplifier CG, various different embodiments can be formed. For example, in... Figure 4 In this embodiment, the similarity to the above is as follows. Figure 3 As shown in (a), a first amplifier CS is formed in the left region of the active region AA, while a second amplifier CG is formed in the right region of the active region AA. Multiple gate structures G are formed in the active region AA as gates for the first amplifier CS or the second amplifier CG. Source / drain doped regions SD can be formed on both sides of the gate structure G through doping or other methods. Then, multiple contact structures CT are formed on each gate structure G or source / drain doped region SD. The contact structures CT are used to connect the gate structure G or source / drain doped region SD to other components, such as metal wire layers M1, M2, etc.

[0072] In this embodiment, the multiple gate structures G on the left side of the active region AA constitute the gate of the first amplifier CS, and the multiple source / drain doped regions SD on the left side of the active region AA constitute the source / drain of the first amplifier CS. The multiple gate structures G on the right side of the active region AA constitute the gate of the second amplifier CG, and the multiple source / drain doped regions SD on the right side of the active region AA constitute the source / drain of the second amplifier CG. To better understand the composition of the first amplifier CS and the second amplifier CG, in... Figure 4The diagram defines a first source doped region S1, a second source doped region S2, a first drain doped region D1, a second drain doped region D2, a first gate structure G1, and a second gate structure G2. The first source doped region S1, the second source doped region S2, the first drain doped region D1, and the second drain doped region D2 all belong to the source / drain doped region SD, while the first gate structure G1 and the second gate structure G2 belong to the gate structure G. In this embodiment, the first source doped region S1, the first drain doped region D1, and the first gate structure G1 form the first amplifier CS, while the second source doped region S2, the second drain doped region D2, and the second gate structure G2 form the second amplifier CG. Furthermore, the active region AA also contains more gate structures G and source / drain doped regions SD. These gate structures G and source / drain doped regions SD can be connected in parallel with the first amplifier CS or the second amplifier CG; therefore, in the circuit diagram, it is still considered that only the first amplifier CS or the second amplifier CG are connected in series. In actual manufacturing processes, the number of gate structures G and source / drain doped regions SD can be increased or decreased as needed.

[0073] Additionally, you can refer to the following: Figure 1 The circuit diagram shows that the gate CS-G of the first amplifier CS is connected to the metal conductor layer M1 via the contact structure CT, and then to the voltage source VG1. The source CS-S of the first amplifier CS is connected to the second metal layer M2, and can also be connected to the voltage source V- via the second metal layer M2. The gate CG-G of the second amplifier CG is connected to the metal conductor layer M1 via the contact structure CT, and then to the voltage source VG2. The drain CG-D of the second amplifier CS is connected to the second metal layer M2, and can also be connected to the voltage source output signal Vout via the second metal layer M2. In this embodiment and other embodiments below, the source S, drain D, drain CS-D of the first amplifier, gate CS-G of the first amplifier, source CS-S of the first amplifier, drain CG-D of the second amplifier, gate CG-G of the second amplifier, source CG-S of the second amplifier, voltage source VG1, and voltage source VG2 are directly labeled on the diagram to facilitate understanding of the connection relationships between the components. Other connection details can be found in [reference needed]. Figure 1 The circuit diagram shown will not be elaborated upon here.

[0074] It is worth noting that the first amplifier CS and the second amplifier CG share a portion of the source / drain doped region SD to connect the first amplifier CS and the second amplifier CG. For example... Figure 4 As shown, the drain CS-D of the first amplifier CS and the source CG-S of the second amplifier CG share the same source / drain doped region, that is... Figure 4The source / drain doped region SD3 is indicated in the diagram. Here, the source / drain doped region SD3 can be defined as the shared doped region SD3. In this embodiment, the first amplifier CS and the second amplifier CG are formed together within the same active region AA and share a portion of the doped region SD3. Therefore, the distance between the first amplifier CS and the second amplifier CG can be significantly reduced.

[0075] The above Figure 4 The layout pattern shown is one embodiment of the present invention. In other embodiments of the present invention, the arrangement positions of the first amplifier CS and the second amplifier CG can also be changed within the same active region AA. For example... Figure 5 In the active region AA, a first amplifier CS and a second amplifier CG are also formed. However, in this embodiment, the second amplifier CG is located between the two first amplifiers CS. The layout arrangement in this embodiment is similar to that described above. Figure 3 As shown in (b). Similarly, in this embodiment, the first amplifier CS and the second amplifier CG also share a portion of the doped region SD3, thus achieving the advantages of reducing component size and improving amplifier performance. Other components or connection methods in this embodiment are similar to those in the above embodiments and will not be repeated here.

[0076] In other embodiments, such as Figure 6 As shown, a first amplifier CS and a second amplifier CG are also formed within the active region AA. However, in this embodiment, the first amplifier CS and the second amplifier CG are arranged alternately and repeatedly. The layout arrangement of this embodiment is similar to that described above. Figure 3 As shown in (d). Similarly, in this embodiment, the first amplifier CS and the second amplifier CG also share a portion of the doped region SD3, thus achieving the advantages of reducing component size and improving amplifier performance. Other components or connection methods in this embodiment are similar to those in the above embodiments and will not be repeated here.

[0077] From Figure 4 , Figure 5 and Figure 6 As can be seen, the first amplifier CS and the second amplifier CG are both formed within the same active region AA and share a portion of the doped region SD3. Therefore, the distance between the first amplifier CS and the second amplifier CG will be significantly smaller than in embodiments where the two amplifiers are formed in different active regions (e.g., ...). Figure 2 (The embodiment on the left). Meanwhile, because the distance between the two amplifiers is reduced, the distance between the wires is also shorter, reducing the influence of wire impedance and improving amplifier efficiency. Based on the applicant's experimental results, this invention... Figure 4 , Figure 5 and Figure 6 The embodiments compared to Figure 2The embodiment shown on the left half has an amplifier area reduced by more than 20%, while amplifier efficiency is improved by more than 11%.

[0078] The amplifier of the present invention can also be applied to radio frequency (RF) amplifiers. Figure 7 A schematic diagram illustrating the layout of a radio frequency circuit pattern according to an embodiment of the present invention is shown. Figure 7 As shown, in this embodiment, most of the components are the same as those described above. Figures 4 to 6 Similarly, elements such as the active region AA, gate structure G, contact structure CT, metal conductor layer M1, and metal conductor layer M2 are represented by the same reference numerals. In this embodiment, the source / drain doped regions are the active regions AA on both sides of the gate structure G, which are not shown for the sake of simplicity in the accompanying drawings. This embodiment proposes a layout pattern for an RF amplifier, wherein a first amplifier T1 and a second amplifier T2 are included within the active region AA. The first amplifier T1 and the second amplifier T2 are connected in series and are formed together within the same active region AA, sharing a portion of the source / drain doped regions. Therefore, the layout pattern applied to the RF amplifier in this embodiment also has the advantages of reducing components and improving performance. Other details regarding the RF amplifier are prior art and will not be elaborated here.

[0079] In the above embodiments, the concept of the present invention is applied to stacked amplifiers and radio frequency amplifiers. However, as mentioned above, the concept of the present invention can also be applied to other types of circuits, such as series circuits for two or more transistors. For example, Figure 8 Draw a circuit diagram of a stacked MOSFET. Figure 9 A schematic diagram of the layout of a stacked field-effect transistor according to an embodiment of the present invention is then drawn. For example... Figure 8 As shown in the circuit diagram of a stacked field-effect transistor, the gates of the first amplifier T1 and the second amplifier T2 are connected to each other (connected to the voltage source VG), but the drain of the first amplifier T1 and the source of the second amplifier T2 are connected to each other. Please refer to the corresponding layout diagram. Figure 9The active region AA includes a gate structure G, source / drain doped regions SD, contact structure CT, metal conductor layers M1 and M2, etc. The characteristics of these components are the same as in the above embodiment, and will not be repeated here. In this embodiment, the drain of the first amplifier T1 and the source of the second amplifier T2 are connected to each other and share a portion of the doped region SD3, which also achieves the effect of reducing component size. Therefore, this invention can be applied to stacked amplifiers, RF amplifiers, and other secondary amplifiers, including stacked field-effect transistors (stack MOS), Gilbert mixers, RF switches, active inductors, etc., all of which are within the scope of this invention.

[0080] Based on the above description and accompanying drawings, the present invention provides a semiconductor layout pattern comprising a substrate Sub, an active region AA defined on the substrate Sub, a plurality of gate structures G located within the active region AA, wherein each gate structure is arranged parallel to each other along a first direction (e.g., along the X direction), and a plurality of doped regions SD located within the active region AA, with each doped region SD located in the substrate Sub on either side of each gate structure G. The plurality of gate structures G included within the active region AA includes a first gate structure G1 and a second gate structure G2. The doped region SD includes a first source doped region S1, a first drain doped region D1, a second source doped region S2, and a second drain doped region D2. The first gate structure G1, the first source doped region S1, and the first drain doped region D1 form a first amplifier CS. The second gate structure G2, the second source doped region S2, and the second drain doped region D2 form a second amplifier CG. Furthermore, the first drain doped region D1 and the second source doped region S2 contain the same doped region from among multiple doped regions; this same doped region is defined as a common doped region SD3 (please refer to...). Figure 4 (Example shown).

[0081] In some embodiments of the present invention, a plurality of doped regions SD are arranged parallel to each other along a first direction (e.g., the X direction), and along the first direction, the plurality of doped regions SD are alternately arranged with a plurality of gate structures G.

[0082] In some embodiments of the present invention, in a top view, the plurality of gate structures G and the plurality of doped regions SD are all elongated strips, and the long side of the elongated strip SD extends along a second direction (e.g., the Y direction), wherein the second direction (Y direction) is perpendicular to the first direction (X direction).

[0083] In some embodiments of the present invention, a common doped region SD3 is located between the first gate structure G1 and the second gate structure G2, as viewed from a top view, and the common doped region SD3 is adjacent to the first gate structure G1 and the second gate structure G2.

[0084] In some embodiments of the present invention, the common doped region SD3 is located on one side of the first gate G1, and the first source doped region S1 is located on the other side of the first gate G1 relative to the common doped region SD3, the common doped region SD3 is located on one side of the second gate G2, and the second drain doped region D2 is located on the other side of the second gate G2 relative to the common doped region SD3.

[0085] In some embodiments of the present invention, the first amplifier CS includes a common source amplifier, the second amplifier includes a common gate amplifier, and the first amplifier CS and the second amplifier CG are connected in series to form a cascode amplifier.

[0086] In some embodiments of the present invention, a first gate structure G1 is connected to a voltage source VG1 and a second drain doped region is connected to an output signal Vout.

[0087] In some embodiments of the present invention, the active region AA further includes a plurality of common source amplifiers CS and a plurality of common gate amplifiers CG, wherein each region containing a common source amplifier CS is defined as a first region and each region containing a common gate amplifier CG is defined as a second region.

[0088] In some embodiments of the present invention, at least one of the plurality of first regions is located between two adjacent second regions, and at least one of the plurality of second regions is located between two adjacent first regions (e.g., Figure 3 (d), multiple first regions and multiple second regions are arranged in an interactive and overlapping manner.

[0089] In some embodiments of the present invention, the doped regions SD within the active region AA do not include a shallow trench isolation structure.

[0090] The present invention also provides a radio frequency circuit layout pattern, including a substrate Sub, an active region AA defined on the substrate Sub, a plurality of gate structures G located in the active region AA, wherein each gate structure G is arranged parallel to each other along a first direction (e.g., the X direction), a plurality of doped regions SD located in the active region AA, and each doped region SD is located in the substrate Sub on both sides of each gate structure G, wherein the plurality of gate structures G and the plurality of doped regions SD contained in the active region AA constitute a first amplifier CS and a second amplifier CG, wherein a drain CS-D of the first amplifier CS and a source CG-S of the second amplifier CG are connected to each other, and the drain CS-D of the first amplifier CS and the source CG-S of the second amplifier CG are both located on a common doped region SD3.

[0091] In some embodiments of the present invention, a plurality of doped regions SD are arranged parallel to each other along a first direction (X direction), and along the first direction, the plurality of doped regions SD are alternately arranged with a plurality of gate structures G.

[0092] In some embodiments of the present invention, in a top view, the plurality of gate structures G and the plurality of doped regions SD are all elongated strips, and the long sides of the strips extend along a second direction (e.g., the Y direction), wherein the second direction (Y direction) is perpendicular to the first direction (X direction).

[0093] In some embodiments of the present invention, the plurality of gate structures G include a first gate structure G1 and a second gate structure G2, and the plurality of doped regions SD included in the active region AA include a first source doped region S1, a first drain doped region D1, a second source doped region S2 and a second drain doped region D2. The first gate structure G1, the first source doped region S1 and the first drain doped region D1 form a first amplifier CS, and the second gate structure G2, the second source doped region S2 and the second drain doped region D2 form a second amplifier CG. The first drain doped region D1 and the second source doped region S2 include the same doped region among the plurality of doped regions SD. The same doped region is defined as a common doped region SD3.

[0094] In some embodiments of the present invention, a common doped region SD3 is located between the first gate structure G1 and the second gate structure G2, as viewed from a top view, and the common doped region SD3 is adjacent to the first gate structure G1 and the second gate structure G2.

[0095] In some embodiments of the present invention, the common doped region SD3 is located on one side of the first gate G1, and the first source doped region S1 is located on the other side of the first gate G1 relative to the common doped region SD3, the common doped region SD3 is located on one side of the second gate G2, and the second drain doped region D2 is located on the other side of the second gate G2 relative to the common doped region SD3.

[0096] In some embodiments of the present invention, the first amplifier CS includes a common source amplifier, the second amplifier CG includes a common gate amplifier, and the first amplifier CS and the second amplifier CG are connected in series to form a cascode amplifier.

[0097] In some embodiments of the present invention, the active region AA further includes a plurality of common-source amplifiers and a plurality of common-gate amplifiers, wherein each region containing a common-source amplifier CS is defined as a first region, and each region containing a common-gate amplifier CG is defined as a second region.

[0098] In some embodiments of the present invention, at least one of the plurality of first regions is located between two adjacent second regions, and at least one of the plurality of second regions is located between two adjacent first regions (e.g., Figure 3 (d), multiple first regions and multiple second regions are arranged in an interactive and overlapping manner.

[0099] In some embodiments of the present invention, the doped regions SD within the active region AA do not include a shallow trench isolation structure.

[0100] In summary, the key feature of this invention is that, in order to save component space and reduce the influence of wire impedance when fabricating the layout pattern of the two-stage amplifier, the two amplifiers are fabricated within the same active region. This allows the two amplifiers within the two-stage amplifier to share a portion of the doped region; that is, there is no shallow trench separating the two amplifier regions. Under this invention, component size can be effectively reduced, and due to the reduced influence of wire impedance, amplifier performance can also be improved.

[0101] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor layout pattern, comprising: A substrate on which an active region is defined; Multiple gate structures are located within the active region, wherein each gate structure is arranged parallel to each other along a first direction; Multiple doped regions are located within the active region, and each doped region is located in the substrate on both sides of each gate structure; in, The active region includes a first gate structure and a second gate structure among the plurality of gate structures. The active region includes a first source doped region, a first drain doped region, a second source doped region, and a second drain doped region. The first gate structure, the first source doped region, and the first drain doped region form a first amplifier. The second gate structure, the second source doped region, and the second drain doped region form a second amplifier. The first drain doped region and the second source doped region include the same doped region among the plurality of doped regions. The same doped region is defined as a shared doped region.

2. The semiconductor layout pattern of claim 1, wherein the plurality of doped regions are arranged parallel to each other along the first direction, and the plurality of doped regions are alternately arranged with the plurality of gate structures along the first direction.

3. The semiconductor layout pattern as claimed in claim 1, wherein, from a top view, the plurality of gate structures and the plurality of doped regions are all elongated strips, and the long sides of the strips extend along a second direction, wherein the second direction is perpendicular to the first direction.

4. The semiconductor layout pattern of claim 1, wherein, viewed from a top view, the common doped region is located between the first gate structure and the second gate structure, and the common doped region is adjacent to the first gate structure and the second gate structure.

5. The semiconductor layout pattern of claim 4, wherein the common doped region is located on one side of the first gate, and the first source doped region is located on the other side of the first gate relative to the common doped region, the common doped region is located on one side of the second gate, and the second drain doped region is located on the other side of the second gate relative to the common doped region.

6. The semiconductor layout pattern of claim 1, wherein the first amplifier includes a common source amplifier, the second amplifier includes a common gate amplifier, and the first amplifier and the second amplifier are connected in series to form a cascode amplifier.

7. The semiconductor layout pattern of claim 6, wherein the first gate structure is connected to a voltage source VG1 and the second drain doped region is connected to an output signal Vout.

8. The semiconductor layout pattern of claim 1, wherein the active region further includes a plurality of common-source amplifiers and a plurality of common-gate amplifiers, wherein each region containing the common-source amplifier is defined as a first region, and each region containing the common-gate amplifier is defined as a second region.

9. The semiconductor layout pattern of claim 8, wherein at least one of the plurality of first regions is located between two adjacent second regions, and at least one of the plurality of second regions is located between two adjacent first regions.

10. The semiconductor layout pattern of claim 1, wherein the doped regions within the active region do not include shallow trench isolation structures.

11. A radio frequency circuit layout pattern, comprising: A substrate on which an active region is defined; Multiple gate structures are located within the active region, wherein each gate structure is arranged parallel to each other along a first direction; Multiple doped regions are located within the active region, and each doped region is located in the substrate on both sides of each gate structure; in, The active region contains a plurality of gate structures and a plurality of doped regions that constitute a first amplifier and a second amplifier, wherein the drain of the first amplifier and the source of the second amplifier are connected to each other, and the drain of the first amplifier and the source of the second amplifier are both located on a common doped region.

12. The radio frequency circuit layout pattern of claim 11, wherein the plurality of doped regions are arranged parallel to each other along the first direction, and the plurality of doped regions are alternately arranged with the plurality of gate structures along the first direction.

13. The radio frequency circuit layout pattern of claim 11, wherein, from a top view, the plurality of gate structures and the plurality of doped regions are all elongated strips, and the long sides of the strips extend along a second direction, wherein the second direction is perpendicular to the first direction.

14. The RF circuit layout pattern of claim 11, wherein the plurality of gate structures includes a first gate structure and a second gate structure, the plurality of doped regions included in the active region include a first source doped region, a first drain doped region, a second source doped region and a second drain doped region, wherein the first gate structure, the first source doped region and the first drain doped region constitute the first amplifier, the second gate structure, the second source doped region and the second drain doped region constitute the second amplifier, and wherein the first drain doped region and the second source doped region include the same doped region among the plurality of doped regions, the same doped region being defined as the common doped region.

15. The radio frequency circuit layout pattern of claim 14, wherein, viewed from a top view, the common doped region is located between the first gate structure and the second gate structure, and the common doped region is adjacent to the first gate structure and the second gate structure.

16. The radio frequency circuit layout pattern of claim 15, wherein the common doped region is located on one side of the first gate, and the first source doped region is located on the other side of the first gate relative to the common doped region, the common doped region is located on one side of the second gate, and the second drain doped region is located on the other side of the second gate relative to the common doped region.

17. The radio frequency circuit layout pattern of claim 11, wherein the first amplifier includes a common source amplifier, the second amplifier includes a common gate amplifier, and the first amplifier and the second amplifier are connected in series to form a cascode amplifier.

18. The radio frequency circuit layout pattern of claim 11, wherein the active region further includes a plurality of common source amplifiers and a plurality of common gate amplifiers, wherein each region containing the common source amplifier is defined as a first region, and each region containing the common gate amplifier is defined as a second region.

19. The radio frequency circuit layout pattern of claim 18, wherein at least one of the plurality of first regions is located between two adjacent second regions, and at least one of the plurality of second regions is located between two adjacent first regions.

20. The RF circuit layout pattern of claim 11, wherein the doped regions within the active region do not include shallow trench isolation structures.

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