Preparation method and structure of LED chip passivation layer based on PECVD (Plasma Enhanced Chemical Vapor Deposition) multi-stage deposition

Abstract

The invention relates to the technical field of semiconductor device manufacturing, in particular to an LED chip passivation layer preparation method and structure based on PECVD multi-section deposition, and the method comprises the following steps: providing an LED chip substrate with a light-emitting structure and an electrode formed on the surface; a passivation layer is deposited on the substrate through a PECVD (Plasma Enhanced Chemical Vapor Deposition) process in three stages: in the first deposition stage, an interface bonding layer is deposited and formed under the process conditions of low radio frequency power, high reaction pressure and low silicon-nitrogen gas flow ratio; and in the second deposition stage, a stress buffer layer is deposited and formed on the interface bonding layer under the process conditions of medium radio frequency power, medium reaction pressure and medium silicon-nitrogen gas flow ratio. Through deposition under the conditions of low power, high pressure and rich nitrogen in the first stage, firm combination, mainly based on strong chemical bonding (such as Si-N-Ga), between a passivation layer and a bottom layer (such as GaN) is achieved, and the problems of film layering and blistering caused by a traditional process are fundamentally solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for preparing a passivation layer for an LED chip and the resulting chip structure. Background Technology

[0002] In the manufacturing process of LED chips, especially vertical or flip-chip chips, a high-quality passivation layer (typically silicon nitride SiNx or silicon oxide SiOx) needs to be deposited on the light-emitting layer (such as multiple quantum wells, MQW) and metal electrodes. The main functions of this passivation layer are to protect the internal structure of the chip from external moisture and ions, provide mechanical protection, prevent epitaxial layer cracking by adjusting stress, and provide good insulation to prevent leakage between electrodes.

[0003] Currently, plasma-enhanced chemical vapor deposition (PECVD) is widely used in the industry to prepare this passivation layer. However, traditional single-step or uniform process parameter PECVD methods have inherent drawbacks: 1. Underlying Material Adhesion Issues: Due to differences in the coefficients of thermal expansion and chemical bonding capabilities between the passivation layer and the underlying material (such as GaN epitaxial layer, SiO2 dielectric layer, or metal electrode), the film deposited under single high stress or high deposition rate conditions has weak adhesion to the underlying material. This can easily lead to delamination, blistering, or cracking during subsequent chip dicing, packaging, or reliability testing, resulting in device failure.

[0004] 2. Leakage Channel Issue: While dense thin films deposited directly at high RF power exhibit good bulk properties, the high-energy plasma generated during the initial deposition stage can bombard the underlying layer (especially GaN surfaces with defects or dangling bonds). These micro-damages can form leakage channels that penetrate the thin film, leading to a significant increase in reverse leakage current under high-voltage operating conditions, thus reducing device reliability and lifespan.

[0005] Therefore, there is an urgent need for a novel preparation method that can simultaneously solve the problems of passivation layer adhesion and leakage. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and structure for preparing an LED chip passivation layer based on PECVD multi-segment deposition. This method, by designing a specific sequence of multi-segment deposition parameters, aims to achieve high-strength bonding and low interface damage between the passivation layer and the underlying layer, ultimately obtaining a high-density, low-stress, high-quality passivation layer, thereby solving the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a method for preparing an LED chip passivation layer based on PECVD multi-segment deposition, comprising the following steps: S1. Providing a substrate: Providing an LED chip substrate with a light-emitting structure and electrodes formed on its surface, and placing it in a PECVD reaction chamber; S2. First deposition stage: Deposition interface bonding layer; S3. Second deposition stage: Deposit a stress buffer layer on the interface bonding layer; S4. Third deposition stage: Deposit a passivation layer on the stress buffer layer.

[0008] Preferably, in step S2, the process parameters for the first deposition stage are: RF power: 50W to 100W; Reaction pressure: 500 mTorr to 1000 mTorr; Deposition gas: The flow rate ratio of silicon source gas to nitrogen source gas is 0.1 to 0.5; Deposition thickness: 10nm to 100nm.

[0009] Preferably, in step S3, the process parameters for the second deposition stage are: RF power: increasing linearly or stepwise from the power of the first deposition stage to 300W to 500W; Reaction pressure: Reduced to 300 mTorr to 700 mTorr; Deposition gas: The flow ratio of silicon source gas to nitrogen source gas is increased to 0.5 to 1.2; Deposition thickness: 50nm to 200nm.

[0010] Preferably, in step S4, the process parameters for the third deposition stage are: RF power: 600W to 900W; Reaction pressure: 150 mTorr to 400 mTorr; Deposition gas: The flow rate ratio of silicon source gas to nitrogen source gas is maintained at 1.0 to 2.0; Deposition thickness: to achieve a total passivation layer thickness of 500 nm to 1500 nm.

[0011] Preferably, the silicon source gas is silane (SiH4), the nitrogen source gas is nitrous oxide (N2O), and inert nitrogen gas (N2) is introduced as a carrier gas in each deposition stage.

[0012] The present invention also provides an LED chip structure prepared by the above method, which includes, from bottom to top: a substrate, a light-emitting structure, an electrode, and a passivation layer; the passivation layer is a composite layer structure formed by multi-segment deposition by PECVD, including an interface bonding layer in direct contact with the electrode and the light-emitting structure, a stress buffer layer located on the interface bonding layer, and a bulk passivation layer located on the outermost layer.

[0013] Compared with the prior art, the beneficial effects of the present invention are: 1. Significantly improved adhesion: Through the first stage of low-power, high-pressure, nitrogen-rich deposition, a strong bond is achieved between the passivation layer and the underlying layer (such as GaN) mainly by strong chemical bonding (such as Si-N-Ga), which fundamentally solves the problems of film delamination and blistering caused by traditional processes.

[0014] 2. Effectively reduces leakage current: The low plasma bombardment energy in the initial deposition stage avoids damage to the underlying GaN or electrode surface, cutting off the formation of leakage channels at the source. This reduces the reverse leakage current of the chip by more than an order of magnitude, significantly improving the reliability and lifespan of the device.

[0015] 3. Excellent stress management: Through the gradual transition of parameters in the second stage, the internal stress distribution between the low-stress, relatively loose interface layer and the high-stress, highly dense body layer is smoothed, effectively releasing the interface stress, improving the overall mechanical stability of the passivation layer, and preventing the occurrence of cracking.

[0016] 4. Strong process compatibility: The method of this invention is based on conventional PECVD equipment and does not require additional hardware. It can be achieved simply by optimizing the deposition process parameter sequence, making it easy to integrate into existing LED chip production lines and possessing good prospects for industrial application. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a process flow diagram of the multi-segment deposition method for LED chip passivation layer described in this invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Please see Figure 1 The present invention provides a technical solution: Example 1 A SiNx passivation layer for a flip-chip blue LED is prepared.

[0021] S1. Provide sapphire substrate GaN-based LED chips that have completed front-end processes such as photolithography, etching, and metal electrode evaporation, and place them into the PECVD reaction chamber after cleaning.

[0022] S2. First deposition stage (interfacial bonding layer): The radio frequency power was set to 80W and the reaction pressure to 800mTorr.

[0023] Introduced gases: SiH4 flow rate 50 sccm, N2O flow rate 200 sccm (SiH4 / N2O flow rate ratio = 0.25), N2 carrier gas flow rate 2000 sccm.

[0024] Deposition time is controlled to form an interfacial bonding layer with a thickness of approximately 50 nm.

[0025] S3. Second deposition stage (stress buffer layer): Within 5 minutes, the RF power was linearly increased to 400W, and the reaction pressure was reduced to 500mTorr.

[0026] Adjust the gas flow rate: increase the SiH4 flow rate to 150 sccm, the N2O flow rate to 200 sccm (SiH4 / N2O flow rate ratio = 0.75), and keep the N2 flow rate unchanged.

[0027] Deposition time is controlled to form a stress buffer layer with a thickness of approximately 150 nm.

[0028] S4. Third deposition stage (volume passivation layer): Maintain RF power at 800W and reaction pressure at 250mTorr.

[0029] Adjust the gas flow rate: SiH4 flow rate is 180 sccm, N2O flow rate is 120 sccm (SiH4 / N2O flow rate ratio = 1.5), and the N2 flow rate remains unchanged.

[0030] The total thickness of the passivation layer deposited reaches approximately 1000 nm.

[0031] After deposition, the chip is removed for subsequent processes. Testing showed that the passivation layer of this chip exhibited no delamination or cracking, and its leakage current under a 20V reverse bias was approximately 15 times lower than that of chips fabricated using traditional single-stage processes.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a passivation layer for an LED chip based on PECVD multi-segment deposition, characterized in that, Includes the following steps: Provide an LED chip substrate with a light-emitting structure and electrodes formed on its surface; A passivation layer is deposited on the substrate in three stages using a PECVD process: In the first deposition stage, an interfacial bonding layer is deposited under process conditions of low radio frequency power, high reaction pressure, and low silicon-nitrogen gas flow ratio. In the second deposition stage, under process conditions of moderate radio frequency power, moderate reaction pressure and moderate silicon-nitrogen gas flow ratio, a stress buffer layer is deposited on the interface bonding layer. In the third deposition stage, a bulk passivation layer is deposited on the stress buffer layer under process conditions of high radio frequency power, low reaction pressure, and high silicon-nitrogen gas flow ratio.

2. The method for preparing an LED chip passivation layer based on PECVD multi-segment deposition according to claim 1, characterized in that, The process parameters for the first deposition stage satisfy: RF power ranges from 50W to 100W; The reaction pressure is 500 mTorr to 1000 mTorr; The flow rate ratio of silicon source gas to nitrogen source gas is 0.1 to 0.5; The thickness of the deposited interfacial bonding layer is 10 nm to 100 nm.

3. The method for preparing an LED chip passivation layer based on PECVD multi-segment deposition according to claim 1, wherein the process parameters of the second deposition stage satisfy: The radio frequency power is 300W to 500W; The reaction pressure is 300 mTorr to 700 mTorr; The flow rate ratio of silicon source gas to nitrogen source gas is 0.5 to 1.2; The thickness of the deposited stress buffer layer ranges from 50 nm to 200 nm.

4. The method for preparing an LED chip passivation layer based on PECVD multi-segment deposition according to claim 1, characterized in that, The process parameters for the third deposition stage satisfy: The radio frequency power is 600W to 900W; The reaction pressure is from 150 mTorr to 400 mTorr; The flow rate ratio of silicon source gas to nitrogen source gas is 1.0 to 2.0; The thickness of the deposited bulk passivation layer results in a total passivation layer thickness of 500 nm to 1500 nm.

5. A method for preparing an LED chip passivation layer based on PECVD multi-segment deposition according to any one of claims 1-4, characterized in that, The silicon source gas is silane (SiH4), and the nitrogen source gas is nitrous oxide (N2O).

6. In the method for preparing an LED chip passivation layer based on PECVD multi-stage deposition according to claim 5, nitrogen (N2) is introduced as a carrier gas in each deposition stage.

7. An LED chip structure, characterized in that, The LED chip structure is prepared by any one of claims 1 to 6, and its passivation layer is a composite layer structure, including an interface bonding layer in direct contact with the chip surface, a stress buffer layer located on the interface bonding layer, and a bulk passivation layer located on the outermost layer.

8. The LED chip structure according to claim 7, characterized in that, The interface bonding layer, stress buffer layer, and bulk passivation layer are all silicon nitride (SiNx) layers or silicon oxide (SiOx) layers.

9. An LED chip structure according to claim 7 or 8, characterized in that, The LED chip is a flip-chip LED chip or a vertical-chip LED chip.

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