Visible light communication semiconductor device, manufacturing method thereof and epitaxial structure

Abstract

The invention provides a visible light communication semiconductor device, a manufacturing method thereof and an epitaxial structure. The visible light communication semiconductor device comprises a substrate, a lighting chip arranged on the surface of one side of the substrate and at least one communication chip. The first semiconductor layer is divided into an illumination area and a communication area which are insulated from each other; the lighting chip comprises a second semiconductor layer, a first active layer and a lighting area; each communication chip comprises a third semiconductor layer, a second active layer and a communication area; the area of the second active layer is smaller than that of the first active layer, and the first active layer and the second active layer are located on the two opposite sides of the first semiconductor layer respectively; the second semiconductor layer and the third semiconductor layer are the same in doping type, and the first semiconductor layer and the second semiconductor layer are opposite in doping type. The visible light communication semiconductor device has a lighting function and a communication function at the same time, the number of used devices is reduced, and the complexity and loss of a module are reduced.

Description

Technical Field

[0001] This invention relates to the field of visible light communication semiconductor devices, and more specifically, to a visible light communication semiconductor device, its fabrication method, and its epitaxial structure. Background Technology

[0002] Visible light communication (VLC), as a novel high-speed communication technology with abundant spectrum resources and energy efficiency, is considered one of the most effective ways to solve the problem of scarce communication spectrum resources faced by traditional radio communication. It is expected to integrate with other communication technologies to jointly address the challenges of spectrum, energy consumption, and communication capacity in 6G. With the rapid development of third-generation semiconductor materials such as gallium nitride (GaN) and diamond, and the continuous in-depth research on VLC technology, developing LED chips with faster response speeds and higher luminous efficiency has become crucial for the development of VLC technology.

[0003] The modulation bandwidth of an LED chip is closely related to its RC parameter, where R represents the resistance and C represents the capacitance. The product of RC is the time constant of the LED chip. Reducing the time constant increases the modulation bandwidth, making it more responsive to changes in high-frequency signals. However, the time constant of an LED chip is also closely related to the size of its active region. A larger active region results in a larger capacitance, leading to an increased time constant and a decreased modulation bandwidth. Currently, GaN-based LED chips for conventional lighting typically offer only a modulation bandwidth of tens of megahertz while still providing illumination. LED chips with modulation bandwidths exceeding hundreds of megahertz are primarily Micro LEDs, as their extremely small size allows for a smaller RC constant and thus, higher modulation bandwidth. The development of Micro LED technology has provided a higher-performance light source for VLC technology, enabling VLC systems to achieve higher data transmission rates and wider applications.

[0004] However, conventional LED chips, in order to meet the needs of lighting applications, typically require stable illumination and a stable luminous flux under constant current drive. The human eye is only sensitive to frequencies below 120Hz, which cannot meet the requirements of communication applications. High-bandwidth communication chips transmit information at high speeds at MHz, requiring extremely short response times. This creates a contradiction: high-speed modulation leads to flicker that is invisible to the naked eye, but the junction capacitance effect of the LED chip under high current drive severely limits the modulation bandwidth. Existing technologies can only use chips with single lighting or communication functions, combined with complex driving techniques to control the lighting and communication chips in separate zones, increasing module complexity and losses. Therefore, how to enable semiconductor devices to simultaneously possess lighting and communication functions has become a pressing problem to be solved. Summary of the Invention

[0005] In view of this, the present invention provides a visible light semiconductor device and its fabrication method and epitaxial structure, which integrates lighting and communication functions through a single semiconductor device.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A visible light communication semiconductor device, comprising

[0008] substrate;

[0009] An illumination chip and at least one communication chip are disposed on one side surface of the substrate; the illumination chip and the communication chip share a first semiconductor layer, which is divided into an illumination region and a communication region that are insulated from each other;

[0010] The lighting chip includes a second semiconductor layer, a first active layer, and the lighting region; the second semiconductor layer and the first active layer are located in the lighting region, and the first active layer is located between the second semiconductor layer and the lighting region;

[0011] Each of the communication chips includes a third semiconductor layer, a second active layer, and the communication region; the third semiconductor layer and the second active layer are located in the communication region, and the second active layer is located between the third semiconductor layer and the communication region;

[0012] The area of ​​the second active layer is smaller than that of the first active layer, and the first and second active layers are located on opposite sides of the first semiconductor layer; the second and third semiconductor layers have the same doping type, while the first and second semiconductor layers have opposite doping types.

[0013] Furthermore, the communication chip comprises multiple chips; each communication chip is disposed on the outside of the lighting chip.

[0014] Furthermore, it also includes a first electrode, a second electrode, a third electrode, and a fourth electrode;

[0015] The substrate is a conductive substrate;

[0016] The first active layer and the second semiconductor layer are located on the side of the first semiconductor layer facing the substrate;

[0017] The second active layer and the third semiconductor layer are located on the side of the first semiconductor layer that is away from the substrate;

[0018] The first electrode is located between the substrate and the second semiconductor layer, and is electrically connected to the substrate and the second semiconductor layer;

[0019] The second electrode is located on the lighting area and is electrically connected to the lighting area;

[0020] The third electrode is located on the third semiconductor layer and is electrically connected to the third semiconductor layer;

[0021] The fourth electrode is located on the communication area and is electrically connected to the communication area.

[0022] Furthermore, a first insulating region is obtained by ion implantation into the first semiconductor layer; the first insulating region surrounds the lighting region.

[0023] Furthermore, a second insulating region is obtained by ion implantation of the second active layer and the third semiconductor layer of each of the communication chips on the side adjacent to the lighting chip.

[0024] Furthermore, the visible light communication semiconductor device also includes a passivation layer; the passivation layer is located on the side of the communication region away from the second active layer, and is disposed around the first active layer and the second semiconductor layer.

[0025] The present invention also provides an epitaxial structure for fabricating a visible light communication semiconductor device according to any of the above-mentioned claims;

[0026] The epitaxial structure includes a growth substrate;

[0027] A second semiconductor layer, a first active layer, a second active layer, and a third semiconductor layer are sequentially stacked on the growth substrate in a direction away from the growth substrate; the second semiconductor layer and the third semiconductor layer have the same doping type, while the first semiconductor layer and the second semiconductor layer have opposite doping types;

[0028] The first active layer is an InGaN / GaN multi-quantum-well layer;

[0029] The second active layer is an InGaN quantum dot layer or a superlattice structure including InGaN quantum dots and GaN quantum dots.

[0030] The present invention also provides a method for fabricating a visible light communication semiconductor device, characterized in that it includes:

[0031] Provide a growth substrate;

[0032] A second semiconductor layer, a first active layer, a first semiconductor layer, a second active layer, and a third semiconductor layer are sequentially grown on one side of the growth substrate; the second semiconductor layer and the third semiconductor layer have the same doping type, while the first semiconductor layer and the second semiconductor layer have opposite doping types;

[0033] A first transfer substrate is bonded to the side of the third semiconductor layer opposite to the growth substrate, and the growth substrate is removed to expose the second semiconductor layer.

[0034] The film layer on the side opposite to the first transfer substrate on the first region of the first semiconductor layer is removed by photolithography and etching processes;

[0035] A first electrode is fabricated on the surface of the second semiconductor layer that is away from the first transfer substrate;

[0036] A passivation layer is filled in the first region;

[0037] A conductive substrate is bonded to the passivation layer and the side of the first electrode facing away from the first transfer substrate, and the first transfer substrate is removed to expose the third semiconductor layer; the first electrode is electrically connected to the substrate and the second semiconductor layer.

[0038] By using photolithography and etching processes, at least the film layer on the side of the first semiconductor layer facing away from the substrate in the second region is removed, and the remaining film layer is divided into at least one independent chip region.

[0039] The first semiconductor layer is divided into an insulating lighting region and a communication region, with the first region corresponding to the communication region and the second region corresponding to the lighting region, forming a lighting chip and at least one communication chip. The lighting chip and the communication chip share the first semiconductor layer. The lighting chip includes a second semiconductor layer, a first active layer, and the lighting region. Each of the communication chips includes a third semiconductor layer, a second active layer, and the communication region. The area of ​​the second active layer is smaller than the area of ​​the first active layer.

[0040] A second electrode is fabricated, which is located on the lighting area and electrically connected to the lighting area;

[0041] A third electrode is fabricated, wherein the third electrode is located on the third semiconductor layer and electrically connected to the third semiconductor layer;

[0042] A fourth electrode is fabricated, which is located on the communication area and electrically connected to the communication area.

[0043] Furthermore, in the step of removing at least the film layer on the side opposite to the substrate on the second region of the first semiconductor layer through photolithography and etching processes, and dividing the remaining film layer into at least one independent chip region: the remaining film layer is divided into multiple independent chip regions, and each chip region and the communication region form multiple communication chips.

[0044] Each of the communication chips is disposed on the outside of the lighting chip.

[0045] Furthermore, an ion implantation process is used to implant ions into the first semiconductor layer to obtain a first insulating region; the first insulating region surrounds the lighting region.

[0046] Compared with existing technologies, the technical solution provided by this invention has at least the following advantages:

[0047] 1. This visible light communication semiconductor device integrates a lighting chip and at least one communication chip, enabling a single chip to simultaneously perform both lighting and communication functions. This reduces the number of devices required and lowers the complexity and loss of the module. The lighting chip and communication chip share a first semiconductor layer, while the remaining film layers are independently configured. This reduces the device thickness to some extent and allows for the selection of more suitable active layer materials based on the different performance requirements of the lighting and communication chips. Furthermore, the first semiconductor layer is divided into mutually insulated lighting and communication regions to prevent mutual interference between the lighting and communication chips. The area of ​​the second active layer is smaller than that of the first active layer, increasing the adjustment bandwidth of the communication chip to achieve high-frequency communication. The first and second active layers are located on opposite sides of the first semiconductor layer. In actual fabrication, various wide-bandgap semiconductor materials can be integrated using epitaxial growth, such as sequentially epitaxially growing the second semiconductor layer, the first active layer, the second active layer, and the third semiconductor layer to simplify the material preparation process.

[0048] 2. The lighting chip is controlled via the first and second electrodes, while the communication chip is controlled via the second and third electrodes. This allows the lighting and communication chips to be driven independently without affecting each other, ensuring their functions are independent and maximizing their performance. This achieves better integration of high-frequency communication and lighting.

[0049] 3. A first insulating region is obtained by ion implantation into the first semiconductor layer. The first insulating region surrounds the lighting region, thereby dividing the first semiconductor layer into a lighting region and a communication region that are insulated from each other. The ion implantation process is simple and avoids etching damage.

[0050] 4. By performing ion implantation on the side of the second active layer and the third semiconductor layer of each communication chip that is close to the lighting chip, a second insulating region is obtained, which enables better insulation and isolation between the communication chip and the lighting chip, and can prevent the communication chip and the lighting chip from being connected when the electrodes are connected, which would cause abnormal chip function.

[0051] 5. This epitaxial structure sequentially stacks a second semiconductor layer, a first active layer, a second semiconductor layer, a second active layer, and a third semiconductor layer on a growth substrate, integrating multiple wide-bandgap semiconductor materials through epitaxy, simplifying the material preparation process. During the growth of the epitaxial structure, the required film layers for communication chips and lighting chips are grown simultaneously. Subsequent epitaxial structures can be combined with bonding, photolithography, and etching processes to obtain semiconductor devices integrating communication chips and lighting chips, eliminating the need for multiple furnace cycles, thus saving energy and reducing emissions. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of the structure of an embodiment of a visible light communication semiconductor device;

[0054] Figure 2 This is a schematic diagram of another embodiment of a visible light communication semiconductor device;

[0055] Figure 3 This is a schematic diagram of another embodiment of a visible light communication semiconductor device;

[0056] Figure 4 This is a cross-sectional view of the first semiconductor layer;

[0057] Figure 5 This is a top view schematic diagram of an embodiment of a lighting chip and a communication chip in a visible light communication semiconductor device;

[0058] Figure 6 This is a schematic diagram of one embodiment of the extensional structure;

[0059] Figure 7-15 This is a schematic diagram illustrating the fabrication steps of an embodiment of a visible light communication semiconductor device.

[0060] Figure label:

[0061] Substrate 100; Growth substrate 200; First transfer substrate 300; Communication chip 400; Illumination chip 500; First semiconductor layer 1; Illumination region 11; Communication region 12; Second semiconductor layer 2; Third semiconductor layer 3; First active layer 4; Second active layer 5; First electron blocking layer 6; Second electron blocking layer 7; Nucleation layer 8; Buffer layer 9; First electrode 10; Second electrode 20; Third electrode 30; Fourth electrode 40; Passivation layer 60; First bonding layer 70; Second bonding layer 80; Ion implantation region 90. Detailed Implementation

[0062] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0063] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0064] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included. In this application, unless specifically stated otherwise, all numerical ranges include endpoint values.

[0065] To address the problems mentioned in the background art, this application provides a visible light communication semiconductor device, its fabrication method, and its epitaxial structure.

[0066] like Figure 1 As shown, the visible light communication semiconductor device includes a substrate 100, an illumination chip 500 disposed on one side surface of the substrate 100, and at least one communication chip 400. The illumination chip 500 and the communication chip 400 share a first semiconductor layer 1, which is divided into an illumination region 11 and a communication region 12 that are insulated from each other.

[0067] The lighting chip 500 includes a second semiconductor layer 2, a first active layer 4, and an lighting region 11. The second semiconductor layer 2 and the first active layer 4 are located in the lighting region 11, and the first active layer 4 is located between the second semiconductor layer 2 and the lighting region 11. Each communication chip 400 includes a third semiconductor layer 3, a second active layer 5, and a communication region 12. The third semiconductor layer 3 and the second active layer 5 are located in the communication region 12, and the second active layer 5 is located between the third semiconductor layer 3 and the communication region 12. The area of ​​the second active layer 5 is smaller than the area of ​​the first active layer 4, and the first active layer 4 and the second active layer 5 are located on opposite sides of the first semiconductor layer 1. The second semiconductor layer 2 and the third semiconductor layer 3 have the same doping type, while the first semiconductor layer 1 and the second semiconductor layer 2 have opposite doping types. Specifically, when the second semiconductor layer 2 and the third semiconductor layer 3 are P-type semiconductor layers, the first semiconductor layer 1 is an N-type semiconductor layer; when the second semiconductor layer 2 and the third semiconductor layer 3 are N-type semiconductor layers, the first semiconductor layer 1 is a P-type semiconductor layer. In the embodiments of this application, the second semiconductor layer 2 and the third semiconductor layer 3 are P-type semiconductor layers and the first semiconductor layer 1 is an N-type semiconductor layer is used as an example for illustration. The P-type semiconductor layer includes, but is not limited to, P-type GaN, and the N-type semiconductor layer includes, but is not limited to, N-type GaN. The P-type semiconductor layer and the N-type semiconductor layer can be a single-layer structure or a multi-layer structure, which can be adjusted according to the actual light output requirements.

[0068] Among them, such as Figure 1-3 As shown, in the embodiments of this application, the first active layer 4 and the second semiconductor layer 2 are located on the side of the first semiconductor layer 1 facing the substrate 100, and the second active layer 5 and the third semiconductor layer 3 are located on the side of the first semiconductor layer 1 away from the substrate 100. That is, the communication chip 400 is located above the lighting chip 500.

[0069] It should be understood that in other embodiments, the growth order of the film layers can be adjusted, or bonding flipping can be used, so that the first active layer 4 and the second semiconductor layer 2 are located on the side of the first semiconductor layer 1 away from the substrate 100, and the second active layer 5 and the third semiconductor layer 3 are located on the side of the first semiconductor layer 1 facing the substrate 100; that is, the communication chip 400 is located below the lighting chip 500.

[0070] Optionally, such as Figure 1-3As shown, the visible light communication semiconductor device further includes a first electron blocking layer 6 and / or a second electron blocking layer 7 to reduce electron leakage. The accompanying drawings of this application illustrate a visible light communication semiconductor device including a first electron blocking layer 6 and a second electron blocking layer 7. The first electron blocking layer 6 is disposed between the first active layer 4 and the second semiconductor layer 2. The second electron blocking layer 7 is disposed between the second active layer 5 and the third semiconductor layer 3. The materials of the first electron blocking layer 6 and the second electron blocking layer 7 can be one of the following: monolayer AlGaN, monolayer InAlGaN, monolayer AlN, a combination of AlGaN thin films with different compositional gradients, a combination of InAlGaN thin films with different compositional gradients, an AlGaN / AlN superlattice structure, or an InAlGaN / AlN superlattice structure.

[0071] Further optionally, the first active layer 4 includes, but is not limited to, an InGaN / GaN multi-quantum-well layer, and the second active layer 5 includes, but is not limited to, an InGaN quantum dot layer or a superlattice structure including InGaN quantum dots and GaN quantum dots. Setting the second active layer 5 as a quantum dot structure helps the communication chip 400 achieve higher modulation bandwidth.

[0072] The specific areas of the first active layer 4 and the second active layer 5 can be reasonably set according to the overall size of the visible light communication semiconductor device and the modulation bandwidth requirements, and this application does not impose any limitations. For example, the ratio of the first active layer to the second active layer can range from 20 to 2000, including the endpoint values.

[0073] This visible light communication semiconductor device integrates an illumination chip 500 and at least one communication chip 400, enabling a single chip to simultaneously perform both illumination and communication functions. This reduces the number of devices required, lowers module complexity, and reduces losses. The illumination chip 500 and communication chip 400 share a first semiconductor layer 1, while the remaining film layers are independently configured. This reduces the device thickness to some extent and allows for the selection of more suitable active layer materials based on the different performance requirements of the illumination chip 500 and communication chip 400. Furthermore, the first semiconductor layer 1 is divided into mutually insulated illumination regions 11 and communication regions 12, preventing mutual interference between the illumination chip 500 and communication chip 400. The area of ​​the second active layer 5 is smaller than that of the first active layer 4, increasing the adjustment bandwidth of the communication chip 400 to achieve high-frequency communication. The first active layer 4 and the second active layer 5 are located on opposite sides of the first semiconductor layer 1. In the actual fabrication process, various wide bandgap semiconductor materials can be integrated by epitaxy, such as epitaxially growing the second semiconductor layer 2, the first active layer 4, the first semiconductor layer 1, the second active layer 5 and the third semiconductor layer 3 in sequence to simplify the material preparation process.

[0074] Based on the above embodiments, in a preferred embodiment, the communication chip 400 includes a plurality of chips, and each communication chip 400 is disposed on the outside of the lighting chip 500.

[0075] Specifically, lighting chip 500, such as Figure 5 The illumination chip 500 has a left side wall, a right side wall, a front side wall, and a rear side wall. The communication chip 400 can be located outside any one of the left, right, front, and rear side walls of the illumination chip 500. The communication chip 400 can be located outside any two of the left, right, front, and rear side walls of the illumination chip 500. The communication chip 400 can be located outside any three of the left, right, front, and rear side walls of the illumination chip 500. The communication chip 400 can be located outside the left, right, front, and rear side walls of the illumination chip 500, meaning the communication chip 400 is arranged around the illumination chip 500; for example, an array of communication chips 400 is arranged around the illumination chip 500. Figure 5 The diagram illustrates a configuration where a communication chip 400 array surrounds a lighting chip 500, wherein the communication chip 400 is... Figure 5 The black shadow area in the middle.

[0076] Figure 5 The diagram only uses a rectangle as the top view of the lighting chip and the communication chip. In other embodiments, the top view of the lighting chip and the communication chip can also be other shapes, such as circles, polygons, etc.

[0077] In this embodiment, the communication chip 400 is preferably arranged in an array around the lighting chip 500. This arrangement ensures that while achieving high-frequency communication, the overall brightness of the chip is relatively uniform, thus balancing both lighting and communication.

[0078] Based on any of the above embodiments, in a preferred embodiment, such as Figure 1-3 As shown, the visible light communication semiconductor device also includes a first electrode 10, a second electrode 20, a third electrode 30, and a fourth electrode 40. The substrate 100 is a conductive substrate 100. Specifically, a second bonding layer 80 is provided on the surface of the substrate 100 facing the lighting chip 500 and the communication chip 400, and the second bonding layer 80 is made of a conductive material.

[0079] The first active layer 4 and the second semiconductor layer 2 are located on the side of the first semiconductor layer 1 facing the substrate 100. The second active layer 5 and the third semiconductor layer 3 are located on the side of the first semiconductor layer 1 away from the substrate 100. The first electrode 10 is located between the substrate 100 and the second semiconductor layer 2 and is electrically connected to the substrate 100 and the second semiconductor layer 2. Specifically, the first electrode 10 is electrically connected to the substrate 100 and the second semiconductor layer 2 through the second bonding layer 80. The second electrode 20 is located on the illumination region 11 and is electrically connected to the illumination region 11. The third electrode 30 is located on the third semiconductor layer 3 and is electrically connected to the third semiconductor layer 3. The fourth electrode 40 is located on the communication region 12 and is electrically connected to the communication region 12. When multiple communication chips 400 are provided, each communication chip 400 can be provided with an independent third electrode 30 and a fourth electrode 40; or each communication chip 400 has an independent third electrode 30 and shares a fourth electrode 40, which can be configured according to requirements.

[0080] The lighting chip 500 is controlled by the first electrode 10 and the second electrode 20, while the communication chip 400 is controlled by the second electrode 20 and the third electrode 30. This allows the lighting chip 500 and the communication chip 400 to be driven independently without affecting each other, ensuring their functions are independent and maximizing their performance. This better enables high-frequency communication and lighting.

[0081] It should be understood that in this embodiment, the first electrode 10 and the second electrode 20 are located on opposite sides of the lighting chip 500. In some embodiments, the first electrode 10 and the second electrode 20 may also be located on the same side of the lighting chip 500, in which case the substrate 100 and the second bonding layer 80 may not be conductive; for example, the first electrode 10 and the second electrode 20 may be located on the side of the lighting chip 500 away from the substrate 100, that is, on the side of the lighting region 11 away from the substrate 100.

[0082] Based on any of the above embodiments, in a preferred embodiment, a first insulating region is obtained by ion implantation into the first semiconductor layer 1; the first insulating region surrounds the lighting region 11. This configuration divides the first semiconductor layer 1 into a mutually insulated lighting region 11 and a communication region 12. Furthermore, the ion implantation process is simple and avoids etching damage.

[0083] Figure 4 This is a cross-sectional view of the first semiconductor layer 1. The ion implantation region 90 surrounding the illumination region 11 is the first insulating region. The communication region 12 surrounds the ion implantation region 90 and the illumination region 11. Figure 4 The communication region 12 shown is annular. When multiple communication chips 400 are provided, each communication chip 400 shares the communication region 12, and the remaining film layers of each communication chip 400 are independent of each other. It should be understood that in some other embodiments, in Figure 4 Based on the communication region 12, it can be further divided into multiple independent regions by ion implantation. The remaining film layers of the communication chip 400 are set on each independent region, so that the communication region 12 and the remaining film layers of each communication chip 400 are independent of each other.

[0084] Based on any of the above embodiments, in a preferred embodiment, such as Figure 2 As shown, a second insulating region is obtained by ion implantation of the second active layer 5 and the third semiconductor layer 3 of each communication chip 400 on the side adjacent to the lighting chip 500. The establishment of the second insulating region provides better insulation and isolation between the communication chip 400 and the lighting chip 500, preventing electrical conduction between them during wiring and thus avoiding device malfunction. When the visible light communication semiconductor device also includes a second electron blocking layer 7, the second insulating region is obtained by ion implantation of the second active layer 5, the second electron blocking layer 7, and the third semiconductor layer 3 of each communication chip 400 on the side adjacent to the lighting chip 500. Figure 2 The ion implantation region 90 shown starts at the surface of the third semiconductor layer 3 away from the substrate 100 and ends at the surface of the first semiconductor layer 1 facing the substrate 100. In practice, the depth of ion implantation can be controlled. Figure 2 The portion of the ion implantation region 90 located in the first semiconductor layer 1 forms a first insulating region, and the portion of the ion implantation region 90 located in the second active layer 5, the second electron blocking layer 7 and the third semiconductor layer 3 forms a second insulating region.

[0085] In some embodiments, the implantation depth of the ion implantation region 90 can exceed the first semiconductor layer 1. This configuration ensures that the communication region 12 and the illumination region 11 of the first semiconductor layer 1 are completely isolated, preventing the communication region 12 and the illumination region 11 from affecting the performance of the communication chip 400 and the illumination chip 500. For example, the ion implantation region 90 can be configured as follows: Figure 3 The diagram shows the starting point of the third semiconductor layer 3 away from the surface of the substrate 100 and the ending point of the second bonding layer 80 towards the surface of the substrate 100.

[0086] Based on any of the above embodiments, in a preferred embodiment, the visible light communication semiconductor device further includes a passivation layer 60; the passivation layer 60 is located on the side of the communication region 12 opposite to the second active layer 5, and surrounds the first active layer 4 and the second semiconductor layer 2. The communication region 12 is located on the surface of the passivation layer 60 opposite to the substrate 100.

[0087] Specifically, such as Figure 1-3As shown, the passivation layer 60 is located between the substrate 100 and the communication region 12, and fills the gap between the substrate 100 and the communication region 12. The passivation layer 60 below the communication region 12 causes the projections of the lighting chip 500 and the communication chip 400 on the surface of the substrate 100 to be staggered, so as to prevent the light emitted by the lighting chip 500 from affecting the communication of the communication chip 400.

[0088] This application also provides an epitaxial structure that can be used to fabricate the aforementioned visible light communication semiconductor device.

[0089] like Figure 6 As shown, the epitaxial structure includes a growth substrate 200, and a second semiconductor layer 2, a first active layer 4, a first semiconductor layer 1, a second active layer 5, and a third semiconductor layer 3 are sequentially stacked on the growth substrate 200 along a direction away from the growth substrate 200. The second semiconductor layer 2 and the third semiconductor layer 3 have the same doping type, while the first semiconductor layer 1 and the second semiconductor layer 2 have opposite doping types. The first active layer 4 is an InGaN / GaN multiple quantum well layer, and the second active layer 5 is an InGaN quantum dot layer or a superlattice structure layer including InGaN quantum dots and GaN quantum dots. This epitaxial structure consists of a second semiconductor layer 2, a first active layer 4, a second semiconductor layer 2, a second active layer 5, and a third semiconductor layer 3 sequentially stacked on a growth substrate 200. It integrates multiple wide-bandgap semiconductor materials using epitaxy, simplifying the material fabrication process. During the growth of the epitaxial structure, the film layers required for both the communication chip 400 and the lighting chip 500 are grown simultaneously. Subsequent epitaxial processes such as bonding, photolithography, and etching can then be combined to obtain a chip integrating the communication chip 400 and the lighting chip 500, eliminating the need for multiple furnace cycles and saving energy and reducing emissions. Furthermore, the communication chip and lighting chip can flexibly select appropriate materials to achieve superior performance.

[0090] Optionally, the thickness of the first active layer 4 is 10nm-200nm, including the endpoint values. The thickness of the second active layer 5 is 5nm-100nm, including the endpoint values.

[0091] Specifically, when the second semiconductor layer 2 and the third semiconductor layer 3 are P-type semiconductor layers, the first semiconductor layer 1 is an N-type semiconductor layer; when the second semiconductor layer 2 and the third semiconductor layer 3 are N-type semiconductor layers, the first semiconductor layer 1 is a P-type semiconductor layer. In the embodiments of this application, the second semiconductor layer 2 and the third semiconductor layer 3 are P-type semiconductor layers and the first semiconductor layer 1 is an N-type semiconductor layer as an example for illustration. The P-type semiconductor layer includes, but is not limited to, P-type GaN, and the N-type semiconductor layer includes, but is not limited to, N-type GaN. The P-type semiconductor layer and the N-type semiconductor layer can be a single-layer structure or a multi-layer structure, which can be adjusted according to the actual light output requirements.

[0092] The thickness of N-type semiconductors ranges from 0.5 μm to 4 μm, including endpoints. For example, the thickness of an N-type semiconductor layer is 0.5 μm, 2 μm, or 4 μm. The thickness of P-type semiconductors ranges from 20 nm to 500 nm, including endpoints. For example, the thickness of a P-type semiconductor layer is 20 nm, 50 nm, 100 nm, 200 nm, or 300 nm.

[0093] Optionally, the material of the growth substrate 200 includes, but is not limited to, sapphire, silicon, silicon carbide, etc.

[0094] Optionally, the epitaxial structure further includes a nucleation layer 8 and a buffer layer 9 located between the growth substrate 200 and the second semiconductor layer 2; the buffer layer 9 is closer to the second semiconductor layer 2 than the nucleation layer 8. The nucleation layer 8 and the buffer layer 9 can be at least one of AlN, GaN, AlGaN, InAlGaN, InAlN, and AlN / GaN superlattice structures. Preferably, the thickness of the buffer layer 9 is 0.02 μm to 3 μm, including the endpoint values; the thickness of the nucleation layer 8 is 5 nm to 500 nm, including the endpoint values.

[0095] Optionally, the epitaxial structure further includes a first electron blocking layer 6 and / or a second electron blocking layer 7. The first electron blocking layer 6 is disposed between the first active layer 4 and the second semiconductor layer 2. The second electron blocking layer 7 is disposed between the second active layer 5 and the third semiconductor layer 3. The materials of the first electron blocking layer 6 and the second electron blocking layer 7 can be one of monolayer AlGaN, monolayer InAlGaN, monolayer AlN, a combination of AlGaN thin films with different compositional gradients, a combination of InAlGaN thin films with different compositional gradients, an AlGaN / AlN superlattice structure, and an InAlGaN / AlN superlattice structure.

[0096] This application also provides a method for fabricating a visible light communication semiconductor device. This method can be used to fabricate the aforementioned visible light communication semiconductor device, and the equipment used can be an MOCVD (Metal-Organic Chemical Vapor Deposition) device; specifically, it includes the following steps:

[0097] S01: A growth substrate 200 is provided. The material of the growth substrate 200 includes, but is not limited to, sapphire, silicon, silicon carbide, etc. In this step, hydrogen gas can be introduced at a high temperature of 900℃-1150℃ for 5 minutes for hydrogenation treatment to remove impurities, scratches, particles, etc. from the surface of the growth substrate 200.

[0098] S02: A second semiconductor layer 2, a first active layer 4, a first semiconductor layer 1, a second active layer 5, and a third semiconductor layer 3 are sequentially grown on one side of the growth substrate 200. The second semiconductor layer 2 and the third semiconductor layer 3 have the same doping type, while the first semiconductor layer 1 and the second semiconductor layer 2 have opposite doping types. Specifically, when the second semiconductor layer 2 and the third semiconductor layer 3 are P-type semiconductor layers, the first semiconductor layer 1 is an N-type semiconductor layer; when the second semiconductor layer 2 and the third semiconductor layer 3 are N-type semiconductor layers, the first semiconductor layer 1 is a P-type semiconductor layer. In the embodiments of this application, the second semiconductor layer 2 and the third semiconductor layer 3 are P-type semiconductor layers, and the first semiconductor layer 1 is an N-type semiconductor layer, as an example. The P-type semiconductor layer includes, but is not limited to, P-type GaN, and the N-type semiconductor layer includes, but is not limited to, N-type GaN. The P-type semiconductor layer and the N-type semiconductor layer can be a single-layer structure or a multi-layer structure, which can be adjusted according to the actual light output requirements.

[0099] The growth temperature of the second semiconductor layer 2 is 900℃-1000℃, for example 960℃. The P-type doping source is Cp2Mg, and the doping flux is 1800sccm-2100sccm, for example 2000sccm.

[0100] The InGaN layer 4 has a thickness ranging from 2nm to 6nm, for example, 3nm; and a growth temperature of 700℃ to 800℃, for example, 750℃. The GaN layer has a thickness ranging from 7nm to 12nm, for example, 10nm; and a growth temperature of 800℃ to 900℃, for example, 850℃. The superlattice has a growth cycle of 7-13, for example, alternating growth of 10 cycles.

[0101] The growth temperature of the first semiconductor layer 1 is 980℃-1150℃, for example 1050℃; the thickness ranges from 0.5μm to 4μm, for example 2μm. The N-type dopant is SiH4.

[0102] The growth temperature of the second active layer 5 is 750℃-850℃, for example 800℃; taking InGaN / GaN superlattice quantum dots as an example, the alternating growth cycle is 3-8, for example 5 cycles.

[0103] The growth temperature of the third semiconductor layer 3 is 900℃-1000℃, for example 950℃. The P-type doping source is Cp2Mg, and the doping flux is 1800sccm-2100sccm, for example 2000sccm.

[0104] Optionally, before growing the second semiconductor layer 2, a nucleation layer 8 is first grown on the growth substrate 200, a buffer layer 9 is grown on the nucleation layer 8, and then the second semiconductor layer 2 and subsequent film layers are grown on the buffer layer 9. The growth temperature of the nucleation layer 8 is 750℃-920℃, including the endpoint values; the growth temperature of the buffer layer 9 is 1010℃-1100℃, including the endpoint values. Preferably, the thickness of the buffer layer 9 is 0.02 μm-3 μm, including the endpoint values; and the thickness of the nucleation layer 8 is 5 nm-500 nm, including the endpoint values.

[0105] Optionally, after growing the second semiconductor layer 2, a first electron blocking layer 6 is grown on the surface of the second semiconductor layer 2 facing away from the growth substrate 200, and then a first active layer 4 and subsequent film layers are grown on the first electron blocking layer 6. And / or after growing the second active layer 5, a second electron blocking layer 7 is grown on the surface of the second active layer 5 facing away from the growth substrate 200, and then a third semiconductor layer 3 is grown on the second electron blocking layer 7.

[0106] Preferably, the materials of the first electron blocking layer 6 and the second electron blocking layer 7 can be one of monolayer AlGaN, monolayer InAlGaN, monolayer AlN, a combination of AlGaN films with different compositional gradients, a combination of InAlGaN films with different compositional gradients, an AlGaN / AlN superlattice structure, or an InAlGaN / AlN superlattice structure. The first electron blocking layer 6 and the second electron blocking layer 7 are preferably 8nm-20nm thick, for example, the thickness of the first electron blocking layer 6 is 10nm, and the thickness of the second electron blocking layer 7 is 15nm. The growth temperature of the first electron blocking layer 6 can be 950℃-1100℃, for example, 1050℃; the growth temperature of the second electron blocking layer 7 can be 900℃-1000℃, for example, 950℃. The above-mentioned epitaxial structure can be obtained through steps S01 and S02. After the epitaxial structure is fabricated, it can be cooled to 700℃-800℃, for example, 750℃ and held at that temperature for three minutes, and then cooled in the furnace. The subsequent steps are shown in the accompanying drawings. Figure 6 The steps are explained using the epitaxial structure shown as an example.

[0107] S03: As Figure 6 , 7 As shown, a first transfer substrate 300 is bonded to the side of the third semiconductor layer 3 facing away from the growth substrate 200, and the growth substrate 200 is removed to expose the second semiconductor layer 2. Specifically, a bonding layer is formed on the surface of the third semiconductor layer 3 facing away from the growth substrate 200 and the surface of the first transfer substrate 300, respectively, and then the two bonding layers are bonded together to form a first bonding layer 70. The growth substrate 200 is peeled off using laser lift-off technology. When the epitaxial structure has a nucleation layer 8 and a buffer layer 9, the nucleation layer 8 and the buffer layer 9 are removed to expose the second semiconductor layer 2.

[0108] S05: As Figure 8 As shown, the film layer on the first region of the first semiconductor layer 1 facing away from the first transfer substrate 300 is removed by photolithography and etching processes. For example, dry etching can be used, and this application is not limited to this. It should be understood that when the first electron blocking layer 6 is not provided, the film layer on the first region of the first semiconductor layer 1 facing away from the first transfer substrate 300 includes the first active layer 4 and the second semiconductor layer 2. When the first electron blocking layer 6 is provided, the film layer on the first region of the first semiconductor layer 1 facing away from the first transfer substrate 300 includes the first active layer 4, the first electron blocking layer 6, and the second semiconductor layer 2.

[0109] S06: As Figure 9 As shown, a first electrode 10 is fabricated on the surface of the second semiconductor layer 2 facing away from the first transfer substrate 300. Annealing can be performed after the first electrode 10 is fabricated to ensure electrode contact quality. The first electrode 10 can completely cover the surface of the second semiconductor layer 2 facing away from the first transfer substrate 300, and a reflective material is selected to reflect the light from the first active layer 4 to the illumination area 11 side for emission.

[0110] S07: As Figure 10 As shown, a passivation layer 60 is filled in the first region. The side of the passivation layer 60 facing away from the first semiconductor layer 1 is on the same horizontal plane as the first electrode 10. By filling the first region with the passivation layer, the stress is more uniform during subsequent bonding of the substrate 100, and the overall stability and reliability of the chip are increased.

[0111] S08: As Figure 11 As shown, a conductive substrate 100 is bonded to the passivation layer 60 and the side of the first electrode 10 facing away from the first transfer substrate 300, and the first transfer substrate 300 is removed to expose the third semiconductor layer 3; specifically, the first bonding layer 70 also needs to be removed at the same time. The first electrode 10 is electrically connected to the substrate 100 and the second semiconductor layer 2. The material of the substrate 100 includes, but is not limited to, a metal Mo substrate, a Cu substrate, a CuW substrate, a conductive Si substrate, etc. Specifically, when bonding the substrate 100, a metal bonding layer is formed on the side of the first electrode 10 facing away from the passivation layer 60 and the first transfer substrate 300, and a metal bonding layer is also formed on one side surface of the substrate 100. Then, the two metal bonding layers are bonded to form a second bonding layer 80, and the first electrode 10 is electrically connected to the substrate 100 and the second semiconductor layer 2 through the second bonding layer 80.

[0112] S09: By photolithography and etching processes, at least the film layer on the side of the second region of the first semiconductor layer 1 facing away from the substrate 100 is removed, and the remaining film layer is divided into at least one independent chip region.

[0113] The first semiconductor layer 1 is divided into an insulated lighting region 11 and a communication region 12, with the first region corresponding to the communication region 12 and the second region corresponding to the lighting region 11, forming a lighting chip 500 and at least one communication chip 400. The lighting chip 500 and the communication chip 400 share the first semiconductor layer 1; the lighting chip 500 includes a second semiconductor layer 2, a first active layer 4, and the lighting region 11, and each communication chip 400 includes a third semiconductor layer 3, a second active layer 5, and the communication region 12; the area of ​​the second active layer 5 is smaller than the area of ​​the first active layer 4.

[0114] It should be understood that when the second electron blocking layer 7 is not provided, the film layer on the side of the second region of the first semiconductor layer 1 facing away from the substrate 100 includes the second active layer 5 and the third semiconductor layer 3; the film layer in the remaining region includes the second active layer 5 and the third semiconductor layer 3. When the first electron blocking layer 6 is provided, the film layer on the side of the second region of the first semiconductor layer 1 facing away from the substrate 100 includes the second active layer 5, the second electron blocking layer 7, and the third semiconductor layer 3; the film layer in the remaining region includes the second active layer 5, the second electron blocking layer 7, and the third semiconductor layer 3.

[0115] In this step, the order of operations at least removing the film layer on the side of the second region of the first semiconductor layer 1 away from the substrate 100 and dividing the first semiconductor layer 1 into an illumination region 11 and a communication region 12 that are insulated from each other can be selected according to specific settings, and this application does not impose any restrictions.

[0116] S10: Fabricate a second electrode 20, which is located on and electrically connected to the lighting area 11. Fabricate a third electrode 30, which is located on and electrically connected to the third semiconductor layer 3. Fabricate a fourth electrode 40, which is located on and electrically connected to the communication area 12. These three electrodes can be fabricated separately or together.

[0117] Furthermore, in the step of removing at least the film layer on the side opposite to the substrate 100 on the second region of the first semiconductor layer 1 through photolithography and etching processes, and dividing the remaining film layer into at least one independent chip region (i.e., step S09): the remaining film layer is divided into multiple independent chip regions, and each chip region and the communication region 12 form multiple communication chips 400; each communication chip 400 is disposed on the outside of the lighting chip 500.

[0118] That is, when removing the film layer on the side of the first semiconductor layer 1 facing away from the substrate 100 in the second region, the remaining film layer can be partially etched simultaneously or subsequently to divide it into at least one independent chip region, exposing the communication region, so that the film layers of each communication chip 400 on the communication region 12 are independent of each other. That is, the second active layer 5 and the third semiconductor layer 3 of each communication chip 400 are independent of each other, or the second active layer 5, the second electron blocking layer 7 and the third semiconductor layer 3 are independent of each other.

[0119] Furthermore, the first semiconductor layer 1 is ion implanted using an ion implantation process to obtain a first insulating region; the first insulating region surrounds the lighting region 11, such that the first semiconductor layer 1 is divided into a lighting region 11 and a communication region 12 that are insulated from each other. Figure 4 This is a cross-sectional view of the first semiconductor layer 1. The ion implantation region 90 surrounding the illumination region 11 is the first insulating region. The communication region 12 surrounds the ion implantation region 90 and the illumination region 11. Figure 4 The communication region 12 shown is annular. When multiple communication chips 400 are provided, each communication chip 400 shares the communication region 12, and the remaining film layers of each communication chip 400 are independent of each other. It should be understood that in some other embodiments, in Figure 4 Based on the communication region 12, it can be further divided into multiple independent regions by ion implantation, so that the communication region 12 and the other film layers of each communication chip 400 are independent of each other.

[0120] Furthermore, ion implantation is performed on the side of the second active layer 5 and the third semiconductor layer 3 of each communication chip 400 that approaches the lighting chip 500 to obtain a second insulating region. When the visible light communication semiconductor device also includes a second electron blocking layer 7, the second insulating region is obtained by ion implantation on the side of the second active layer 5, the second electron blocking layer 7, and the third semiconductor layer 3 of each communication chip 400 that approaches the lighting chip 500.

[0121] Wherein, when the visible light communication semiconductor device has a first insulating region but no second insulating region ( Figure 1 Example), such as Figure 12 , 13 As shown, after etching "at least the film layer on the side opposite to the substrate 100 on the second region of the first semiconductor layer 1 and dividing the remaining film layer into at least one independent module", an ion implantation process can be performed on the exposed first semiconductor layer 1 to obtain the ion implantation region 90 to obtain the first insulating region.

[0122] When a visible light optical communication semiconductor device has a first insulating region and a second insulating region ( Figure 2 Or 3 examples), such as Figure 14 , 15An ion implantation process can be performed before etching the second active layer 5 and the third semiconductor layer 3 to "at least remove the film layer on the side of the first semiconductor layer 1 facing away from the substrate 100 in the second region and divide the remaining film layer into at least one independent module". The depth of ion implantation is controlled so that the depth of the ion implantation region 90 reaches the expected position. Then, the film layer on the second region of the first semiconductor layer 1 facing away from the substrate 100 is etched away.

[0123] For example, in some embodiments, such as Figure 2 As shown, the depth of ion implantation is controlled so that the ion implantation region 90 starts at the surface of the third semiconductor layer 3 away from the substrate 100 and ends at the surface of the first semiconductor layer 1 facing the substrate 100, thus obtaining a first insulating region and a second insulating region.

[0124] For example, in some embodiments, the implantation depth of the ion implantation region 90 can exceed that of the first semiconductor layer 1. This configuration ensures that the communication region 12 and the illumination region 11 of the first semiconductor layer 1 are completely isolated, preventing the communication region 12 and the illumination region 11 from being connected and affecting the performance of the communication chip 400 and the illumination chip 500. For example, the ion implantation region 90 can be set as follows: Figure 3 The diagram shows the starting point of the third semiconductor layer 3 away from the surface of the substrate 100 and the ending point of the passivation layer 60 towards the surface of the substrate 100.

[0125] Furthermore, the ion implantation process includes, but is not limited to, implanting N ions; any ion capable of achieving insulation can be used.

[0126] The method for fabricating this visible light communication semiconductor device can be used to fabricate the aforementioned visible light communication semiconductor device, and therefore has the beneficial effects of the aforementioned visible light communication semiconductor device, which will not be elaborated further here.

[0127] For the three aspects of visible light communication semiconductor devices, epitaxial structures, and fabrication methods, refer to each other for similar or identical parts.

[0128] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0129] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0130] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A visible light communication semiconductor device, characterized in that, include substrate; An illumination chip and at least one communication chip are disposed on one side surface of the substrate; the illumination chip and the communication chip share a first semiconductor layer, which is divided into an illumination region and a communication region that are insulated from each other; The lighting chip includes a second semiconductor layer, a first active layer, and the lighting area; The second semiconductor layer and the first active layer are located in the lighting region, and the first active layer is located between the second semiconductor layer and the lighting region; Each of the communication chips includes a third semiconductor layer, a second active layer, and the communication region; the third semiconductor layer and the second active layer are located in the communication region, and the second active layer is located between the third semiconductor layer and the communication region; The area of ​​the second active layer is smaller than that of the first active layer, and the first and second active layers are located on opposite sides of the first semiconductor layer; the second and third semiconductor layers have the same doping type, while the first and second semiconductor layers have opposite doping types.

2. The visible light communication semiconductor device as described in claim 1, characterized in that, The communication chip comprises multiple components; Each of the communication chips is disposed on the outside of the lighting chip.

3. A visible light communication semiconductor device as described in claim 1 or 2, characterized in that, It also includes a first electrode, a second electrode, a third electrode, and a fourth electrode; The substrate is a conductive substrate; The first active layer and the second semiconductor layer are located on the side of the first semiconductor layer facing the substrate; The second active layer and the third semiconductor layer are located on the side of the first semiconductor layer that is away from the substrate; The first electrode is located between the substrate and the second semiconductor layer, and is electrically connected to the substrate and the second semiconductor layer; The second electrode is located on the lighting area and is electrically connected to the lighting area; The third electrode is located on the third semiconductor layer and is electrically connected to the third semiconductor layer; The fourth electrode is located on the communication area and is electrically connected to the communication area.

4. The visible light communication semiconductor device as described in claim 1, characterized in that, A first insulating region is obtained by ion implantation into the first semiconductor layer; the first insulating region surrounds the lighting region.

5. A visible light communication semiconductor device as described in claim 1 or 2, characterized in that, The second insulating region is obtained by ion implantation into the second active layer and the third semiconductor layer of each of the communication chips on the side adjacent to the lighting chip.

6. A visible light communication semiconductor device as described in claim 1, characterized in that, The visible light communication semiconductor device also includes a passivation layer; The passivation layer is located on the side of the communication region away from the second active layer and is disposed around the first active layer and the second semiconductor layer.

7. An epitaxial structure, characterized in that, For use in manufacturing a visible light communication semiconductor device according to any one of claims 1-6; The epitaxial structure includes a growth substrate; A second semiconductor layer, a first active layer, a second active layer, and a third semiconductor layer are sequentially stacked on the growth substrate in a direction away from the growth substrate; the second semiconductor layer and the third semiconductor layer have the same doping type, while the first semiconductor layer and the second semiconductor layer have opposite doping types; The first active layer is an InGaN / GaN multi-quantum-well layer; The second active layer is an InGaN quantum dot layer or a superlattice structure including InGaN quantum dots and GaN quantum dots.

8. A method for fabricating a visible light communication semiconductor device, characterized in that, include: Provide a growth substrate; A second semiconductor layer, a first active layer, a first semiconductor layer, a second active layer, and a third semiconductor layer are sequentially grown on one side of the growth substrate; the second semiconductor layer and the third semiconductor layer have the same doping type, while the first semiconductor layer and the second semiconductor layer have opposite doping types; A first transfer substrate is bonded to the side of the third semiconductor layer opposite to the growth substrate, and the growth substrate is removed to expose the second semiconductor layer. The film layer on the side opposite to the first transfer substrate on the first region of the first semiconductor layer is removed by photolithography and etching processes; A first electrode is fabricated on the surface of the second semiconductor layer that is away from the first transfer substrate; A passivation layer is filled in the first region; A conductive substrate is bonded to the passivation layer and the side of the first electrode opposite to the first transfer substrate, and the first transfer substrate is removed to expose the third semiconductor layer. The first electrode is electrically connected to the substrate and the second semiconductor layer; By using photolithography and etching processes, at least the film layer on the side of the first semiconductor layer facing away from the substrate in the second region is removed, and the remaining film layer is divided into at least one independent chip region. The first semiconductor layer is divided into an illumination region and a communication region that are insulated from each other. The first region corresponds to the communication region, and the second region corresponds to the illumination region, forming an illumination chip and at least one communication chip. The illumination chip and the communication chip share the first semiconductor layer. The illumination chip includes a second semiconductor layer, a first active layer, and the illumination region. Each of the communication chips includes a third semiconductor layer, a second active layer, and the communication region. The area of ​​the second active layer is smaller than the area of ​​the first active layer; A second electrode is fabricated, which is located on the lighting area and electrically connected to the lighting area; A third electrode is fabricated, wherein the third electrode is located on the third semiconductor layer and electrically connected to the third semiconductor layer; A fourth electrode is fabricated, which is located on the communication area and electrically connected to the communication area.

9. The method for fabricating a visible light communication semiconductor device as described in claim 8, characterized in that, In the step of removing at least the film layer on the side opposite to the substrate on the second region of the first semiconductor layer by photolithography and etching processes, and dividing the remaining film layer into at least one independent chip region: the remaining film layer is divided into multiple independent chip regions, and each chip region and the communication region form multiple communication chips; each communication chip is disposed on the outside of the lighting chip.

10. The method for fabricating a visible light communication semiconductor device as described in claim 8, characterized in that, The first semiconductor layer is ion implanted using an ion implantation process to obtain a first insulating region; the first insulating region surrounds the lighting region.

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