Packaging structure, packaging method and electronic equipment

Abstract

The invention provides a packaging structure, a packaging method and electronic equipment. The packaging structure comprises an interposer, an application-specific integrated circuit and a plurality of storage chips. The application-specific integrated circuit and the plurality of memory chips are bonded on the upper surface of the intermediate layer; wherein the plurality of memory chips are positioned on two sides of the application-specific integrated circuit along the first direction. The interposer comprises a plurality of interconnection bridges and connection structures embedded in the interposer; wherein the two ends of the interconnection bridge are connected with the connecting structures, and the connecting structures extend in the vertical direction; a plurality of layers of interconnection bridges are arranged in the intermediate layer along the vertical direction; and the interconnection bridge is respectively connected with the application-specific integrated circuit and the storage chip through a connection structure. The first direction is perpendicular to the vertical direction.

Description

Technical Field

[0001] This application relates to optoelectronic chip packaging technology, and more particularly to a packaging structure, packaging method and electronic device. Background Technology

[0002] In modern electronic systems, with the continuous improvement of chip performance, input / output (I / O) transmission speed has gradually become a key factor affecting overall computing performance. To improve the data transmission efficiency between chips, silicon bridge technology has been introduced to achieve high-speed interconnection between chips. This technology achieves direct connection between the processor and memory chips by embedding conductive paths in the interposer layer, thereby reducing signal latency and improving system performance.

[0003] In existing technologies, silicon bridge structures are typically used to connect application-specific integrated circuits (ASICs) with multiple memory chips, and wiring is achieved through an interposer. However, in this type of packaging structure, the interconnect bridges are mainly arranged in a single plane, making it difficult to fully utilize the internal space of the interposer, resulting in limited integration density. At the same time, since the interconnect bridges are only arranged on a single plane, their layout is limited, and dense wiring is prone to occur in local areas, affecting signal transmission rate. Summary of the Invention

[0004] This application provides a packaging structure, packaging method, and electronic device that can fully utilize the internal space of the interposer layer, increase integration density, and enable more memory chips to transmit data with application-specific integrated circuits.

[0005] The technical solution of this application embodiment is implemented as follows: This application provides a packaging structure comprising: an interposer, an application-specific integrated circuit (ASIC), and a plurality of memory chips; the ASIC and the plurality of memory chips are all bonded to the upper surface of the interposer; wherein the plurality of memory chips are located on both sides of the ASIC along a first direction; the interposer includes: a plurality of interconnect bridges and connection structures embedded in the interposer; wherein both ends of the interconnect bridges are connected to the connection structures, and the connection structures extend along a vertical direction; multiple layers of the interconnect bridges are arranged within the interposer along the vertical direction; the interconnect bridges connect the ASIC and the memory chips respectively through the connection structures; the first direction is perpendicular to the vertical direction.

[0006] In some embodiments of this disclosure, any layer of interconnect bridges is located within the projection range of the interconnect bridges of the adjacent next layer along the vertical direction; the memory chip connected to any layer of interconnect bridges is located on the side of the memory chip connected to the interconnect bridges of the adjacent next layer that is closer to the application-specific integrated circuit.

[0007] In some embodiments of this disclosure, the interconnect bridges in the interposer layer are arranged at intervals along the vertical direction; wherein adjacent interconnect bridges along the vertical direction are separated by an insulating material.

[0008] In some embodiments of this disclosure, the interconnect bridges adjacent to each other along the vertical direction in the intermediary layer are bonded to each other.

[0009] This disclosure also provides a packaging method, the packaging method comprising: forming an interposer layer; the interposer layer comprising: a plurality of interconnect bridges and connection structures embedded in the interposer layer; wherein both ends of the interconnect bridges are connected to the connection structures, and the connection structures extend in a vertical direction; multiple layers of the interconnect bridges are arranged in the interposer layer along the vertical direction; bonding an application-specific integrated circuit (ASIC) and a plurality of memory chips to the upper surface of the interposer layer; wherein the plurality of memory chips are located on both sides of the ASIC along a first direction; the interconnect bridges connect the ASIC and the memory chips respectively through the connection structures; the first direction is perpendicular to the vertical direction.

[0010] In some embodiments of this disclosure, the interposer layer includes: n sub-interposer layers; n is an integer greater than 1; the method of forming the interposer layer includes: providing n first dielectric layers; etching first grooves in the n first dielectric layers respectively; wherein the projection of the first groove in any first dielectric layer along the vertical direction is smaller than the projection of the first groove in the next first dielectric layer along the vertical direction; forming interconnect bridges in the first grooves of the n first dielectric layers respectively; and filling the first grooves of the n first dielectric layers respectively with insulating material covering the interconnect bridges; The n-layer first dielectric layer is etched to form a plurality of first vias extending along the vertical direction; wherein, in the i-th layer of the first dielectric layer, the first via is located at both ends of the interconnect bridge in the i-th layer of the first dielectric layer, and at corresponding positions at both ends of the interconnect bridge in the (i+1)-th to n-th layers of the first dielectric layer; i is an integer greater than or equal to 1 and less than n; in the n-th layer of the first dielectric layer, the first via is located at both ends of the interconnect bridge in the n-th layer of the first dielectric layer; conductive material is deposited in the plurality of first vias to form a plurality of connection structures, thereby forming the n-layer sub-intermediate layer.

[0011] In some embodiments of this disclosure, bonding the application-specific integrated circuit (ASIC) and the plurality of memory chips to the upper surface of the interposer layer includes: bonding the ASIC and the plurality of memory chips to the upper surface of the first sub-interposer layer; bonding the upper surface of the second sub-interposer layer to the lower surface of the first sub-interposer layer; continuing to bond the next sub-interposer layer until the upper surface of the nth sub-interposer layer is bonded to the lower surface of the (n-1)th sub-interposer layer.

[0012] In some embodiments of this disclosure, bonding the application-specific integrated circuit (ASIC) and multiple memory chips to the upper surface of the interposer layer includes: stacking and bonding n layers of the sub-interposer layer along the vertical direction; wherein any interconnect bridge in any layer is located within the projection range of the interconnect bridge in the adjacent next layer along the vertical direction; the connection structure in each sub-interposer layer not connected to the interconnect bridge is bonded to the connection structure in the adjacent sub-interposer layer along the vertical direction; and bonding the ASIC and multiple memory chips to the upper surface of the first sub-interposer layer.

[0013] In some embodiments of this disclosure, the method of forming the interposer further includes: providing a second dielectric layer and a plurality of interconnect bridges; bonding the plurality of interconnect bridges along the vertical direction to form a plurality of interconnect bonding structures; wherein the interconnect bridges of the previous layer are located within the projection range of the interconnect bridges of the next layer along the vertical direction; etching the second dielectric layer to form a plurality of second grooves; bonding the plurality of interconnect bonding structures to the bottom of the plurality of second grooves respectively; filling the plurality of second grooves with an insulating material covering the interconnect bonding structures; etching the insulating material to form a plurality of second vias extending along the vertical direction; wherein the second vias are located at both ends of the plurality of interconnect bridges; depositing conductive material in the second vias to form a plurality of connection structures, thereby forming the interposer.

[0014] This disclosure also provides an electronic device, the electronic device including: a memory and / or a processor; the memory and / or the processor includes the packaging structure described in any of the above embodiments, or the memory and / or the processor is manufactured according to the packaging method described in any of the above embodiments.

[0015] The embodiments of this application have the following beneficial effects: By embedding multi-layer interconnect bridges and connection structures within the interposer layer, the internal space of the interposer layer can be fully utilized, increasing integration density and enabling more memory chips to transmit data with application-specific integrated circuits (ASICs). The two ends of the interconnect bridge are connected to connection structures that extend vertically to connect the ASIC and the memory chip, resulting in shorter signal transmission paths and avoiding crosstalk problems caused by dense interconnects in a single-layer plane. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a schematic diagram of the packaging structure provided in the embodiments of this application; Figure 2 This is a flowchart illustrating the encapsulation method provided in an embodiment of this application; Figure 3 Schematic diagram of the packaging method provided in the embodiments of this application Figure 1 ; Figure 4 Schematic diagram of the packaging method provided in the embodiments of this application Figure 2 ; Figure 5 Schematic diagram of the packaging method provided in the embodiments of this application Figure 3 ; Figure 6 Schematic diagram of the packaging method provided in the embodiments of this application Figure 4 ; Figure 7 Schematic diagram of the packaging method provided in the embodiments of this application Figure 5 ; Figure 8 Schematic diagram of the packaging method provided in the embodiments of this application Figure 6 ; Figure 9 Schematic diagram of the packaging method provided in the embodiments of this application Figure 7 ; Figure 10 Schematic diagram of the packaging method provided in the embodiments of this application Figure 8 ; Figure 11 Schematic diagram of the packaging method provided in the embodiments of this application Figure 9 ; Figure 12 Schematic diagram of the packaging method provided in the embodiments of this application Figure 10 ; Figure 13 Schematic diagram of the packaging method provided in the embodiments of this application Figure 10 one; Figure 14 Schematic diagram of the packaging method provided in the embodiments of this application Figure 10 two; Figure 15Schematic diagram of the packaging method provided in the embodiments of this application Figure 10 three. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate the embodiments of this application, but are not intended to limit the scope of the embodiments of this application.

[0018] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0019] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0020] In this document, when a layer / component is referred to as being "above" another layer / component, the layer / component may be directly above the other layer / component, or there may be an intermediate layer / component between them. Furthermore, in one orientation, a layer / component is "above" another layer / component; when the orientation is reversed, the layer / component may be "below" the other layer / component.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of embodiments of this application.

[0022] This application provides a packaging structure, referring to... Figure 1 and Figure 15 As shown, the package structure includes: an interposer 10, an application-specific integrated circuit 20, and multiple memory chips 30.

[0023] It should be noted that, referring to Figure 1 and Figure 15As shown, the interposer 10 is an intermediate substrate or structural layer used to carry and connect signals between chips, and is typically made of silicon. The interposer 10 possesses good thermal stability, electrical conductivity, and mechanical strength, effectively supporting the integration of high-density interconnect structures. The interposer 10 serves to carry and connect multiple chips, such as the application-specific integrated circuit (ASIC) 20 and the memory chip 30. The ASIC 20 is an integrated circuit custom-designed for specific application needs, featuring high performance and low power consumption. The memory chip 30 is used to cache large amounts of data to support efficient parallel computing tasks. The memory chip 30 can be a high-bandwidth memory chip.

[0024] In this embodiment of the disclosure, reference is made to Figure 1 and Figure 15 As shown, the application-specific integrated circuit 20 and multiple memory chips 30 are bonded to the upper surface of the interposer layer 10; wherein, the multiple memory chips 30 are located on both sides of the application-specific integrated circuit 20 along the first direction X.

[0025] It should be noted that, referring to Figure 1 and Figure 15 As shown, by directly bonding the application-specific integrated circuit 20 and multiple memory chips 30 to the interposer layer 10, the transmission path between the application-specific integrated circuit 20 and the multiple memory chips 30 can be shortened, signal delay can be reduced, and the system response speed can be improved. Distributing the multiple memory chips 30 on both sides of the application-specific integrated circuit 20 can shorten the transmission path, thereby improving the reliability of the system.

[0026] In this embodiment of the disclosure, reference is made to Figure 1 and Figure 15 As shown, the intermediary layer 10 includes: a plurality of interconnect bridges 11 and a connection structure 14 embedded in the intermediary layer 10; wherein, both ends of the interconnect bridges 11 are connected to the connection structure 14, and the connection structure 14 extends along the vertical direction Z; multiple interconnect bridges 11 are arranged in the intermediary layer 10 along the vertical direction Z; the interconnect bridges 11 are connected to the application-specific integrated circuit 20 and the memory chip 30 respectively through the connection structure 14; the first direction X is perpendicular to the vertical direction Z.

[0027] It should be noted that, referring to Figure 1 and Figure 15 As shown, interconnect bridge 11 can be connected to a specific input / output (I / O) interface on application-specific integrated circuit 20 via connection structure 14, and then connected to a corresponding interface on memory chip 30 via another connection structure 14, thereby establishing a low-latency, high-bandwidth data channel. Since interconnect bridge 11 is embedded in interposer layer 10, it does not occupy external space and does not affect the overall structure of the package. Interconnect bridge 11 can typically be fabricated using silicon or organic materials.

[0028] Understandably, referring to Figure 1 and Figure 15 As shown, by embedding multi-layer interconnect bridges 11 and connection structures 14 within the interposer layer 10, the internal space of the interposer layer 10 can be fully utilized, increasing integration density and enabling more memory chips 30 to transmit data with the application-specific integrated circuit 20. The two ends of the interconnect bridges 11 are connected to the connection structures 14, which extend along the vertical direction Z to connect the application-specific integrated circuit 20 and the memory chips 30, resulting in shorter signal transmission paths and avoiding crosstalk problems caused by dense interconnects in a single-layer plane.

[0029] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 15 As shown, any layer of interconnect bridge 11 is located within the projection range of the interconnect bridge 11 of the next adjacent layer along the vertical direction Z; the memory chip 30 connected to any layer of interconnect bridge 11 is located on the side of the memory chip 30 connected to the next adjacent layer of interconnect bridge 11 that is closer to the application-specific integrated circuit 20.

[0030] It should be noted that, referring to Figure 1 and Figure 15 As shown, the projection range refers to the mapping range of the spatial area occupied by an object on another plane in a specific direction (such as the vertical direction Z). That is, the horizontal position of each interconnect bridge 11 will not exceed the horizontal coverage range of the interconnect bridge 11 below it. The memory chip 30 connected to the upper interconnect bridge 11 is always located on the side of the memory chip 30 connected to the lower interconnect bridge 11 closest to the application-specific integrated circuit 20. In other words, the uppermost interconnect bridge 11 connects to the memory chip 30 closest to the application-specific integrated circuit 20, and the interconnect bridges 11 connect to memory chips 30 sequentially until the lowermost interconnect bridge 11 connects to the memory chip 30 furthest from the application-specific integrated circuit 20. This layout ensures that the connection structures 14 on each interconnect bridge 11 are independent of each other in the fabrication process, avoiding mutual interference during the formation of the connection structures 14, and also avoiding signal interference problems caused by misalignment of the interconnect bridges 11. Furthermore, it helps to shorten the data transmission path and reduce signal transmission delay.

[0031] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 15 As shown, in the intermediate layer 10, the multilayer interconnect bridges 11 are arranged at intervals along the vertical direction Z; wherein, the interconnect bridges 11 that are adjacent along the vertical direction Z are separated by an insulating material.

[0032] It should be noted that, referring to Figure 1 and Figure 15As shown, isolating adjacent interconnect bridges 11 with insulating materials can prevent electrical signal crosstalk and improve signal integrity. Commonly used insulating materials include silicon dioxide (SiO2) and silicon nitride (Si3N4), which have high dielectric constants and good thermal stability. Materials such as silicon dioxide and silicon nitride can effectively reduce electromagnetic interference and ensure electrical isolation between layers, thereby improving the stability of the overall system.

[0033] In some embodiments of this disclosure, reference is made to Figure 15 As shown, in the intermediary layer 10, adjacent interconnect bridges 11 along the vertical direction Z are bonded to each other.

[0034] It should be noted that, through a fused bonding process, the interconnect bridges 11 of each layer are bonded to the adjacent interconnect bridges 11 above and below. This increases the interconnect density of the application-specific integrated circuit 20 and the multiple memory chips 30, and enhances the stability of the overall structure. Furthermore, there are no gaps between the interconnect bridges 11 of each layer, thus achieving a more compact chip structure and saving overall footprint.

[0035] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 11 As shown, the interconnect bridge 11 includes a transmission channel 111; the two ends of the transmission channel 111 are respectively in contact with the two connection structures 14, and are used to transmit data between the application-specific integrated circuit 20 and the plurality of memory chips 30.

[0036] Based on the same inventive concept, this disclosure also provides a packaging method, referring to... Figure 2 As shown, the encapsulation method includes forming Figure 2 The specific steps S101-S102 will be explained in conjunction with each step.

[0037] S101: Forming an intermediary layer; the intermediary layer includes: multiple interconnecting bridges and connection structures embedded in the intermediary layer; wherein, both ends of the interconnecting bridges are connected to the connection structures, and the connection structures extend in the vertical direction; multiple interconnecting bridges are arranged in the intermediary layer along the vertical direction.

[0038] In this embodiment of the disclosure, reference is made to Figure 4 , Figure 7 and Figure 8As shown, an interposer layer 10 is formed, and multiple interconnect bridges 11 and connection structures 14 are embedded in the interposer layer 10. Each interconnect bridge 11 is connected to a connection structure 14 at both ends, and the connection structure 14 extends along the vertical direction Z. Multiple interconnect bridges 11 are arranged within the interposer layer 10 along the vertical direction Z. The interposer layer 10 is an intermediate substrate or structural layer used to carry and connect signal transmission between chips, and is typically made of silicon. By embedding multiple interconnect bridges 11 and connection structures 14 within the interposer layer 10, the internal space of the interposer layer 10 can be fully utilized.

[0039] S102: Bonding an application-specific integrated circuit (ASIC) and multiple memory chips onto the upper surface of an interposer; wherein the multiple memory chips are located on both sides of the ASIC along a first direction; an interconnect bridge connects the ASIC and the memory chips respectively through a connection structure.

[0040] In this embodiment of the disclosure, reference is made to Figure 9 and Figure 15 As shown, an application-specific integrated circuit (ASIC) 20 and multiple memory chips 30 are bonded to the upper surface of an interposer layer 10 using a hybrid bonding process. The multiple memory chips 30 are located on both sides of the ASIC 20 along the first direction X, which shortens the transmission path and improves system reliability. An interconnect bridge 11 connects the ASIC 20 and the memory chips 30 via a connection structure 14. The first direction X is perpendicular to the vertical direction Z.

[0041] It should be noted that the packaging method is compatible with existing wafer and chip bonding processes and equipment, requiring no additional equipment and saving process costs.

[0042] Understandably, referring to Figure 9 and Figure 15 As shown, by embedding multi-layer interconnect bridges 11 and connection structures 14 within the interposer layer 10, the internal space of the interposer layer 10 can be fully utilized, increasing integration density and enabling more memory chips 30 to transmit data with the application-specific integrated circuit 20. The two ends of the interconnect bridges 11 are connected to the connection structures 14, which extend along the vertical direction Z to connect the application-specific integrated circuit 20 and the memory chips 30, resulting in shorter signal transmission paths and avoiding crosstalk problems caused by dense interconnects in a single-layer plane.

[0043] In some embodiments of this disclosure, reference is made to Figure 4 , Figure 7 and Figure 8 As shown, the intermediary layer includes: n sub-intermediary layers 13; n is an integer greater than 1. The method for forming the intermediary layer includes steps S201-S206.

[0044] S201: Provides n first dielectric layers.

[0045] In this embodiment of the disclosure, reference is made to Figure 3 and Figure 6 As shown, n first dielectric layers 15 are provided, which are typically made of silicon material.

[0046] S202: First grooves are etched in n first dielectric layers respectively; wherein, the projection of the first groove in any first dielectric layer along the vertical direction is smaller than the projection of the first groove in the next first dielectric layer along the vertical direction.

[0047] In this embodiment of the disclosure, reference is made to Figure 3 and Figure 6 As shown, first grooves 12 are etched into each of the n first dielectric layers 15; wherein the projection of the first groove 12 in any first dielectric layer 15 along the vertical direction Z is smaller than the projection of the first groove 12 in the next first dielectric layer 15 along the vertical direction Z. This layout ensures that the connection structures 14 formed on each interconnect bridge 11 in subsequent processes are independent of each other in the fabrication process, avoiding mutual interference during the formation of the connection structures 14.

[0048] S203: Interconnect bridges are formed in the first groove of the first dielectric layer of the nth layer.

[0049] In this embodiment of the disclosure, reference is made to Figure 4 and Figure 7 As shown, by forming interconnect bridges 11 in the first groove 12 of the first dielectric layer 15 of the nth layer, the space resources of the intermediate layer 10 can be fully utilized, thereby improving the overall wiring density and integration.

[0050] S204: The first groove of the first dielectric layer of the nth layer is filled with insulating material covering the interconnect bridge.

[0051] In this embodiment of the disclosure, combined with Figure 6 and Figure 7 As shown, insulating material covering the interconnect bridges 11 is filled into the first grooves 12 of the n-layer first dielectric layer 15. The insulating material may include silicon dioxide (SiO2) or organosilicon materials. By filling the interconnect bridges 11 with insulating material, signal interference between different interconnect bridges 11 can be effectively isolated, thereby further improving signal quality.

[0052] S205: Etch the n-layer first dielectric layer to form multiple first vias extending in the vertical direction Z. In the i-th first dielectric layer, the first via is located at both ends of the interconnect bridge in the i-th first dielectric layer, and at corresponding positions at both ends of the interconnect bridges from the (i+1)-th to the n-th first dielectric layers; i is an integer greater than or equal to 1 and less than n; in the n-th first dielectric layer, the first via is located at both ends of the interconnect bridge in the n-th first dielectric layer; deposit conductive material within the multiple first vias to form multiple connection structures, thereby forming an n-layer sub-intermediate layer.

[0053] In this embodiment of the disclosure, combined with Figure 6 , Figure 7 and Figure 8 As shown, n first dielectric layers 15 are etched to form multiple first vias extending in the vertical direction Z. In the i-th first dielectric layer 15, the first via is located at both ends of the interconnect bridge 11 of the i-th first dielectric layer 15, and at corresponding positions at both ends of the interconnect bridge 11 of the (i+1)-th to n-th first dielectric layers 15; i is an integer greater than or equal to 1 and less than n. That is, except for the bottom layer, the position of the first via in each first dielectric layer 15 includes not only the two ends of the interconnect bridge 11 in that layer, but also the corresponding positions at both ends of the interconnect bridge 11 in the adjacent next layer. In the n-th first dielectric layer 15, the first via is located at both ends of the interconnect bridge 11 of the n-th first dielectric layer 15. In this way, the connection structures 14 formed on each first dielectric layer 15 are independent of each other in the fabrication process, avoiding mutual interference during the formation of the connection structures 14.

[0054] S206: Conductive material is deposited in multiple first through-holes to form multiple interconnect structures, thereby forming n sub-intermediate layers.

[0055] In this embodiment of the disclosure, reference is made to Figure 8 As shown, conductive material is deposited within multiple first vias to form multiple interconnect structures 14, thereby forming n sub-intermediate layers 13. The conductive material is typically copper (Cu) or other alloys with good conductivity.

[0056] In some embodiments of this disclosure, reference is made to Figure 9 As shown, the application-specific integrated circuit 20 and multiple memory chips 30 are bonded to the upper surface of the interposer layer 10, including steps S301-S303. Each step will be described in conjunction with the steps.

[0057] S301: Bonding an application-specific integrated circuit and multiple memory chips to the upper surface of the first sub-intermediate layer.

[0058] In this embodiment of the disclosure, reference is made to Figure 9As shown, by using a hybrid bonding process, the application-specific integrated circuit 20 and multiple memory chips 30 are bonded to the upper surface of the first sub-intermediate layer 13, which enables electrical connection between the application-specific integrated circuit 20 and multiple memory chips 30 and provides basic support for subsequent layer stacking.

[0059] S302: Bond the upper surface of the second sub-intermediate layer to the lower surface of the first sub-intermediate layer.

[0060] In this embodiment of the disclosure, reference is made to Figure 9 As shown, the upper surface of the second sub-intermediate layer 13 is bonded to the lower surface of the first sub-intermediate layer 13 using a hybrid bonding process.

[0061] S303: Continue bonding the next sub-intermediate layer until the upper surface of the nth sub-intermediate layer is bonded to the lower surface of the (n-1)th sub-intermediate layer.

[0062] In this embodiment of the disclosure, reference is made to Figure 9 As shown, the next sub-intermediate layer 13 is continued to be bonded until the upper surface of the nth sub-intermediate layer 13 is bonded to the lower surface of the (n-1)th sub-intermediate layer 13. By bonding the n sub-intermediate layers 13 one by one, a three-dimensional wiring channel can be constructed. The three-dimensional wiring channel can avoid the crosstalk problem caused by traditional single-layer wiring, and the three-dimensional wiring channel can also improve signal transmission efficiency. Constructing a multi-layer structure by stacking them sequentially not only improves the overall integration of the package, but also enhances the scalability and flexibility of the system.

[0063] In some embodiments of this disclosure, reference is made to Figure 8 and Figure 9 As shown, the application-specific integrated circuit 20 and a plurality of memory chips 30 are bonded to the upper surface of the interposer layer 10, including steps S401-S402. Each step will be described in conjunction with the steps.

[0064] S401: Stack and bond n sub-intermediate layers along the vertical direction Z; wherein any interconnect bridge in any layer is located within the projection range of the interconnect bridge in the adjacent next layer along the vertical direction Z; the connection structures in each sub-intermediate layer that are not connected to the interconnect bridge are bonded to the connection structures in the adjacent sub-intermediate layer along the vertical direction.

[0065] In this embodiment of the disclosure, reference is made to Figure 8 and Figure 9As shown, n sub-intermediate layers 13 are stacked and bonded along the vertical direction Z using a hybrid bonding process. Any interconnect bridge 11 in one layer is located within the projection range of the interconnect bridge 11 in the adjacent next layer along the vertical direction Z. In each sub-intermediate layer 13, the connection structures 14 not connected to the interconnect bridge 11 are bonded along the vertical direction Z to the connection structures 14 in the adjacent sub-intermediate layer 13. This layout ensures that the connection structures 14 on each interconnect bridge 11 are independent of each other during the fabrication process, avoiding mutual interference during the formation of the connection structures 14, and preventing signal interference problems caused by misalignment of the interconnect bridges 11. Simultaneously, it helps to shorten the data transmission path and reduce signal transmission delay.

[0066] S402: The application-specific integrated circuit 20 and multiple memory chips 30 are bonded to the upper surface of the first sub-intermediate layer 13.

[0067] In this embodiment of the disclosure, reference is made to Figure 8 and Figure 9 As shown, the application-specific integrated circuit 20 and multiple memory chips 30 are bonded to the upper surface of the first sub-intermediate layer 13 using a hybrid bonding process. Thus, the interconnect bridge 11 enables electrical connection between the application-specific integrated circuit 20 and the multiple memory chips 30 through the connection structure 14.

[0068] In some embodiments of this disclosure, reference is made to Figures 10 to 14 As shown, the method for forming the intermediate layer 10 further includes steps S501-S502. These steps will be explained in conjunction with each other.

[0069] S501: Provides a second dielectric layer and multiple interconnect bridges.

[0070] In this embodiment of the disclosure, reference is made to Figure 10 and Figure 11 As shown, a second dielectric layer 16 and a plurality of interconnect bridges 11 are provided. The second dielectric layer 16 refers to the insulating material layer used to carry and support the interconnect bridges 11, and is typically made of a low-k dielectric material to reduce parasitic capacitance and crosstalk during signal transmission. As the structural basis of the interposer layer 10, the second dielectric layer 16 plays a role in isolating and fixing the interconnect bridges 11 in subsequent processes.

[0071] S502: Multiple interconnect bridges are bonded along the vertical direction to form multiple sets of interconnect bonding structures; wherein, the interconnect bridge of the previous layer is located within the projection range of the interconnect bridge 11 of the next layer along the vertical direction Z.

[0072] In this embodiment of the disclosure, reference is made to Figure 12As shown, multiple interconnect bridges 11 are bonded along the vertical direction Z using a melt bonding process to form multiple sets of interconnect bonding structures 17. The interconnect bridge 11 of the previous layer is located within the projection range of the interconnect bridge 11 of the next layer along the vertical direction Z, to avoid interference from the previous interconnect bridge 11 when forming the connection structure 14 of the next layer interconnect bridge 11. This simplifies the manufacturing process.

[0073] S503: Etch the second dielectric layer to form multiple second grooves.

[0074] In this embodiment of the disclosure, reference is made to Figure 13 As shown, the second dielectric layer 16 is etched to form a plurality of second grooves 18. The second grooves 18 provide space for interconnect bonding structures.

[0075] S504: Bond multiple sets of interconnect bonding structures 17 to the bottom of multiple second grooves 18 respectively.

[0076] In this embodiment of the disclosure, reference is made to Figure 13 As shown, multiple interconnect bonding structures 17 are bonded to the bottom of multiple second grooves 18 respectively, so that multiple interconnect bridges 11 are embedded in the second dielectric layer 16, making full use of the space of the intermediary layer 10.

[0077] S505: Fill the plurality of second grooves 18 with insulating material covering the interconnect bonding structure; etch the insulating material to form a plurality of second vias extending in the vertical direction Z; wherein the second vias are located at both ends of the plurality of interconnect bridges 11; deposit conductive material in the second vias to form a plurality of connection structures 14, thereby forming an interposer layer 10.

[0078] In this embodiment of the disclosure, reference is made to Figure 14 As shown, insulating material covering the interconnect bonding structure is filled within multiple second grooves 18. The insulating material covers and protects the interconnect bonding structure, preventing interference or damage from the external environment. It also helps improve the electrical isolation capability of the interposer 10, reducing crosstalk and signal distortion, thereby reducing overall signal integrity issues. The insulating material is etched to form multiple second vias extending in the vertical direction Z; these vias are located at both ends of multiple interconnect bridges 11. Conductive material is deposited within the second vias to form multiple connection structures 14, thus forming the interposer 10. The conductive material is typically a metal with good conductivity and reliability, such as copper (Cu), tungsten (W), or aluminum (Al). After depositing the conductive material within the second vias, the connection structures 14 are formed, enabling high-speed data transmission between the application-specific integrated circuit 20 and the memory chip 30 via the interconnect bridges 11.

[0079] Based on the same inventive concept, this disclosure also provides an electronic device, comprising: a memory and / or a processor; the memory and / or processor includes the packaging structure of any of the above embodiments, or the memory and / or processor is manufactured according to the packaging method of any of the above embodiments. The electronic device may be: a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0080] It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments of this application are merely for description and do not represent the superiority or inferiority of the embodiments. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0081] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0082] The above are merely specific implementations of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application.

Claims

1. A packaging structure, characterized in that, The packaging structure includes: an interposer, an application-specific integrated circuit (ASIC), and multiple memory chips; The application-specific integrated circuit (ASIC) and the plurality of memory chips are all bonded to the upper surface of the interposer layer; wherein, the plurality of memory chips are located on both sides of the ASIC along a first direction; The intermediate layer includes: a plurality of interconnect bridges and connection structures embedded in the intermediate layer; wherein both ends of the interconnect bridges are connected to the connection structures, and the connection structures extend in a vertical direction; multiple interconnect bridges are arranged in the intermediate layer along the vertical direction; the interconnect bridges are respectively connected to the application-specific integrated circuit and the memory chip through the connection structures; the first direction is perpendicular to the vertical direction.

2. The packaging structure according to claim 1, characterized in that, The interconnect bridge in any layer is located within the projection range of the interconnect bridge in the next adjacent layer along the vertical direction; the memory chip connected to the interconnect bridge in any layer is located on the side of the memory chip connected to the interconnect bridge in the next adjacent layer that is closer to the application-specific integrated circuit.

3. The packaging structure according to claim 2, characterized in that, In the intermediate layer, multiple interconnect bridges are arranged at intervals along the vertical direction; wherein adjacent interconnect bridges along the vertical direction are separated by an insulating material.

4. The packaging structure according to claim 2, characterized in that, In the intermediate layer, the interconnecting bridges that are adjacent along the vertical direction are bonded to each other.

5. A packaging method, characterized in that, The encapsulation method includes: An intermediary layer is formed; the intermediary layer includes: a plurality of interconnect bridges and connection structures embedded in the intermediary layer; wherein, both ends of the interconnect bridges are connected to the connection structures, and the connection structures extend in a vertical direction; multiple layers of the interconnect bridges are arranged in the intermediary layer along the vertical direction; An application-specific integrated circuit (ASIC) and multiple memory chips are bonded to the upper surface of the interposer layer; wherein, the multiple memory chips are located on both sides of the ASIC along a first direction; the interconnect bridge connects the ASIC and the memory chips respectively through the connection structure; the first direction is perpendicular to the vertical direction.

6. The packaging method according to claim 5, characterized in that, The intermediation layer includes: n sub-intermediation layers; n is an integer greater than 1; The method of forming the intermediary layer includes: Provide n first dielectric layers; First grooves are etched in each of the n first dielectric layers; wherein the projection of the first groove in any first dielectric layer along the vertical direction is smaller than the projection of the first groove in the next first dielectric layer along the vertical direction. The interconnect bridges are formed in the first grooves of the first dielectric layer of the n-layer first dielectric layer, respectively; The first grooves of the first dielectric layer of the nth layer are respectively filled with insulating material covering the interconnect bridge; The n-th first dielectric layer is etched to form a plurality of first vias extending along the vertical direction; wherein, in the i-th first dielectric layer, the first via is located at both ends of the interconnect bridge in the i-th first dielectric layer, and at the corresponding positions at both ends of the interconnect bridge in the (i+1)-th to n-th first dielectric layers; i is an integer greater than or equal to 1 and less than n; In the first dielectric layer of the nth layer, the first via is located at both ends of the interconnect bridge of the first dielectric layer of the nth layer; Conductive material is deposited within multiple first vias to form multiple connection structures, thereby forming n sub-intermediate layers.

7. The packaging method according to claim 6, characterized in that, The bonding of the application-specific integrated circuit and multiple memory chips to the upper surface of the interposer layer includes: The application-specific integrated circuit and the plurality of memory chips are bonded to the upper surface of the first sub-intermediate layer; The upper surface of the second sub-intermediate layer is bonded to the lower surface of the first sub-intermediate layer; Continue bonding the next sub-intermediate layer until the upper surface of the nth sub-intermediate layer is bonded to the lower surface of the (n-1)th sub-intermediate layer.

8. The packaging method according to claim 6, characterized in that, The bonding of the application-specific integrated circuit and multiple memory chips to the upper surface of the interposer layer includes: The n sub-intermediate layers are stacked and bonded along the vertical direction; wherein, any interconnect bridge in any layer is located within the projection range of the interconnect bridge in the adjacent next layer along the vertical direction; the connection structure in each sub-intermediate layer that is not connected to the interconnect bridge is bonded to the connection structure in the adjacent sub-intermediate layer along the vertical direction; The application-specific integrated circuit and the plurality of memory chips are bonded to the upper surface of the first sub-intermediate layer.

9. The packaging method according to claim 5, characterized in that, The method for forming the intermediary layer further includes: Provide a second dielectric layer and a plurality of the aforementioned interconnect bridges; Multiple interconnect bridges are bonded along the vertical direction to form multiple sets of interconnect bonding structures; wherein the interconnect bridges in the previous layer are located within the projection range of the interconnect bridges in the next layer along the vertical direction; The second dielectric layer is etched to form multiple second grooves; Multiple sets of the interconnect bonding structures are respectively bonded to the bottom of multiple second grooves; The plurality of second grooves are filled with insulating material covering the interconnect bonding structure; The insulating material is etched to form a plurality of second through holes extending along the vertical direction; wherein the second through holes are located at both ends of the plurality of interconnecting bridges; Conductive material is deposited within the second via to form multiple connection structures, thereby forming the intermediary layer.

10. An electronic device, characterized in that, The electronic device includes: a memory and / or a processor; the memory and / or the processor includes a packaging structure as described in any one of claims 1 to 4, or the memory and / or the processor is manufactured using a packaging method as described in any one of claims 5 to 9.

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