Directed refresh management (DRFM) address capture in high bandwidth memory (HBM)

Abstract

Examples herein describe techniques for directed refresh management (DRFM) address capture in high bandwidth memory (HBM). Some examples are based on an activation command that includes a DRFM flag, including examples in which the activation command is received and processed when a bank is open, examples in which an address of a target row is captured without opening a corresponding bank, and examples in which the address of the target row is further captured based on a mode register. Other examples are based on a pre-charge command that includes a DRFM flag.

Description

TECHNICAL FIELD

[0001] Examples of the present disclosure generally relate to directional refresh management (DRFM) address capture in high bandwidth memory (HBM). BACKGROUND

[0002] Many workloads and applications today, such as AI, data analytics, video transcoding, and genomic analysis, require increasing amounts of memory bandwidth. Conventional double data rate (DDR) memory solutions have been unable to keep up with the growing compute and memory bandwidth intensive workloads are becoming a bottleneck for data movement and access. High bandwidth memory (HBM) helps to alleviate this bottleneck. High bandwidth memory (HBM) devices include multiple vertically stacked dynamic random access memory (DRAM) dies that can be mounted above a high speed logic layer and a wide interface (e.g., 1024-bit interface). The DRAM dies are connected to the high speed logic layer with through silicon vias (TSVs). HBM devices use a super-wide (e.g., 1024-bit) interface architecture to provide high bandwidth, high speed, and low power operation. The HBM standard is maintained by the Joint Electron Device Engineering Council (JEDEC) Committee JC-42.2, including JEDEC Standard JESD238C, JEDEC.

[0003] Directional refresh management (DRFM) is a process of refreshing a host-requested row of memory and physically adjacent neighboring rows. DRFM can be used to combat the row hammering (RH) phenomenon, where a frequently activated row (attacker) causes bit flips in adjacent rows (victims). RH can occur when the activation rate of the attacker exceeds a RH threshold (FlipTH). RH affects data integrity and can be abused in various attack scenarios.

[0004] DRFM is not available in current HBM devices and is not addressed in the current HBM3 JEDEC standard. SUMMARY

[0005] Techniques for directional refresh management (DRFM) address capture in high bandwidth memory (HBM) are described. One example is an integrated circuit device that includes an HBM device having a stack of dynamic random access memory (DRAM) dies, where the DRAM dies include respective banks of memory cells and control circuitry that receives an activate command directed to a bank of the DRAM dies, where the activate command includes an address of a target row of memory cells within the bank and a DRFM flag field, and if the DRFM flag field is set, the control circuitry captures the address of the target row of memory cells.

[0006] Another example is an integrated circuit device that includes an HBM device having a stack of DRAM dies, where a DRAM die includes a respective bank of memory cells and a control circuit that receives a precharge command directed to a bank of memory cells, where the precharge command includes an address of a memory cell of a target row of the bank and a DRFM flag field, and if the DRFM flag is set, the control circuit captures the address of the memory cell of the target row of the bank of memory cells.

[0007] Another example is a system that includes a host device that interfaces with an HBM device that includes a stack of DRAM dies, where a DRAM die includes a respective bank of memory cells, and the host device issues an activate command directed to a bank of DRAM dies, where the activate command includes an address of the bank, an address of a memory cell of a target row within the bank, and a DRFM flag field. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to provide a thorough understanding of the above-described features, a more particular description followed by specific examples will be rendered with reference to the figures. It is appreciated that these figures depict only typical examples and are therefore not to be considered limiting in scope.

[0009] Figure 1 is a block diagram of an integrated circuit (IC) device according to an example, the IC device including a high bandwidth memory (HBM) having a stack of dynamic random access memory (DRAM) dies.

[0010] Figure 2 is a block diagram of an HBM DRAM die stack according to an example.

[0011] Figure 3 is a timing diagram illustrating row and column commands for capturing a row address of a DRFM event based on a DRFM flag of an activate command according to an example.

[0012] Figure 4 is a timing diagram illustrating row and column commands for a host to decide to capture a row address of an open bank / row case according to an example.

[0013] Figure 5 is a timing diagram according to an example in which an HBM DRAM (e.g., a state machine of an HBM DRAM) is designed to handle an activate command containing a set DRFM flag (i.e., DRFM = 1) at the time the target bank / row is open, without having to wait until the target bank / row is closed.

[0014] Figure 6The timing diagram 600 according to the example is illustrated, where the HBM DRAM is designed to process activation command 302 (i.e., where DRFM=1) when the target memory bank / row is opened, as shown in the reference above. Figure 5 As described above, the activation command 302 overlaps with the column command 404.

[0015] Figure 7 An example timing diagram is shown, where the HBM DRAM is designed to process activation commands (i.e., where DRFM=1) when the target bank / row is closed, without opening the target bank / row.

[0016] Figure 8 An example of an activation command with a field for the DRFM flag is shown.

[0017] Figure 9 An example is given of the PREbp command, formatted according to the HBM standard.

[0018] Figure 10 An example is provided for the 2-UI (i.e., single-cycle) precharge per cell command PREbp_DRFM, which includes a field for the DRFM flag, based on the example.

[0019] Figure 11 This is a block diagram of a configurable circuit 1100 according to an implementation scheme, the configurable circuit including an array of configurable or programmable circuit blocks or cell blocks.

[0020] For ease of understanding, the same reference numerals are used where possible to denote common elements in the accompanying figures. Consider that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0021] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended as an exhaustive description of the features, nor as a limitation on the scope of the claims. Furthermore, the illustrated examples do not necessarily possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described.

[0022] This article provides examples of techniques for Directed Refresh Management (DRFM) address capture in high-bandwidth memory (HBM).

[0023] HBMs include a wide-interface architecture that provides high-bandwidth / high-speed, low-power operation to a stack of DRAM dies across multiple independent interfaces called channels. Channel interfaces may include a 64-bit data bus operating at Double Data Rate (DDR). In the example, the DRAM stack supports up to 16 channels. Each channel provides access to a separate set of DRAM memory banks. A request from one channel may not be able to access data attached to a different channel. Channels can be timed independently and do not need to be synchronized with each other. Based on applicable specifications, HBM designs / devices may be designated as HBM1, HBM2, HBM3, etc.

[0024] Figure 1 The block diagram of an example integrated circuit (IC) device 100 includes an HBM having a stack of DRAM dies, illustrated here as four DRAM dies 102-1 to 102-1.

[0025] Figure 2 This is a block diagram based on the example of a 200-die stack of HBM DRAM. Figure 2 In the example, the DRAM die stack 200 includes four DRAM dies 202-1 to 202-4 (collectively referred to as dies 202), each of which supports four channels. However, dies 202 are not limited to four channels. Each die 202 contributes additional capacity and additional channels to the stack 200 (e.g., up to 16 channels per stack). Each channel may include independent command and data interfaces.

[0026] HBMs may include semi-independent row command interfaces and column command interfaces for each channel. Semi-independent interfaces can increase command bandwidth and performance by allowing read and write commands to be issued simultaneously with other commands, such as activation and precharge commands.

[0027] HBM DRAM stacks may include interface dies that provide signal redistribution and other functions (i.e., respectively in...). Figure 1 and 2 (Base logic dies 104 and 204 in the DRAM). The interface die may further include DRAM logic that could originally be located on DRAM dies 102 and / or 202.

[0028] HBM DRAM can operate in either conventional mode or pseudo-channel (PC) mode. In PC mode, the channel is divided into two separate sub-channels (e.g., each sub-channel has 32-bit I / O, with each pseudo-channel providing 256-bit prefetch per memory read and write access). The sub-channels can operate semi-independently (e.g., via a shared row and column command bus and CK and R0 inputs), but commands can be decoded and executed independently. In conventional mode, the channel is not divided.

[0029] HBM DRAM is divided into memory banks (e.g., 8 to 16 memory banks). Each memory bank is divided into rows. A row may include, for example, 64 columns. In pseudo-channel mode, each column stores, for example, 128 bits of data, and, if supported, associated error code correction (ECC). In conventional mode, each column stores, for example, 256 bits of data, and ECC (if supported).

[0030] In HBM DRAM devices, typical memory access operations (e.g., read or write) involve an activation command (ACT), followed by a column command (e.g., a read (RD) or write (WR) operation), and then a precharge (PRE) command. The ACT command instructs the HBM DRAM to open the host-selected (i.e., target) bank / row (e.g., copying data from the target row of a memory cell to a buffer). The column command instructs the HBM DRAM to execute a column command on buffered data from the target row. The PRE command instructs the HBM DRAM to close the target bank / column (e.g., writing data from the buffer back to the target row of the memory cell). HBM devices include separate row command buses and column command buses. However, as with any complex circuitry, certain memory access operations / activities need to be time-separated to avoid conflicts. The JEDEC HBM standard addresses these timing issues, examples of which are provided below.

[0031] Targeted Refresh Management (DRFM) events can involve refreshing the memory row requested by the host, as well as physically adjacent rows. While specific implementation details of DRFM may vary by vendor, DRFM events typically require a target bank and row address. In other types of DRAM (e.g., DDR5 / LPDDR5 / GDDR7), the host device can initiate a DRFM event by setting the DRFM flag in the Precharge Per Bank (PREpb) command or Automatic Precharge (AP) command. However, under the current JEDEC HBM standard, there is no space for a DRFM flag in the PREPab or WRA / RDA commands.

[0032] This article discloses techniques for capturing row addresses in HBM DRAM for use in DRFM events. These techniques are designed to minimize hardware redesign work, latency, and overhead, and are adaptable to other industry problems.

[0033] In the example, the field of the activation command is used as the DRFM flag, and the HBM DRAM is designed to recognize the DRFM flag (i.e., capture the row address of the activation command after a subsequent precharge command), as referenced below. Figure 3 As described.

[0034] Figure 3A timing diagram 300 illustrates row command 312 and column command 314 for capturing DRFM events based on the DRFM flag of the activation command, according to an example.

[0035] for Figure 3 For example, HBM DRAM is designed to capture the row address of an activation command when the memory bank is shut down, and to execute a DRFM event in response to subsequent refresh management control if the DRFM flag is set in the activation command.

[0036] exist Figure 3 In the process, the host issues an activation command 302 with the DRFM flag set (e.g., set to 1) to instruct the HBM DRAM to open the target memory bank and target row based on the bank address BAx and row address RAY of the activation command 302. The host then issues a precharge command (PRE) 304 to instruct the HBM DRAM to close the target memory bank. Because the DRFM flag is set in the activation command 302, the DRAM captures the target row address RAY of the activation command 302 when the HBM DRAM closes the target memory bank. Afterward, the host issues a refresh management per-bank command RFMpb 306. Because the DRFM flag is set in the activation command 302, the DRAM interprets RFMpb 306 as a command to execute a DRFM event based on the captured row address.

[0037] In the example, the DRAM is designed to capture the row address of activation command 302 in the absence of a corresponding column command (e.g., a read or write command). In another example, the host issues column command 308 when the DRAM controller requires a corresponding column command.

[0038] exist Figure 3 In the example, row command 312 and column command 314 conform to timing separation specified as tRCD 315, tRTP / tWR 316, tRAS 317, tRP 318 and tRC 319, which may be based on specifications (e.g., JEDEC specifications).

[0039] exist Figure 3 In the example, the target memory bank is idle (i.e., closed) when the host issues activation command 302. There may be a case where the host decides to capture the row address of the currently open memory bank / row. In some other types of DRAM devices (i.e., non-HBM devices), if the host decides to initiate a row capture for the DRFM event when the target memory bank / row is open (i.e., after the host issues the activation command but before the host issues a subsequent precharge command), the host sets the DRFM flag in the subsequent precharge command. When the DRFM flag is provided in the activation command (e.g., activation command 302), the situation is not so simple, as described in the following reference.Figure 4 As described.

[0040] Figure 4 Timing diagram 400 illustrates the row command 312 and column command 314 according to the example, where the host determines to capture the row address of the open memory bank / row. Figure 4 In this process, the host issues an activation command 402 to the target memory bank, where the DRFM flag is not set (e.g., set to 0), followed by a column command 404 and a precharge command 406. If the host decides to issue an activation command 302 (i.e., where the DRFM flag is set) when the target memory bank / row is open (i.e., within time frame 408), the host will need to wait until the DRAM closes the target memory bank / row in response to the precharge control 406 (i.e., at the end of time tRC 412).

[0041] For example, if the host decides to capture the target row address at time 410, the host will need to wait for almost the duration of tRC412. If the host decides to capture the target row address at time 414, the host will need to wait for almost the sum of time 416 (i.e., tRTP or tWR) and time tRP 418.

[0042] Figure 5 An example timing diagram 500 is illustrated, in which the HBM DRAM (e.g., the state machine of the HBM DRAM) is designed to process activation command 302 (i.e., where DRFM=1) when the target bank / row is open, without having to wait until the target bank / row is closed.

[0043] exist Figure 5 In the example, the host issues an activation command 402 to the target bank / row (i.e., where the DRFM flag = 0), followed by multiple column commands 404 and 504 to the target bank / row, and then a PRE command 406. When the target bank / row is open (i.e., before the PRE command 406), the host also issues an activation command 302 to the target bank / row (i.e., where the DRFM flag = 1).

[0044] Based on activation command 302 (i.e., where DRFM flag = 1), HBM DRAM captures the target row address (e.g., when or before the DRAM closes the target memory bank / row in response to PRE command 406). Subsequently, the HBM DRAM controller, in response to RFMpb command 306, performs a DRFM event based on the captured row address, as further described above.

[0045] Compared to Figure 4 Example, Figure 5 The example reduces the latency between the time it takes for the host to decide to capture the target row address and the time it takes for DRAM to capture the target row address.

[0046] exist Figure 5 In the example, activation commands 302 and 402 are separated by time tRRDL. In one example, the host can issue activation command 302 anywhere within time frame 508.

[0047] Figure 6 The timing diagram 600 according to the example is illustrated, where the HBM DRAM is designed to process activation command 302 (i.e., where DRFM=1) when the target memory bank / row is opened, as shown in the reference above. Figure 5 As described above, the activation command 302 overlaps with the column command 404.

[0048] Figure 7 An example timing diagram 700 is illustrated, where the HBM DRAM is designed to process activation command 302 (i.e., where DRFM=1) when the target bank / row is closed, without opening the target bank / row. For Figure 7 For example, when the host issues an activation command with DRFM flag=1 (e.g., activation command 302) and sets the mode register, HBM DRAM is designed to capture the target row address without opening the target bank / row (e.g., before or after a subsequent RFMpb command) (i.e., suppress or override the opening of the target bank / row).

[0049] exist Figure 7 In this process, the host issues a mode register command 702 to instruct the HBM DRAM to set the mode register ACT_DRFM to 1. Subsequently, the host may issue an activation command 402 (i.e., DRFM flag = 0), followed by a column command 404 and a precharge command 406, as further described above.

[0050] Subsequently, the host issues activation command 302 (i.e., DRFM flag = 1) to capture the target row address specified in activation command 302. The target address of activation command 302 can be the same target row address as activation command 402, or a different target row address. (The host may decide to capture the target row address within time frame 704). Since the mode register ACT_DRFM is set to 1 (i.e., via mode register command 702), the DRAM captures the target row address specified in activation command 302 without opening the target memory bank / row. Subsequently, the HBM DRAM controller responds to RFMpb command 306 by performing a DRFM event based on the captured row address, as further described above.

[0051] exist Figure 7In the example, the host does need to issue a precharge command or an automatic precharge (AP) command. Since the target memory bank / row is not open and precharge / AP is not required, power consumption is reduced.

[0052] In addition, Figure 7 In the example, the delay tRP 510 between PRE command 406 and RFMpb 306 is avoided. Figure 5 Conversely, there is a delay of tRRDL 710 between activation command 302 and RFMpb 306.

[0053] Figure 8 An activation command 802 with fields for the DRFM flag is illustrated according to the example. Activation command 802 includes command encoding fields R0, R1, and R2, and address fields R3 through R9. Figure 8 In the example, activation command 802 is a 3-unit interval (3-UI) command, which includes a first UI 804, a second UI 806, and a third UI 808. Address fields (e.g., address field R8 of the second UI 806) can be used as DRFM fields.

[0054] In another example, the precharge command includes a DRFM field, as referenced below. Figure 9 and 10 As described.

[0055] Figure 9 An example of a precharge per bank command PREbp 902 formatted according to the HBM standard is shown. PREbp 902 is shown as a half-cycle (i.e., 1-UI) command that can be issued on either the rising or falling edge of the clock. The address fields R3 through R9 of PREbp 902 include a pseudo-channel field R3, stack identifier (SID) fields R4 and R5 (which are used as bank address bits for command execution), and bank address fields R6 through R9. Figure 9 As illustrated, all address fields of PREbp 902 are occupied, leaving no space for the DRFM flag.

[0056] In the example, PREbp 902 is translated into a multi-loop command to provide additional fields, one of which is reserved for the DRFM flag. In this example, when the DRFM flag is set, HBM DRAM captures the address of the target line specified in the translated PREbp 902 because HBM DRAM closes the target line.

[0057] In another example, the 2-UI (i.e., single-cycle) precharge command includes a DRFM flag, as referenced below. Figure 10 As described. The 2-UI precharge command is superior to the multi-cycle command.

[0058] Figure 10 An example of a 2-UI (i.e., single-cycle) precharge per bank command PREbp_DRFM 1002, including a field for the DRFM flag, is illustrated. In the first UI 1004 of PREbp_DRFM 1002, the pseudo-channel field R3 is used as a pseudo-channel flag. In the second UI 1006 of PREbp_DRFM 1002, the pseudo-channel field R3 is used as a DRFM field. When the DRFM flag is set, HBM DRAM captures the address of the target row specified in the address field of PREbp 1002 because HBM DRAM closes the target row. When the DRFM flag is not set, HBM DRAM closes the target row without capturing the address of the target row.

[0059] PREbp 1002 can represent a modified version of the Precharge Per Bank (PREpb) command. Figure 10 In the example, the command encoding fields R0, R1, and R2 of the first part 1004 and the second part 1006 are encoded as high, low, and high, respectively. And... Figure 9 In the PREPb 902 command encoding fields R0, R1, and R2 are encoded as high, low, and low, respectively.

[0060] exist Figure 8 In the middle, the third UI 808 is issued on the rising edge of the clock. Figure 9 In this context, PREPb 902 can be issued on either the rising edge or the falling edge of the clock. Therefore, PREPb 902 can occur on a falling edge immediately following the third UI of activation command 802. Figure 10 In this context, the first UI 1004 of PREPb_DRFM 1002 can be emitted on the rising edge of the clock. For Figure 10 For example, the host can issue an operation-free (RNOP) command on the falling edge of the clock 810 ( Figure 8 The activation command 802, immediately followed by the third UI 806 and the first UI 1004 of PREPb_DRFM 1002, can be issued as early as the next rising edge of the clock.

[0061] In another example, a field from the Precharge All Banks (PREab) command can be used as a DRFM flag (e.g., address field R4). In this example, when the DRFM flag is set, the HBM DRAM captures the target row address specified in the PREab command because the HBM DRAM is closing the target row.

[0062] In another example, the field of the Flush Per Bank (RFpb) command is used as the DRFM flag. In this example, when the DRFM flag is set, the HBM DRAM captures the target row address specified in the RFpb command because the HBM DRAM closes the target row.

[0063] IC device 100 may include one or more of various types of configurable circuit blocks, such as those referenced below. Figure 11 Described. Figure 11 This is a block diagram of a configurable circuit 1100 according to an implementation scheme, the configurable circuit including an array of configurable or programmable circuit blocks or cell blocks. Figure 11 Examples may represent field-programmable gate arrays (FPGAs) and / or other IC devices that utilize configurable interconnect structures to selectively couple circuit / logic elements such as complex programmable logic devices (CPLDs).

[0064] exist Figure 11 In the example, the unit block includes a multi-gigabit transceiver (MGT) 1101, a configurable logic block (CLB) 1102, a block random access memory (BRAM) 1103, an input / output block (IOB) 1104, configuration and clock logic (Config / Clock) 1105, a digital signal processing (DSP) block 1106, dedicated input / output blocks (I / O) 1107 (e.g., configuration ports and clock ports), and other programmable logic 1108, which may include, but are not limited to, a digital clock manager, an analog-to-digital converter, and / or system monitoring logic. The unit block also includes a dedicated processor 1110.

[0065] One or more cell blocks may include programmable interconnect elements (INTs) 1111 having input and output terminals 1120 to programmable logic elements within the same cell block and / or to one or more other cell blocks. The programmable INT 1111 may include connections to interconnect segments 1122 of another programmable INT 1111 in the same cell block and / or another cell block. The programmable INT 1111 may include connections to interconnect segments 1124 of a general routing resource between logic blocks (not shown). The general routing resource may include a routing channel between two sources: a logic block (not shown) comprising tracks of interconnect segments (e.g., interconnect segment 1124); and a switch block (not shown) for connecting interconnect segments. The interconnect segments of the general routing resource (e.g., interconnect segment 1124) may span one or more logic blocks. The combination of the programmable INT 1111 and the general routing resource represents a programmable interconnect structure.

[0066] CLB 1102 may include configurable logic elements (CLEs) 1112 that can be programmed to implement user logic. CLB 1102 may also include programmable INTs 1111.

[0067] BRAM 1103 may include BRAM logic elements (BRL) 1113 and one or more programmable INTs 1111. The number of interconnect elements included in the cell block may depend on the height of the cell block. BRAM 1103 may, for example, have a height of five CLBs 1102. Other numbers may also be used (e.g., four).

[0068] DSP block 1106 may include DSP logic elements (DSPL) 1114 other than one or more programmable INTs 1111. For example, IOB 1104 may include two instances of input / output logic elements (IOL) 1115 other than one or more instances of programmable INTs 1111. I / O pads connected to, for example, I / O logic elements 1115 are not necessarily limited to the area of ​​I / O logic elements 1115.

[0069] exist Figure 11 In the example, configuration / clock 1105 can be used for configuration, clocking, and / or other control logic. Vertical column 1109 can be used to assign clock and / or configuration signals.

[0070] Logic blocks (e.g., fixed-function programmable logic blocks) may disrupt the columnar structure of configurable circuitry 1100. For example, processor 1110 spans several columns of CLB 1102 and BRAM 1103. Processor 1110 may include one or more of a variety of components, such as, but not limited to, a complete programmable processing system from a single microprocessor to a microprocessor, memory controller, and / or peripheral devices.

[0071] exist Figure 11 The configurable circuitry 1100 also includes analog circuitry 1150, which may include, but is not limited to, one or more analog switches, multiplexers, and / or demultiplexers. Analog switches can help reduce leakage current.

[0072] Figure 11 Provided for illustrative purposes. The configurable circuit 1100 is not limited to the number of logic blocks in a row, the relative width of the rows, the number and order of rows, the type of logic blocks included in the rows, the relative size of the logic blocks, the illustrated interconnect / logic implementation, or... Figure 11 Other example features.

[0073] In the foregoing, reference has been made to the examples presented in this disclosure. However, the scope of this disclosure is not limited to the specifically described examples. Rather, any combination of the described features and elements is contemplated to implement and practice the contemplated examples, regardless of whether different examples are involved. Furthermore, while the examples disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved by a given example does not limit the scope of this disclosure. Therefore, the foregoing aspects, features, examples, and advantages are illustrative only and should not be considered as elements or limitations of the appended claims unless expressly recited in the claims.

[0074] As those skilled in the art will understand, the examples disclosed herein may be embodied as systems, methods, or computer program products. Therefore, aspects may take the form of entirely hardware examples, entirely software examples (including firmware, resident software, microcode, etc.), or examples combining software and hardware aspects, all of which may generally be referred to herein as “circuit,” “module,” or “system.” Furthermore, aspects may take the form of computer program products embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0075] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be (e.g., but not limited to) an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (not an exhaustive list) of computer-readable storage media will include: electrical connections having one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium is any tangible medium that can contain or store programs for use by or in connection with an instruction execution system, apparatus, or device.

[0076] Computer-readable signal media may include propagated data signals having computer-readable program code embodied therein (e.g., in baseband or as part of a carrier wave). Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. Computer-readable signal media may be any computer-readable medium that is not a computer-readable storage medium and can convey, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.

[0077] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, or any suitable combination of the foregoing.

[0078] Computer program code used to perform operations relating to the aspects of this disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages). The program code may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet through an Internet service provider).

[0079] Various aspects of this disclosure are described below with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to the examples presented in this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create components for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0080] These computer program instructions may also be stored in a computer-readable medium that can instruct a computer, other programmable data processing apparatus or other device to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing including instructions that implement the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0081] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operational steps to be performed on the computer, other programmable apparatus or other equipment to produce a computer-implemented method, such that the instructions, which execute on the computer or other programmable apparatus, provide a process for implementing the function / action specified in one or more boxes of a flowchart and / or block diagram.

[0082] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible specific implementations of systems, methods, and computer program products according to various examples of the invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0083] The above-described technology may also be described in one or more of the following non-limiting embodiments.

[0084] Example 1. An integrated circuit device, the integrated circuit device comprising: a high-bandwidth memory (HBM) device, the HBM device including a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies include corresponding memory banks of memory cells and control circuitry, the control circuitry being configured to: receive an activation command pointing to a memory bank of the DRAM dies, wherein the activation command includes an address of a memory cell in a target row within the memory bank and a Directed Refresh Management (DRFM) flag field; and if the DRFM flag field is set, capture the address of the memory cell in the target row.

[0085] Example 2. The integrated circuit device according to Example 1, wherein the control circuit is further configured to: open the memory based on the activation command; When the memory bank is opened, a column command is received pointing to a memory cell in the target row; the column command is executed on the memory cell in the target row when the memory bank is opened; and after the column command is executed, the memory bank is closed based on a precharge command pointing to the memory bank.

[0086] Example 3. The integrated circuit device according to Example 1, wherein the control circuit is further configured to: capture the address of the memory cell of the target row without opening the memory bank if the DRFM flag field is set.

[0087] Example 4. The integrated circuit device according to Example 1, wherein the control circuit is further configured to perform a Directed Refresh Management (DRFM) event based on the captured address of the memory cell of the target row.

[0088] Example 5. The integrated circuit device according to Example 4, wherein the control circuit is further configured to execute the DRFM event based on a refresh management per-page command pointing to the address of the memory.

[0089] Example 6. The integrated circuit device according to Example 1, wherein the control circuit is further configured to receive the activation command when the memory is opened.

[0090] Example 7. The integrated circuit device according to Example 6, wherein the control circuit is further configured to: receive a column command pointing to a memory cell of the target row when the memory is opened; and execute the column command on the memory cell of the target row when the memory is opened.

[0091] Example 8. The integrated circuit device according to Example 6, wherein the control circuit is further configured to: if the DRFM flag is set, capture the address of the memory cell of the target row without executing a column command on the memory cell of the target row.

[0092] Example 9. The integrated circuit device according to Example 1, wherein the control circuit is further configured to: capture the address of the memory cell of the target row if the DRFM flag is set and the mode register bit is set.

[0093] Example 10. The integrated circuit device according to Example 9, wherein the control circuit is further configured to set the mode register bit based on a mode register command from the host device.

[0094] Example 11. An integrated circuit device, the integrated circuit device comprising: a high-bandwidth memory (HBM) device, the HBM device including a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies include a corresponding bank of memory cells and control circuitry, the control circuitry being configured to: receive a precharge command directed to a bank of memory cells, wherein the precharge command includes an address of a memory cell in a target row of the bank of memory cells and a DRFM flag field; and, if the DRFM flag is set, capture the address of the memory cell in the target row of the bank of memory cells.

[0095] Example 12. The integrated circuit device according to Example 11, wherein the precharge command includes one of the following: a multi-cycle precharge per memory command; and a single-cycle precharge command, wherein the pseudo-channel field of the unit interval of the single-cycle precharge command is used as the DRFM flag field.

[0096] Example 13. A system comprising: a host device configured to: interface with a high-bandwidth memory (HBM) device, the HBM device including a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies include corresponding banks of memory cells; and issue a first activation command to a bank of memory cells of the DRAM dies, wherein the first activation command includes an address of the bank of memory cells, an address of a memory cell in a target row within the bank of memory cells, and a Directed Refresh Management (DRFM) flag field.

[0097] Example 14. The system according to Example 13, wherein the host device is further configured to: issue a first precharge command to shut down the memory; issue a first activation command a predetermined amount of time after issuing the first precharge command; and issue a second precharge command to shut down the memory after issuing the first precharge command.

[0098] Example 15: According to the system described in Example 14, the host device is further configured to: after issuing the first activation command, issue a column command pointing to the memory; and after issuing the column command, issue the second precharge command.

[0099] Example 16. The system according to Example 14, wherein the host device is further configured to: after issuing the first precharge command, issue the second precharge command to shut down the memory bank, without issuing an intermediate column command pointing to the memory cell of the target row.

[0100] Example 17. The system according to Example 13, wherein the host device is further configured to: issue the first activation command without setting the DRFM flag field; and issue a second activation command pointing to the memory when the memory is opened, wherein the second activation command includes the address of the memory cell of the target row and the DRFM flag field, wherein the DRFM flag field is set.

[0101] Example 18. The system according to Example 17, wherein the host device is further configured to: issue a column command to a memory cell of the target row when the memory is opened, wherein the column command is associated with the first activation command; and after issuing the column command, issue a precharge command to close the memory without issuing the column command associated with the second activation command.

[0102] Example 19. The system according to Example 13, wherein the host device is further configured to: issue a mode register command to the HBM device to set the mode register bits of the HBM device to signal that the address of the memory of the target row is to be captured.

[0103] Example 20. A system comprising: a host device configured to interface with a high-bandwidth memory (HBM) device, the HBM device including a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies include corresponding banks of memory cells, and wherein the host device is configured to: issue a precharge command to a bank of memory cells, wherein the precharge command includes an address of a memory cell in a target row of the bank and a DRFM flag field, wherein the precharge command includes one of: a multi-cycle per bank precharge command; and a single-cycle precharge command, wherein a pseudo-channel field of unit interval in the single-cycle precharge command is used as the DRFM flag field.

[0104] While the foregoing describes specific embodiments, other and additional examples may be devised without departing from the basic scope of the invention, the scope of which is defined by the appended claims.

Claims

1. An integrated circuit device, the integrated circuit device comprising: A high-bandwidth memory (HBM) device, the HBM device comprising a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies include corresponding memory banks of memory cells and control circuitry configured to, Receive an activation command pointing to the memory bank of the DRAM die, wherein the activation command includes the address of the memory cell in the target row within the memory bank and a Directed Refresh Management (DRFM) flag field, and If the DRFM flag field is set, the address of the memory cell of the target row is captured.

2. The integrated circuit device according to claim 1, wherein the control circuit is further configured to: The storage device is opened based on the activation command; When the memory bank is opened, a column command is received pointing to the memory cell of the target row; When the memory bank is opened, the column command is executed on the memory cell of the target row; and After executing the column command, the memory is shut down based on the precharge command pointing to the memory.

3. The integrated circuit device according to claim 1, wherein the control circuit is further configured to: If the DRFM flag field is set, the address of the memory cell of the target row is captured without opening the memory bank.

4. The integrated circuit device according to claim 1, wherein the control circuit is further configured to: Execute a Directed Refresh Management (DRFM) event based on the captured address of the memory cell in the target row.

5. The integrated circuit device according to claim 1, wherein the control circuit is further configured to: The activation command is received when the storage is opened.

6. The integrated circuit device according to claim 1, wherein the control circuit is further configured to: If the DRFM flag is set and the mode register bit is set, the address of the memory cell of the target row is captured.

7. An integrated circuit device, the integrated circuit device comprising: A high-bandwidth memory (HBM) device, the HBM device comprising a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies include corresponding memory banks of memory cells and control circuitry, the control circuitry being configured to: Receive a precharge command for a memory bank pointing to the memory cell, wherein the precharge command includes the address of the memory cell in the target row of the memory bank and a DRFM flag field; as well as If the DRFM flag is set, the address of the memory cell in the target row of the memory bank of the memory cell is captured.

8. The integrated circuit device of claim 7, wherein the precharge command includes one of the following: Multi-cycle precharge per memory command; and A single-cycle precharge command, wherein the pseudo-channel field of the unit interval of the single-cycle precharge command is used as the DRFM flag field.

9. A system comprising: The host device is configured to, Interfacing with a high-bandwidth memory (HBM) device, the HBM device comprising a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies include corresponding memory banks for memory cells, and A first activation command is issued to the memory bank of the DRAM die, wherein the first activation command includes the address of the memory bank, the address of the memory cell in the target row within the memory bank, and a Directed Refresh Management (DRFM) flag field.

10. The system of claim 9, wherein the host device is further configured to: Issue a first precharge command to shut down the memory; The first activation command is issued after a predetermined time interval following the issuance of the first pre-charge command; and After issuing the first precharge command, a second precharge command is issued to shut down the memory.

11. The system of claim 10, wherein the host device is further configured to: After issuing the first activation command, a column command pointing to the memory bank is issued; and After issuing the column command, the second precharge command is issued.

12. The system of claim 10, wherein the host device is further configured to: After issuing the first precharge command, a second precharge command is issued to shut down the memory bank, without issuing an intermediate column command pointing to the memory cell of the target row.

13. The system of claim 9, wherein the host device is further configured to: The first activation command is issued without setting the DRFM flag field; and When the memory bank is opened, a second activation command is issued pointing to the memory bank, wherein the second activation command includes the address of the memory cell of the target row and the DRFM flag field, wherein the DRFM flag field is set.

14. The system of claim 9, wherein the host device is further configured to: A mode register command is issued to the HBM device to set the mode register bits of the HBM device, thereby signaling that the address of the memory of the target row is to be captured.

15. A system comprising: A host device configured to interface with a high-bandwidth memory (HBM) device, the HBM device comprising a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies comprise respective banks of memory cells, and wherein the host device is configured to: Issue a precharge command for the memory bank pointing to the memory cell, wherein the precharge command includes the address of the memory cell in the target row of the memory bank and a DRFM flag field, wherein the precharge command includes one of the following: Multi-cycle precharge per memory command, and A single-cycle precharge command, wherein the pseudo-channel field of the unit interval of the single-cycle precharge command is used as the DRFM flag field.

Images