Vapor deposition of carbon-based films

Abstract

Methods of forming graphene hard mask films are disclosed. Some methods are advantageously performed at lower temperatures. The substrate is exposed to an aromatic precursor to form a graphene hard mask film. The substrate includes one or more of titanium nitride (TiN), tantalum nitride (TaN), silicon (Si), cobalt (Co), titanium (Ti), silicon dioxide (SiO2), copper (Cu), and a low dielectric constant dielectric material.

Description

[0001] This application is a divisional application of the invention patent application with application number 202110235601.0. Technical Field

[0002] Embodiments of this disclosure generally relate to methods for depositing or forming graphene. Some embodiments of this disclosure relate to methods for forming a graphene hard mask film on a dielectric substrate. Some embodiments relate to methods for improving substrate surface quality or deposition parameters while depositing graphene. Background Technology

[0003] Graphene has attracted considerable attention in semiconductor manufacturing due to its superior optical and electrical properties. With its unique 2D honeycomb lattice and atomic-layer structure, graphene, a single layer of carbon atoms arranged in a hexagonal lattice, holds extraordinary potential for the future of the electronics industry. Graphene is the thinnest material, with a thickness of only one carbon atom, approximately 3.35 angstroms. Therefore, among carbon materials, graphene possesses the highest recorded specific surface area (SSA). This high SSA provides graphene with the promising property of storing more energy than other carbonaceous materials. Furthermore, delocalized electrons in graphene sheets can reach speeds of approximately 2–2.5 × 10⁻⁶. 5 cm 2 The inherent mobility of / vs allows for high-speed travel, thus facilitating efficient current transmission.

[0004] As the resistance of metal wires increases with shrinking thickness and size, graphene, due to its thinness and high electron mobility, can serve as a replacement for traditional metal barrier layers in next-generation semiconductor devices. Graphene also exhibits high optical transparency, making it suitable for flexible electronic devices, such as smartwatches.

[0005] Traditional graphene CVD growth requires high temperatures (>1000°C) and the use of metal foil as a catalyst. At these high temperatures, most materials used in electronic applications can be damaged. Furthermore, the metal foil needs to be removed after graphene growth. This transfer process is expensive, can damage the graphene hard masking film, and also leads to metal contamination. Therefore, low-temperature growth without the use of metal catalysts is highly desirable.

[0006] Currently, chemical vapor deposition (CVD) using metal catalysts is used to grow graphene films. While high-quality graphene films can be deposited via CVD growth, this process requires high growth temperatures, typically 800-1000°C or higher. This is incompatible with current integration processes in the semiconductor industry, as metal lines and low-dielectric-constant (k) films on device wafers cannot withstand such high temperatures. Furthermore, the graphene deposited via high-temperature CVD needs to be transferred from the metal foil. This transfer process is expensive and can lead to film damage, defects, and metal contamination. Therefore, high-temperature CVD using known methods is neither convenient nor feasible for industrial applications. Consequently, direct growth on any substrate at relatively lower temperatures without the use of metal catalysts is highly desirable.

[0007] Therefore, there is a need for improved methods for depositing graphene hard mask films. Summary of the Invention

[0008] One or more embodiments of this disclosure relate to a method for forming a graphene hard mask film. The method includes: exposing a substrate to an aromatic precursor in a processing chamber; purging the processing chamber of the aromatic precursor; heating the substrate to a temperature below 600°C to polymerize the aromatic precursor and deposit a graphene hard mask film on the substrate; and purging the processing chamber.

[0009] Additional embodiments of this disclosure relate to methods of forming films. In one or more embodiments, the method includes: forming a flowable graphene hard mask film on a substrate by exposing the substrate to an aromatic precursor; and exposing the substrate to plasma.

[0010] Further embodiments of this disclosure relate to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: exposing a substrate to an aromatic precursor in the processing chamber; purging the aromatic precursor from the processing chamber; heating the substrate to a temperature below 600°C to polymerize the aromatic precursor and deposit a graphene hard mask film on the substrate; and purifying the processing chamber. Attached Figure Description

[0011] To gain a detailed understanding of the features described above, reference can be made to embodiments that provide a more specific description of the disclosure, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of the present disclosure and should not be construed as limiting the scope of the invention, as other equivalent embodiments are permissible.

[0012] Figure 1 A process flow diagram of a method according to one or more embodiments of the present disclosure is shown;

[0013] Figure 2 A process flow diagram of a method according to one or more embodiments of the present disclosure is shown;

[0014] Figure 3 Clustering tools according to one or more implementations are shown. Detailed Implementation

[0015] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps set forth in the following description. This disclosure can have other embodiments and can be practiced or performed in various ways.

[0016] As used in this specification and the appended claims, the term "substrate" refers to a surface or part of a surface on which a process is performed. Those skilled in the art will also understand that, unless explicitly stated in the context, reference to substrate may also refer to only a portion of a substrate. Furthermore, reference to deposition on a substrate may refer to a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0017] As used herein, “substrate” means any substrate or material surface formed on a substrate on which a film treatment is performed during manufacturing. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any film treatment steps disclosed herein, as described in more detail below, can also be performed on an underlayer formed on the substrate, and the term “substrate surface” is intended to include such an underlayer as indicated by the context. Thus, for example, where a layer or portion of a layer has already been deposited on the substrate surface, the exposed surface of a newly deposited layer can also be described as a substrate surface.

[0018] One or more embodiments of the method are back-to-line process (BEOL) integration schemes. In one or more embodiments, the substrate comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), silicon (Si), cobalt (Co), titanium (Ti), silicon dioxide (SiO2), copper (Cu), and a low-dielectric-constant dielectric material (e.g., Black Diamond®). As used herein, the term "Black Diamond®" refers to a low-dielectric-constant dielectric film manufactured by Applied Materials®. As used herein, the term "low-dielectric-constant dielectric" refers to a material having a smaller relative dielectric constant (k) relative to silicon dioxide (SiO2). In one or more embodiments, the low-dielectric-constant dielectric can be any acceptable material known to those skilled in the art. In one or more embodiments, the low-dielectric-constant dielectric is Black Diamond®.

[0019] Embodiments of this disclosure relate to methods for forming graphene hard mask films. Further embodiments of this disclosure relate to methods for improving graphene deposition processes. Some embodiments of this disclosure advantageously provide methods for forming graphene hard mask films at lower temperatures. Some embodiments of this disclosure advantageously provide methods for forming graphene hard mask films of a predetermined thickness at lower temperatures. Some embodiments of this disclosure advantageously provide methods for forming graphene hard mask films with lower resistance.

[0020] According to one or more embodiments, the method uses a chemical vapor deposition (CVD) process. As used herein, "chemical vapor deposition" refers to a process in which the substrate surface is simultaneously or substantially simultaneously exposed to precursors and / or co-reagents. As used herein, "substantially simultaneously" means that there is a significant overlap in the exposure of the co-flow or precursors.

[0021] According to one or more embodiments, the method uses chemical vapor deposition (CVD) and atomic layer deposition (ALD) processes. In such embodiments, the substrate surface is exposed sequentially or substantially sequentially to a precursor (or reactive gas). As used throughout this specification, "substantially sequentially" means that the duration of precursor exposure does not largely overlap with exposure to the co-reagent, but there may be some overlap. As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," etc., are used interchangeably to refer to any gaseous substance capable of reacting with the substrate surface.

[0022] As used herein, “atomic layer deposition” or “cyclic deposition” refers to the sequential exposure of two or more reactive compounds to deposit a material layer on a substrate surface. Alternatively, a substrate or a portion thereof may be individually exposed to two or more reactive compounds introduced into a reaction zone within a processing chamber. In time-domain ALD processes, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface before being degassed from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In spatial ALD processes, different portions of the substrate surface or material on the substrate surface are simultaneously exposed to two or more reactive compounds such that any given point on the substrate is substantially not simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, and as will be understood by those skilled in the art, the term “substantially” as used herein means that, due to diffusion, a small portion of the substrate may be simultaneously exposed to multiple reactive gases, and that such simultaneous exposure is unintentional.

[0023] In one aspect of the time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, such as an aromatic precursor) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B (e.g., an oxidant) is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone, or otherwise remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either case, the ALD process of pulsedly feeding compound A, purge gas, compound B, and purge gas is a cycle. The cycle may begin with compound A or compound B and continue in the corresponding order until a film with a predetermined thickness is achieved.

[0024] In one embodiment of the space ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen) are simultaneously delivered to the reaction zone, but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery device such that any given point on the substrate is exposed to the first and second reactive gases.

[0025] As used herein, “pulse” or “dose” refers to the amount of source gas introduced into the processing chamber intermittently or discontinuously. Depending on the duration of the pulse, the amount of a particular compound within each pulse may vary over time. A particular process gas may contain a single compound or a mixture / combination of two or more compounds, such as the process gases described below.

[0026] The duration of each pulse / dose is variable and can be adjusted to suit, for example, the volumetric capacity of the processing chamber and the capabilities of the vacuum system coupled to the processing chamber. Furthermore, the dosing time of the process gas can vary depending on the flow rate of the process gas, the temperature of the process gas, the type of control valve, the type of processing chamber employed, and the ability of the process gas components to adsorb onto the substrate surface. The dosing time can also be varied based on the type of layer being formed and the geometry of the device being formed. The dosing time should be long enough to provide a volume of compound sufficient for adsorption / chemisorption onto substantially the entire surface of the substrate and to form a layer of process gas components thereon.

[0027] According to one or more embodiments, graphene can be grown via chemical vapor deposition and / or atomic layer deposition for many applications. One or more embodiments of this disclosure advantageously provide a process for performing chemical vapor deposition to form a graphene hard mask film. As used in this specification and the appended claims, the term "graphene hard mask film" refers to a film containing graphene. Graphene is an allotrope of carbon, existing as a single layer of atoms in a two-dimensional hexagonal lattice, in which one atom forms each vertex. It can be considered an infinitely large aromatic molecule, the ultimate case of the flat polycyclic aromatic hydrocarbon family.

[0028] Figure 1 A process flow diagram of a method according to one or more embodiments is shown. Figure 1 The method shown is representative of chemical vapor deposition (CVD) processes, in which reactive gases are mixed in a processing chamber to allow for gas-phase reactions of the reactive gases and deposition of thin films. In some embodiments, Figure 1 The method shown is representative of atomic layer deposition (ALD) processes, in which a substrate or substrate surface is sequentially exposed to reactive gases in a manner that prevents or minimizes gas-phase reactions of the reactive gases.

[0029] Figure 1 A flowchart depicts a method 100 for depositing a film according to one or more embodiments of the present disclosure. (See also...) Figure 1Method 100 includes a deposition cycle 110. Method 100 begins at operation 102 by preparing a substrate to be processed. In some embodiments, the method includes a chemical vapor deposition (CVD) process, in which reactive gases are mixed in a processing chamber to allow for gas-phase reaction of the reactive gases and deposition of a hard mask film on the substrate. In the CVD reaction, the substrate (or substrate surface) may be exposed to a mixture of precursor and reactant gases to deposit a graphene hard mask film of a predetermined thickness. In the CVD reaction, the graphene hard mask film may be deposited in a single exposure to the mixed reactive gases, or it may be exposed to the mixed reactive gases multiple times, with degassing between the multiple exposures. In some embodiments, method 100 is representative of an atomic layer deposition (ALD) process, in which the substrate or substrate surface is sequentially exposed to the reactive gases in a manner that prevents or minimizes gas-phase reaction of the reactive gases.

[0030] In some embodiments, preparing substrate 102 includes pretreatment operations. Pretreatment can be any suitable pretreatment known to those skilled in the art. Suitable pretreatments include, but are not limited to, preheating, cleaning, soaking, removal of natural oxides, or deposition of an adhesion layer (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.).

[0031] In one or more embodiments, the substrate is washed. Washing can be performed by any suitable technique known to a person skilled in the art, including but not limited to isopropyl alcohol (IPA) washing, standard cleaning known to a person skilled in the art (including Standard Clean 1 (SC1) and Standard Clean 2 (SC2)), vapor phase cleaning (such as Automated Process Control (APC) cleaning), e-APC cleaning, etc. After washing the substrate, the substrate is loaded into a processing chamber.

[0032] At deposition 110, a process is performed to deposit a graphene hard mask film on a substrate (or substrate surface). The deposition process may include one or more operations for forming a hard mask on the substrate. In operation 112, the substrate (or substrate surface) is exposed to an aromatic precursor to deposit the graphene hard mask film on the substrate (or substrate surface).

[0033] At deposition 110, a process cycle can be performed to deposit a graphene hard mask film on a substrate (or substrate surface). The deposition process may include one or more operations to form a hard mask film on the substrate. In operation 112, the substrate (or substrate surface) is exposed to an aromatic precursor to deposit the graphene hard mask film on the substrate (or substrate surface). The aromatic precursor may be any suitable aromatic compound capable of reacting with the substrate surface (i.e., adsorbing or chemisorbing onto the substrate surface) to leave an aromatic substance on the substrate surface.

[0034] At operation 112, the substrate is loaded into the processing chamber along with one or more precursors, and the substrate is exposed to the precursors. In some embodiments, the precursors include aromatic precursors. An aromatic precursor contains at least one aromatic ring.

[0035] As used herein, in one or more embodiments, the term "aromatic precursor" refers to an aromatic precursor. As those skilled in the art will recognize, aromaticity is a property of cyclic (ring-shaped), planar (flat) structures with resonant rings that imparts increased stability compared to other geometric or interconnected arrangements with the same atomic set. Aromatic molecules are very stable and do not readily decompose or react with other substances. Aromaticity describes a conjugated system, typically composed of alternating single and double bonds within a ring. This configuration allows electrons in the molecular π-system to delocalize around the ring, thereby increasing molecular stability.

[0036] In one or more embodiments, the aromatic precursor may include any aromatic precursor known to those skilled in the art. In some embodiments, the aromatic precursor includes one or more of benzene, substituted benzene, naphthalene, substituted naphthalene, anthracene, and substituted anthracene. In one or more embodiments, the aromatic precursor may be substituted with one or more alkyl groups, one or more alkoxy groups, one or more vinyl groups, one or more silyl groups, one or more amino groups, or one or more halides.

[0037] Unless otherwise stated, the terms “lower alkyl,” “alkyl,” or “alk” as used alone or as part of another group herein include straight-chain and branched hydrocarbons containing 1 to 20 carbons in the positive chain, such as methyl, ethyl, propyl, isopropyl, butyl, tert-butyl, isobutyl, pentyl, hexyl, isohexyl, heptyl, 4,4-dimethylpentyl, octyl, 2,2,4-trimethylpentyl, nonyl, decyl, undecyl, dodecyl, and their various branched isomers. Such groups may optionally contain up to 1 to 4 substituents.

[0038] As used herein, the term "alkoxy" includes any of the aforementioned alkyl groups bonded to an oxygen atom.

[0039] As used herein, the term “vinyl” or “vinyl-containing” refers to a group containing a vinyl group (-CH=CH2).

[0040] As used herein, the term "amine" refers to any organic compound containing at least one basic nitrogen atom, such as NR'2, where R' is independently selected from hydrogen (H) or alkyl.

[0041] As used herein, the term "silane" refers to the compound SiR'3, where R' is independently selected from hydrogen (H) or alkyl groups.

[0042] As used herein, the term "halide" refers to a binary phase, one part of which is a halogen atom and the other part is an element or group with a lower electronegativity than the halogen, to form a fluoride, chloride, bromide, iodide, or astatine compound. A halide ion is a negatively charged halogen atom. As is known to those skilled in the art, halide anions include fluoride (F-), chloride (Cl-), bromide (Br-), iodide (I-), and astatine (At-).

[0043] In one or more embodiments, the aromatic precursor comprises a small aromatic molecule having a temperature-sensitive functional group. In one or more specific embodiments, the aromatic precursor is selected from one or more of naphthalene, 2,6-dibromonaphthalene, trimethyl 1,3,5-benzenetricarboxylate, 9,10-dibromoanthracene, benzoic acid, 2,6-di-tert-butylnaphthalene, 1,3,5-trimethoxybenzene, and hexabromobenzene.

[0044] The substrate can be any substrate known to those skilled in the art. In one or more embodiments, the substrate comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), silicon (Si), cobalt (Co), titanium (Ti), silicon dioxide (SiO2), copper (Cu), and low dielectric constant dielectric materials (such as Black Diamond®).

[0045] At operation 114, the processing chamber is purged. Purge (i.e., vacuum generation) can be accomplished using any suitable gas that does not react with the substrate, the film on the substrate, and / or the walls of the processing chamber. Suitable purge gases include, but are not limited to, N2, He, and Ar. The purge gas can be used to remove aromatic precursors and / or oxidants from the processing chamber. In some embodiments, the same purge gas is used for each purge operation. In other embodiments, different purge gases are used for each purge operation. In one or more embodiments, the purge pressure is in the range of 0.1 mTorr to about 100 Torr, including the range of about 0.5 mTorr to about 50 Torr, and the range of about 1 mTorr to about 100 Torr.

[0046] At operation 114, the processing chamber is purged to remove unreacted aromatic precursors, reaction products, and byproducts. When used in this manner, the term "processing chamber" also includes a portion of the processing chamber adjacent to the substrate surface, and does not encompass the entire internal volume of the processing chamber. For example, in spatially separated sectors of the processing chamber, tellurium precursors are purged from a portion of the processing chamber adjacent to the substrate surface using any suitable technique, including but not limited to moving the substrate through a gas curtain to a portion or sector of the processing chamber that does not contain or substantially does not contain aromatic precursors. In some embodiments, purging the processing chamber includes flowing a purge gas over the substrate. In some embodiments, the portion of the processing chamber refers to a micro-volume or small-volume processing station within the processing chamber. The term "adjacent" to the substrate surface refers to the physical space immediately adjacent to the substrate surface that provides sufficient space for surface reactions (e.g., precursor adsorption) to occur.

[0047] At operation 116, the substrate (or substrate surface) is heated to a temperature ranging from about 150°C to about 700°C. In one or more embodiments, the chamber temperature is less than about 500°C. In other embodiments, the deposition process is performed at temperatures ranging from about 0°C to about 500°C, including temperatures ranging from about 25°C, about 50°C, about 75°C, about 100°C, about 125°C, about 150°C, about 175°C, about 200°C, about 425°C, about 250°C, about 275°C, about 300°C, about 325°C, about 350°C, about 375°C, about 400°C, about 425°C, about 450°C, about 475°C, and about 500°C.

[0048] In one or more embodiments, the functional groups of the aromatic precursor decompose and activate molecules to polymerize in a 2D direction to form a graphene hard mask film on a substrate. In other embodiments, reactants may be introduced into a processing chamber at operation 116. The reactants may react with aromatic substances on the substrate surface to form a graphene hard mask film. In some embodiments, the reactants comprise a reducing agent. In one or more embodiments, the reducing agent may include any reducing agent known to those skilled in the art. In other embodiments, the reactants comprise an oxidizing agent. In one or more embodiments, the oxidizing agent may include any oxidizing agent known to those skilled in the art. In further embodiments, the reactants comprise one or more of an oxidizing agent and a reducing agent.

[0049] At operation 116, the temperature of the substrate in the processing chamber is brought to a temperature in the range of about 150°C to about 700°C, including temperatures of about 150°C, about 200°C, about 250°C, about 300°C, about 350°C, about 400°C, about 450°C, about 500°C, about 550°C, about 600°C, about 650°C, and about 700°C. In one or more embodiments, a hard mask film is deposited on the substrate. During deposition, functional groups on the aromatic precursor decompose and activate molecules to polymerize in a 2D direction, thereby forming a graphene hard mask film on the substrate.

[0050] At operation 118, the processing chamber is cooled and purified, and the substrate can be removed from the processing chamber. Purification (i.e., creating a vacuum) can be accomplished using any suitable gas that does not react with the substrate, the film on the substrate, and / or the walls of the processing chamber. Suitable purging gases include, but are not limited to, N2, He, and Ar. The purging gas can be used to remove aromatic precursors and / or oxidants from the processing chamber. In some embodiments, the same purging gas is used for each purging operation. In other embodiments, different purging gases are used for each purging operation.

[0051] In operation 118, a purification process chamber is used. The purification process chamber in operation 118 can be the same process as or a different process than the purification process in operation 114. The purification process chamber, a portion of the purification chamber, and areas adjacent to the substrate surface, etc., remove unreacted reactants, reaction products, and byproducts from areas adjacent to the substrate surface.

[0052] Deposition cycle 110 can be performed until graphene of a predetermined thickness has been formed. At operation 120, the thickness of the formed graphene hard mask film is evaluated to determine whether the predetermined thickness has been reached. If not, method 100 returns to operation 112 for further formation. If yes, method 100 proceeds to an optional post-processing step at operation 130, or method 100 ends.

[0053] At decision 120, the thickness of the deposited graphene hard mask film or the number of cycles for the aromatic precursor is considered. If the deposited hard mask film has reached a predetermined thickness or a predetermined number of process cycles has been performed, method 100 proceeds to optional post-processing operation 130. If the thickness of the deposited hard mask film or the number of process cycles has not yet reached a predetermined threshold, method 100 returns to operation 110 to expose the substrate surface to the aromatic precursor again in operation 112 and continues.

[0054] Optional post-processing operation 130 may be, for example, a process to modify membrane properties (e.g., annealing) or a further membrane deposition process (e.g., additional ALD or CVD process) for growing an additional membrane. In some embodiments, optional post-processing operation 130 may be a process to modify the properties of the deposited hard mask membrane. In some embodiments, optional post-processing operation 130 includes annealing the deposited membrane. In some embodiments, annealing is performed at a temperature in the range of about 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C. The annealing environment in some embodiments includes one or more of an inert gas (e.g., molecular nitrogen (N2), argon (Ar)) or a reducing gas (e.g., molecular hydrogen (H2) or ammonia (NH3)) or an oxidizing agent (such as, but not limited to, oxygen (O2), ozone (O3), or peroxide). Annealing can be performed for any suitable duration. In some embodiments, the film is annealed for a predetermined time ranging from about 15 seconds to about 90 minutes, or from about 1 minute to about 60 minutes. In some embodiments, annealing the deposited hard mask film increases density, reduces resistivity, and / or increases film purity.

[0055] Method 100 can be performed at any suitable temperature, which depends on, for example, the thermal budget of the aromatic precursor, reactant, or device. In some embodiments, exposure to the aromatic precursor (operation 112) and reactant (operation 116) occurs at the same temperature. In some embodiments, the substrate is maintained at a temperature ranging from about 150°C to about 700°C, or from about 150°C to about 650°C, or from about 150°C to about 500°C. The temperature of the substrate surface can be controlled during the formation of the graphene hard mask film. In some embodiments, the substrate surface is maintained at a temperature less than or equal to about 700°C, less than or equal to about 650°C, less than or equal to about 600°C, less than or equal to about 500°C, less than or equal to about 400°C, less than or equal to about 300°C, less than or equal to about 200°C, less than or equal to about 100°C, less than or equal to about 50°C, or less than or equal to about 25°C.

[0056] Typically, CVD processes for forming graphene hard mask films are performed at temperatures exceeding 1000°C. One or more embodiments provide methods for depositing graphene hard mask films at lower temperatures, below about 700°C, or below about 600°C, or below about 500°C, or below about 400°C. Without being bound by theory, these lower temperatures are believed to be more compatible with the thermal budget of electronic devices during manufacturing.

[0057] In some embodiments, the graphene hard mask film formed by the disclosed method comprises less than or equal to about 1, less than or equal to about 2, less than or equal to about 5, less than or equal to about 10, less than or equal to about 20, less than or equal to about 25, or less than or equal to about 30 monolayer graphene. In some embodiments, the graphene hard mask film formed by the disclosed method comprises graphene in the range of about 0.5 to about 25 monolayers, or in the range of about 0.5 to about 10 monolayers, or in the range of about 1 to about 5 monolayers, or in the range of about 5 to about 10 monolayers. In some embodiments, the thickness of the graphene hard mask film formed by the disclosed method is less than or equal to about 3 Å, less than or equal to about 5 Å, less than or equal to about 10 Å, less than or equal to about 15 Å, less than or equal to about 20 Å, less than or equal to about 25 Å, less than or equal to about 30 Å, less than or equal to about 40 Å, or less than or equal to about 50 Å.

[0058] In some embodiments, method 100 can be performed over a relatively short period of time. In some embodiments, the graphene hard mask film is formed over a period of less than or equal to about 15 minutes, less than or equal to about 10 minutes, less than or equal to about 5 minutes, less than or equal to about 2 minutes, or less than or equal to about 1 minute. In other embodiments, the graphene hard mask film is formed over a period of about 1 hour to about 48 hours.

[0059] In some embodiments, the improved substrate surface quality is increased smoothness. In some embodiments, the improved substrate surface quality is reduced hydrogen concentration. In some embodiments, the improved substrate surface quality is reduced contamination.

[0060] In some embodiments, the improved deposition parameters are increased film thickness. In some embodiments, the improved deposition parameters are reduced film resistance. In some embodiments, the improved deposition parameters are increased uniformity. These improvements are relative to graphene hard mask films deposited with similar process parameters (e.g., reactants, temperature, plasma power, deposition time).

[0061] refer to Figure 2 One or more embodiments of this disclosure relate to a method 200 for depositing a graphene hard mask film. Figure 2 The method shown is representative of plasma-enhanced processes, in which reactive gases are mixed in a processing chamber to allow for gas-phase reactions of the reactive gases and deposition of thin films.

[0062] In some embodiments, method 200 includes a pretreatment operation 205. The pretreatment can be any suitable pretreatment known to those skilled in the art. Suitable pretreatments include, but are not limited to, preheating, cleaning, soaking, removal of natural oxides, or deposition of a layer (e.g., titanium nitride (TiN)).

[0063] At deposition operation 210, a process is performed to deposit a graphene hard mask film on a substrate (or substrate surface). The deposition process may include one or more operations to form a graphene hard mask film on the substrate. In operation 212, the substrate (or substrate surface) is exposed to an aromatic precursor to deposit a film on the substrate (or substrate surface).

[0064] In one or more embodiments, the aromatic precursor may include any aromatic precursor known to those skilled in the art. In some embodiments, the aromatic precursor includes one or more of benzene, substituted benzene, naphthalene, substituted naphthalene, anthracene, and substituted anthracene. In one or more embodiments, the aromatic precursor may be substituted with one or more alkyl groups, one or more alkoxy groups, one or more vinyl groups, one or more silyl groups, one or more amino groups, or one or more halides.

[0065] In one or more embodiments, the aromatic precursor comprises a small aromatic molecule having a temperature-sensitive functional group. In one or more specific embodiments, the aromatic precursor is selected from one or more of naphthalene, 2,6-dibromonaphthalene, trimethyl 1,3,5-benzenetricarboxylate, 9,10-dibromoanthracene, benzoic acid, 2,6-di-tert-butylnaphthalene, 1,3,5-trimethoxybenzene, and hexabromobenzene.

[0066] The substrate can be any substrate known to those skilled in the art. In one or more embodiments, the substrate comprises one or more of titanium nitride (TiN), silicon (Si), cobalt (Co), titanium (Ti), silicon dioxide (SiO2), copper (Cu), and a low dielectric constant dielectric material (such as Black Diamond®).

[0067] At operation 214, the chamber is cleaned to remove unreacted precursors, reaction products, and byproducts.

[0068] In one or more embodiments, the deposition process includes remote plasma-enhanced chemical vapor deposition (PECVD). After forming a graphene hard mask film on the substrate, the substrate is exposed to plasma at operation 216. In one or more embodiments, exposing the graphene hard mask film to plasma in a processing chamber improves film properties. For example, in one or more embodiments, the wet etching rate is improved, indicating that the density of the graphene hard mask film has been enhanced by plasma treatment. In one or more embodiments, the plasma includes one or more of nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), carbon monoxide (CO), or carbon dioxide (CO2). In some embodiments, the plasma is a remote plasma. In other embodiments, the plasma is a direct plasma.

[0069] In one or more embodiments, the plasma can be generated remotely or within a processing chamber. In one or more embodiments, the plasma is inductively coupled plasma (ICP) or conduction-coupled plasma (CCP). Any suitable power can be used, depending on factors such as reactants or other process conditions. In some embodiments, the plasma is generated at a plasma power in the range of about 10 W to about 3000 W. In some embodiments, the plasma is generated at a plasma power of less than or equal to about 3000 W, less than or equal to about 2000 W, less than or equal to about 1000 W, less than or equal to about 500 W, or less than or equal to about 250 W.

[0070] At operation 218, after exposure to plasma, the processing chamber is optionally cleaned. The cleaning process in operation 218 can be the same as or a different process than the cleaning process in operation 214. The cleaning process chamber, a portion of the processing chamber, and areas adjacent to the substrate surface, etc., remove plasma, reaction products, and byproducts from areas adjacent to the substrate surface.

[0071] At decision point 220, in one or more embodiments, the thickness of the deposited film, or the number of cycles of the precursor and reactants, is considered. In one or more embodiments, if the deposited film has reached a predetermined thickness or a predetermined number of process cycles has been performed, method 200 proceeds to post-processing operation 230. In one or more embodiments, if the thickness of the deposited film or the number of process cycles has not yet reached a predetermined threshold, method 200 returns to deposition operation 210 to expose the substrate surface to the aromatic precursor again in operation 212 and continues.

[0072] In one or more embodiments, optional post-processing operation 230 includes, for example, processes that alter membrane properties (e.g., annealing) or further membrane deposition processes (e.g., additional ALD or CVD processes) for growing additional membranes. In some embodiments, post-processing operation 230 is a process that alters the properties of the deposited membrane. In some embodiments, post-processing operation 230 includes annealing the deposited membrane. In some embodiments, annealing is performed at temperatures in the range of about 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C. The annealing environment in some embodiments includes one or more of an inert gas (e.g., molecular nitrogen (N2), argon (Ar)) or a reducing gas (e.g., molecular hydrogen (H2) or ammonia (NH3)) or an oxidizing agent (such as, but not limited to, oxygen (O2), ozone (O3), or peroxide). In one or more embodiments, annealing is performed for any suitable duration. In some embodiments, the graphene hard mask film is annealed for a predetermined time ranging from about 15 seconds to about 90 minutes, or from about 1 minute to about 60 minutes. In some embodiments, annealing the deposited film increases its density, reduces its resistivity, and / or increases its purity.

[0073] In one or more embodiments, method 200 can be performed at any suitable temperature, the suitable temperature depending on, for example, the thermal budget of the precursor, reactant, or device. In some embodiments, the substrate is maintained at a temperature ranging from about 0°C to about 500°C.

[0074] In one or more embodiments, the substrate (or substrate surface) is exposed to a precursor during the PE-CVD reaction. In the PE-CVD reaction, the substrate (or substrate surface) is exposed to a gas mixture of the precursor and optionally reactants to deposit a graphene hard mask film of a predetermined thickness. In the PE-CVD reaction, the graphene hard mask film may be deposited through a single exposure to the mixed reactive gases, or it may be exposed to the mixed reactive gases multiple times, with degassing between the multiple exposures.

[0075] In one or more embodiments, a deposition process is performed in a process volume at pressures ranging from 0.1 mTorr to 100 Torr, including pressures of about 0.1 mTorr, about 10 mTorr, about 100 mTorr, about 1000 mTorr, about 5000 mTorr, about 1 Torr, about 20 Torr, about 30 Torr, about 40 Torr, about 50 Torr, about 60 Torr, about 70 Torr, about 80 Torr, about 90 Torr, and about 100 Torr.

[0076] The gas mixture containing the precursor may also include one or more diluent gases selected from helium (He), argon (Ar), xenon (Xe), nitrogen (N2), or hydrogen (H2). In some embodiments, the diluent gas includes a compound that is inert relative to the reactants and substrate material.

[0077] The plasma (e.g., capacitively coupled plasma) can be formed by top and bottom or side electrodes. Electrodes can be formed by a single-supply electrode, a dual-supply electrode, or multiple electrodes having multiple frequencies such as, but not limited to, 350 kHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, and 100 MHz, which are used alternately or simultaneously with any or all of the reactive gases listed herein in a CVD system to deposit dielectric thin films. In some embodiments, the plasma is capacitively coupled plasma (CCP). In some embodiments, the plasma is inductively coupled plasma (ICP). In some embodiments, the plasma is microwave plasma.

[0078] In one or more embodiments, deposition operation 210 may be repeated to form a graphene hard mask film having a predetermined thickness. In some embodiments, deposition operation 210 is repeated to provide a graphene hard mask film with a thickness greater than about 0.1 nm or in the range of about 0.1 nm to about 1000 nm, including about 10 nm to about 500 nm, about 10 nm to about 100 nm, about 5 nm to about 50 nm, about 10 nm to about 50 nm, or about 20 nm to about 30 nm.

[0079] In some embodiments, a graphene hard mask film is deposited in a chamber, wherein the substrate is maintained below about 700°C, or below about 600°C, or below about 500°C, or below about 400°C, or below about 300°C, and the pressure is maintained at about 5 Torr, wherein the plasma is generated at the wafer level (i.e., direct plasma) by applying a bias voltage of about 200 watts to an electrostatic chuck. In some embodiments, an additional RF power of about 1000 watts at 2 MHz is also supplied to the electrostatic chuck, thereby generating wafer-level dual-bias plasma.

[0080] Typically, according to one or more embodiments, the following exemplary deposition process parameters can be used to form the deposited film. In one or more embodiments, the wafer temperature can range from about 150°C to about 700°C, or from about 150°C to about 500°C. The chamber pressure can range from about 0.1 mTorr to about 100 Torr. The flow rate of the gas mixture containing the precursor can range from about 10 sccm to about 1,000 sccm. The flow rate of the dilution gas can be individually in the range from about 50 sccm to about 50,000 sccm.

[0081] In one or more embodiments, the graphene hard mask film may be deposited to a thickness in the range of about 5 Å to about 60,000 Å, including the range of about 300 Å to about 10,000 Å, the range of about 2,000 Å to about 3,000 Å, or the range of about 5 Å to about 200 Å.

[0082] According to one or more embodiments, the substrate is processed before and / or after the formation of the layer. This processing can be performed in the same chamber or in one or more separate processing chambers. In one or more embodiments, the substrate is then moved to another processing chamber for further processing. The substrate can be moved directly from the physical vapor deposition chamber to the separate processing chamber, or the substrate can be moved from the physical vapor deposition chamber to one or more transfer chambers and then to the separate processing chamber. Therefore, the processing apparatus may include multiple chambers communicating with a transfer station. This type of apparatus may be referred to as a "cluster tool" or "cluster system," etc.

[0083] Typically, clustering tools are modular systems comprising multiple chambers that perform various functions, including substrate centering and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, the clustering tool includes at least a first chamber and a central transfer chamber. The central transfer chamber houses a robot that can shuttle the substrate back and forth between the processing chamber and the load-locking chamber. The transfer chamber is typically maintained under vacuum and provides an intermediate stage for transporting the substrate from one chamber to another and / or to the load-locking chamber located at the front end of the clustering tool.

[0084] Two well-known clustering tools applicable to this invention are Centura® and Endura®, both of which are available from Applied Materials, Inc., of Santa Clara, California. However, the exact arrangement and combination of chambers can be varied for the purpose of performing specific steps of the process as described herein. Other processing chambers that can be used include, but are not limited to, circulating layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal treatments (such as RTP), plasma nitriding, degassing, orientation, hydroxylation, and other substrate treatments. By processing within chambers on a clustering tool, contamination of the substrate surface by atmospheric impurities can be avoided without oxidation prior to the deposition of subsequent films.

[0085] According to one or more embodiments, the substrate is continuously under vacuum or "load-locked" conditions and is not exposed to ambient air when moved from one chamber to the next. Therefore, the transfer chamber is under vacuum and is "evacuated" under vacuum pressure. An inert gas may be present in the processing chamber or transfer chamber. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants. According to one or more embodiments, purge gas is injected at the outlet of the deposition chamber to prevent reactants from moving from the deposition chamber to the transfer chamber and / or additional processing chamber. Therefore, the flow of inert gas forms a curtain at the chamber outlet.

[0086] Substrates can be processed in a single substrate deposition chamber, where a single substrate is loaded, processed, and unloaded before another substrate is processed. Substrates can also be processed in a continuous manner, similar to a conveyor system, where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shapes of the chambers and associated conveyor systems can form straight or curved paths. Alternatively, the processing chamber can be a disc conveyor belt in which multiple substrates move about a central axis and are exposed to processes such as deposition, etching, annealing, and cleaning throughout the disc conveyor belt path.

[0087] During processing, the substrate may be heated or cooled. This heating or cooling can be achieved by any suitable means, including but not limited to changing the temperature of the substrate support and allowing heated or cooled gas to flow to the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to conductively change the substrate temperature. In one or more embodiments, the employed gas (reactive or inert gas) is heated or cooled to locally change the substrate temperature. In some embodiments, the heater / cooler is located within a chamber adjacent to the substrate surface to convectively change the substrate temperature.

[0088] During processing, the substrate can be stationary or rotating. A rotating substrate can be rotated continuously or in discrete steps. For example, the substrate can be rotated throughout the entire process, or it can be rotated in small increments between exposures to different reactive or purge gases. Rotating the substrate during processing (continuously or in stages) can help produce more uniform deposition or etching by minimizing the effects of local variability in, for example, gas flow geometry.

[0089] Additional embodiments of this disclosure relate to a processing tool 900 for forming the device and practicing the method, such as Figure 3 As shown. The clustering tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are located within the central transfer stations 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0090] The cluster tool 900 includes multiple processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as processing stations, which are connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers can be any suitable chamber, including but not limited to physical vapor deposition chambers, UV curing chambers, ICP chambers, etching chambers, etc. The specific arrangement of the processing chambers and components may vary depending on the cluster tool and should not be considered as limiting the scope of this disclosure.

[0091] In some embodiments, the swarm tool 900 includes at least one physical vapor deposition chamber. In some embodiments, the swarm tool 900 includes a physical vapor deposition chamber having a remote plasma source connected to a central transfer station.

[0092] exist Figure 3In the illustrated embodiment, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a load chamber 954 and an unload chamber 956 located on the front 951 of the factory interface 950. Although the load chamber 954 is shown on the left and the unload chamber 956 is shown on the right, those skilled in the art will understand that this is merely one possible configuration representation.

[0093] The size and shape of the loading chamber 954 and the unloading chamber 956 can vary depending on, for example, the substrate being processed in the clustering tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette in which multiple wafers are located.

[0094] Robot 952 is located within factory interface 950 and can move between load chamber 954 and unload chamber 956. Robot 952 is capable of transferring wafers from a cassette in load chamber 954 to a load locking chamber 960 via factory interface 950. Robot 952 is also capable of transferring wafers from load locking chamber 962 to a cassette in unload chamber 956 via factory interface 950. As those skilled in the art will understand, factory interface 950 may have more than one robot 952. For example, factory interface 950 may have a first robot that transfers wafers between load chamber 954 and load locking chamber 960; and a second robot that transfers wafers between load locking chamber 962 and unload chamber 956.

[0095] The clustering tool 900 shown has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 via load-locking chambers 960, 962. The first section 920 includes a first transfer chamber 921 in which at least one robot 925 is placed. The robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load-locking chambers 960, 962, processing chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the robot 925 is a multi-armed robot capable of independently moving more than one wafer at a time. In some embodiments, the first transfer chamber 921 includes more than one robotic wafer transfer mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are transported on wafer transfer blades located at the distal end of the first robotic mechanism.

[0096] After the wafer is processed in the first section 920, it can be transferred to the second section 930 via a pass-through chamber. For example, chambers 922 and 924 can be unidirectional or bidirectional pass-through chambers. Pass-through chambers 922 and 924 can be used, for example, to cryogenically cool the wafer before processing in the second section 930, or to allow wafer cooling or post-processing before being moved back to the first section 920.

[0097] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918 and the second plurality of processing chambers 906, 908, 910, 912 and 914.

[0098] The system controller 990 can be any suitable component capable of controlling the processing chamber and the robot. For example, the system controller 990 can be a computer including a central processing unit (CPU) 992, memory 994, input / output (I / O) 996, and support circuitry 998. The controller 990 can directly control the processing tool 900, or control the processing tool 900 via a computer (or controller) associated with a specific processing chamber and / or support system component.

[0099] In one or more embodiments, the controller 990 may be a general-purpose computer processor of any type, which can be used in an industrial environment to control various chambers and subprocessors. The memory 994 or computer-readable medium of the controller 990 may be one or more readily available memories, such as non-transitory memory (e.g., random access memory (RAM)), read-only memory (ROM), floppy disk, hard disk, optical storage media (e.g., optical disc or digital video disk), flash drive, or any other form of local or remote digital storage device. The memory 994 may store an instruction set that can be operated by a processor (CPU 992) to control the parameters and components of the processing tool 900.

[0100] Support circuitry 998 is coupled to CPU 992 to support the processor in a conventional manner. This circuitry includes cache, power supply, clock circuitry, input / output circuitry, and subsystems. One or more processes may be stored as software programs in memory 994, which, when executed or invoked by the processor, cause the processor to control the operation of processing tool 900 or individual processing units in the manner described herein. The software programs may also be stored and / or executed by a second CPU (not shown), located remotely from the hardware controlled by CPU 992.

[0101] Some or all of the processes and methods disclosed herein can also be performed in hardware. Thus, the process can be implemented as software and executed using a computer system, implemented as hardware, as an application-specific integrated circuit (ASIC) or other type of hardware, or as a combination of software and hardware. When executed by a processor, the software program transforms a general-purpose computer into a dedicated computer (controller) that controls the chamber operation, thereby enabling the process to be performed.

[0102] In some embodiments, the controller 990 has one or more configurations to perform individual processes or sub-processes to perform the method. The controller 990 may be connected to an intermediate component and configured to operate the intermediate component to perform the functions of the method. For example, the controller 990 may be connected to a physical vapor deposition chamber and configured to control the physical vapor deposition chamber.

[0103] The process can typically be stored as a software program in the memory 994 of the system controller 990, which, when executed by a processor, causes the processing chamber to perform the process of this disclosure. The software program can also be stored and / or executed by a second processor (not shown), located remotely from the hardware controlled by the processor. Some or all of the methods in this disclosure can also be executed in hardware. Thus, the process can be implemented as software and executed using a computer system, implemented as hardware, as an application-specific integrated circuit (ASIC) or other type of hardware, or as a combination of software and hardware. When executed by a processor, the software program transforms a general-purpose computer into a dedicated computer (controller) that controls the chamber operation, enabling the process to be executed.

[0104] In some embodiments, the system controller 990 has a configuration for controlling a physical vapor deposition chamber to deposit a film on a wafer at a temperature ranging from about 20°C to about 400°C and for controlling a remote plasma source to form a polysilazane film on the wafer.

[0105] In one or more embodiments, the processing tool includes: a central transfer station including a robot configured to move a wafer; a plurality of processing stations, each connected to the central transfer station and providing a processing area separate from the processing areas of adjacent processing stations, the plurality of processing stations including a physical vapor deposition chamber and a remote plasma source; an ultraviolet curing chamber; an ICP chamber; and a controller connected to the central transfer station and the plurality of processing stations, the controller being configured to activate the robot to move the wafer between the processing stations and to control the processes occurring in each processing station.

[0106] Unless otherwise specified herein or obviously contradicted by the context, the use of the terms “a,” “one,” and “the,” and similar indicator words, in the context of describing the materials and methods discussed herein (especially in the context of the following claims), shall be construed as covering both the singular and plural. Unless otherwise indicated herein, the description of value ranges herein is intended only as a shorthand method of referring to each individual value falling within that range, and each individual value is incorporated into this specification as if it were separately referenced herein. Unless otherwise stated herein or obviously contradicted by the context, all methods described herein may be performed in any suitable order. The use of any and all examples or exemplary language (e.g., “such as”) provided herein is intended only to better elucidate the materials and methods and does not constitute a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0107] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, a particular feature, structure, material, or characteristic may be combined in any suitable manner.

[0108] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method of forming a film on a semiconductor substrate, the method comprising: exposing a surface of the semiconductor substrate to an aromatic precursor in a process chamber; purging the process chamber of the aromatic precursor; heating the semiconductor substrate to a temperature less than 600 °C to polymerize the aromatic precursor and deposit a graphene hardmask film on the semiconductor substrate; and purging the process chamber, wherein the aromatic precursor is selected from one or more of naphthalene, 2,6-dibromonaphthalene, 1,3,5-benzene tricarboxylic acid trimethyl ester, 9,10-dibromoanthracene, benzoic acid, 2,6-di-tert-butyl naphthalene, 1,3,5-trimethoxybenzene, and hexabromobenzene.

2. The method of claim 1, wherein the semiconductor substrate comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), silicon (Si), cobalt (Co), titanium (Ti), silicon dioxide (Si02), copper (Cu), and a low dielectric constant dielectric material.

3. The method of claim 1, further comprising repeating the method to provide a graphene hardmask film having a thickness of 0.3 nm to 100 nm.

4. The method of claim 1, further comprising exposing the semiconductor substrate to a reactant.

5. The method of claim 4, wherein the semiconductor substrate is simultaneously exposed to the aromatic precursor and the reactant.

6. The method of claim 4, wherein the semiconductor substrate is sequentially exposed to the aromatic precursor and the reactant.

7. A method of forming a film on a semiconductor substrate, the method comprising: forming a flowable graphene hardmask film on a surface of the semiconductor substrate by exposing the semiconductor substrate to an aromatic precursor, wherein the flowable graphene hardmask film is formed; and exposing the semiconductor substrate to a plasma, wherein the aromatic precursor is selected from one or more of naphthalene, 2,6-dibromonaphthalene, 1,3,5-benzene tricarboxylic acid trimethyl ester, 9,10-dibromoanthracene, benzoic acid, 2,6-di-tert-butyl naphthalene, 1,3,5-trimethoxybenzene, and hexabromobenzene.

8. The method of claim 7, wherein the semiconductor substrate comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), silicon (Si), cobalt (Co), titanium (Ti), silicon dioxide (Si02), copper (Cu), and a low dielectric constant dielectric material.

9. The method of claim 7, wherein the plasma is a remote plasma.

10. The method of claim 7, wherein the plasma comprises one or more of ammonia (NH3), nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), carbon monoxide (CO), or carbon dioxide (C02).

11. The method of claim 7, wherein the substrate is maintained at a temperature in a range of about 150 °C to about 700 °C or in a range of about 300 °C to about 500 °C.

12. The method of claim 7, further comprising repeating the method to provide a graphene hard mask film having a thickness of about 0.3 nm to about 100 nm.

13. A non-transitory computer readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to: expose a semiconductor substrate to an aromatic precursor in the processing chamber; purge the processing chamber of the aromatic precursor; heat the semiconductor substrate to a temperature less than 600 °C to polymerize the aromatic precursor and deposit a graphene hard mask film on the substrate; and purge the processing chamber, wherein the aromatic precursor is selected from one or more of naphthalene, 2,6-dibromonaphthalene, 1,3,5-benzenetricarboxylic acid trimethyl ester, 9,10-dibromoanthracene, benzoic acid, 2,6-di-tert-butyl-naphthalene, 1,3,5-trimethoxybenzene, and hexabromobenzene.

14. The non-transitory computer readable medium of claim 13, wherein the semiconductor substrate comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), silicon (Si), cobalt (Co), titanium (Ti), silicon dioxide (SiO2), copper (Cu), and a low dielectric constant dielectric material.

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