Semiconductor device and semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor arrangement comprising a wafer (1) having a preferably monolithic semiconductor substrate, in particular a silicon substrate (2), and at least one integrated electronic component (3) extending within and / or on the semiconductor substrate (2), the wafer (1) comprising a front-end process (5) having the integrated electronic component (3) or at least one integrated electronic component, and comprising a back-end process (6) located above the front-end process (5) and a photonic platform (8) manufactured on a side (9) of the wafer (1) facing away from the front-end process (5), the platform comprising at least one waveguide (12) and at least one electro-optical device (15), in particular at least one photodetector and / or at least one electro-optical modulator, wherein the electro-optical device (15) or at least one electro-optical device of the photonic platform (8) is connected to the integrated electronic component (3) or at least one integrated electronic component of the wafer (1).

Description

[0001] This application is a divisional application of application number 202080095177.8, filed on December 21, 2020, entitled "Semiconductor device and semiconductor apparatus and method of manufacturing thereof". Technical Field

[0002] This invention relates to semiconductor devices and methods for manufacturing the same. Furthermore, this invention relates to semiconductor apparatuses and methods for manufacturing the same. Background Technology

[0003] Data exchange within and, particularly, between chips is increasingly approaching capacity limits. The number of possible connections is constrained by available chip area and technical factors affecting manufacturability. Furthermore, the bandwidth of electrical connections is limited by electrical losses that increase dramatically with frequency. For a wide range of applications, the demand for broadband I / O (input / output) interfaces exceeds current capacity. An example of this is in so-called categorized computing, which specifically involves or includes configurable networks of CPUs or GPUs and memory, CPU-memory connections, and IoT networks for autonomous mobility. In these cases, extremely high bandwidths, typically ranging from Gb / s to Tb / s, are required.

[0004] Currently, I / O interfaces are primarily implemented electronically. This applies to fundamental areas such as memory connectivity, sensor networks (IoT), and data communication. The I / O bandwidth achievable with current technology is often insufficient to reach the required transmission rates. Fundamentally limiting physical relationships, such as electrical contact losses and minimum size, hinder significant performance improvements. Electrical losses play a crucial role, especially at high frequencies (e.g., 10 dB / m for coaxial cable in the range of around 50 GHz), compared to the negligible loss of fiber optics in the 0.1 dB / km range. A change to optical interfaces could address the bandwidth and range issues. However, manufacturing a large number of readily available, low-cost, high-performance components remains a major challenge. Currently, only silicon technology can achieve this, but it offers limited photonic functionality. III-V semiconductors are more suitable but cannot be monolithically integrated into silicon technology.

[0005] Beyond I / O interfaces, other application areas can be considered. Optical systems for machine learning, such as filters, spectrometers, or neural networks, can also be implemented. The tight integration of photonics and electronics enables novel chip architectures.

[0006] Optical interfaces for data communication have been realized to some extent through heterogeneous integration or bonding techniques of electronic and optical chips. This means that optical and electronic chips are manufactured and connected using different technologies. For this purpose, optical circuits based on III-V transition semiconductors are typically bonded to silicon wafers via electronic control circuitry. The advantage is that each circuit type can be manufactured in its optimal process. However, significant disadvantages include high cost and a strong sequential nature, making the bonding process (each chip must be bonded to the wafer one at a time) and line interruptions time-consuming. After a single chip is bonded to the wafer, the wafer cannot be further processed as a whole. The wafer is separated in the next step, and the chips are completed individually (however, the main part of the manufacturing process has already been completed).

[0007] Alternatively, silicon can be used as a starting material, and both electronic and photonic circuits can be fabricated on a single chip. However, in this case, the combination of electronic and photonic circuit technologies is fixed because the optical and electronic circuits are fabricated on the same layer. Silicon electronics and photonics are located side-by-side on a single wafer. This can be seen, for example, in the article "Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip", Nature 556, pp. 349-354 (2018), doi:10.1038 / s41586-018-0028-z. The advantage of this silicon bonding technology compared to die-on bonding or bonding strategies for III-V semiconductors is that it can significantly reduce costs and time. The disadvantage is that the performance of silicon photonic devices is generally inferior compared to III-V transition semiconductors. Another significant drawback is that the electronic and photonic technologies are fixed, thus limiting the fabrication of only certain types of microchips for technical and economic reasons.

[0008] US 2014 / 0264400 A1 discloses a semiconductor device having integrated circuits. The device includes multiple chips having integrated circuits, which are spaced apart and fixed in recesses on a carrier substrate. Planar coatings, including waveguides and photonic devices, are deposited on the chip and substrate surfaces to provide intra-chip optical interconnects for photonic devices on a single chip, or inter-chip optical interconnects for photonic devices on different chips.

[0009] Previously known semiconductor devices have proven themselves in principle. However, alternative devices are still needed. In particular, there is a need for the ability to obtain large quantities of individual chips with integrated photonics at a reasonable cost with reasonable manufacturing effort. Summary of the Invention

[0010] The object of this invention is to provide an alternative semiconductor device in which electronic circuitry and photonic components are integrated, enabling the production of a large number of chips with integrated photonics with reasonable effort. Furthermore, the object of this invention is to provide a method for manufacturing such a device.

[0011] The first mentioned objective is achieved through a semiconductor device comprising a wafer having a preferred monolithic semiconductor substrate (particularly a silicon substrate) and at least one integrated electronic component extending within and / or on the semiconductor substrate. The wafer has a front-end process and a back-end process located above the front-end process, wherein the front-end process includes the integrated electronic component or at least one of the integrated electronic components, and a photonic platform fabricated on a side of the wafer opposite to the front-end process. The photonic platform includes at least one waveguide and at least one electro-optic device, particularly at least one photodetector and / or at least one electro-optic modulator, wherein the electro-optic device of the photonic platform or at least one of the electro-optic devices is connected to the integrated electronic component of the wafer or at least one of the integrated electronic components.

[0012] The second mentioned objective is achieved through a method for manufacturing semiconductor devices, the method comprising the following steps:

[0013] A wafer is provided having a preferred monolithic semiconductor substrate, particularly a silicon substrate, and at least one integrated electronic component extending in and / or on the semiconductor substrate. The wafer has a front-end process and a back-end process located above the front-end process, wherein the front-end process includes the integrated electronic component or at least one of the integrated electronic components.

[0014] A photonic platform is fabricated on the side of the wafer away from the front-end process. The photonic platform includes at least one waveguide and at least one electro-optic device, particularly at least one photodetector and / or at least one electro-optic modulator.

[0015] In other words, the basic idea of ​​this invention is to manufacture directly on the back-end of the wafer process, and in particular to build a photonic platform with at least one waveguide and at least one electro-optic device directly on it.

[0016] In the prior art, a wafer is generally understood in a known manner as a component, element, or device of multiple chips obtained through wafer dicing, also known as wafer shards (Wafer-Zerkleinern in German). Dicing or splitting can include, for example, (laser) cutting, sawing, scribing, or breaking of the wafer. In English, a single or singular chip is also called a bare die, or a plural chip is also called a bare die or die. It should be noted that some chips after dicing are also called bare chips or bare dies. "Bare" means that the chip has not yet been packaged. A "bare" chip without a package is also called a chip.

[0017] If we observe a wafer in cross-section, its vertical structure can be divided into different sub-regions. The lowest part is the front-end process, or FEOL for short, which consists of one or more integrated electronic components. These integrated electronic components can be, for example, transistors and / or capacitors and / or resistors. Above the front-end process is the back-end process, or BEOL for short, which typically contains various metal planes through which the integrated electronic components of the FEOL are interconnected.

[0018] A wafer comprises multiple regions, each of which forms a chip or bare die after dicing / splitting / unifying. These regions are also referred to herein as chip or bare die regions. Each chip region of the wafer preferably comprises a portion or localized area of ​​a single semiconductor substrate of the wafer. Preferably, each chip region also includes one or more integrated electronic components extending within and / or on the corresponding region of the semiconductor substrate, particularly in FEOL when viewed in cross-section. It should be emphasized that a chip region does not represent isolated chips; that is, the wafer does not contain isolated chips.

[0019] The integrated electronic components in some (especially all) chip regions of a wafer can be identical. In this case, multiple identical chips with a photonic platform fabricated thereon (or in some part of it in each case) can be obtained from the device according to the invention by dicing.

[0020] There are one or more markings on the wafer, and cutting can or must be done along these markings.

[0021] In the context of this invention, the photonic platform can be built directly on the wafer, even before the wafer is diced (cut) into individual chips. Because the photonic platform is fabricated, particularly built, on the wafer in the device according to the invention, a large number of chips with integrated photonics can subsequently be obtained simply by dicing. Dicing can be performed in the same manner as conventional wafers without a photonic platform in the back-end processes. In particular, existing equipment or facilities can be used for this purpose. Therefore, with reasonable effort, individual chips with photonics can also be mass-produced.

[0022] The side of the wafer away from the front-end process on which the photonic platform is being or will be fabricated can also be referred to as the upper side of the wafer. In useful embodiments, the device according to the invention is characterized in that the photonic platform region fabricated thereon extends above a plurality (particularly each) chip region of the wafer, each platform region conveniently including at least one (preferably a plurality) waveguide and at least one (preferably a plurality) electro-optic device, said electro-optic device being connected to at least one integrated electronic component or circuit of a corresponding lower chip region.

[0023] The photonic platform advantageously includes multiple functional units, and it is particularly preferred that at least one (especially exactly one) of the functional units extending over the respective chip regions is assigned to each chip region of the wafer.

[0024] According to the present invention, the photonic platform is manufactured in the back-end of the wafer fabrication process, particularly after the (conventional) wafer fabrication process is fully completed. In particular, in this case, it can be performed without adjusting the (conventional) wafer fabrication steps. The photonic platform fabrication can also be performed completely separately from (conventional) wafer fabrication. Therefore, it offers a high degree of flexibility.

[0025] The integrated electronic components extend in and / or on the semiconductor substrate of the wafer of the device according to the invention, specifically meaning that they are arranged within and / or directly on the substrate. Of course, it is possible that the integrated electronic components extend in portions within the substrate and portions directly on the substrate, for example, extending directly on one or more sides of the substrate.

[0026] The semiconductor substrate of the semiconductor device according to the present invention is preferably a monolithic substrate. In particular, a monolithic substrate. The substrate can be fabricated in multiple layers.

[0027] The semiconductor substrate may also be characterized by a circumference. Optionally or additionally, the diameter of the semiconductor substrate may be in the range of 50 mm to 600 mm, preferably 100 mm to 500 mm. Exemplary diameters include 150 mm, 200 mm, 300 mm and 450 mm.

[0028] The fact that photonic platforms are manufactured at the back end, on a different level from the front-end electronic devices, offers a significant advantage: photonic devices do not require additional space (also known as "substrate surface"). Therefore, the problem of limited substrate surface that sometimes exists is not further exacerbated at the front end.

[0029] Photonic platforms are fabricated on wafers, meaning they are fabricated directly on the wafer. This includes, for example, the deposition / stacking of material directly on the wafer. Preferably, the photonic platform is characterized by material deposited on the side of the wafer facing away from the front-end processes. Therefore, in the method according to the invention, the fabrication of the photonic platform can be configured to include depositing material on the side of the wafer facing away from the front-end processes. In particular, the photonic platform is not or has not yet been fabricated independently of the wafer, for example on another substrate, and then transferred to the wafer and, for example, bonded to the wafer by bonding. Conversely, the photonic platform is or has already been obtained on the wafer.

[0030] Apart from one or more electro-optical devices or at least one of them, the photonic platform of the semiconductor device of the present invention may not have a bonding layer.

[0031] In a particularly advantageous embodiment, the photonic platform includes a planarization coating composed of a dielectric material. This is preferably fabricated on a side of the wafer facing away from the front-end processes. More preferably, a waveguide or at least one of the waveguides can be fabricated on the side of the planarization coating facing away from the wafer.

[0032] Therefore, a more detailed feature of the method according to the invention is that the fabrication of the photonic platform includes: fabricating a planarization coating composed of a dielectric material, particularly on the side of the wafer opposite to the front-end process.

[0033] The planarization coating of the photonic platform configured according to these embodiments can form the basis of one or more photonic layers or planes, each photonic layer or plane preferably including at least one waveguide and / or at least one electro-optical device.

[0034] Then, preferably, a waveguide or at least one of the waveguides can be fabricated on the side of the planarization coating away from the wafer.

[0035] Fabrication of at least one waveguide may also include applying a waveguide material, preferably by deposition, spin coating, or transfer, particularly on the side of the wafer away from the planarization coating, and then preferably structuring the deposited waveguide material, particularly by photolithography and / or reactive ion etching. For example, the same deposition process described below in conjunction with the planarization coating can be used.

[0036] If the photonic platform includes a planarization coating disposed in the back-end process, the planarization coating is not fabricated independently of the wafer (e.g., on another substrate) and then transferred to the wafer and bonded to it by bonding (e.g., via bonding). Instead, the photonic platform is or has already been obtained thereon. Therefore, it can also be said that the planarization coating is a monolithic layer, particularly a layer monolithically attached to the wafer.

[0037] In a further detailed description, the planarization coating has a roughness of less than 2.0 nm RMS, preferably less than 1.0 nm RMS, and particularly preferably less than 0.3 nm RMS on its side facing away from the wafer. For example, the lower limit can be 0.01 nm RMS. In other words, the roughness can be, for example, in the range of 2.0 nm RMS to 0.01 nm RMS, preferably in the range of 1.0 nm RMS to 0.01 nm RMS, and particularly preferably in the range of 0.3 nm RMS to 0.01 nm RMS. The abbreviation nm is used herein and hereinafter to represent nanometer (10 nm) in a manner known per se. -9 The abbreviation RMS stands for Root Mean Square. Root mean square roughness is also known as "quadradische Rauheit" in German.

[0038] In another embodiment of the device according to the invention, the planarization coating comprises or consists of spin-coated glass and / or at least one polymer and / or at least one oxide (particularly silicon dioxide) and / or at least one nitride. Therefore, the method according to the invention may include manufacturing a planarization coating comprising or consisting of spin-coated glass and / or at least one polymer and / or at least one oxide, particularly silicon dioxide and / or at least one nitride.

[0039] Spin-coated glass is typically a liquid substance that can be coated onto wafers using a spin-coating process. After spin-coating, a layer forms on the wafer, the thickness of which depends on the surface profile. Recesses are thus partially compensated, resulting in a planarization effect. Spin-coated glass is usually heated after deposition to form a glass-like layer.

[0040] Optionally or additionally, a planarization coating may be specified to be formed by deposition, particularly chemical vapor deposition (CVD), preferably low-pressure chemical vapor deposition (LPCVD) and / or plasma-enhanced chemical vapor deposition (PECVD), and / or by physical vapor deposition of a coating material on the side of the wafer away from the front-end process, and preferably by chemical mechanical polishing and / or by photoresist planarization on the side away from the wafer to form a planarization coating.

[0041] In the method according to the invention, it can be correspondingly specified that, as part of the planarization coating fabrication, at least one coating material is deposited on the side of the wafer away from the previous process, particularly by chemical vapor deposition, preferably low-pressure chemical vapor deposition and / or plasma-assisted chemical vapor deposition, and / or by physical vapor deposition. Preferably, the deposited material is then chemically mechanically polished and / or photoresist planarized on the side away from the wafer, particularly preferably in such a manner as to obtain a roughness of less than 2.0 nm, preferably less than 1.0 nm RMS, and especially preferably less than 0.3 nm RMS. Chemical mechanical polishing and / or photoresist planarization can be particularly performed in such a manner as to obtain a roughness in the range of 2.0 nm RMS to 0.01 nm RMS, preferably in the range of 1.0 nm RMS to 0.01 nm RMS, and especially preferably in the range of 0.3 nm RMS to 0.01 nm RMS.

[0042] The roughness of these regions has proven to be particularly suitable. This roughness is especially advantageous in preventing stress and strain in the overlying layers. In this regard, reference is also made to the paper "Identifying suitable substrates for high-quality graphene-based heterostructures" by L. Banszerus et al., 2D Mater., Vol. 4, No. 2, 025030, 2017.

[0043] Atomic force microscopy (AFM) can be used as a method for determining roughness, particularly as described in EN ISO 25178. Atomic force microscopy is mainly discussed in Part 6 of this standard (EN ISO 25178-6:2010-01), which relates to methods for determining roughness.

[0044] Various prior art chemical vapor deposition processes exist, all of which can be used in this invention. What all these processes have in common is generally the introduction of a chemical reaction of a gas, which leads to the deposition of the desired material. Furthermore, regarding physical vapor deposition, all variations known in the prior art can be used. By way of example only, electron beam evaporation (where the material is melted and evaporated by an electron beam), thermal evaporation (where the material is heated to its melting point by a heater and evaporated onto a target substrate), and sputtering deposition (where atoms are detached from a material carrier by plasma and deposited onto the target substrate) can be mentioned.

[0045] As an alternative to or supplement to the above deposition processes, atomic layer deposition is also possible. In this process, insulating or conductive materials (dielectrics, semiconductors, or metals) are deposited in atomic layer sequence.

[0046] In chemical mechanical polishing (CMP), the object to be polished, such as a wafer, is typically polished through the rotational motion between polishing pads. Polishing is achieved through both chemical methods and physical treatment using polishing paste. By combining chemical and physical actions, sub-nanometer-scale smooth surfaces can be obtained.

[0047] Specifically, resist planarization involves a single or repeated spin-coated glass deposition followed by etching, preferably reactive ion etching (RIE). If planarization of a surface with height differences (e.g., a SiO2 surface) is desired, it can be achieved through spin-coated glass deposition and etching. The spin-coated glass coating partially compensates for the height difference; that is, after the spin-coated glass coating, the valleys of the topology have a higher coating thickness than adjacent ridges. In a suitable RIE process, the etching rates of the spin-coated glass and, for example, SiO2 are similar or the same. "Suitable" here specifically refers to the appropriate selection of pressure, gas flow, gas mixture composition, and power. If the entire spin-coated glass coating is etched by RIE after the spin-coated glass coating, the height difference is reduced due to the planarization effect of the spin-coated glass coating. By repeating the steps, the height difference can be further reduced. When depositing a SiO2 coating, the thickness of the SiO2 coating consumed must be considered so that the desired SiO2 coating thickness is achieved after the final etching step. It should be emphasized that resist planarization is not limited to SiO2 and can also be considered for other materials. It is convenient if a material etching rate similar to, or at least substantially the same as, that of spin-coated glass can be achieved. SiO2 and spin-coated glass satisfy this condition. It should be noted, for example, that the etching rate of the material can differ from that of spin-coated glass by a factor of two, in which case several steps are typically required. Hydrogen silsesquioxanes and / or polymers, for example, can be applied as liquid materials (especially in spin-coating). They vitrify during subsequent annealing, which is why they are also called spin-coated glasses. Hydrogen silsesquioxanes (HSQ) are a class of materials with the molecular formula [HSiO2]. 3 / 2 ] n Inorganic compounds.

[0048] In a further advantageous embodiment, the photonic platform includes at least one additional planarization coating. This planarization coating, or at least one of the additional planarization coatings (in many cases), can then preferably be made of the same material as the planarization coating. It can also be or be manufactured in the same manner as the planarization coating. However, this should be understood as optional and not limiting.

[0049] Additional planarization coatings (in many cases) or one of the additional planarization coatings may be arranged or fabricated in at least one waveguide and / or planarization coating arrangement.

[0050] In the method according to the invention, it may be stipulated that, preferably, at least one additional planarization coating is manufactured after at least one waveguide is manufactured. The manufacture of the at least one additional planarization coating particularly preferably includes coating (specifically depositing) a coating material onto the at least one waveguide and / or the side of the planarization coating opposite to the wafer.

[0051] Much like the planarization coating, the coating material of the additional planarization coating may be or has been planarized at least on its side facing away from the wafer, particularly through chemical mechanical polishing and / or resist planarization. Again, this is or has preferably been done in such a manner that a roughness of less than 2.0 nm, preferably less than 1.0 nm RMS, and particularly preferably less than 0.3 nm RMS is obtained on the side facing away from the wafer. Also with respect to at least one additional planarization coating, it is preferred that the chemical mechanical polishing and / or resist planarization be performed in such a manner that a roughness in the range of 2.0 nm RMS to 0.01 nm RMS, preferably in the range of 1.0 nm RMS to 0.01 nm RMS, and particularly preferably in the range of 0.3 nm RMS to 0.01 nm RMS is obtained.

[0052] The fabrication of a planarization coating and / or additional planarization coatings may also include applying additional coating material to the treated side after the planarization process. The treated side may also be referred to as the upper side.

[0053] Furthermore, it may be specified that a planarization coating and / or an additional planarization coating, or an additional planarization coating comprising one or more overlays, are preferably disposed on the planarized surface and may be, for example, an aluminum chloride layer or an aluminum chloride heterostructure, or may also be a boron nitride layer. It is preferable to deposit or transfer these materials without requiring further chemical mechanical polishing or further resist planarization, although re-performing such a process is not excluded.

[0054] Of course, a photonic platform may include layers other than one or more planarization coatings and / or one or more top coatings.

[0055] A coating may consist of only one or more layers. The coating may consist of only one material, or it may include several materials. For example, a coating may have two or more layers of two or more different materials. Of course, a coating may also have multiple layers, but they may all be made of the same material. In particular, coatings with more than one layer can be obtained or exist because multiple layers (e.g., multiple atomic layers) are provided or deposited for the manufacture of the coating.

[0056] Furthermore, also regarding the waveguides of the devices according to the invention, these waveguides are not bonded to an underlying coating, but are instead in the underlying coating, particularly a planarization coating, or also fabricated on the wafer. For example, the planarization coating provides or has provided a suitable waveguide material, for example, constructed or deposited in the planarization coating, and then, if necessary, the waveguide can be constructed by, for example, photolithography and / or etching. Photolithography preferably involves applying a photoresist in a manner known per se, particularly by spin-coating it and exposing it, especially to ultraviolet light. Unexposed portions can be conveniently covered with a mask. After development, the structure on the mask is transferred to the photoresist coating.

[0057] Waveguides, or at least one or all of them, may be embedded in a coating and / or extend between two coatings. For example, one or more waveguides may be considered to be embedded in an additional planarization coating or at least one of additional planarization coatings. For example, one or more waveguides extending between two coatings and embedded in the coating can be obtained by fabricating a waveguide on a side of the planarization coating away from the wafer, and then fabricating another planarization coating on the waveguide, said fabrication including applying (particularly depositing) a coating material to the waveguide and the uncovered areas of the underlying planarization coating.

[0058] In a preferred embodiment, the waveguide of the photonic platform, or at least one of several waveguides, comprises or is composed of at least one material transparent to electromagnetic radiation at wavelengths of 850 nm and / or 1310 nm and / or 1550 nm. Particularly preferably, the material is transparent to electromagnetic radiation in the wavelength range of 800 nm to 900 nm and / or 1260 nm to 1360 nm (referred to as the original band or O-band) and / or 1360 nm to 1460 nm (referred to as the extended band or E-band) and / or 1460 nm to 1530 nm (referred to as the short-wave band or S-band) and / or 1530 nm to 1565 nm (referred to as the conventional band or C-band) and / or 1565 nm to 1625 nm (referred to as the long-wave band or L-band). These bands are known in the field of communications engineering.

[0059] In a further advantageous embodiment, at least one of the waveguides, or in many cases, of the photonic platform of the semiconductor device according to the invention may comprise titanium dioxide and / or aluminum nitride and / or tantalum pentoxide and / or silicon nitride and / or aluminum oxide and / or silicon oxynitride and / or lithium niobate and / or silicon, particularly polycrystalline silicon and / or indium phosphite and / or gallium arsenide and / or indium gallium arsenide and / or aluminum gallium arsenide and / or at least one dichalcogenide, particularly two-dimensional transition metal dichalcogenides, and / or chalcogenide glass and / or resin or resin-containing materials, particularly SU8, and / or polymer or polymer-containing materials, particularly OrmoComp, or composed of one or more of these materials. In the method according to the invention, at least one waveguide is preferably manufactured that comprises or is composed of one of these materials, or comprises or is composed of a combination of one or more of these materials.

[0060] At least one waveguide advantageously comprises or is composed of a material whose refractive index differs from that of one or more materials of the planarization coating and / or additional planarization coating (if present). This is particularly true if at least one waveguide has a common interface with the planarization coating and / or additional planarization coating.

[0061] Pure exemplary refractive index pairs include 3.4 (Si) for the waveguide and 1.5 (SiO2) for the planarization coating, or in the case of a dielectric, 2.4 (TiO2) for the waveguide and 1.5 (SiO2) for the planarization coating, or 2 (SiN) for the waveguide and 1.47 for the planarization coating.

[0062] If at least one additional planarization coating is provided, it can also be applied to additional planarization coatings, i.e., those composed of or comprising materials with a refractive index different from that of at least one waveguide material. This is particularly applicable to cases in contact with at least one waveguide, i.e., having or forming a common interface with the latter.

[0063] Particularly preferred is that the refractive index of the waveguide material is at least 20% greater than that of the material of the planarization coating and / or the additional planarization coating, preferably at least 30%.

[0064] In other words, in these embodiments, a refractive index contrast has been or is being achieved between at least one waveguide and a planarization coating and / or at least one waveguide and an additional planarization coating (if present).

[0065] A waveguide is an element or component that guides electromagnetic waves (especially light). To guide these waves, it is advantageous to provide a material with a wavelength-dependent cross-section that is optically transparent at least for that wavelength and is distinguished from adjacent materials that are also transparent to that wavelength by means of refractive index contrast. If the surrounding material has a lower refractive index, light will be guided in the region with the higher refractive index. In the special case of slit mode, two regions with high refractive indices are separated from a narrower region with low refractive indices relative to the wavelength, and light is guided in the low refractive index region. Low sidewall roughness is advantageous to achieve low scattering loss.

[0066] Regarding waveguide dimensions, the following may be particularly applicable. The thickness is preferably in the range of 150 nanometers to 10 micrometers. The width and length of the waveguide, i.e., the lateral extent parallel to the wafer surface, are particularly suitable in the range of 100 nanometers and 10 micrometers.

[0067] For example, one or more waveguides can be designed as strip waveguides, characterized by having a rectangular or square cross-section. Optionally or additionally, one or more waveguides can be formed as ridge waveguides with a T-shaped cross-section. Further optionally or additionally, one or more waveguides can be provided as slotted waveguides.

[0068] The waveguides of the device according to the invention may (e.g., viewed in cross-section) comprise several portions or segments, and may be formed as several portions, for example, comprising or consisting of a first segment (e.g., below or left side) and a second segment (e.g., above or right side), in other words, portions or sections. One or more waveguide segments may have rectangular or square cross-sections. If the waveguide comprises or consists of two or more segments, these segments may be adjacent to or merged with each other, or spaced apart, for example, forming gaps or grooves.

[0069] The photonic platform provided according to the invention advantageously includes multiple waveguides. It can then be further specified that at least two waveguides extend, at least in one portion, one above the other. In other words, there are two or more waveguide planes, or they are “stacked” on each other, thereby further saving space and allowing for more complex circuitry with extended functionality.

[0070] Furthermore, passive structures can be made from waveguides, such as multimode interferometric couplers (MMIs), i.e., interference-based 50:50 beam splitters, or directional couplers, where two waveguides extend side-by-side over a certain length and guide light from one directional coupler to the other. For example, a Mach-Zehnder interferometer (2 × 50 / 50 MMIs as beam splitters with two arms in the middle) can also be obtained.

[0071] A further embodiment is characterized in that, in addition to at least one electro-optical device, the photonic platform also includes at least one optical device, particularly at least one interferometer, such as a Mach-Zehnder interferometer, and / or at least one interference coupler, such as a multimode interference coupler, and / or at least one directional coupler and / or at least one polarization converter and / or at least one beam splitter and / or at least one ring resonator. The at least one optical device preferably comprises or is formed of one or more waveguides and / or waveguide portions. In particular, viewed longitudinally from the waveguide, the optical device may comprise only a portion or part of the waveguide, i.e., the longitudinal portion. An optical device formed as a ring resonator advantageously comprises a preferably independent, ring-shaped waveguide forming the resonator, and a preferably straight waveguide portion coupled to the waveguide. Coupling can be achieved by a directional coupler, which preferably comprises or is formed of a region in which the distance between the ring-shaped waveguide and the straight waveguide portion allows light to couple between them.

[0072] Therefore, the method according to the invention is characterized by manufacturing at least one optical device, preferably at least one interferometer, such as a Mach-Zehnder interferometer, and / or at least one interference coupler, such as a multimode interference coupler, and / or at least one directional coupler and / or at least one polarization converter and / or at least one beam splitter and / or at least one ring resonator.

[0073] Furthermore, the photonic platform may include one or more thermo-optical devices. Such devices include, for example, a heating element and a longitudinal portion of a waveguide, with the heating element arranged relative to the waveguide portion such that it can heat the waveguide portion. For example, the heating element may be an element whose temperature rises when current passes through it. For example, the heating element may be arranged near the waveguide. Heating the waveguide by the heating element can change the refractive index of the waveguide. For example, this effect can be used for phase matching. The thermo-optical devices may also be associated with or constitute part of an interferometer of the photonic platform.

[0074] In a further embodiment, the photonic platform has a passivation coating and / or cladding on its side facing away from the wafer. The photonic platform preferably terminates at the passivation coating and / or cladding. In other words, the passivation coating and / or cladding forms the final or top coating of the photonic platform.

[0075] The cladding is particularly well-suited for or designed to have a slightly lower refractive index contrast so that the roughness of the sidewalls does not have a significant impact; typically, the loss returns to the waveguide.

[0076] Passivating coatings are preferably used to protect devices or circuits from environmental influences, particularly water. For example, passivating coatings can be composed of dielectric materials. Alumina (Al₂O₃) and silicon dioxide (SiO₂) have proven to be particularly suitable.

[0077] The final passivation coating on the upper layer advantageously has openings or interruptions leading to contacts on the lower layer to achieve electrical connection. These openings or interruptions in the passivation coating can be, or have been, obtained through, for example, photolithography and / or etching, particularly reactive ion etching.

[0078] Reactive ion etching (RIE) is a dry etching process in which a substrate surface is selectively and directionally etched by a special gaseous chemical substance that excites a plasma. A resist mask is used to protect areas that do not need to be etched. The etching chemistry and process parameters typically determine the selectivity of the process, i.e., the etching rate of different materials. This property is crucial for limiting the depth of the etching process and thus confines the coatings to each other.

[0079] In a further advantageous embodiment, the semiconductor device according to the invention is characterized in that the back-end process of the wafer and photonic platform includes interconnect elements, and at least one of the integrated circuits of the wafer is connected to an electro-optic device of the photonic platform or at least one of the electro-optic devices via the interconnect elements.

[0080] Therefore, in the method according to the invention, in an advantageous further development, it can be specified that the back-end process of the provided wafer includes interconnect elements connected to at least one of the integrated circuits or integrated circuits of the front-end process, and the interconnect elements are manufactured in a connected photonic platform, said interconnect elements being connected on one hand to the interconnect elements of the back-end process, and on the other hand to an electro-optic device or at least one of the electro-optic devices.

[0081] Interconnect elements can be, in particular, vertical electrical interconnects, also known as vertical interconnect pathways, or Vias or VIAs. VIAs are typically defined by photolithography and dry chemical etching using RIE. Subsequently, metallization is preferred, and the metallized surface is constructed by CMP (Catalyst Processing) or by photolithography and RIE.

[0082] Interconnecting elements advantageously include or consist of at least one conductive material, particularly a metal, such as copper and / or aluminum and / or tungsten.

[0083] In a further embodiment, the electro-optic device or at least a portion thereof may also be fabricated on one or more waveguides and / or on the sides of a planarization coating away from the wafer and / or on the sides of another planarization coating away from the wafer (if present).

[0084] The electro-optic device of the semiconductor device according to the present invention can, in principle, be any device designed to generate and / or transmit and / or receive optical signals. In particular, the electro-optic device can or may be a device for optical data communication, and / or a spectrometer, and / or a tunable electro-optic filter and / or a switch and / or attenuator, especially a device for machine learning. Nonlinear optical elements may also be included.

[0085] Electro-optic devices designed as filters may include, for example, ring resonators, preferably in combination with modulators.

[0086] In practical embodiments, an electro-optic device or (in many cases) at least one electro-optic device or each electro-optic device includes at least two contacts or contact elements, said contacts and contact elements being specifically used to contact active elements, or in each case for contacting active elements having interconnecting elements.

[0087] Preferably, the electro-optic device or (in many cases) at least one or each electro-optic device further includes at least one active element. In addition to at least one active element, the electro-optic device may also include a waveguide portion, particularly a longitudinal portion. The active element or a portion thereof of the electro-optic device may also form a waveguide or at least a portion, particularly a longitudinal portion of the waveguide. It is also possible that several (e.g., two) active elements or portions thereof may together form a waveguide or a portion, particularly a longitudinal portion of the waveguide, such as a ridge waveguide. Then, advantageously, one or more active elements are composed of a material transparent to electromagnetic radiation of at least one wavelength, preferably at least one wavelength range. Preferably, at least one material is then applied that is transparent to electromagnetic radiation of wavelengths of 850 nm and / or 1310 nm and / or 1550 nm. Particularly preferably, the material is transparent to electromagnetic radiation in the wavelength range of 800 nm to 900 nm and / or 1260 nm to 1360 nm (referred to as the original band or O band) and / or 1360 nm to 1460 nm (referred to as the extended band or E band) and / or 1460 nm to 1530 nm (referred to as the short band or S band) and / or 1530 nm to 1565 nm (referred to as the conventional band or C band) and / or 1565 nm to 1625 nm (referred to as the long band or L band).

[0088] If at least one active element is provided, the active element preferably comprises or is composed of at least one material that absorbs electromagnetic radiation of at least one wavelength, preferably at least one wavelength range, and generates an electro-optic signal due to absorption and / or a change in its refractive index with the presence of voltage and / or charge and / or electric field. Preferably, then at least one material capable of absorbing electromagnetic radiation with wavelengths of 850 nm and / or 1310 nm and / or 1550 nm is applied, and an optical signal is generated due to absorption. Particularly preferably, the material can absorb electromagnetic radiation in the wavelength range of 800 nm to 900 nm and / or 1260 nm to 1360 nm (referred to as the original band or O band) and / or 1360 nm to 1460 nm (referred to as the extended band or E band) and / or 1460 nm to 1530 nm (referred to as the short band or S band) and / or 1530 nm to 1565 nm (the so-called conventional band or C band) and / or from 1565 nm to 1625 nm (referred to as the long band or L band), and can generate optical signals due to absorption.

[0089] A material's change in refractive index should be understood specifically as a change in its dispersion (particularly the refractive index) and / or absorption. Dispersion or refractive index is typically given by the real part of the complex refractive index, while absorption is given by the imaginary part. Materials whose refractive index changes with the presence of voltage and / or charge and / or electric field are understood in this paper as materials exhibiting characteristics of the Pockels effect and / or the Franz-Keldysh effect and / or the Kerr effect. Furthermore, materials exhibiting plasmon dispersion effects are also considered to be of this category.

[0090] Exemplary materials for the active element are graphene, possibly chemically modified graphene, and / or germanium and / or lithium niobate and / or electro-optic polymers and / or silicon and / or compound semiconductors, such as III-V semiconductors and / or II-VI semiconductors, and / or dichalcogenides, particularly two-dimensional transition metal dichalcogenides, and / or heterostructures of two-dimensional materials. Therefore, 2D materials other than graphene are also possible, optionally and additionally. Electro-optic polymers should be particularly understood as polymers having a strong linear electro-optic coefficient (Pockell effect). A strong linear electro-optic coefficient is preferably understood to be equal to at least 150 pm / V, preferably at least 250 pm / V. The electro-optic coefficient is at least five times that of lithium niobate.

[0091] There are different chalcogenides. In the context of this invention, transition metal dichalcogenides, as two-dimensional materials such as MoS2 or WSe2, have proven to be particularly suitable.

[0092] It should be noted that lithium niobate and electro-optic polymers are based on electro-optics, particularly the Pockel effect, where an electric field alters the refractive index (e.g., the Pockel effect applied to a Pockel cell). In germanium, it is the Franz-Keldish effect, where a field causes the valence band and conduction band edges to shift relative to each other, thus altering optical properties. These effects are field-based. For silicon or graphene, this is based on the plasmon dispersion effect of charge carriers, where charge carriers (electrons or holes) are introduced into optical mode regions (either in a charged capacitor in a device or in a diode with a depleted and enriched junction). The refractive index (the real part of the refractive index) and absorption (the imaginary part of the refractive index, leading to absorption by free carriers) change with the charge carrier concentration.

[0093] III-V semiconductors are compound semiconductors composed of Group III and V elements in a manner known per se. II-VI semiconductors are compound semiconductors composed of Group II or Group 12 elements and Group VI elements.

[0094] Among other materials, graphene has proven to be a particularly suitable material for the active element of the electro-optic device used in the semiconductor device of the present invention.

[0095] Many materials are characterized by their refractive index changing with the presence of voltage and / or charge and / or electric field, and their absorption of electromagnetic radiation of at least one wavelength, generating photoelectric signals due to absorption. This is true of graphene, for example. Therefore, graphene is suitable as an active element in photodetectors and modulators. This also applies to dichalcogenides, such as two-dimensional transition metal dichalcogenides, two-dimensional materials, heterostructures of germanium and silicon, and compound semiconductors, particularly III-V and / or II-VI semiconductors. For example, lithium niobate is typically only suitable for modulators. Because it is transparent, it lacks absorption properties and is therefore unsuitable for photodetectors.

[0096] At least one active element of one or more electro-optic devices may be in the form of a film. The film is preferably characterized in a manner known per se, and its lateral extent is significantly greater than its thickness. At least one active element of one or more electro-optic devices may also have a square or rectangular cross-section.

[0097] One or more active elements may comprise one or more layers or coatings of at least one material, the refractive index of which may change and / or absorb, or may be formed from one or more layers or coatings of at least one such material. In particular, it may be specified that at least one active element is formed as a film comprising multiple coatings or layers of one or different materials.

[0098] Graphene films (possibly chemically modified graphene), or dichalcogenide-graphene heterostructures consisting of at least one layer of graphene and at least one layer of dichalcogenide, or arrays of at least one layer of boron nitride and at least one layer of graphene, have proven particularly suitable.

[0099] For example, the active element may also include or be provided by one or more silicon coatings. In particular, one or more active elements or portions thereof may be provided to form a waveguide (part).

[0100] Active components may be further doped or have doped portions or regions, such as p-doped and / or n-doped, or include corresponding portions or regions. P-doped and n-doped regions, as well as preferably intermediate undoped regions, may also be present or provided. This is also known as pin transition, where i represents intrinsic, i.e., undoped.

[0101] A further advantageous embodiment is characterized by providing an active element having a p-doped region and an n-doped region, the two doped regions being adjacent to each other or an undoped region being located between them, and the two doped regions optionally forming a waveguide or a portion of such a waveguide together with a possible intermediate undoped region.

[0102] Furthermore, the electro-optic polymer element or coating can be disposed between two active elements, such as silicon-doped active elements.

[0103] Furthermore, it can be specified that, in order to obtain active elements for multiple electro-optic devices, at least one film or coating (having one or more layers) optionally extending over the entire lateral extent of the wafer is provided or has been provided, for example, deposited, and multiple smaller film- or coating-like active elements for multiple devices, adjacent to each other in a plane, are obtained or have been obtained from this large film through a suitable structuring process, which may include, for example, photolithography and / or etching. Thus, multiple active elements can be obtained for many electro-optic devices with relatively little effort.

[0104] Optionally or additionally, the active element or at least one of the active elements may be or has been provided by a transfer process. This specifically means that the individual elements are not fabricated monolithically on a wafer or coated thereon, but are fabricated individually and then transferred, in other words, have been transferred. For example, the transfer process for graphene is described in the paper "Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils" by Li et al., Science 324, 1312, (2009) and "Roll-to-roll production of 30-inch graphene films for transparent electrodes" by Bae et al., Nature Nanotech 5, 574-578 (2010), or for LiNbO, in the paper "Integrated lithium niobate electro-optic modulators operating at CMOS-compatible voltages" Nature volume 562, pp. 101104 (2018), or especially for GaAs, in the paper "Transfer print techniques for heterogeneous integration of photonic components" Progress in Quantum Electronics, Vol. 52, March 2017, pp. 1-17. One of these methods can also be used in the context of this invention to obtain one or more graphene or LiNbO or GaAs coatings / films.

[0105] Structured processes can also follow a transfer process.

[0106] In a further embodiment, the electro-optic device or at least one of the electro-optic devices is provided by a modulator including an active element comprising or composed of at least one material whose refractive index changes with the presence of voltage and / or charge and / or electric field, and includes an active element or electrode having or composed of at least one material whose refractive index changes with the presence of voltage and / or charge and / or electric field or electrode. The two active elements or active elements and electrodes are preferably spaced apart from each other and arranged staggered, such that in a portion one is above the other. At least one corresponding material of one or both active elements may be graphene and / or at least one dichalcogenide, particularly a two-dimensional transition metal dichalcogenide, and / or a heterostructure of a two-dimensional material and / or germanium and / or lithium niobate and / or at least one electro-optic polymer and / or silicon and / or at least one compound semiconductor, particularly at least one III-V semiconductor and / or at least one II-VI semiconductor.

[0107] In other words, one active element and one conventional electrode are sufficient to replace two active elements. Specifically, the electrode does not include at least one material with a changing refractive index, or does not include such a material, but instead includes at least one conductive material. If the electrode is provided instead of one of the active elements, it can be in the form of a film, possibly having multiple layers, such as a single-layer or multi-layer metal film, similar to the active element.

[0108] Similarly, in the case of a modulator, the active element preferably includes graphene, optionally chemically modified graphene and / or at least one dichalcogenide, particularly a two-dimensional transition metal dichalcogenide, and / or a two-dimensional material and / or germanium and / or lithium niobate and / or at least one electro-optic polymer and / or a heterostructure of silicon and / or at least one compound semiconductor, particularly at least one III-V semiconductor and / or at least one II-VI semiconductor.

[0109] Preferably, the two active elements or one active element and electrode are arranged at a distance from each other and / or staggered, such that in a portion, one is above the other. In other words, a portion of one active element is then aligned with or overlaps with a portion of the other active element or electrode, even without such contact if necessary. Preferably, at least in the region above the other, in other words, in the overlapping region, the two active elements or at least a portion of the active element and electrode extend at least substantially parallel to each other.

[0110] Furthermore, in the case of a modulator having one or two active elements and conventional electrodes, the respective active elements or one active element and electrode can be formed as a film.

[0111] Electro-optic modulators are particularly useful for optical signal encoding. Electro-optic modulators can also be designed as ring modulators.

[0112] Optionally or additionally, the electro-optic device or at least one of the electro-optic devices may be provided by a photodetector comprising one, preferably exactly one, active element, said active element comprising or composed of at least one material that absorbs electromagnetic radiation of at least one wavelength, preferably at least one wavelength range, and generates a photoelectric signal due to absorption, particularly graphene and / or at least one dichalcogenide, particularly two-dimensional transition metal dichalcogenides, and / or heterostructures of two-dimensional materials and / or germanium and / or silicon and / or at least one compound semiconductor, particularly at least one III-V semiconductor and / or at least one II-VI semiconductor.

[0113] In a photodetector, at least one electro-optically active material is used to absorb light.

[0114] In particular, photodetectors can be used to convert signals from the optical world back to the electronic world.

[0115] The electro-optic device, or at least one electro-optic device (in the case of a modulator and detector), can be further designed or (in the case of the method according to the invention) fabricated by plasma coupling.

[0116] Advantageously, at least one plasma structure is then disposed on or above the active element or at least one of the active elements, said plasma structure comprising or composed of a plasma-active material (preferably gold and / or silver and / or aluminum and / or copper). The plasma structure preferably comprises at least a pair of plasma elements arranged adjacent to each other and comprising or composed of a plasma-active material. A characteristic of the plasma element may be a portion that gradually tapers in the direction of its respective other plasma element. For example, a plasma element may be triangular.

[0117] Preferably, in the case of a modulator, an elongated plasma element may also be provided. The elongated plasma element may / has been arranged at least substantially parallel to the waveguide. Then, in other words, the optical and plasma waveguides are guided parallel to each other through the active element, as described by Zhu et al. in "Efficient electro-optic modulation in low-lossgraphene-plasmonic slot waveguides", Optical Communications (2019), doi:https: / / doi.org / 10.1016 / j.optcom.2019.124559.

[0118] In particular, the responsivity of photodetectors including graphene can be enhanced through plasmonically enhanced absorption. For example, plasmonically enhanced structures are fabricated on graphene channels and positioned as active elements in waveguides, as described by Ma et al. in "Plasmonically Enhanced Graphene Photodetector Featuring 100 Gbit / s Data Reception, High Responsivity, and Compact Size," ACS Photonics 2019, 6, pp. 154–161 (2018). The resonant density fluctuations in the plasmon structure are excited by optical modes. This collective motion of electron distribution, called plasmon resonances, propagates within the plasmon structure. Its characteristics include a higher electric field intensity compared to optical modes. This results in stronger absorption capabilities in graphene, or absorbing materials in general.

[0119] A further embodiment is characterized in that a waveguide is disposed on at least one side of an active element or at least one of the active elements, the waveguide having a gradually tapering end portion along the direction of the active element or at least one active element, preferably terminating at a tip. The gradually tapering end portion may extend to the active element or at least one active element. Optionally or additionally, a contact element may be disposed on each side of the tapering portion, the contact element being connected to the active element and having a gradually tapering portion in the opposite direction, and adjacent to the gradually tapering end portion of the waveguide.

[0120] It can also be specified that, on both sides of the active element or at least one active element, in each case, the waveguide has an end portion that tapers gradually in the direction of the active element, preferably terminating at a tip. This can then be applied to two end portions that extend upwards to the active element or at least one active element. Furthermore, on both sides of each taper portion, in each case, contact elements can be provided, connected to the active element or at least one active element, and having tapered portions located beside the respective taper ends of the waveguide, tapering gradually in opposite directions. Two contact elements can be provided, each contact element having two widened portions (preferably on opposite sides and one for each end portion). The respective widened portions of the contact elements preferably follow the taper of their respective waveguide end portions. It is possible that, in the direction of the active element, the distance between the taper ends of the waveguide and the widened contact element portions adjacent to them on both sides remains constant. However, it is also possible, at least to some extent, to increase or decrease this distance.

[0121] In particular, in this embodiment, the active element may also be specified to include or be composed of at least one electro-optic polymer (see also Koos et al., "Silicon-Organic Hybrid (SOH) and Plasmonic-Organic Hybrid (POH) Integration", Journal of Optical Technology, Vol. 34, No. 2, 2016).

[0122] In other words, plasmonic coupling can occur even without a waveguide beneath the absorbing material, i.e., a conversion from optical mode to plasmonic mode, followed by interaction between the plasmonic mode and the absorbing material. This is also described in the publication "Ultra-compact integrated graphene plasmonic photodetector with bandwidth above 110 GHz" by Ding, Y., Cheng, Z., Zhu, X. et al. (in the context of a photodetector), Nanophotonics, doi:10.1515 / nanoph-2019-0167. For further information on modulators, see Ding et al.'s publication "Efficient electro-optic modulation in low-loss graphene-plasmonic slot waveguides," Nanoscale, 2017, 9, 15576.

[0123] Specifically, the modulator, as an electro-optic device, may alternatively or additionally further include two active elements, each provided by a silicon film or coating. For example, the active element may be a coating or a film comprising or composed of polycrystalline silicon, or a film comprising or composed of crystalline silicon. Alternatively, there may be two active elements, both comprising or composed of polycrystalline silicon. Of these two active elements, one is preferably p-doped and the other preferably n-doped. Different doping results in capacitance. The two active elements are then preferably offset from each other, such that they overlap in portions. The overlapping region then preferably forms a waveguide or waveguide portion. By applying a voltage, the charge carrier concentration in the region of the waveguide or waveguide portion can be changed, i.e., during operation in optical mode, thereby enabling the encoding of optical signals. The corresponding silicon-based modulator is also described on pages 1-2 of the paper "An efficient MOS-capacitor-based silicon modulator and CMOS drivers for optical transmitters" published by M. Webster et al. at the 11th International Conference on Photonics Group 4 (GFP) in Paris in 2014, doi:10.1109 / Group4.2014.6961998.

[0124] When an electro-optic device or at least one of an electro-optic device is or becomes a modulator, it may be further configured to include a diode or a capacitor. In particular, it may be an integrated III-V semiconductor modulator, as described in Hiaki's paper "Heterogeneously integrated III-V / Si MOS capacitor Mach-Zehnder modulator", Nature Photonics, Vol. 11, pp. 482-485 (2017).

[0125] If a diode has already been provided for an electro-optic device or at least one electro-optic device, the diode may include, for example, multiple coatings of different compositions (e.g., InGaAsP), specifically for creating a pn junction and two contact regions.

[0126] For example, one or more active elements and electrodes for electro-optic devices (if applicable) can be disposed on the side of the planarization coating opposite to the wafer, or on an additional planarization coating, particularly in waveguide fabrication. Each element can be connected to a contact or contact element on the side or opposite side. The contact or contact element can be connected from the front-end process to one or more electronic components via interconnecting elements (particularly VIAs). The interconnecting elements (particularly VIAs) can extend through the planarization coating, an additional planarization coating (if present), and the semiconductor substrate to one or more electronic components. This connection can be readily understood as a conductive connection.

[0127] It should be noted that, particularly in the case of a detector with only one active element, the active element (especially for connection to one or more electronic components from the front-end process) can be configured to contact two contact elements, preferably on opposite sides. In the case of a modulator with two active elements or one active element and one electrode, it is suitable that each of these elements (especially for connection to one or more electronic components from the front-end process) is in contact with one contact element. This is preferably in those end regions, or at the ends away from the areas where the elements overlap in sections.

[0128] It is also possible to place at least one active element on one or more sides of the waveguide away from the wafer. This provides the advantage of placing the active element closer to the waveguide. More interaction can then be achieved between the active element and the optical modes in the waveguide. Furthermore, since an additional planarization coating is not required in this case, shorter components can be obtained, and fewer process steps are needed.

[0129] In another embodiment, active elements are disposed on one or more control electrodes away from the side of the wafer, preferably disposed on one or more control electrodes away from the side of the wafer, and the control electrodes or these control electrodes are sequentially fabricated on one or more waveguides away from the side of the wafer.

[0130] It should be noted that the side of a component facing away from the wafer can also be referred to as its upper side. For example, the side of a planarization coating, another planarization coating, a waveguide, a waveguide substrate, a deposited material, a graphene film, a control electrode, and / or a photonic platform facing away from the wafer can also be referred to as the upper side.

[0131] For modulators having two active elements or one active element and one electrode, a passivation coating can also be provided between the two active elements or between the active element and the electrode. The passivation coating is advantageously composed of a dielectric material. Therefore, the passivation coating can also be called a dielectric coating. It can simultaneously form etch protection. Oxides or nitrides are particularly suitable materials for this coating. Alumina, silicon nitride, and hafnium oxide have proven to be particularly suitable. If a passivation coating is provided between two active elements or between an active element and an electrode, a sandwich-like structure with active elements, a passivation coating, and an active element or electrode is preferably present, with the two active elements or the active element and electrode preferably laterally offset from each other.

[0132] It is also possible that at least one active element and electrode (if any) of an electro-optic device extends in one or more waveguide portions and in one or more planarization coatings or additional planarization coatings or one or more control electrodes portions.

[0133] In addition, it is possible, at least partially or completely, to place one or more active elements within the waveguide or at least one portion of the waveguide or between two portions of the waveguide.

[0134] An active element, or at least one of the active elements, is advantageously arranged relative to at least one waveguide such that it is at least partially exposed to the evanescent field of electromagnetic radiation guided by the waveguide. Preferably, at least one active element is arranged at a distance of less than or equal to 50 nm, more preferably less than or equal to 30 nm, for example, 10 nm from at least one waveguide.

[0135] In a waveguide, the portion of electromagnetic radiation, particularly light, is evanescently guided outside the waveguide. The waveguide interface is dielectric, and therefore the intensity distribution is described by Maxwell's exponential decay boundary conditions. If an electro-optically active material (such as graphene) is brought into or near the waveguide in an evanescent field, photons can interact with the electro-optically active material, particularly graphene.

[0136] Photodetectors conveniently have an active element comprising or consisting of at least one such material and two contacts.

[0137] Four effects in graphene contribute to photocurrent. One is the radiative thermal effect, where absorbed energy increases the resistance of graphene and decreases the applied direct current. This change in direct current is the light signal. Another effect is photoconductivity. Here, since resistance is proportional to charge carrier concentration, absorbed photons lead to an increase in charge carrier concentration, and the additional charge carriers reduce the resistance of graphene. This increase in applied direct current results in the light signal. A thermoelectric effect also exists, where a thermoelectric voltage is generated by the pn junction and the temperature gradient at that junction due to the different Seebeck coefficients in the p and n regions. This temperature gradient is generated by the energy of the absorbed light signal. This thermoelectric voltage is the signal. The fourth effect is due to the separation of electron-hole pairs excited at the pn junction. The resulting photocurrent is the signal.

[0138] As described above, in the case of a modulator, electrical control electrodes and active elements suitably insulated for this purpose can be provided, comprising or composed of at least one material whose refractive index (especially graphene) changes with voltage, charge, or electric field. Alternatively, the electrodes can also be made of a corresponding material (especially graphene). Thus, in operation, the two active elements are combined in an evanescent field and perform an electro-optic function. For example, the optical properties of graphene can be altered by controlling the voltage. In cases where the graphene-dielectric-graphene arrangement is particularly advantageous, a capacitance is generated, and the two graphene films influence each other. The voltage charges the capacitor formed by the graphene electrodes, which constitute two active elements, and electrons occupy states in the graphene. This causes the Fermi energy (the energy of the last occupied state in the wafer) to shift to higher energies (or to lower energies due to symmetry). When the Fermi energy reaches half the photon energy, they are no longer absorbed because the free state required for the absorption process has been occupied at the correct energy. Therefore, in this state, the graphene is transparent because absorption is prohibited. By changing the voltage, graphene switches between absorption and transparency. This can be used for information transmission by modulating the intensity of a continuously emitting laser beam. Similarly, the real part of the refractive index changes with the control voltage. By changing the voltage, the phase of the laser can be modulated by changing the refractive index, thus achieving phase modulation. Preferably, phase modulation is operated within a range in which all states occupy more than half of the photon energy, making the graphene transparent, and the real part of the refractive index significantly shifted, while changes in absorption have a smaller effect.

[0139] An electro-optic device, or at least one electro-optic device, may further include at least one, preferably two, gate electrodes. In particular, in the case of an electro-optic device implemented as a photodetector, the two gate electrodes may preferably be assigned to an active element. They are then preferably implemented and arranged in such a way that the charge carrier concentration in the active element (e.g., a graphene film) can be adjusted via these gate electrodes, thereby achieving, for example, pn transitions. The gate electrodes are then preferably arranged at a suitable distance from the active element and electrically insulated from the active element, for example, by a dielectric coating. The active element may be disposed on the dielectric coating, and the gate electrodes may be disposed on the dielectric coating.

[0140] A further particularly advantageous embodiment is characterized in that the semiconductor device according to the invention, especially its photonic platform, includes at least one coupling device associated with at least one (preferably exactly one) waveguide. The respective coupling device is then conveniently used to couple electromagnetic radiation (particularly in the infrared and / or visible wavelength range) into at least one waveguide of the photonic platform associated with the respective coupling device, and / or to couple electromagnetic radiation (particularly in the infrared and / or visible wavelength range) out of at least one waveguide of the photonic platform associated with the respective coupling device. For this purpose, the coupling devices can be suitably implemented and arranged. It should be noted that, for silicon photonics, due to the bandgap, it is generally only applicable to the infrared wavelength range, as all wavelengths shorter than 1100 nm are absorbed by silicon. This is generally not the case for dielectrics, which are also transparent in the visible wavelength range, which is why they are well-suited for spectroscopy.

[0141] Particularly preferably, the implementation and arrangement of the coupling device, or at least one of the coupling devices, allows electromagnetic radiation (particularly in the infrared and / or visible wavelength range) to be coupled from the optical fiber into at least one of the waveguides of the photonic platform, and / or the electromagnetic radiation (particularly in the infrared and / or visible wavelength range) to be coupled from at least one of the waveguides of the photonic platform into the optical fiber. The optical fiber typically has a larger diameter than the waveguide, and the coupling device will be further preferably configured to enable coupling in and / or out in this case.

[0142] The coupling device may include a portion of the associated waveguide (particularly the end portion), such as an end portion that tapers or widens towards the end.

[0143] In a further detailed description, at least one coupling device may have at least one grating structure, which is then designed and arranged, in particular, in a manner that its first diffraction order is located in the associated waveguide. Such a coupling device may also be simply referred to as a grating coupling device or a grating coupler. For further information on the design and operation of grating couplers, see also the article "CMOS-compatible high efficiency double-etched apodized waveguide grating coupler," Optics Express 21, 7868-7874 (2013).

[0144] If at least one coupling device is provided by a grating coupler, it is further preferred that it includes or is equipped with a reflector. Reflectors are particularly suitable because their arrangement allows for maximum coupling. Without a reflector, the interface between the back-end process and the planarization coating typically forms automatically due to the refractive index jump. Reflectors are also particularly advantageous if a grating coupler is provided, as this situation (compared to the interface situation) is precisely defined. For example, a metal foil or a thin metal coating or dielectric coating stack can be used as a reflector, thereby creating a Bragg reflector.

[0145] The reflector is preferably arranged on the planarization coating. The reflector may be made of metal (e.g., aluminum) and / or have a rectangular shape and / or be slightly larger than the grating coupler and / or be arranged at a suitable distance from the grating coupler, preferably below it.

[0146] Optionally or additionally, at least one of the coupling devices may be designed as a side-coupled device (referred to as a side coupler). The coupling device then advantageously has at least one coupling element implemented and arranged in such a way that electromagnetic radiation can be laterally coupled into and / or laterally coupled out of the coupling element. "Lateral" specifically refers to lateral orientation relative to the transverse extent of the wafer, particularly lateral orientation relative to the side of the wafer facing away from the front-end process.

[0147] For information on the design and operation of grating couplers, please refer to the paper "Ultra-low-loss inverted tapercoupler for silicon-on-insulator ridge waveguide", Optical Communications, Vol. 283, No. 19, October 2010, pp. 3678-3682.

[0148] The grating coupling device can also be designed and arranged in such a way that the electromagnetic radiation to be coupled in can be incident from (oblique) above, particularly onto its grating, or the electromagnetic radiation to be coupled out can be coupled out from (oblique) above, particularly from its grating. It can also preferably be implemented and arranged such that coupling can occur at an angle in the range of 0° to 30° (particularly 10°) relative to a perpendicular line from the side of the wafer or device opposite to the front-end process according to the invention.

[0149] Compared to side couplers, grating couplers, where radiation enters or exits from (obliquely) above, generally have the advantage that their functionality can be checked before cutting. On the other hand, in the case of side couplers, the side or edge of the element to which electromagnetic radiation enters or exits may not be exposed until after cutting, and therefore testing can only be performed after cutting.

[0150] In further development, at least two coupling devices can be provided, at least one of which is a side coupling device (referred to as a side coupler) and at least one is a grating coupling device (referred to as a grating coupler). If both types of couplers are provided, the grating coupler can be used to measure the component during manufacturing, and then the side coupler can be used when everything is ready. Preferably, at least one waveguide has two couplers associated with it, one of which is of one type and the other of another.

[0151] One or more coupling devices are preferably fabricated together with at least one waveguide associated with them. Fabrication methods may include defining them by photolithography (similar to waveguides) and structuring them by etching (especially dry chemical etching).

[0152] The present invention also relates to a method for manufacturing at least one semiconductor device, wherein a semiconductor device according to the invention is disposed therein and the device is fragmented (i.e., diced). By dicing / dicing, at least one chip, typically multiple chips, on which photonics is built, each chip representing a semiconductor device according to the invention. For example, this “bare” chip or these “bare” chips with photonics can be individually inserted into a package. It should be noted that the semiconductor device according to the invention comprises a conventional chip having integrated circuits and a portion of a photonic platform built thereon, which may also be referred to as a chip.

[0153] Another object of the present invention is to provide a semiconductor device obtained by dividing (in other words, cutting) the semiconductor device according to the present invention.

[0154] The semiconductor device according to the invention, obtained by dicing the semiconductor device according to the invention, is characterized in that the lateral extent of the photonic platform or a portion thereof is at least substantially consistent with the lateral extent of the underlying chip or semiconductor substrate. The photonic platform or a portion thereof, like the underlying substrate, is shaped and extended by dicing.

[0155] A housing can be provided to surround the semiconductor device. In this case, it is preferable that the side of the device where the front-end process is located contacts the inside of the housing. Attached Figure Description

[0156] Regarding embodiments of the present invention, reference is also made to the dependent claims and the following description of several embodiments with reference to the accompanying drawings.

[0157] As shown in the figure:

[0158] Figure 1 A top view of an embodiment of a semiconductor device according to the present invention is shown in purely schematic form.

[0159] Figure 2 Shown as a purely schematic diagram Figure 1 A partial cross-sectional view of a semiconductor device;

[0160] Figure 3 Shown as a purely schematic diagram Figure 2 , Figure 4 and Figure 5 A top view of the photodetector in the image;

[0161] Figure 4 A partial cross-sectional view of a second embodiment of the semiconductor device according to the present invention is shown in purely schematic form.

[0162] Figure 5 A partial cross-sectional view of a third embodiment of the semiconductor device according to the present invention is shown in purely schematic form.

[0163] Figure 6 A partial cross-sectional view of a fourth embodiment of the semiconductor device according to the present invention is shown in purely schematic form.

[0164] Figure 7 A partial cross-sectional view of a fifth embodiment of the semiconductor device according to the present invention is shown schematically.

[0165] Figure 8 A partial cross-sectional view of a sixth embodiment of a semiconductor device according to the present invention is shown in purely schematic form.

[0166] Figure 9 Shown as a purely schematic diagram Figure 8 Top view of the modulator;

[0167] Figure 10A partial cross-sectional view of a seventh embodiment of a semiconductor device according to the present invention is shown in purely schematic form.

[0168] Figure 11 A partial cross-sectional view of an eighth embodiment of the semiconductor device according to the present invention is shown in purely schematic form.

[0169] Figures 12 to 16 Five examples of possible contact points for active elements in electro-optic devices of semiconductor devices are illustrated purely as schematic diagrams.

[0170] Figure 17 A partial cross-sectional view of a ninth embodiment of a semiconductor device according to the present invention is shown in purely schematic form.

[0171] Figure 18 A partial cross-sectional view of a tenth embodiment of a semiconductor device according to the present invention is shown in purely schematic form.

[0172] Figure 19 A partial cross-sectional view of the eleventh embodiment of the semiconductor device according to the present invention is shown in purely schematic form.

[0173] Figure 20 A partial cross-sectional view of a semiconductor device according to the present invention is shown in purely schematic form.

[0174] Figure 21 A top view of a first embodiment of a photodetector with plasma coupling is shown in purely schematic form.

[0175] Figure 22 A top view of a second embodiment of a photodetector with plasma coupling is shown in purely schematic form.

[0176] Figure 23 A top view of an embodiment of a modulator with plasma coupling is shown in purely schematic form.

[0177] Figure 24 A top view illustrating an example of a side-coupled device, presented purely as a schematic diagram;

[0178] Figure 25 for Figure 24 A cross-sectional schematic diagram of the side coupling device;

[0179] Figure 26 A top view illustrating an example of a grating coupling device, presented purely as a schematic diagram;

[0180] Figure 27 for Figure 26 A cross-sectional schematic diagram of the grating coupling device is shown.

[0181] Figure 28 It shows the method of manufacturing according to Figure 1 The steps of the method of the apparatus;

[0182] Figure 29 A top view of three semiconductor devices according to the present invention is shown in purely schematic form; and

[0183] Figure 30 To pass according to Figure 29 A purely schematic cross-sectional view of the semiconductor device of the invention.

[0184] In the accompanying drawings, the same parts or elements are labeled with the same reference numerals. Detailed Implementation

[0185] Figure 1 A top view of a semiconductor device according to the present invention is shown in a purely schematic and highly simplified manner. This includes wafer 1, which may also be manufactured according to... Figure 2 As seen in the partial cross-sectional view, the wafer comprises a monolithic silicon substrate 2 and a plurality of integrated electronic components 3, which, in the illustrated example, extend into the semiconductor substrate 2. The integrated electronic components 3 may, in particular, be transistors and / or resistors and / or capacitors, as shown in the schematic diagram. Figure 2 The figures are simplified and indicated only by shaded lines with reference numeral 3. At corresponding locations in the substrate 2, a large number of integrated electronic components 3 are manufactured in a well-known manner. These integrated electronic components may also be components of a processor, such as a CPU and / or GPU, or such components may be formed in the same known manner.

[0186] Wafer 1 is a component or device from which multiple chips can be obtained by dicing in a manner well known in the art, also known in German as "Wafer-zerkleirnn". For example, dicing or splitting can be performed by (laser) cutting, sawing, scribing, or destroying wafer 1. Therefore, the wafer comprises multiple regions, each of which forms a chip after dicing. These regions are referred to as chip regions 4.

[0187] exist Figure 1 In the diagram, these are only schematically represented by thin lines. Each chip region 4 of wafer 1 comprises a portion or a portion of a monolithic semiconductor substrate 2 and typically includes at least one (preferably several) integrated electronic components 3. Depending on the design of wafer 1 (depending on the specific application), for example, up to ten or even dozens, hundreds or thousands of integrated electronic components 3 may be provided in each chip region 4. These integrated electronic components may be arranged adjacent to each other and / or overlap each other.

[0188] Wafer 1 has a front-end process (FEOL) 5 and an overlying back-end process (BEOL) 6. Multiple integrated electronic components 3 are arranged in the front-end process 5. In the back-end process 6, or via the back-end process 6, the integrated electronic components 3 of the front-end process 5 are interconnected through different metal planes. The integrated electronic components 3 in FEOL 5 and the associated interconnections in BEOL 6 form the integrated circuit of wafer 1 in a manner well known. FEOL 5 is sometimes referred to as the transistor front end, and BEOL as the metal back end. The metal planes include multiple interconnect elements 7, given in this example by the so-called VIA, which is an abbreviation for Vertical Interconnect Path. VIA 7 is made of metal, such as copper, aluminum, or tungsten.

[0189] The described semiconductor device 1 also includes a photonic platform 8, as shown in [the original text]. Figure 2 As can be clearly seen in the cross-sectional view, the photonic platform 8 is located above wafer 1, and according to the present invention, the photonic platform 8 has been fabricated in the back-end process 6 of wafer 1, particularly directly on wafer 1. It should be noted that... Figure 1 Chip region 4 is indicated by a thin line because it is located below photonic platform 8 in the top view.

[0190] In the illustrated embodiment, wafer 1 is characterized by a diameter of 200 mm. This is also the diameter of the photonic platform 8 and the semiconductor device as a whole (see [reference]). Figure 1 This whole comprises wafer 1 and a photonic platform 8 fabricated on top of wafer 1. Figure 2 The partial sectional view is shown in the vertical direction according to Figure 1 The entire device, which has overlapping parts, coatings, or elements, is shown, but only a very small portion of the device is shown in the horizontal direction, specifically only a small part or portion of one of the chip regions 4, which is very small compared to the overall extent of the device in the horizontal direction. This also applies to the other partial sectional views. In this example, chip region 4 is characterized as a rectangle in the plan view, with an edge length of 2 mm in one direction and 3 mm in the other in each case. It should be noted that in purely schematic... Figure 1 It is represented as a square only for simplification.

[0191] from Figure 2 As can be seen, the photonic platform 8 provided according to the present invention includes a planarization coating 10, which has been fabricated on the side 9 of the wafer 1 away from the front-end process 5 and is made of a dielectric material. In this example, the planarization coating 10 is composed of silicon dioxide (SiO2), although this is understood to be exemplary and other materials may also be used.

[0192] In the illustrated embodiment, the planarization coating 10 is obtained by depositing a corresponding coating material (here, SiO2) on the side 9 of the wafer 1 of the front-end process 5, and subsequently planarizing the deposited material on the side 11 opposite to the wafer 1. The planarization coating 10 is characterized by a roughness of 0.2 nm RMS due to the treatment on its side 11 opposite to the wafer 1, which can be understood as an example.

[0193] In the illustrated example, the planarization coating 10 extends to the entire side 9 of the wafer 1 facing away from the front-end process 5. The material of the planarization coating 10 has been deposited on the entire surface of the wafer 1 facing away from the front-end process 5. It is characterized by having a diameter that at least substantially corresponds to the diameter of the wafer 1.

[0194] The photonic platform 8 also includes a plurality of waveguides 12 fabricated on the side 11 of the planarization coating 10 opposite to the wafer 1. A dielectric, preferably titanium dioxide also used in the illustrated embodiment, is particularly suitable as a waveguide material. Optionally or additionally, the waveguides 12 may be made of aluminum nitride and / or tantalum pentoxide and / or silicon nitride and / or aluminum oxide and / or silicon oxynitride and / or lithium niobate, or may be made of semiconductors such as silicon, indium phosphide, gallium arsenide, indium gallium arsenide, etc., and may be provided with aluminum gallium arsenide or dichalcogenide or chalcogenide glass or polymers, such as SU8 or OrmoComp.

[0195] The typical dimensions of waveguide 12 are a thickness between 150 nm and 10 µm, and a lateral extension parallel to the wafer surface with a width between 100 nm and 10 µm. Purely as an example, a thickness of 300 nm and a width of 1.1 µm can be mentioned. The specific dimensions of waveguide 12 can vary. In particular, the width of said waveguide 12 varies depending on the function they perform.

[0196] In this example, the photonic platform 8 also includes an additional planarization coating 13, which is composed of the same material as the planarization coating 10, i.e., SiO2 in this example. The additional planarization coating 13 is characterized in that it has a roughness corresponding to the roughness of the planarization coating 10 on its side 14 facing away from the wafer 1. It should be emphasized that the planarization coating 10 and the additional planarization coating 13 (as in this example) are characterized in that they have the same material, the same extent, and the same roughness on their sides 11 and 14 facing away from the wafer 1, but this is not necessary and should not be construed as limiting.

[0197] The photonic platform 8 also includes a plurality of electro-optical devices 15, which may in particular be photodetectors and / or modulators. In the illustrated embodiment, the photonic platform 8 includes a plurality of photodetectors 15 and a plurality of modulators 15.

[0198] Figure 2 An example of an electro-optic device is schematically shown, specifically a photodetector 15. Figure 3 Again, only schematically shown. Figure 1 A top view of part of the equipment, specifically... Figure 2 A top view of the photodetector 15.

[0199] Figure 4 and Figure 5 An exemplary partial cross-sectional view of a further embodiment of a semiconductor device according to the present invention is shown, the partial cross-sectional view corresponding in a plan view to Figure 1 The plan view shows the photodetector 15 and the waveguide 12 below it in each case, thus allowing the photodetector 15 and / or the waveguide 12 to be replaced in each case. Figure 2 The photodetector and / or waveguide 12. It should be noted that... Figure 3 The diagram also corresponds to Figure 4 and Figure 5 The detector 15, but only the upper narrow portion of the waveguide with a T-shaped cross-section is shown (see 15). Figure 4 and Figure 5 ).

[0200] Figure 6 and Figure 7 A partial cross-sectional view of a further embodiment of the semiconductor device according to the present invention is shown. Here, the photodetector 15 is also provided as an electro-optic device, and its structure differs from that of the photodetector 15. Figure 2 , 4 and Figure 5 Electro-optical devices in the field.

[0201] Figure 8 , Figure 10 and Figure 11 A partial cross-sectional view of a further embodiment of a semiconductor device according to the present invention is shown, in which an electro-optic device implemented as a modulator 15 can be seen in each embodiment. Figure 9 It shows Figure 8 Top view of modulator 15.

[0202] according to Figure 2 as well as Figures 4 to 7 Each photodetector 15 includes an active element 16, said active element 16 being made of a material that absorbs electromagnetic radiation of at least one wavelength (preferably at least one wavelength range), and generates a photoelectric signal due to absorption. Figure 2 and Figures 4 to 7In this example, each active element 16 of the photodetector 15 is provided by a graphene film 16. The graphene can also change its refractive index (refractive index and / or absorptivity) according to voltage and / or charge and / or electric field. The active element 16 may also be provided by a film comprising or composed of at least one other material, for example, a film comprising or composed of a dichalcogenide-graphene heterostructure comprising at least one layer of graphene and at least one layer of dichalcogenide, or a film comprising at least one layer of boron nitride and at least one layer of graphene. Various chalcogenides are available, with transition metal dichalcogenides, such as MoS2 or WSe2, being particularly suitable as two-dimensional materials.

[0203] In comparison, Figure 2 and Figure 4 The arrangement shown differs only in the shape of waveguide 12. Although Figure 2 A strip waveguide 12 with a rectangular cross-section is shown, but with... Figure 5 Same, Figure 4 A ridge waveguide 12 with a T-shaped cross-section is shown, the ridge waveguide 12 having a first upper waveguide segment 12a with a narrower rectangular cross-section and a second lower waveguide segment 12b with a significantly wider rectangular cross-section. Figure 5 Examples and Figure 4 The difference in this instance is that no additional planarization coating 13 is provided here. It should be noted, for example, according to... Figure 2 In the embodiments, waveguide 12 can alternatively be implemented as a so-called slot waveguide, having two waveguide segments spaced apart from each other to form a slot or gap. If waveguide 12 comprises more than one segment 12a, segment 12b, it may be applicable if all segments are made of the same material, as is the case here. However, this is not necessarily applicable; these segments may also comprise different materials or be composed of different materials.

[0204] exist Figure 2 , Figure 4 and Figure 5 In the examples shown, in each case, the graphene film 16 of each electro-optic device 15 extends above the longitudinal portion of the waveguide 12 visible in the figure. This can also be easily seen from... Figure 3 As can be seen in the top view shown. Based on... Figure 2 and 4 In the examples, in each case, the graphene film or a graphene film 16, graphene film 16a is fabricated or disposed on the side 14 of the additional planarization coating 13 opposite to the wafer 1. It can be seen that in each case, the graphene film 16 extends within the trapezoidal cross-section region of the latter's additional planarization coating 13, particularly due to the planarization of the resist. Figure 5 In the example shown, the graphene film 16 is located directly on the waveguide 12.

[0205] Figure 6 and Figure 7 The example shown is the same as Figure 2 , Figure 4 and Figure 5 Unlike others, the graphene film 16 extends into the interior of its respective waveguide 12. Figure 6 ) or below ( Figure 7 Instead of above. In terms of the shape of waveguide 12, they are again formed as ridge waveguide 12 with a T-shaped cross-section. Therefore, Figure 6 The example waveguide 12 includes a first upper waveguide segment 12a, a middle segment 12b, and a lower waveguide segment 12c. All waveguide segments 12a, 12b, and 12c have a rectangular cross-section, with the middle and lower segments 12b and 12c being significantly wider. The middle waveguide segment 12b is disposed on a graphene film 16 and serves as a passivation coating for the graphene film 16 and as the waveguide segment 12b (also referred to as a waveguide plate). In this example, segment 12b, which also serves as a passivation coating, is made of alumina. Optionally or additionally, segment 12b may also comprise or consist of dichalcogenides and / or dichalcogenide heterostructures and / or SiO2 and / or boron nitride. The other two segments 12a and 12c may also comprise or consist of, for example, alumina or titanium dioxide.

[0206] Figure 7 Examples and Figure 6 The difference in this example is the absence of a lower waveguide segment 12c. The graphene film 16 is here disposed directly on the side 11 of the planarization coating 10 facing away from the wafer 5.

[0207] Especially in the case of an electro-optic device implemented as a photodetector 15, two gate electrodes can also be assigned to the active element 16. It is then preferably implemented and arranged in such a way that the charge carrier concentration in the active element (in this case, the graphene film 16) can be adjusted by these gate electrodes, thereby obtaining, for example, a pn junction. For example, the gate electrodes can be arranged above the graphene film 16 and electrically insulated from the graphene film 16 by a dielectric coating.

[0208] according to Figure 8 , Figure 10 and Figure 11 Each modulator 15 comprises two active elements, specifically a lower layer 16a and an upper layer 16b, each provided by a graphene film 16. Similarly, for modulator 15, the active elements can also be implemented in different ways, for example as films comprising or composed of at least one other material. The two graphene films 16a, 16b extend a distance apart from each other and are not in electrical contact. Instead, they are electrically insulated from each other by an intermediate coating 17 of a dielectric material, preferably an oxide or nitride, currently aluminum oxide. The dielectric coating 17 also serves as passivation and etch protection or a barrier. Figure 2 and Figure 6 The comparison shows that, except Figure 8 The modulator 15 includes a second active element 16b and is provided with an additional dielectric coating 17, and these arrangements are identical.

[0209] Two graphene films 16a, 16b are arranged offset from each other such that they partially cover or overlap each other (without contact). In the overlapping region, two more graphene films 16a, 16b, or their respective portions, are further applied, extending at least substantially parallel to each other. It should be noted that the modulator 15 includes two active elements 16a, 16b; alternatively, an electrode made of a conductive material (e.g., copper or aluminum) could be provided instead of one of the active elements.

[0210] exist Figure 8 In the example shown, the lower graphene film 16a (like...) Figure 2 and Figure 4 The single-layer graphene film 16 of the detector is disposed on the side 14 of the additional planarization coating 13, also in the region of the trapezoidal portion above the waveguide 12. The second upper graphene film extends on the side 18 of the dielectric coating 17 opposite to the wafer 5.

[0211] and Figure 2 , Figure 4 and Figure 5 The various examples in the text are similar, Figure 8 , Figure 10 and Figure 11 The examples in the text also differ fundamentally because waveguide 12 is characterized by its different shape and the absence of a second planarization coating 13, which... Figure 10 and Figure 11 None of them are in China. Although Figure 8 Examples include strip waveguide 12, but according to Figure 10 and Figure 11 Examples include ridge waveguides 12 with a T-shaped cross-section or profile. Viewed in cross-section, Figure 10 The waveguide in the middle includes four waveguide segments: 12a, 12b, 12c, and 12d. Figure 11 The waveguide in the diagram comprises three sections: 12a, 12b, and 12c. All sections 12a to 12d have rectangular cross-sections, although it can be seen from the diagram that the upper section 12a (similar to...) Figure 4 and Figure 5 The width of ) is significantly smaller than that of the lower sections 12b, 12c and Figure 11 In the case of 12d, in the example shown, the two or three lower-level segments 12a, 12b, and 12c are each characterized by having the same width. Figure 10 Section 12d of the middle waveguide 12 can also be regarded as the waveguide base.

[0212] exist Figure 11 In this example, the lower graphene film 16a extends between the single planarization coating 10 and the segment 12c of the ridge waveguide 12 located in the planarization coating 10, and the upper graphene film 16b extends between the segments 12b and 12c. Therefore, the upper graphene film 16b extends within the waveguide 12. The lower graphene film 16a is fabricated or disposed on the side 11 of the planarization coating opposite to the wafer 5, and the upper graphene film 16b is fabricated in segment 12c.

[0213] Each of the active elements 16, 16a, 16b of all detectors 15 and modulators 15 of the photonic platform 8 is arranged and associated with, relative to, the respective identifiable waveguides 12 in the figure, such that they are at least partially exposed to the evanescent field of electromagnetic radiation guided by the respective waveguides 12. Preferably, at least a portion of each active element 16, 16a, 16b extends from the respective waveguides 12 at a distance less than or equal to 50 nm, preferably less than or equal to 30 nm. For example, it can be seen that, in Figure 2 In this process, the additional planarization coating 13 between the waveguide 12 and the graphene film 16 is correspondingly thinner or "thinner" than its thickness in the remaining region.

[0214] In the illustrated embodiment, each electro-optical device, particularly each photodetector 15 and each modulator 15, is further electrically connected to at least one of the integrated electronic components 3 in the front-end process 5 of each wafer 1. Figures 2 to 4 as well as Figure 8 , Figure 10 and Figure 11 As shown, the connection is achieved through VIA 7 of the back-end process 6 of wafer 1 and another VIA 7 extending through the planarization coating 10, as well as possible other coatings or components.

[0215] Specifically, in detector 15, a corresponding graphene film 16 is electrically connected at opposite end regions via contacts or contact elements 19 to the upper end of VIA 7, which extends through planarization coating 10 and may further through coatings or elements to the back-end process 6 of wafer 1. Figure 3 In the top view, VIA 7 (located below contact element 19) connected to contact element 19 is indicated by a thin line.

[0216] In modulator 15, each of the two graphene films 16a, 16b is connected to contact element 19 at an end region and to VIA 7 above contact element 19.

[0217] In principle, the contact between the active element (currently the graphene film 16, 16a, 16b of the electro-optic device 15) and the contact element 19 can be designed in different ways. Figures 12 to 16 Five different possibilities are shown through examples.

[0218] according to Figure 12 In the illustrated option, the end regions of the graphene films 16, 16a, and 16b partially contact the bottom surface of the contact element 19. Here, the contact element 19 is advantageously made of a metal optimized for graphene, such as nickel and / or titanium and / or aluminum and / or copper and / or chromium and / or palladium and / or platinum and / or gold and / or silver.

[0219] Figure 13 The examples shown are based on Figure 10 The only difference in the arrangement is that the contact element 19 includes not one but two metal layers 19a, 19b, thereby achieving better performance for further connections, since the upper layer 19b can be composed of a metal optimized for further connections. The lower layer 19a, in contact with the graphene films 16, 16a, 16b, is advantageously again composed of a metal optimized for graphene. Preferably, layer 19a is composed of nickel and layer 19b is composed of aluminum, or layer 19a is composed of titanium and layer 19b is composed of aluminum. Other combinations of nickel and / or titanium and / or aluminum and / or copper and / or chromium and / or palladium and / or platinum and / or gold and / or silver are also possible for active elements comprising or composed of graphene and for active elements comprising or composed of other electro-optically active materials.

[0220] exist Figure 14 In the example shown, contact element 19 also includes a third lower metal layer 19c, which serves as a bonding agent. For example, this layer 19c may be composed of titanium, chromium, or aluminum oxide. Layer 19a may be composed of, for example, nickel and / or titanium and / or aluminum and / or copper and / or chromium and / or palladium and / or platinum and / or gold and / or silver. Layer 19b may also be composed of one or a combination of these metals.

[0221] According to Figure 15 and Figure 16 In this embodiment, the end regions of the active element (in this case, graphene films 16, 16a, 16b) extend between a first lower metal layer 19a optimized for graphene and a second upper metal layer 19d of the contact element 19, also optimized for graphene. For this purpose, the end regions of the active element 16 have an S-shaped cross-section. The two layers 19a and 19d are preferably composed of a combination of palladium or nickel or gold or platinum or nickel and / or titanium and / or aluminum and / or copper and / or chromium and / or palladium and / or platinum and / or gold and / or silver.

[0222] Figure 16 Examples and Figure 15 The difference between the instances is that, and Figure 14Similarly, contact element 19 includes a third metal layer 19b, which is optimized for further connection, for example, with... Figure 13 Similar to layer 19b, it can be composed of aluminum.

[0223] For all contact examples, the graphene film 16 may be covered by the contact element 19 or layers 19a to 19d of the contact element 19, such that current enters the graphene from the contact element 19 or layers of the contact element 19 in a vertical transition manner (top contact), or the graphene film 16 may terminate at the edge of the contact element 19 or layers 19a to 19d of the contact element 19, such that current enters the graphene film 16 laterally (side contact). For example, according to Figure 13 The arrangement can also be implemented as top contact.

[0224] The passivation coating 25 is preferably disposed above each active element, i.e., preferably above each graphene film 16. This can only be done on... Figures 12 to 16 As seen in the figures, each figure shows a portion of the graphene films 16, 16a, and 16b in a magnified view. In this example, the passivation coating 25 is made of aluminum oxide. Alternatively or in addition, such a passivation coating 25 may also comprise or consist of dichalcogenides and / or dichalcogenide heterostructures and / or SiO2 and / or boron nitride. The passivation coating 25 passivates the active element, in this case, the graphene film, and simultaneously serves as an etch stop layer, making selective etching of the contact element 19 for connection to VIA 7 possible.

[0225] It should be noted that, in the case of modulator 15, the dielectric coating 17 disposed between the two active elements 16a, 16b (see Figure 8 This can already be used to passivate the lower component 16b. In this case, it is not necessary to apply a passivation coating 25 to it.

[0226] Furthermore, it should be noted that even when based on Figures 12 to 16 In the examples shown, active elements 16, 16a, and 16b are provided by graphene films, and the illustrated embodiments are by no means limited to this material. Furthermore, contacts can be designed accordingly for active elements 16 that include or are composed of one or more other materials.

[0227] exist Figures 17 to 20 An embodiment of a photodetector 15 or modulator 15 with active elements but without graphene is shown.

[0228] in this regard, Figure 17An embodiment includes an active element 16 formed from a polycrystalline silicon coating, which also forms a waveguide 12. It can be seen that the silicon coating 16 has the shape of a ridge waveguide with a T-shaped cross-section. In this example, the silicon coating forming the active element 16 and the waveguide 12 has two doped regions, namely a p-doped region 16p and an n-doped region 16n. It should be noted that, optionally, a pin transition may also exist, i.e., an undoped region may also be located between the p-doped and n-doped regions. Silicon coating 6 (similar to...) Figure 2 and Figures 4 to 7 The active element 16 of the example is connected to two contact elements 19. Depending on the polarity of the applied voltage, the charge carrier concentration in the blocking coating changes, and therefore the absorption and refractive index of waveguide 12 also change. Alternatively, waveguide 12 is designed here as a diode to obtain a modulator.

[0229] Figure 18 Another example of a silicon modulator, also known as SISCAP, is shown (see also M. Webster et al., "An efficient MOS-capacitor-based silicon modulator and CMOS drivers for optical transmitters," presented at the 11th International Conference on Photonics Group 4 (GFP), Paris, 2014, pp. 1-2. doi:10.1109 / Group4.2014.6961998). Here, two active elements 16a and 16b are provided, each formed by a silicon coating, preferably formed by wafer silicon, polycrystalline silicon, or amorphous silicon. Here, active element 16a is p-doped, while element 16b is n-doped. Active elements 16a and 16b are further offset from each other such that in overlapping regions, one is above the other, which is similar to... Figure 8 , Figure 10 and Figure 11 The example active element 16. The overlapping region here forms a waveguide 12. The charge carrier concentration can be adjusted within the overlapping region, thereby modulating the optical properties of the waveguide 12.

[0230] Figure 19 Another example of a silicon modulator 15 is shown, which also includes two active elements 16a and 16b, formed of p-type and n-type doped silicon coatings, respectively. They are adjacent to each other in a plane, and an element of an electro-optic polymer 26 is disposed between them. The two active elements 16a and 16b of the electro-optic polymer and element 29 form a ridge waveguide 12, the gap of which is formed by element 26. In other words, the sidewalls of the gap act as electrodes of a capacitor. The electric field in the gap affects the optical properties of the polymer and is capable of modulating optical signals.

[0231] Figure 20 An example of a modulator with diode 27 is shown, which is made of compound semiconductor. Diode 27 consists of coatings 27a to 27d of different compositions, such as InGaAsP, to form a pn junction and two contact regions. The contact regions are connected to contact element 19 and thus to integrated electronic component 4 via electrode 28.

[0232] The electro-optic device, or at least one electro-optic device (in the case of modulator 15 and detector 15), may be further designed or manufactured to have plasma coupling.

[0233] exist Figures 21 to 23 The corresponding examples can be found in the document (each of which is a purely schematic diagram).

[0234] in this regard, Figure 21 An example of a photodetector 15 is shown, in which a plasma structure 29 comprising or composed of a plasma-active material is provided, specifically in the active element 16. In this example, the plasma structure 29 comprises three pairs of adjacently arranged plasma elements 30 and comprises or is composed of a plasma-active material. Currently, the plasma elements are composed of gold. Examples of other suitable materials include silver and / or aluminum and / or copper. The plasma elements 30 form quasi-antennas on the waveguide 12 to increase absorption (see also Ma et al., "Plasmonically Enhanced Graphene Photodetector Featuring 100 Gbit / s Data Reception, High Responsivity, and Compact Size", ACS Photonics 2019, 6, pp. 154–161 (2018)). For example, such a plasma structure can be provided or transformed into a structure according to Figure 2 , Figure 4 or Figure 5 The arrangement of active components 16.

[0235] Figure 22 An example of a photodetector 15 is shown, in which no waveguide 12 or such a portion is disposed below or above the active element 16, but wherein the waveguide 12 is preferably disposed in the plane of the active element 16 and located on its side, the waveguide 12 having a portion 31 that tapers in a V-shape in the direction of the active element 16. Figure 22In the middle, portion 31 gradually tapers to a point extending to the left of the active element 16 (e.g., a graphene film). It can be seen that the contact element 19 here includes portion 19e, which tapers in the opposite direction, i.e., away from the active element 16. In other words, the contact element 19 segmentally follows the gradually tapering end portion 31 of the waveguide 12, enabling plasmonic coupling.

[0236] Figure 23 An analog modulator 15 with plasmonic coupling is shown. It can be seen that waveguide portions 31, such as graphene films, tapering in a V-shape along the direction of the active element 16 are provided on two opposite sides of the active element 16, and portions 19e of contact elements 19 tapering in opposite directions are provided for the two associated waveguide portions 31 and 19e. Therefore, it is possible to couple an optical mode to a plasmonic mode and back to an optical mode here. In particular, in this embodiment, an active element comprising or composed of at least one electro-optic polymer may be further provided (see also the publication "Silicon-Organic Hybrid (SOH) and Plasmonic-Organic Hybrid (POH) Integration" by Kus et al., Journal of Optical Technology, Vol. 34, No. 2, 2016).

[0237] A photonic platform 8 fabricated on a wafer 1 of a semiconductor device according to the present invention typically includes a large number of electro-optical devices 15, which may in particular be provided by photodetectors and / or modulators. This is also the case in the illustrated embodiment. In particular, each portion of the photonic platform 8 extending above the chip region 4 of the wafer 1 will already include multiple electro-optical devices 15 and multiple waveguides 12. For example, dozens, hundreds, or even thousands of electro-optical devices 15 and / or waveguides 12 may be provided in each portion of the photonic platform 8 extending above the chip region 4. In each case, the number can be selected according to the specific application.

[0238] In the illustrated embodiment of the semiconductor device according to the invention, all electro-optical devices 15 and waveguides 12 of the photonic platform 8 are structurally identical. This uniformity makes manufacturing particularly simple and rapid. However, it should be emphasized that the semiconductor device according to the invention may of course also include… Figure 2 , Figures 4 to 8 , Figure 10 , Figure 11 and / or Figures 17 to 23 The different instances shown, for example, according to Figure 2 The detector 15 having a lower waveguide 12 and according to Figure 8 Modulator 15 and waveguide 12. According to Figure 2 , Figures 4 to 8 , Figure 10 , Figure 11 and / or Figures 17 to 23 There can also be two or more different instances; for example, each instance can appear once or more.

[0239] In order to enable the arrangement of an additional planarization coating 13 in the photonic platform 8 (see, for example) Figure 2 , Figure 4 and Figure 8 ) and arrangements without such coatings (see, for example) Figure 5 , Figure 10 and Figure 11 It can be stipulated that, after preferably two-dimensionally fabricating an additional planarization coating 13, this coating is partially removed again (e.g., by photolithography and subsequent etching) in areas where no additional planarization coating is required. For other coatings needed only in some places and not all places, a completely similar procedure can or has been used.

[0240] The active elements 16, 16a, and 16b of each electro-optic device can be... Figures 12 to 16 The conductive connection shown is made to one or (in the case of a detector) to both contact elements 19. All active elements 16, 16a, 16b of the semiconductor device according to the invention may be contacted with the contact element 19 in the same manner. Alternatively, different active elements 16 of the device may be contacted in different manner, of course.

[0241] exist Figure 3 and Figure 9 In addition to active elements 16, 16a, 16b, waveguide 12, and contact element 19, a coupling device 32 of the photonic platform 8 is schematically shown, which is used to couple light into or out of the waveguide 12. One coupling device 32 is arranged at each opposite end of a respective waveguide 12. In this example, each coupling device 32 is designed as a side-mounted or grating-mounted coupling device. Figures 24 to 27 A simple schematic diagram of such an instance is shown. Figure 24 and Figure 25 Plan view and cross-sectional view of the side coupling device 32 are shown. Figure 26 and Figure 27 Plan view and cross-sectional view of grating coupling device 32 are shown.

[0242] The coupling device 32, or two coupling devices 32, may be associated with several waveguides 12 or each waveguide 12 of the photonic platform 8. Specifically, in cases where light will be coupled in and out, two coupling devices 32 are already associated with or connected to waveguides 12. However, it is also possible that only possible initial coupling is required. In that case, one coupling device 32 is sufficient.

[0243] Figure 24 and Figure 25 An example of the side coupling device 32 shown includes a side coupling element 33, which is preferably composed of resin or a resin-containing material (particularly SU8, and / or silicon nitride, and / or silicon oxynitride, or a dielectric) with a refractive index between that of the waveguide 12 (particularly n = 2.4) and that of the element 33 used as a mode field converter (SU8 n = 1.56), such as alumina (n = 1.68). It can be seen that the latter is characterized by the width b and height h exceeding the extension of the waveguide 12 in the respective directions; in this example, each case corresponds to a multiple thereof. The side coupling device 32 also includes an end portion 34 of the waveguide 12 extending into the side coupling element, from... Figure 24 It can be easily seen that the distal portion 34 tapers gradually towards its end in a conical shape. It should be noted that... Figure 24 In the diagram, the outer contour of the tapered portion 34 is represented by a thin line because it is obscured by the cross-section of element 33 in the planar view. Element 33 matches the mode field from the diameter of the optical fiber (e.g., 5 µm to 15 µm) to the dimensions of waveguide 12 (e.g., a height of 300 nm and a width of 1.1 µm). The tapered tip 34 of waveguide 12 causes an adiabatic adjustment of the effective refractive index in the region of the mode field, allowing the optical mode to gradually shift from the coupling structure into waveguide 12.

[0244] from Figure 26 As can be seen from the top view, the grating coupling device 32 is formed by the end portion 35 of the waveguide 12, which widens into a conical shape towards the end, and as... Figure 27 As shown in the cross-sectional view, its side has a grating structure 36 facing away from the wafer 5. This widening allows the dimensions of the waveguide 12 (e.g., 300 nm high, 1.1 µm wide) to accommodate the diameter of the mode field in the optical fiber (e.g., 5 µm to 15 µm), thereby improving coupling efficiency. According to... Figure 26 In the top view, the grating structure 36 is simplified to just a few parallel lines. Incident light is diffracted through a grating arrangement with a refractive index step. The dimensions of the grating are conveniently calculated such that, at a given incident angle, the first diffraction order is located in waveguide 12, thus allowing light to couple into waveguide 12.

[0245] The coupling device 32 and the corresponding waveguide 12 are located in a plane, that is, they are located on the side 11 of the planarization coating 10 away from the wafer 5.

[0246] Including partial views Figures 21 to 23 In the diagram, the waveguide 12, which is only partially shown, may also have an invisible coupling device 32 at its end.

[0247] In addition to the electro-optic device 15, the photonic platform 8 may also include one or more optical devices. For example, these may be one or more interferometers, such as Mach-Zehnder interferometers, and / or MMIs and / or directional couplers and / or ring resonators and / or polarization converters and / or beam splitters. The optical devices are typically formed from multiple sections of the waveguide 12, which are then arranged accordingly. In particular, they constitute a passive structure of the waveguide 12 or a longitudinal waveguide section. The sections, especially the longitudinal sections, i.e., the longitudinal portion of the waveguide 12, are, for example... Figure 2 , Figures 4 to 11 The waveguide 12 shown can be a component of such an optical device in each case, specifically, the portion located in front of or behind the electro-optic device 15 in a direction perpendicular to the plane of the drawing.

[0248] The photonic platform 8 may also include one or more thermo-optical devices. For example, one such device includes a heating element and a longitudinal portion of a waveguide 12, the heating element being arranged relative to the waveguide portion such that the heating element can heat the waveguide portion. Heating the waveguide 12 by the heating element can change the refractive index of the waveguide 12 in the longitudinal portion. For example, this effect can be used for phase matching. The thermo-optical devices may also be associated with or constitute part of an interferometer of the photonic platform. For example, Figure 2 , Figures 4 to 11 The longitudinal portion of the waveguide 12 shown can be part of the thermo-optical device, or it can be a portion located in front of or behind the electro-optical device 15 in a direction perpendicular to the plane of the attached drawing.

[0249] The photonic platform 8 also includes a passivation coating 37 that extends over the electro-optic device 15 and preferably forms the upper surface of the photonic platform 8 and the semiconductor device (see [link]). Figure 1 The passivation coating 37 also constitutes a cladding layer. It should be noted that, according to... Figure 3 and Figure 9 The passivation coating 37 is not shown in the view; only the device 15 below is shown.

[0250] In order to obtain Figure 1 The semiconductor device shown, in step S1 (see...) Figure 28 In this process, wafer 1 is provided with an integrated circuit including integrated electronic components 3 and metallization including VIA 7. Wafer 1 can be any conventional type of wafer 1 obtained by previously known manufacturing processes.

[0251] Then, photonic platform 8 is fabricated on BEOL 6 of wafer 1.

[0252] Specifically, in the second step S2, a planarization coating 10 is fabricated in the back-end process 6 of wafer 1. For this purpose, a coating material (in this case, silicon dioxide (SiO2)) is applied, which can be achieved by chemical vapor deposition, such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition, or spin coating of a spin-coating glass. In this example, PECVD is used. After depositing the coating material, the sides of the coating facing away from wafer 5 are planarized (step S3), in this case, by resist planarization, thereby obtaining sides 11 facing away from wafer 5 with a roughness of 0.2 nm RMS.

[0253] Resist planarization involves a single or repeated spin-coating of glass followed by etching, in this case reactive ion etching (RIE). The spin-coated glass partially compensates for height differences; that is, after spin-coating, valleys in the topology have a higher coating thickness than adjacent ridges. If the entire spin-coated glass is etched afterward, for example by RIE, the height difference is reduced due to the planarization effect of the spin-coated glass. By repeating the steps, the height difference can be further reduced until the desired roughness is achieved.

[0254] It should be noted that, alternatively, for example by chemical mechanical polishing (CMP), the planarization coating 10 can be obtained on the side 11 of the wafer 5 facing away from the wafer 5 with a correspondingly low roughness.

[0255] In the next step S4, the waveguide is fabricated. For this purpose, a waveguide material is deposited, in this case titanium dioxide (TiO2), particularly over the entire surface 11 of the resulting planarization coating 10. Similar to the planarization coating, the material can be deposited by PVD or CVD, particularly PECVD or LPCVD, or by spin coating. Atomic layer deposition (ALD) or transfer processes can also be performed. Similar to the planarization coating 10, LPCVD is used. Individual waveguides 12 are obtained, specifically through photolithography and fabrication by reactive ion etching (RIE).

[0256] To obtain the strip waveguide 12 (for example, see...) Figure 3 and Figure 8 The waveguide material is completely removed where the strip waveguide 12 is not retained; in other words, it is etched into the underlying coating 10.

[0257] Including its waveguide ends 34 and 35 (see Figure 3 , Figure 9 and Figures 24 to 27The coupling device 32, including the ridge waveguide 12 or the strip waveguide 12, is fabricated in this example together with the ridge waveguide 12, wherein for the ridge waveguide 12, the lateral extension of the waveguide 12 in the region of the coupling point can be removed by dry chemical means in a separate etching step. The waveguide 12, consisting of stacked coatings, can be constructed with the uppermost coating 12a after the coating structure is completed, and for the ridge waveguide 12, the lateral extension of the waveguide in the region of the coupling point can be removed by dry chemical means in a separate etching step. In all cases, a mode converter can be defined between the ridge waveguide 12 and the strip waveguide 12, and a portion of the ridge waveguide 12 can be formed into the strip waveguide 12 using photolithography and RIE.

[0258] The grating coupler 32 with grating structure 36 can be photolithographically defined and dry chemically structured.

[0259] For the side-coupled element (mode converter) 33, dielectrics and / or semiconductors and / or resins and / or polymers are deposited in one or more layers and structured by photolithography and / or RIE.

[0260] In the next step S5, an additional planarization coating 13 is fabricated on the side 11 of the waveguide 12 and the planarization coating 10. In this example, this is achieved in a manner completely similar to that of the planarization coating 10, using PECVD and resist planarization deposition. Due to resist planarization, the additional planarization coating 13 above the waveguide 12 has a trapezoidal cross-section (see...). Figure 2 ).

[0261] Furthermore, regarding the additional planarization coating 13, other processes described above besides LPCVD and CMP can be used, and another planarization treatment (e.g., CMP) and / or further planarization are possible, as described above for planarization coating 10. If CMP is used, a flat surface is typically obtained, i.e., no trapezoidal portion above waveguide 12, such as... Figure 2 As shown (for example, Figure 4 and Figure 9 ).

[0262] The planarization coating 10 and the additional planarization coating 13 may include one or more overlays, which are preferably disposed on the planarized surface and may be, for example, a dichalcogenide layer or a dichalcogenide heterostructure or a boron nitride layer. These materials are preferably deposited or transferred without the need for further chemical mechanical polishing or further resist planarization, although the possibility of repeating this process is not excluded.

[0263] For completeness, it should be noted that if the semiconductor device according to the invention also has areas without additional planarization coating 13 (e.g., the structure in the area is the same as according to...), Figure 5 , Figure 10or Figure 11 The area corresponding to the structure is then partially removed again by photolithography and etching, in particular by photolithography and etching.

[0264] In step S6, VIA 7 is fabricated using planarization coating 10 and an additional planarization coating 13. In principle, this can be achieved in any manner known in the prior art. Specifically, these areas to be extended are preferably first defined by photolithography and then dry chemically etched using RIE. Metallization is then performed, and the metallized surface is constructed, for example, by CMP (Catalyst Processing) or by photolithography and RIE. VIA 7 can be fabricated either through planarization coating 10 and planarization coating 13 after the additional planarization coating 13 is completed, or a portion of VIA 7 can be fabricated through the first planarization coating 10 after the first coating 10 is completed, and a portion of VIA 7 can be fabricated through the second planarization coating 13 after the second planarization coating 13 is completed.

[0265] Subsequently, electro-optical device 15 was manufactured.

[0266] Therefore, in step S7, the active elements of the detector given by the graphene film 16 are disposed on the side 14 of the additional planarization coating 3 away from the wafer 5, for example, deposited on the side 14, and then the contact element 19 (single layer or multiple layers) is obtained in step S8.

[0267] The deposition of the graphene film 16 can be performed, for example, by a transfer process as described in more detail above. Then, specifically, in each case, the graphene film, fabricated on a separate substrate or a separate metal foil or a separate germanium sheet, is transferred to an additional planarization coating 13. Alternatively, the graphene film can be prepared directly on the additional planarization coating 13. This can include, for example, material deposition.

[0268] If a transfer process is used, the passivation coating 25 may have already been applied to the side of the corresponding graphene film 16 facing away from the wafer 5, for example, the layer has already been deposited thereon, and then transferred together with it. Alternatively, the passivation coating 25 may also be deposited after the transfer or fabrication of the graphene film 16.

[0269] Alternatively, a full-area graphene film and / or a full-area passivation coating may first be fabricated on another planarization coating 13, extending across the entire surface of the other planarization coating 13. In this case, further structuring is then performed, particularly by photolithography and RIE, to obtain a single graphene film 16 as an active element of a plurality of electro-optic devices 16.

[0270] Then, preferably by depositing a layer over the entire surface ( Figure 12 ) or more layers ( Figures 13 to 16The metal is then used to fabricate contact element 19 or its layers 19a to 19d through photolithography and RIE construction.

[0271] Contact can be achieved by following the manufacturing sequence described first, the graphene film 16, and then the contact element 19, as follows: Figures 12 to 14 As shown.

[0272] for Figure 15 and Figure 16 The contact variant shown first involves fabricating only the lower metal layer 19c or metal layer 19a of the contact element 19, followed by fabricating the graphene film 16, and then fabricating additional layers 19b, 19d, or two additional layers 19a, 19b or 19d, 19b. This can also be accomplished through full-area deposition of appropriate metal and subsequent structuring via photolithography and RIE.

[0273] In the penultimate step S9, passivation 37, preferably Al2O3 and SiO2, is deposited on the upper surface. During this passivation, openings, particularly openings for contact elements, are then appropriately fabricated using photolithography and RIE (step S10). Preferably, openings are fabricated for connecting photonics and / or electronics to external contact elements.

[0274] Through the above steps, a semiconductor device composed of strip waveguide 12 and electro-optic device 15 can be obtained, such as... Figure 2 As shown.

[0275] To obtain a semiconductor device, said semiconductor device specifically (or additionally) has, as Figure 4 If the region shown in the diagram includes the ridge waveguide 12, then only step S4 needs to be changed so that segment 12a is etched laterally to a smaller depth, so that the waveguide material is still retained laterally in segment 12a, and segments 12b and 12c, which are not present in the strip waveguide, are obtained.

[0276] In order to obtain such Figure 5 The structure shown requires the partial removal of the additional planarization coating 13 before fabricating the ridge waveguide 12. If the desired semiconductor device does not have the additional planarization coating 13 at any point, then its fabrication can, of course, be completely omitted.

[0277] In order to obtain Figure 6 In the example shown, the lower waveguide segment 12c is first fabricated on the side of the planarization coating 10 facing away from the wafer using the method described above (e.g., PECVD). Then, active elements (in this case, the graphene film 16) and contact elements 19 are fabricated, the fabrication order again depending on the selected [option / method / process]. Figures 12 to 16 Which contact scheme is shown? Then, on graphene film 16 (only) Figures 12 to 16(As shown) a passivation coating 25 is prepared, and then the passivation coating 25 is prepared in two sections 12b and 12a and coating 37.

[0278] In order to obtain Figure 7 The arrangement shown can follow a basically similar procedure, except that the step of fabricating waveguide segment 12c is omitted, and a graphene film 16 is disposed on the side 11 of the planarization coating 10 away from the wafer 5.

[0279] Furthermore, the process for manufacturing a semiconductor device according to the invention, which includes one or more modulators 15 as electro-optic devices, differs in part from the process described above. Figure 2 The process described.

[0280] For example, for according to Figure 8 In the example, until the additional planarization coating 13 and VIA 7 are manufactured through planarization coating 10 and planarization coating 13, the process can be the same in principle, that is, steps S1 to S6 can be the same.

[0281] However, the fabrication of each modulator 15 involves first setting a lower graphene film 16a as one of two active elements on another planarization coating 13, and in its orientation... Figure 8 The left-hand end region produces only one contact element 19. For one graphene film 16 and two contact elements 19, they can be combined with the above. Figure 2 It is manufactured in the same manner as described.

[0282] Subsequently, the dielectric coating 17 is provided, for example, by deposition of preferably alumina. It is also possible to provide the dielectric coating 17 by a transfer process.

[0283] Then, a second upper graphene film 16b is fabricated, and the graphene film 16b is oriented... Figure 6 The right-hand end region is used to fabricate the second contact element 19. For one graphene film 16 and two contact elements 19, they can be combined with the above. Figure 2 Production is carried out again in the same manner described.

[0284] Then, the above steps S8 and S9 can be followed to obtain the upper passivation 37 and its opening.

[0285] For according to Figure 10 The structure can also be modified by performing steps S1 to S6 in the same way, and then the additional planarization coating 13 can be partially removed again. Alternatively, their production can be omitted (i.e., step S5), and in step S6 only VIA can be manufactured through the planarization coating 10.

[0286] Then, on the side 11 of the planarization coating 10 facing away from the wafer 5, segment 12d (i.e., waveguide substrate) is fabricated by depositing an optically transparent, preferably dielectric, coating or semiconductor and structuring it by photolithography and RIE. In this example, TiO2 is deposited.

[0287] On the side of the waveguide substrate 12d facing away from the wafer 5, a lower graphene film 16a is fabricated, followed by a contact element 19 belonging to it. Above this is the waveguide segment 12c, and above that is an upper graphene film 16b with the associated contact element 19. Above that is the waveguide segment 12b, and above that is the waveguide segment 12a. The waveguide segment 12a is characterized by a width significantly smaller than the other segments 12b, 12c, and 12d. The material of the waveguide segment 12b can be fabricated, for example, by ALD, or by CVD or transfer and ALD to obtain a chalcogenide coating, and / or by PVD to obtain a dielectric or semiconductor material coating, and constructed by photolithography and RIE. Subsequently, segment 12a is provided, wherein a dielectric or semiconductor material and / or dichalcogenide coating obtained by CVD or transfer is provided by ALD and / or PVD and / or PECVD and / or LPCVD, and constructed using photolithography and RIE.

[0288] The manufacturing methods of graphene films 16a and 16b and contact element 19 are combined with the above. Figure 2 The method described is the same.

[0289] In this example, the upper graphene film 16 extends within the waveguide 12.

[0290] Finally, steps S9 and S10 can be performed to obtain the passivation coating 37 and the opening therein again.

[0291] In order to obtain the basis Figure 11 The arrangement can be mainly based on the above. Figure 10 The description is presented in the same way, the only difference being that... Figure 10 The lowermost waveguide segment 12d is fabricated, and the lower graphene film 16a is fabricated directly on the side 11 of the planarization coating 10.

[0292] In order to obtain such Figure 17 The arrangement shown can be followed again with the same procedure until the planarization coating 10 is completed (steps S1 to S3). Then, on its side 11 facing away from wafer 5, the silicon coating 16 is fabricated as an active element. This can again involve material deposition, for example by one of the aforementioned processes, such as CVD or PVD or spin coating, followed by structuring (e.g., photolithography and RIE) to obtain a T-shape. The resulting ridge waveguide side is p-doped, and the other side is n-doped to obtain 16p and 16n regions. Thus, a pn junction is obtained. Contact elements 19 can then be fabricated.

[0293] for Figure 18 The design shown is a so-called SISCAP modulator 15. Steps S1 to S3 can also be the same. Then, two silicon coatings 16a and 16b are fabricated to form active elements. The fabrication process can also include material deposition, for example by one of the aforementioned processes, such as CVD or PVD processes or spin coating, and subsequent structuring (e.g., photolithography and RIE), and fabrication of associated contact elements 19.

[0294] for Figure 19 In principle, it can be as follows Figure 17 As shown, an element 26 made of electro-optic polymer is added between the two elements 16a and 16b.

[0295] In order to obtain such Figure 20 The modulator 15 shown, steps S1 to S5 can be combined with the above. Figure 2 The same applies. Then, a first electrode 28 with associated contact elements 19 can be fabricated on the side 14 of the additional planarization coating 13 away from the wafer 5, followed by the fabrication of a diode 27 with coatings 27a to 27d, and then the fabrication of a second electrode 28 with associated contact elements 19, thereby allowing material deposition and subsequent structuring in each case.

[0296] Finally, Figures 17 to 20 In all instances, coating 37 can be prepared in a manner similar to the remaining instances.

[0297] As can be seen from the above, the photonic platform 8 is fabricated directly on BEOL 6 of wafer 1. In other words, the photonic platform 8 is monolithically fabricated on wafer 1, or it is a monolithic platform 8. Specifically, coatings 10, 13, 37 and waveguide 12 are fabricated directly on wafer 1 by depositing appropriate materials on BEOL 6 of wafer 1 or on coatings already fabricated thereon. There is no separate fabrication of coatings 10, 13, 37 or waveguide 12 and no subsequent bonding.

[0298] It should be noted that the above-described method for manufacturing the semiconductor device according to the present invention is an embodiment of the method according to the present invention.

[0299] After completing the semiconductor device according to the invention, multiple chips with integrated photonics can be obtained from it in a simple and rapid manner, specifically, simply by cutting, or in other words by splitting.

[0300] exist Figure 1The semiconductor device shown can be diced, including, for example, by (laser) cutting and / or sawing and / or breaking along the lines defining chip region 4. In principle, dicing can be performed in any manner known in the prior art, particularly in the manner used in the prior art for conventional wafer 1.

[0301] Figure 29 Three chips with integrated photonics are shown by way of example and purely illustration, obtained by such cutting in the plan view. These represent embodiments of semiconductor devices 38 according to the invention. Each of these semiconductor devices 38 includes a chip 39 and a portion 40 of a photonic platform 8 thereon, the extent of the chip 39 corresponding to chip region 4 of wafer 1, and the lateral extent of the portion 40 being at least substantially consistent with the lateral extent of the chip 39 below due to the cutting. The chip 39 and the upper portion 40 of the photonic platform 8 can be obtained from... Figure 30 The cross-sectional view shown is purely schematic.

[0302] It should be noted that in this highly simplified illustration, only the two superimposed areas defined by chip 39 and photonic device 40 are shown, without showing their coatings and components.

[0303] Chip 39 includes, among other things, a plurality of integrated electronic components 3 (e.g., transistors and / or capacitors and / or resistors), said integrated electronic components 3 may be, for example, part of the processor of chip 39, and part 40 of photonic platform 8 includes, among other things, a plurality of electro-optical devices 15, for example, specifically from... Figures 2 to 11 as well as Figures 17 to 23 Obtained from.

[0304] Semiconductor devices 38 obtained by dicing the semiconductor device according to the invention, each semiconductor device 38 representing a bare die with monolithic integrated photonics, can then be inserted into a package, as known from conventional bare dies, and used for further application.

[0305] The photonic platform section 40 can be used, for example, to convert electrical signals from integrated electronic components of chip 39 into optical signals, enabling communication, for example, with other chips and / or other integrated electronic components 4 of device 38 via optical means. For this purpose, for example, the light can be modulated by a modulator 15 coupled to an integrated electronic component (e.g., transistor 4), and the modulated optical signal can be received by a photodetector 15 coupled to another integrated electronic component (e.g., transistor 4 of the same or different chip).

Claims

1. A semiconductor device comprising a wafer (1) having a preferably monolithic semiconductor substrate (2), particularly a silicon substrate, and at least one integrated electronic component (3) extending in and / or on the semiconductor substrate (2), the wafer (1) having a front-end process (5) and a back-end process (6) located above the front-end process (5), the front-end process (5) including the integrated electronic component or including at least one of the integrated electronic components (3), and a photonic platform (8) fabricated on a side (9) of the wafer (1) away from the front-end process (5), the photonic platform (8) including at least one waveguide (12) and at least one electro-optic device (15), particularly at least one photodetector and / or at least one electro-optic modulator, wherein the electro-optic device (15) of the photonic platform (8) or at least one of the electro-optic device (15) is connected to the integrated electronic component (3) of the wafer (1) or at least one of the integrated electronic components (3).

2. The semiconductor device according to claim 1, characterized in that, The back-end process (6) of the wafer (1) and the photonic platform (8) include interconnect elements (7), and at least one of the integrated electronic components (3) of the wafer (1) is connected to an electro-optic device (15) of the photonic platform (8) or at least one of the electro-optic devices (15) via the interconnect elements (7).

3. The semiconductor device according to claim 1 or 2, characterized in that, The photonic platform (8) includes material deposited on the side (9) of a wafer (1) away from the front-end process (5).

4. The semiconductor device according to any one of the preceding claims, characterized in that, The photonic platform (8) includes a planarization coating (10) composed of a dielectric material, which is particularly fabricated on the side (9) of the wafer (1) away from the front-end process (5), and preferably, at least one of the waveguides is fabricated on the side (11) of the planarization coating (12) away from the wafer (1).

5. The semiconductor device according to claims 3 and 4, characterized in that, The planarization coating (10) is a coating formed by deposition, particularly chemical vapor deposition, preferably low-pressure chemical vapor deposition and / or plasma-assisted chemical vapor deposition, and / or by physical vapor deposition and / or atomic layer deposition of at least one coating material on the side (9) of the wafer (1) away from the front-end process (5), and the planarization coating (10) is preferably a post-processing treatment of the deposited material on the side (11) away from the wafer (1) by chemical mechanical polishing and / or resist planarization. And / or, the planarization coating (10) has a roughness of less than 2.0 nm RMS, preferably less than 1.0 nm RMS, and particularly preferably less than 0.3 nm RMS on its side (11) opposite to the wafer (1). And / or, the planarization coating (10) comprises or consists of spin-coated glass and / or at least one polymer and / or at least one oxide, particularly silicon dioxide, and / or at least one nitride.

6. The semiconductor device according to any one of claims 3 to 5, characterized in that, The photonic platform (8) includes at least one additional planarization coating (13), and at least one of the additional planarization coating (13) is preferably made of the same material as the planarization coating (10).

7. The semiconductor device according to claim 6, characterized in that, The additional planarization coating (13) or at least one of the additional planarization coatings (13) is formed by deposition, particularly chemical vapor deposition, preferably low-pressure chemical vapor deposition and / or plasma-assisted chemical vapor deposition, and / or by physical vapor deposition and / or atomic layer deposition of at least one coating material on the side (9) of the wafer (1) away from the front-end process (5), and preferably by post-processing the deposited material on the side (14) away from the wafer (1) by chemical mechanical polishing and / or resist planarization. And / or, the roughness of at least one of the additional planarization coatings (13) on its side (14) opposite to the wafer (1) is less than 2.0 nm RMS, preferably less than 1.0 nm RMS, particularly preferably less than 0.3 nm RMS. And / or, at least one of the additional planarization coatings (13) or additional planarization coatings (13) comprises or consists of spin-coated glass and / or at least one polymer and / or at least one oxide, particularly silicon dioxide, and / or at least one nitride.

8. The semiconductor device according to any of the preceding claims, characterized in that, At least one waveguide (12) comprises or is composed of titanium dioxide and / or aluminum nitride and / or tantalum pentoxide and / or silicon nitride and / or aluminum oxide and / or silicon oxynitride and / or lithium niobate and / or silicon, particularly polycrystalline silicon, and / or indium phosphite and / or gallium arsenide and / or gallium indium arsenide and / or gallium arsenide aluminum and / or at least one dichalcogenide, particularly two-dimensional transition metal dichalcogenide, and / or chalcogenide glass and / or resin or resin-containing material, particularly SU8, and / or polymer-containing or polymer-containing material, particularly OrmoComp.

9. The semiconductor device according to any of the preceding claims, characterized in that, The photonic platform (8) includes a plurality of waveguides (12), preferably, at least two waveguides (12) extend one above the other in at least one portion.

10. The semiconductor device according to any of the preceding claims, characterized in that, Semiconductor devices, particularly photonic platforms (8), include at least one coupling device (32) associated with at least one of waveguides (12), the at least one coupling device (32) preferably used to couple electromagnetic radiation into at least one associated waveguide (12) and / or couple electromagnetic radiation out of at least one associated waveguide (12).

11. The semiconductor device according to any of the preceding claims, characterized in that, The electro-optic device (15) or at least one of the electro-optic devices (15) includes at least one active element (16, 16a, 16b), the active element (16, 16a, 16b) comprising or composed of at least one material that absorbs electromagnetic radiation of at least one wavelength and generates an electro-optic signal due to absorption and / or the material’s refractive index changing with the presence of voltage and / or charge and / or electric field.

12. The semiconductor device according to claim 11, characterized in that, The electro-optic device (15) or at least one of the electro-optic devices (15) is provided by a modulator (15), the modulator (15) comprising an active element (16a) having or being composed of at least one material whose refractive index changes with the presence of voltage and / or charge and / or electric field, the material comprising, in particular, graphene and / or at least one dichalcogenide, particularly two-dimensional transition dichalcogenides, and / or two-dimensional materials and / or germanium and / or lithium niobate and / or at least one electro-optic polymer and / or silicon heterostructures and / or at least one compound semiconductor, particularly at least one III-V semiconductor and / or at least one II-VI semiconductor. The modulator (15) includes additional active elements (16b) or electrodes, said additional active elements (16b) comprising or composed of at least one material whose refractive index varies with the presence of voltage and / or charge and / or electric field, said material comprising, in particular, graphene and / or at least one dichalcogenide, particularly two-dimensional transition dichalcogenides, and / or two-dimensional materials and / or germanium and / or lithium niobate and / or at least one electro-optic polymer and / or silicon heterostructures and / or at least one compound semiconductor, particularly at least one III-V semiconductor and / or at least one II-VI semiconductor. Two of the active elements (16a, 16b) or the active element and the electrode are preferably spaced apart from each other and / or offset from each other, such that they partially overlap.

13. The semiconductor device according to any of the preceding claims, characterized in that, The electro-optic device (15) or at least one of the electro-optic devices (15) is provided by a photodetector (15), which includes one, preferably exactly one, active element (16), the active element (16) comprising or composed of at least one material that absorbs electromagnetic radiation of at least one wavelength and generates an electro-optic signal due to absorption, the material including, in particular, graphene and / or at least one dichalcogenide, in particular two-dimensional transition dichalcogenide, and / or two-dimensional material and / or heterostructures of germanium and / or silicon and / or at least one compound semiconductor, in particular at least one III-V semiconductor and / or at least one II-VI semiconductor.

14. The semiconductor device according to any one of claims 11 to 13, characterized in that, At least one plasma structure (29) is disposed on or above at least one of the active elements or active elements (16, 16a, 16b), the at least one plasma structure (29) comprising or composed of a plasma-active material, preferably gold and / or silver and / or aluminum and / or copper, the plasma structure (29) preferably comprising at least a pair of plasma elements (30) arranged adjacent to each other, and the plasma elements (30) comprising or composed of a plasma-active material, the plasma elements (30) preferably having a portion that tapers gradually in the direction of the corresponding other plasma elements (30).

15. The semiconductor device according to claim 13, characterized in that, On at least one side of the active element or at least one active element (16, 16a, 16b), the waveguide (12) is provided with an end portion (31) that tapers gradually along the direction of the active element and preferably terminates at a tip, wherein the taper end portion (31) preferably extends to the active element or at least one active element (16, 16a, 16b), and / or wherein a contact element (19) is provided on each side of the taper portion (31), the contact element (19) being connected to the active element or at least one active element (16, 16a, 16b), and the contact element (19) having a portion (19a) that tapers gradually in the opposite direction, the portion (19a) being located next to the taper end portion (31) of the waveguide (12).

16. The semiconductor device according to claim 15, characterized in that, In each case, waveguides (12) are provided on both sides of an active element or at least one active element (16, 16a, 16b), the waveguides (12) having a terminal portion (31) that tapers gradually along the direction of the active element or at least one active element (16, 16a, 16b) and preferably terminates at a tip, wherein the corresponding tapered terminal portion (31) preferably extends to the active element or at least one active element (16, 16a, 16b), and / or wherein a contact element (19) is provided on each side of the corresponding tapered portion (31), the contact element (19) being connected to the active element or at least one active element (16, 16a, 16b), the contact element (19) having a portion (19a) that tapers gradually in the opposite direction, the portion (19a) being located next to the tapered terminal portion (31) of the corresponding waveguide (12).

17. A method for manufacturing a semiconductor device, comprising the following steps: A wafer (1) is provided, the wafer (1) having a preferably monolithic semiconductor substrate (2), particularly a silicon substrate, and at least one integrated electronic component (3) extending within and / or on the semiconductor substrate (2), the wafer (1) having a front-end process (5) and a back-end process (6) located above the front-end process (5), wherein the front-end process (5) includes the integrated electronic component (3) or at least one of the integrated electronic components (3). A photonic platform (8) is fabricated on the side (9) of a wafer (1) away from the front-end process (5). The photonic platform (8) includes at least one waveguide (12) and at least one electro-optic device (15), particularly at least one photodetector and / or at least one electro-optic modulator.

18. The method according to claim 17, characterized in that, The back-end process (6) of the provided wafer (1) includes interconnect elements (7) which are connected to the integrated electronic components (3) or at least one of the integrated electronic components (3) of the front-end process (5), and the interconnect elements (7) are fabricated in the photonic platform (8) which are connected to the interconnect elements (7) of the back-end process (6) on one hand and to the electro-optic device (15) or at least one of the electro-optic device (15) on the other hand.

19. The method according to claim 17 or 18, characterized in that, The fabrication of the photonic platform (8) involves depositing material on the side (9) of the wafer (1) away from the front-end process (5).

20. The method according to any one of claims 17 to 19, characterized in that, The fabrication of the photonic platform (8) includes: fabricating a planarization coating (10) consisting of a dielectric material, particularly on the side (9) of the wafer (1) away from the front-end process (5), and preferably, at least one of the waveguides (12) is fabricated on the side (11) of the planarization coating (10) away from the wafer (1).

21. The method according to claim 20, characterized in that, The fabrication of the planarization coating (10) includes applying a coating material, particularly depositing it onto the side (9) of the wafer (1), and the coating material is subsequently planarized at least on the side (11) of the planarization coating (10) facing away from the wafer (1), particularly by chemical mechanical polishing and / or resist planarization, preferably in such a way as to obtain a side roughness of less than 2.0 nm, preferably less than 1.0 nm RMS, and especially preferably less than 0.3 nm RMS.

22. The method according to any one of claim 20 or 21, characterized in that, Preferably, at least one additional planarization coating (13) is manufactured after at least one waveguide (12). The manufacture of the additional planarization coating (13) preferably includes coating material, particularly depositing it onto the side (11) of the planarization coating (10) away from the wafer (1) and / or at least one waveguide (12), and then planarizing the coating material at least on the side (14) of the additional planarization coating (13) away from the wafer (1), particularly chemical mechanical polishing and / or etch-resistant planarization, preferably in such a way as to obtain a side roughness of less than 2.0 nm, preferably less than 1.0 nm RMS, and especially preferably less than 0.3 nm RMS.

23. The method according to any one of claims 20 to 22, characterized in that, The fabrication of the planarization coating (10) and / or the additional planarization coating (13) includes applying an additional coating material to the treated side after the planarization process.

24. The method according to any one of claims 20 to 23, characterized in that, Fabrication of at least one waveguide (12) includes, in particular, coating waveguide material onto the side (11) of a planarization coating (10) away from the wafer (5), preferably deposited, rotated, or transferred on the side, and then preferably, in particular, structuring the coated waveguide material by photolithography and / or reactive ion etching.

25. The method according to any one of claims 17 to 24, characterized in that, For waveguide (12) or at least one waveguide (12), at least one coupling device (32) is manufactured, the coupling device (32) being used to couple electromagnetic radiation into the at least one waveguide (12) and / or to couple electromagnetic radiation out of the at least one waveguide (12).

26. A method of manufacturing at least one semiconductor device (38), wherein a semiconductor device according to any one of claims 1 to 16 is provided and said semiconductor device is diced.

27. A semiconductor device (38) obtained by dividing a semiconductor device according to any one of claims 1 to 16.

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