Reflective transmission line with negative impedance unit

Abstract

The invention relates to a reflective transmission line with a negative impedance unit. An integrated circuit includes a transmission line that includes a bandpass component. Each band-pass component (900, Fig. 9) comprises: a first inductor (L7, Fig. 9) having a first terminal and a second terminal; a second inductor (L9, Fig. 9) having a first terminal and a second terminal, the first inductor (L7) and the second inductor (L9) forming a transformer; a first capacitor (C11, Fig. 9) having a first terminal and a second terminal, the first terminal of the first capacitor (C11) being coupled to the first terminal of the first inductor (L7) and the second terminal of the first capacitor (C11) being coupled to the second terminal of the first inductor (L7); and a second capacitor (C13, Fig. 9) having a first terminal and a second terminal, the first terminal of the second capacitor (C13) being coupled to the first terminal of the second inductor (L9).

Description

Technical Field

[0001] This application relates to a reflective transmission line with negative impedance units. Background Technology

[0002] Integrated circuit (IC) transmission lines are used in RF / microwave circuits and influence passive design, impedance matching, and IC size. These transmission lines perform signal filtering operations, such as low-pass or band-pass filtering. Crosstalk between the reflecting elements of the transmission line can lead to reduced speed and accuracy. Some switches used in the reflecting elements are frequency-limited. Summary of the Invention

[0003] In one example, an integrated circuit includes a transmission line comprising bandpass units. Each bandpass unit includes: a first inductor having a first terminal and a second terminal; a second inductor having a first terminal and a second terminal, the first inductor and the second inductor forming a transformer; a first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the first terminal of the first inductor, and the second terminal of the first capacitor being coupled to the second terminal of the first inductor; and a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the first terminal of the second inductor, and the second terminal of the second capacitor being coupled to the second terminal of the second inductor.

[0004] In another example, a phase shifter includes a reflective phase shifter circuit system. The reflective phase shifter circuit system includes: a first distributed reflective load comprising a first negative impedance element; a second distributed reflective load comprising a second negative impedance element; and an I / Q generator having a first terminal, a second terminal, a third terminal, and a fourth terminal. The second terminal of the I / Q generator is coupled to the first distributed reflective load. The third terminal of the I / Q generator is coupled to the second distributed reflective load.

[0005] In another example, a device includes: a processor; a transceiver circuit system coupled to the processor; and an antenna array terminal coupled to the transceiver circuit system. The transceiver circuit system includes a bidirectional phase shifter circuit system. The bidirectional phase shifter circuit system includes: a first distributed reflective load including a first negative impedance element; a second distributed reflective load including a second negative impedance element; and an I / Q generator having a first terminal, a second terminal, a third terminal, and a fourth terminal. The second terminal of the I / Q generator is coupled to the first distributed reflective load. The third terminal of the I / Q generator is coupled to the second distributed reflective load. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating the example system.

[0007] Figure 2 This is a diagram illustrating another example system.

[0008] Figure 3 This is a diagram showing an example transceiver.

[0009] Figure 4 This is a diagram illustrating an example distributed reflective load (DRL) with negative impedance elements.

[0010] Figures 5A to 5E This is a schematic diagram illustrating an example negative impedance unit.

[0011] Figures 6A to 6F This is a schematic diagram showing other examples of negative impedance units.

[0012] Figure 7 This is a schematic diagram illustrating another example of a negative impedance unit.

[0013] Figures 8A to 8C This is a schematic diagram illustrating an example transmission line.

[0014] Figure 9 This is a diagram showing a bandpass component based on a dual-tuned transformer.

[0015] Figure 10 This is a graph showing the S-parameters of the phase shifter as a function of frequency under different control settings.

[0016] Figure 11 and 12 This is a diagram showing an example phase shifter. Detailed Implementation

[0017] Use the same reference numerals or other reference designators in the accompanying drawings to designate the same or similar features. Such features may be identical or similar in function and / or structure.

[0018] In the described examples, transmission lines with negative impedance units are used to provide distributed reflected load (DRL) functionality. As used herein, a “negative impedance unit” refers to a circuit that responds with a negative current to a positive voltage excitation at the input or with a positive current to a negative voltage excitation at the input (i.e., the current and voltage are 180 degrees out of phase). Each transmission line can provide low-pass or band-pass filtering. In some examples, each transmission line is a band-pass transmission line based on a double-tuned transformer, preventing crosstalk between negative impedance units. In some examples, the transmission line provides passive functionality or impedance matching for RF / microwave applications (e.g., through amplifiers, filters, etc.).

[0019] In some instances, the transmission line is part of a phase shifter or a related IC such as a transceiver integrated circuit (IC). An example phase shifter includes: a first transmission line having a first negative impedance unit; a second transmission line having a second negative impedance unit; and an I / Q generator having a first terminal, a second terminal, a third terminal, and a fourth terminal. The second terminal of the I / Q generator is coupled to the first transmission line. The third terminal of the I / Q generator is coupled to the second transmission line. In some instances, the phase shifter is used in radar or phased array communications (e.g., satellite communications (Satcom) / 5G) to control quadrature phase and amplitude, which reduces the calibration complexity of beam steering and sidelobe suppression. In some instances, the phase shifter is a passive phase shifter supporting bidirectional operation, which simplifies beamformer architecture. In some instances, the phase shifter is a bidirectional, calibration-free, low-loss phase shifter with low root-mean-square (RMS) amplitude and low phase error. In some instances, the phase shifter supports wideband operation based on a real-time delay option.

[0020] In some instances, the phase shifter operates at frequencies where switching cannot be designed (e.g., above 77 GHz). In such instances, the phase shifter comprises one or more of the following: a DRL with active open-circuit switches; or a DRL with active short-circuit switch circuitry. Each active open-circuit switch circuitry simulates an open circuit along the transmission line of the DRL. Each active short-circuit switch circuitry simulates a short circuit along the transmission line of the DRL.

[0021] In one example, the phase shifter is a bidirectional active reflective phase shifter (RTPS) with a DRL. In some examples, the DRL functionality provided by the negative impedance unit supports embedded phase inversion. In some examples, the negative impedance unit has inversion states including 0 degrees and 180 degrees. In some examples, the negative impedance unit has inversion states including 0 degrees and 360 degrees. In some examples, the impedance of each negative impedance unit is adjustable to match different impedance values ​​(e.g., 50Ω, 100Ω, etc.).

[0022] Figure 1 This is a diagram illustrating an example system 100. System 100 is an example of a phased array communication system (e.g., satellite communication or a 5G system). System 100 includes a first device 102 that communicates with a second device 132 via channel 130. Figure 1 In this example, channel 130 is a wireless channel. The first device 102 and the second device 132 are phased array communication components.

[0023] As shown in the figure, the first device 102 includes a processor 104, a transceiver 110, and an antenna array 122. The processor 104 has a first terminal 106 and a second terminal 108. In some embodiments, the first terminal 106 and the second terminal 108 are unidirectional terminals. In other embodiments, bidirectional terminals replace the first terminal 106 and the second terminal 108. The transceiver 110 has a first terminal 112, a second terminal 114, and third terminals 116A to 116N. In some embodiments, the first terminal 112 and the second terminal 114 are unidirectional terminals. In other embodiments, bidirectional terminals replace the first terminal 112 and the second terminal 114. The antenna array 122 has terminals 124A to 124N. Figure 1 In one example, transceiver 110 includes a bidirectional phase shifter 118 with a DRL 120. In some examples, the DRL 120 is based on a transmission line with negative impedance units as described herein.

[0024] The second device 132 includes a processor 134, a transceiver 140, and an antenna array 152. The processor 134 has a first terminal 136 and a second terminal 138. In some embodiments, the first terminal 136 and the second terminal 138 are unidirectional terminals. In other embodiments, bidirectional terminals replace the first terminal 136 and the second terminal 138. The transceiver 140 has a first terminal 142, a second terminal 144, and third terminals 146A to 146N. In some embodiments, the first terminal 142 and the second terminal 144 are unidirectional terminals. In other embodiments, bidirectional terminals replace the first terminal 142 and the second terminal 144. The antenna array 152 has terminals 154A to 154N. Figure 1 In one example, transceiver 140 includes a bidirectional phase shifter 148 with a DRL 150. In some examples, the DRL 150 is based on a transmission line with negative impedance units as described herein.

[0025] The first terminal 106 of the processor 104 is coupled to the first terminal 112 of the transceiver 110. The second terminal 108 of the processor 104 is coupled to the second terminal 114 of the transceiver 110. Each of the third terminals 116A to 116N of the transceiver 110 is coupled to a corresponding terminal of the antenna array 122, which is connected to terminals 124A to 124N.

[0026] The first terminal 136 of the processor 134 is coupled to the first terminal 142 of the transceiver 140. The second terminal 138 of the processor 134 is coupled to the second terminal 144 of the transceiver 140. Each of the third terminals 146A to 146N of the transceiver 140 is coupled to a corresponding terminal of the antenna array 152, which is connected to terminals 154A to 154N.

[0027] During the data transmission operation, the first device 102 is used to: generate data using the processor 104; encode the data for transmission using the transceiver 110; and transmit the encoded data to the channel 130 via the antenna array 122. In some instances, a bidirectional phase shifter 118 with a DRL 120 is used to phase shift the data of each antenna in the antenna array 122 (before or after encoding).

[0028] During the data reception operation, the first device 102 is used to: receive encoded data via channel 130 using antenna array 122; decode the encoded data using transceiver 110; and process the decoded data using processor 104. In some instances, a bidirectional phase shifter 118 with DRL 120 is used to phase shift the data from each antenna in antenna array 122 (before or after decoding).

[0029] During the data transmission operation, the second device 132 is used to: generate data using the processor 134; encode the data for transmission using the transceiver 140; and transmit the encoded data to the channel 130 via the antenna array 152. In some instances, a bidirectional phase shifter 148 with a DRL 150 is used to phase shift the data of each antenna in the antenna array 152 (before or after encoding).

[0030] During the data reception operation, the second device 132 is used to: receive encoded data via channel 130 using antenna array 152; decode the encoded data using transceiver 140; and process the decoded data using processor 134. In some instances, a bidirectional phase shifter 148 with DRL 150 is used to phase shift the data from each antenna in antenna array 152 (before or after decoding).

[0031] Figure 2 This diagram illustrates another example system. System 200 is an example of a radar system. System 200 includes device 202. In some instances, device 202 is a phased array communication component. Figure 2 In this example, device 202 is used to: transmit electromagnetic signals; receive reflections from objects in the surrounding environment 230; and determine parameters of the objects (e.g., position, velocity). Figure 2 In the example, the first object 232 and the second object 234 represent the surrounding environment 230.

[0032] As shown in the figure, device 202 includes a processor 204, a transceiver 210, and an antenna array 222. The processor 204 has a first terminal 206 and a second terminal 208. In some embodiments, the first terminal 206 and the second terminal 208 are unidirectional terminals. In other embodiments, bidirectional terminals replace the first terminal 206 and the second terminal 208. The transceiver 210 has a first terminal 212, a second terminal 214, and third terminals 216A to 216N. In some embodiments, the first terminal 212 and the second terminal 214 are unidirectional terminals. In other embodiments, bidirectional terminals replace the first terminal 212 and the second terminal 214. The antenna array 222 has terminals 224A to 224N. Figure 2 In one example, transceiver 210 includes a bidirectional phase shifter 218 with a DRL 220. In some examples, the DRL 220 is based on a transmission line with negative impedance units as described herein.

[0033] The first terminal 206 of the processor 204 is coupled to the first terminal 212 of the transceiver 210. The second terminal 208 of the processor 204 is coupled to the second terminal 214 of the transceiver 210. Each of the third terminals 216A to 216N of the transceiver 210 is coupled to a corresponding terminal of the antenna array 222, which is connected to terminals 224A to 224N.

[0034] During signal transmission operation, device 202 is used to: generate instructions using processor 204; in response to the instructions, prepare a signal or signal pattern for transmission using transceiver 210; and transmit the prepared signal or signal pattern to the surrounding environment 230 via antenna array 222. In some instances, a bidirectional phase shifter 218 with DRL 220 is used to phase shift the signal or signal pattern of each antenna in antenna array 222 (before or after preparation).

[0035] During signal reception operation, device 202 is used to: receive reflected signals or signal patterns from the surrounding environment 230 (e.g., due to the first object 232 and the second object 234) using antenna array 222; phase shift the received signals or signal patterns using transceiver 210; and analyze the phase-shifted signals or signal patterns using processor 204 to determine parameters of the first object 232 and / or the second object 234.

[0036] Figure 3 This is a diagram illustrating an example transceiver 300. Transceiver 300 is... Figure 1 Transceiver 110 in the middle Figure 1 Transceiver 140 or Figure 2 An example of transceiver 210 in [the context of the transceiver]. Figure 3In this example, the transceiver 300 has a first terminal 302, a second terminal 304, a third terminal 306, a fourth terminal 308, and a fifth terminal 310. The first terminal 302, the second terminal 304, the third terminal 306, and the fourth terminal 308 are... Figure 1 The third terminal 116A to 116N in the middle, Figure 1 The third terminal 146A to 146N or Figure 2 Examples of terminals 216A to 216N in the third terminal configuration. Terminal 310 is a bidirectional terminal (replacing...). Figure 1 The bidirectional terminals of the first terminal 112 and the second terminal 114 of the transceiver 110 in the middle are replaced Figure 1 The bidirectional terminals of the first terminal 142 and the second terminal 144 of the transceiver 140, or alternatively Figure 2 An example of a transceiver 210 (the bidirectional terminals of the first terminal 212 and the second terminal 214).

[0037] exist Figure 3 In this example, transceiver 300 includes switch S1, a first low-noise amplifier (LNA) 312A, a first power amplifier 318A, switch S2, a first bidirectional phase shifter 324A, and a first variable gain circuit 330A. Transceiver 300 also includes switch S3, a second LNA 312B, a second power amplifier 318B, switch S4, a second bidirectional phase shifter 324B, and a second variable gain circuit 330B. Transceiver 300 further includes switch S5, a third LNA 312C, a third power amplifier 318C, switch S6, a third bidirectional phase shifter 324C, and a third variable gain circuit 330C. Transceiver 300 also includes switch S7, a fourth LNA 312D, a fourth power amplifier 318D, switch S8, a fourth bidirectional phase shifter 324D, and a fourth variable gain circuit 330D. The transceiver 300 also includes a first combiner / splitter circuit 336A, a second combiner / splitter circuit 336B, and a third combiner / splitter circuit 350.

[0038] Switch S1 has a first terminal T1, a second terminal T2, and a third terminal T3. First LNA 312A has a first terminal 314A and a second terminal 316A. First power amplifier 318A has a first terminal 320A and a second terminal 322A. Switch S2 has a first terminal T1, a second terminal T2, and a third terminal T3. First bidirectional phase shifter 324A has a first terminal 326A and a second terminal 328A. First variable gain circuit 330A has a first terminal 332A and a second terminal 334A.

[0039] Switch S3 has a first terminal T1, a second terminal T2, and a third terminal T3. Second LNA 312B has a first terminal 314B and a second terminal 316B. Second power amplifier 318B has a first terminal 320B and a second terminal 322B. Switch S4 has a first terminal T1, a second terminal T2, and a third terminal T3. Second bidirectional phase shifter 324B has a first terminal 326B and a second terminal 328B. Second variable gain circuit 330B has a first terminal 332B and a second terminal 334B.

[0040] Switch S5 has a first terminal T1, a second terminal T2, and a third terminal T3. The third LNA 312C has a first terminal 314C and a second terminal 316C. The third power amplifier 318C has a first terminal 320C and a second terminal 322C. Switch S6 has a first terminal T1, a second terminal T2, and a third terminal T3. The third bidirectional phase shifter 324C has a first terminal 326C and a second terminal 328C. The third variable gain circuit 330C has a first terminal 332C and a second terminal 334C.

[0041] Switch S7 has a first terminal T1, a second terminal T2, and a third terminal T3. The fourth LNA 312D has a first terminal 314D and a second terminal 316D. The fourth power amplifier 318C has a first terminal 320C and a second terminal 322C. Switch S8 has a first terminal T1, a second terminal T2, and a third terminal T3. The fourth bidirectional phase shifter 324D has a first terminal 326D and a second terminal 328D. The fourth variable gain circuit 330D has a first terminal 332D and a second terminal 334D.

[0042] The first combiner / splitter circuit 336A has a first terminal 338A, a second terminal 340A, and a third terminal 342A.

[0043] The second combiner / splitter circuit 336B has a first terminal 338B, a second terminal 340B, and a third terminal 342B.

[0044] The third combiner / splitter circuit 350 has a first terminal 352, a second terminal 354, and a third terminal 356.

[0045] The first terminal T1 of switch S1 is coupled to the first terminal 302 of transceiver 300. The second terminal T2 of switch S1 is coupled to the first terminal 314A of the first LNA 312A. The second terminal 316A of the first LNA 312A is coupled to the second terminal T2 of switch S2. The third terminal T3 of switch S1 is coupled to the second terminal 322A of the first power amplifier 318A. The first terminal 320A of the first power amplifier 318A is coupled to the second terminal T2 of switch S2. The first terminal T1 of switch S2 is coupled to the first terminal 326A of the first bidirectional phase shifter 324A. The second terminal 328A of the first bidirectional phase shifter 324A is coupled to the first terminal 332A of the first variable gain circuit 330A. The second terminal 334A of the first variable gain circuit 330A is coupled to the first terminal 338A of the first combiner / splitter circuit 336A.

[0046] The first terminal T1 of switch S3 is coupled to the second terminal 304 of transceiver 300. The second terminal T2 of switch S3 is coupled to the first terminal 314B of the second LNA 312B. The second terminal 316B of the second LNA 312B is coupled to the second terminal T2 of switch S4. The third terminal T3 of switch S3 is coupled to the second terminal 322B of the second power amplifier 318B. The first terminal 320B of the second power amplifier 318B is coupled to the second terminal T2 of switch S4. The first terminal T1 of switch S4 is coupled to the first terminal 326B of the second bidirectional phase shifter 324B. The second terminal 328B of the second bidirectional phase shifter 324B is coupled to the first terminal 332B of the second variable gain circuit 330B. The second terminal 334B of the second variable gain circuit 330B is coupled to the second terminal 340A of the first combiner / splitter circuit 336A.

[0047] The first terminal T1 of switch S5 is coupled to the third terminal 306 of transceiver 300. The second terminal T2 of switch S5 is coupled to the first terminal 314C of the third LNA 312C. The second terminal 316C of the third LNA 312C is coupled to the second terminal T2 of switch S6. The third terminal T3 of switch S5 is coupled to the second terminal 322C of the third power amplifier 318C. The first terminal 320C of the third power amplifier 318C is coupled to the second terminal T2 of switch S6. The first terminal T1 of switch S6 is coupled to the first terminal 326C of the third bidirectional phase shifter 324C. The second terminal 328C of the third bidirectional phase shifter 324C is coupled to the first terminal 332C of the third variable gain circuit 330C. The second terminal 334C of the third variable gain circuit 330C is coupled to the first terminal 338B of the second combiner / splitter circuit 336B.

[0048] The first terminal T1 of switch S7 is coupled to the fourth terminal 308 of transceiver 300. The second terminal T2 of switch S7 is coupled to the first terminal 314D of the fourth LNA 312D. The second terminal 316D of the fourth LNA 312D is coupled to the second terminal T2 of switch S8. The third terminal T3 of switch S7 is coupled to the second terminal 322D of the fourth power amplifier 318D. The first terminal 320D of the fourth power amplifier 318D is coupled to the second terminal T2 of switch S8. The first terminal T1 of switch S8 is coupled to the first terminal 326D of the fourth bidirectional phase shifter 324D. The second terminal 328D of the fourth bidirectional phase shifter 324D is coupled to the first terminal 332D of the fourth variable gain circuit 330D. The second terminal 334D of the fourth variable gain circuit 330D is coupled to the second terminal 340B of the second combiner / splitter circuit 336B. The third terminal 342A of the first combiner / splitter circuit 336A is coupled to the first terminal 352 of the third combiner / splitter circuit 350. The third terminal 342B of the second combiner / splitter circuit 336B is coupled to the second terminal 354 of the third combiner / splitter circuit 350. The third terminal 356 of the third combiner / splitter circuit 350 is coupled to the fifth terminal 310 of the transceiver 300.

[0049] exist Figure 3 In this example, the first terminal 302, the second terminal 304, the third terminal 306, and the fourth terminal 308 may be referred to as antenna terminals. The fifth terminal 310 may be referred to as a processor terminal. In different examples, the number of antenna terminals and processor terminals of the transceiver may vary to support different numbers of antennas and processors.

[0050] In some instances, transceiver 300 is used to receive or transmit signals from each of the first terminal 302, the second terminal 304, the third terminal 306, or the fourth terminal 308. To support receive and transmit operations, each of switches S1 through S8 may have a corresponding control terminal (not shown) and may be controlled by a controller (not shown) for either transmit or receive operations. When a first signal is received at the first terminal 302, switch S1 is configured for receive operation and couples the first terminal 302 of transceiver 300 to the first terminal 314A of the first LNA 312A. The first LNA 312A is used to: amplify the first signal received at the first terminal 314A based on low-noise amplification to obtain a first amplified signal; and provide the first amplified signal to the second terminal 316A. The first bidirectional phase shifter 324A is configured to: receive a first amplified signal at a first terminal 326A via a switch S2, the switch being configured to receive and couple a second terminal 316A of a first LNA 312A to the first terminal 326A of the first bidirectional phase shifter 324A; perform a phase shift on the first amplified signal to obtain a first phase-shifted signal; and provide the first phase-shifted signal at a second terminal 328A. The first variable gain circuit 330A is configured to: receive the first phase-shifted signal at a first terminal 332A; apply a gain to the first phase-shifted signal to obtain a first adjustment signal; and provide the first adjustment signal at a second terminal 334A. In some instances, the gain applied by the first variable gain circuit 330A inverts the amplitude variation introduced by the first bidirectional phase shifter 324A, and / or normalizes the amplitude of the first adjustment signal relative to other received signals (e.g., signals received at the second terminal 304, the third terminal 306, and / or the fourth terminal 308). In some instances, the gain applied by the first variable gain circuit 330A is less than 1 (i.e., attenuation is applied).

[0051] When a second signal is received at the second terminal 304, switch S3 is configured to receive and couple the second terminal 304 of transceiver 300 to the first terminal 314B of the second LNA 312B. The second LNA 312B is configured to: amplify the second signal received at the first terminal 314B based on low-noise amplification to obtain a second amplified signal; and provide the second amplified signal to the second terminal 316B. The second bidirectional phase shifter 324B is configured to: receive the second amplified signal at the first terminal 326B via switch S4, which is configured to receive and couple the second terminal 316B of the second LNA 312B to the first terminal 326B of the second bidirectional phase shifter 324B; perform a phase shift on the second amplified signal to obtain a second phase-shifted signal; and provide the second phase-shifted signal at the second terminal 328B. The second variable gain circuit 330B is configured to: receive the second phase-shifted signal at the first terminal 332B; apply gain to the second phase-shifted signal to obtain a second adjustment signal; and provide the second adjustment signal at the second terminal 334B. In some instances, the gain applied by the second variable gain circuit 330B inverts the amplitude change introduced by the second bidirectional phase shifter 324B, and / or normalizes the amplitude of the second adjustment signal relative to other received signals (e.g., signals received at the first terminal 302, the third terminal 306, and / or the fourth terminal 308). In some instances, the gain applied by the second variable gain circuit 330B is less than 1 (i.e., attenuation is applied).

[0052] When a third signal is received at the third terminal 306, switch S5 is configured to receive and couple the third terminal 306 of transceiver 300 to the first terminal 314C of the third LNA 312C. The third LNA 312C is configured to: amplify the third signal received at the first terminal 314C based on low-noise amplification to obtain a third amplified signal; and provide the third amplified signal to the second terminal 316C. The third bidirectional phase shifter 324C is configured to: receive the third amplified signal at the first terminal 326C via switch S6, which is configured to receive and couple the second terminal 316C of the third LNA 312C to the first terminal 326C of the third bidirectional phase shifter 324C; perform a phase shift on the third amplified signal to obtain a third phase-shifted signal; and provide the third phase-shifted signal at the second terminal 328C. The third variable gain circuit 330C is configured to: receive the third phase-shifted signal at the first terminal 332C; apply gain to the third phase-shifted signal to obtain a third adjustment signal; and provide the third adjustment signal at the second terminal 334C. In some instances, the gain inversion applied by the third variable gain circuit 330C is an amplitude change introduced by the third bidirectional phase shifter 324C, and / or the amplitude of the third adjustment signal is normalized relative to other received signals (e.g., signals received at the first terminal 302, the second terminal 304, and / or the fourth terminal 308). In some instances, the gain applied by the third variable gain circuit 330C is less than 1 (i.e., attenuation is applied).

[0053] When a fourth signal is received at the fourth terminal 308, switch S7 is configured to receive and couple the fourth terminal 308 of transceiver 300 to the first terminal 314D of the fourth LNA 312D. The fourth LNA 312D is configured to: amplify the fourth signal received at the first terminal 314D based on low-noise amplification to obtain a fourth amplified signal; and provide the fourth amplified signal to the second terminal 316D. The fourth bidirectional phase shifter 324D is configured to: receive the fourth amplified signal at the first terminal 326D via switch S8, which is configured to receive and couple the second terminal 316D of the fourth LNA 312D to the first terminal 326D of the fourth bidirectional phase shifter 324D; perform a phase shift on the fourth amplified signal to obtain a fourth phase-shifted signal; and provide the fourth phase-shifted signal at the second terminal 328D. The fourth variable gain circuit 330D is configured to: receive the fourth phase-shifted signal at the first terminal 332D; apply gain to the fourth phase-shifted signal to obtain a fourth adjustment signal; and provide the fourth adjustment signal at the second terminal 334D. In some instances, the gain inversion applied by the fourth variable gain circuit 330D is an amplitude change introduced by the fourth bidirectional phase shifter 324D, and / or the amplitude of the fourth adjustment signal is normalized relative to other received signals (e.g., signals received at the first terminal 302, the second terminal 304, and / or the third terminal 306). In some instances, the gain applied by the fourth variable gain circuit 330D is less than 1 (i.e., attenuation is applied).

[0054] The first combiner / splitter circuit 336A is configured to: receive a first adjustment signal at a first terminal 338A; receive a second adjustment signal at a second terminal 340A; and provide a first summation signal at a third terminal 342A in response to the first and second adjustment signals. The second combiner / splitter circuit 336B is configured to: receive a third adjustment signal at a first terminal 338B; receive a fourth adjustment signal at a second terminal 340B; and provide a second summation signal at a third terminal 342B in response to the third and fourth adjustment signals. The third combiner / splitter circuit 350 is configured to: receive the first summation signal at a first terminal 352; receive the second summation signal at a second terminal 354; and provide a third summation signal at a third terminal 356 in response to the first and second summation signals. The third summation signal is provided to a fifth terminal 310 of the transceiver 300. In some embodiments, the third summation signal is provided to a processor for processing.

[0055] When transmitting, transceiver 300 is used to: receive a basic signal at the fifth terminal 310; separate the basic signal into branch signals using a third combiner / splitter circuit 350, a first combiner / splitter circuit 336A, and a second combiner / splitter circuit 336B; and adjust the branch signals using first, second, third, and fourth variable gain circuits 330A to 330D and first, second, third, and fourth bidirectional phase shifters 324A to 324D.

[0056] In some instances, the third combiner / splitter circuit 350 is configured to: receive a basic signal at a third terminal 356; provide a first separation signal at a first terminal 352 in response to the basic signal and the signal separation operation of the third combiner / splitter circuit 350; and provide a second separation signal at a second terminal 354 in response to the basic signal and the signal separation operation of the third combiner / splitter circuit 350.

[0057] In some instances, the first combiner / splitter circuit 336A is configured to: receive a first split signal at a third terminal 342A; provide a first branch signal at a first terminal 338A in response to the first split signal and the signal splitting operation of the first combiner / splitter circuit 336A; and provide a second branch signal at a second terminal 340A in response to the first split signal and the signal splitting operation of the first combiner / splitter circuit 336A.

[0058] In some instances, the second combiner / splitter circuit 336B is configured to: receive a second split signal at a third terminal 342B; provide a third branch signal at a first terminal 338B in response to the second split signal and the signal splitting operation of the second combiner / splitter circuit 336B; and provide a fourth branch signal at a second terminal 340B in response to the second split signal and the signal splitting operation of the second combiner / splitter circuit 336B.

[0059] The first bidirectional phase shifter 324A is configured to: receive a first branch signal at a second terminal 328A; and, in response to the first branch signal and the phase shift operation of the first bidirectional phase shifter 324A, provide a first phase-shifted branch signal at a first terminal 326A. The first power amplifier 318A is configured to: receive the first phase-shifted branch signal at a first terminal 320A via a switch S2, the switch being configured for transmission operation and coupling the first terminal 326A of the first bidirectional phase shifter 324A to the first terminal 320A of the first power amplifier 318A; and, in response to the first phase-shifted branch signal and the operation of the first power amplifier 318A, provide a first amplified signal at a second terminal 322A. The first amplified signal is provided from the second terminal 322A of the first power amplifier 318A to the first terminal 302 of the transceiver 300 via a switch S1, the switch being configured for transmission operation and coupling the second terminal 322A of the first power amplifier 318A to the first terminal 302 of the transceiver 300.

[0060] The second bidirectional phase shifter 324B is configured to: receive a second branch signal at a second terminal 328B; and, in response to the second branch signal and the phase shift operation of the second bidirectional phase shifter 324B, provide a second phase-shifted branch signal at a first terminal 326B. The second power amplifier 318B is configured to: receive the second phase-shifted branch signal at a first terminal 320B via a switch S4, the switch being configured for transmission operation and coupling the first terminal 326B of the second bidirectional phase shifter 324B to the first terminal 320B of the second power amplifier 318B; and, in response to the second phase-shifted branch signal and the operation of the second power amplifier 318B, provide a second amplified signal at a second terminal 322B. The second amplified signal is provided from the second terminal 322B of the second power amplifier 318B to the second terminal 304 of the transceiver 300 via a switch S3, the switch being configured for transmission operation and coupling the second terminal 322B of the second power amplifier 318B to the second terminal 304 of the transceiver 300.

[0061] The third bidirectional phase shifter 324C is configured to: receive a third branch signal at the second terminal 328C; and provide a third phase-shifted branch signal at the first terminal 326C in response to the third branch signal and the phase-shifting operation of the third bidirectional phase shifter 324C. The third power amplifier 318C is configured to: receive the third phase-shifted branch signal at the first terminal 320C via a switch S6, the switch being configured for transmission operation and coupling the first terminal 326C of the third bidirectional phase shifter 324C to the first terminal 320C of the third power amplifier 318C; and provide a third amplified signal at the second terminal 322C in response to the third phase-shifted branch signal and the operation of the third power amplifier 318C. The third amplified signal is provided from the second terminal 322C of the third power amplifier 318C to the third terminal 306 of the transceiver 300 via a switch S5, the switch being configured for transmission operation and coupling the second terminal 322C of the third power amplifier 318C to the third terminal 306 of the transceiver 300.

[0062] The fourth bidirectional phase shifter 324D is configured to: receive a fourth branch signal at the second terminal 328D; and, in response to the fourth branch signal and the phase shift operation of the fourth bidirectional phase shifter 324D, provide a fourth phase-shifted branch signal at the first terminal 326D. The fourth power amplifier 318D is configured to: receive the fourth phase-shifted branch signal at the first terminal 320D via a switch S8, the switch being configured for transmission operation and coupling the first terminal 326D of the fourth bidirectional phase shifter 324D to the first terminal 320D of the fourth power amplifier 318D; and, in response to the fourth phase-shifted branch signal and the operation of the fourth power amplifier 318D, provide a fourth amplified signal at the second terminal 322D. The fourth amplified signal is provided from the second terminal 322D of the fourth power amplifier 318D to the fourth terminal 308 of the transceiver 300 via a switch S7, the switch being configured for transmission operation and coupling the second terminal 322D of the fourth power amplifier 318D to the fourth terminal 308 of the transceiver 300.

[0063] In some instances, each of the first bidirectional phase shifter 324A, the second bidirectional phase shifter 324B, the third bidirectional phase shifter 324C, and the fourth bidirectional phase shifter 324D includes a transmission line with negative impedance units to provide DRL functionality. Each transmission line can provide low-pass or band-pass filtering. In some instances, each transmission line is a band-pass transmission line based on a dual-tuned transformer, which prevents crosstalk between negative impedance units. In some instances, the transmission lines provide passive functionality or impedance matching for RF / microwave applications (e.g., through amplifiers, filters, etc.).

[0064] In some instances, transceiver 300 is an IC, and each phase shifter (e.g., each of the first, second, third, and fourth bidirectional phase shifters 324A to 324D) includes: a first transmission line having a first negative impedance unit; a second transmission line having a second negative impedance unit; and an I / Q generator having a first terminal, a second terminal, a third terminal, and a fourth terminal. The second terminal of the I / Q generator is coupled to the first transmission line. The third terminal of the I / Q generator is coupled to the second transmission line. In some instances, transceiver 300 is used in radar or phased array communications (e.g., satellite communications / 5G) to control quadrature phase and amplitude, which reduces the calibration complexity of beam steering and sidelobe suppression. In some instances, each phase shifter is a passive phase shifter supporting bidirectional operation, which simplifies beamformer architecture. In some instances, the phase shifter is a bidirectional "calibration-free" low-loss phase shifter with low RMS amplitude and low phase error. In some instances, each phase shifter supports wideband operation based on a real-time delay option. In some instances, each phase shifter operates at frequencies where switching is not feasible. In some instances, each phase shifter includes one or more of the following: a DRL; an active open-circuit switching circuit; and an active short-circuit switching circuit. In one instance, the phase shifter is a bidirectional active RTPS with a DRL. In some instances, the DRL functionality is based on a negative impedance unit that implements embedded phase inversion. For example, such a negative impedance unit can switch between two states to support embedded phase inversion with a flat amplitude response. In the first state A, the negative impedance unit may have a resistance... Where Z0 is the characteristic impedance of the transmission line, and α is a universal value. In the second state B, the negative impedance unit can have resistance. The results for both states are given below: and Where Γ negA It is the reflection coefficient of state A in the first state, Γ negB It is the reflection coefficient of state B in the second state. In some instances, Γ negA and Γ negB They have the same amplitude, but are 180 degrees out of phase.

[0065] Figure 4 This is a diagram illustrating an example DRL 400 with negative impedance units 412A to 412N. Figure 4In one example, the DRL400 includes terminals 402, an impedance line (signal path) 404, a resistor R0, and negative impedance units 412A to 412N. The impedance line 404 has a first terminal 406, a second terminal 408, and third terminals 410A to 410N. Each of the negative impedance units 412A to 412N has a corresponding first terminal 414A to 414N and a corresponding second terminal 416A to 416N. The resistor R0 has a first terminal and a second terminal. In some examples, the impedance line 404 and the resistor R0 have a matched resistance (e.g., 50Ω).

[0066] Terminal 402 of DRL 400 is coupled to the first terminal 406 of impedance line 404. The second terminal 408 of impedance line 404 is coupled to the first terminal of resistor R0. The second terminal of resistor R0 is coupled to ground or a grounded terminal. Each of the first terminals 414A to 414N of negative impedance units 412A to 412N is coupled to a corresponding terminal of the third terminals 410A to 410N of impedance line 404. Each of the second terminals 416A to 416N of negative impedance units 412A to 412N is coupled to ground or a grounded terminal.

[0067] exist Figure 4 In some examples, each of the negative impedance units 412A to 412N provides a phase shift θ. In some examples, the negative impedance units 412A to 412N are active open-circuit switching circuits or active short-circuit switches. In some examples, the active open-circuit switch provides a phase shift of 0 or 360 degrees, while the active short-circuit switch provides a phase shift of 0 or 180 degrees. The impedance of each negative impedance unit 412A to 412N can be varied as needed (e.g., to match a specific impedance line).

[0068] Utilizing reflection, each phase shift is doubled relative to terminal 402. For example, for a phase shift of 2Kθ relative to terminal 402, only the Kth negative impedance unit 412K is activated. For a phase shift of 2Nθ relative to terminal 402, only the Nth negative impedance unit 412N is activated. In some instances, the DRL 400 forms an "active open circuit" on the right side independent of the phase code. In some instances, the DRL 400 is bidirectional because each of the negative impedance units 412A to 412N is a parallel negative impedance unit relative to impedance line 404. In some instances, each of the negative impedance units 412A to 412N compensates only for resistor R0 to reduce instabilities caused by parasitic series / parallel resonances. Figure 4 In this example, the input voltage to terminal 402 is an alternating current (AC) voltage. In such an example, the positive voltage at terminal 402 is V. + =A∠0, the negative voltage at terminal 402 is V - =A∠(0+2Kθ), and the total voltage at terminal 402 is V = V+ +V - , where A is the amplitude of the input voltage and ∠ is the phase.

[0069] exist Figure 4 In some instances, the number of negative impedance units (e.g., negative impedance units 412A to 412N) can vary to support different phase shift resolutions. In some instances, the number of negative impedance units is limited by the transmission line length while maintaining the characteristic impedance (sqrt(L / C)). In some instances, the λ / 4 transmission line length is determined for the lowest target operating frequency. This λ / 4 transmission line length defines a 180-degree phase shift based on round trip. The transmission line contains smaller components (e.g., ...). Figures 8A to 8C The capacitors shown are LC pairs or bandpass components based on double-tuned transformers, where each component contains negative impedance units. The minimum number of components depends on the capacitive load of the negative impedance units. As the capacitance of the negative impedance units increases, a higher inductance is needed to achieve the characteristic impedance (sqrt(L / C)) of the transmission line, and fewer components are added. In some instances, λ / 4 transmission lines have 6 to 12 negative impedance units.

[0070] Figures 5A to 5E This is a schematic diagram illustrating example negative impedance units 500, 510, 520, 530, and 550. Each of the negative impedance units 500, 510, 520, 530, and 550 is an example of an active open-circuit switching circuit. Figure 5A The negative impedance unit 500 has a first terminal 501A and a second terminal 501B, wherein a negative impedance exists across the first terminal 501A and the second terminal 501B. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, the first terminal 501A and the second terminal 501B are coupled to an impedance line (e.g., Figure 4 Impedance line 404 in the middle.

[0071] The negative impedance unit 500 includes transistors M1 and M2 and a current source 502. Figure 5A In this example, transistors M1 and M2 are NPN bipolar transistors. In other examples, metal-oxide-semiconductor (MOS) transistors may be used. Transistor M1 has a first terminal, a second terminal, and a control terminal. Transistor M2 has a first terminal, a second terminal, and a control terminal. Current source 502 has a first terminal 504, a second terminal 506, and a third terminal 508.

[0072] The first terminal 501A of the negative impedance unit 500 is coupled to the first terminal of transistor M1 and the control terminal of transistor M2. The second terminal 501B of the negative impedance unit 500 is coupled to the first terminal of transistor M2 and the control terminal of transistor M1. The second terminals of transistors M1 and M2 are coupled to the first terminal 504 of the current source 502. The second terminal 506 of the current source 502 is coupled to ground or a grounding terminal. The third terminal 508 of the current source 502 receives a control signal CTL1 from a controller (not shown). The control signal CTL1 adjusts the current flow of the current source 502 in response to the target impedance (e.g., 50Ω, 100Ω, or others) of the negative impedance unit 500.

[0073] Figure 5B The negative impedance unit 510 has a first terminal 511A and a second terminal 511B, wherein a negative impedance exists across the first terminal 511A and the second terminal 511B. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, the first terminal 511A and the second terminal 511B are coupled to an impedance line (e.g., Figure 4 Impedance line 404 in the middle.

[0074] The negative impedance unit 510 includes transistors M3 and M4, capacitor C1, a first current source 512, and a second current source 516. Figure 5B In this example, transistors M3 and M4 are NPN bipolar transistors. In other examples, MOS transistors may be used.

[0075] Transistor M3 has a first terminal, a second terminal, and a control terminal. Transistor M4 has a first terminal, a second terminal, and a control terminal. Capacitor C1 has a first terminal and a second terminal. First current source 512 has a first terminal 513, a second terminal 514, and a third terminal 515. Second current source 516 has a first terminal 517, a second terminal 518, and a third terminal 519.

[0076] The first terminal 511A of the negative impedance unit 510 is coupled to the first terminal of transistor M3 and the control terminal of transistor M4. The second terminal 511B of the negative impedance unit 510 is coupled to the first terminal of transistor M4 and the control terminal of transistor M3. The second terminal of transistor M3 is coupled to the first terminal of capacitor C1 and the first terminal 513 of the first current source 512. The second terminal 514 of the first current source 512 is coupled to ground or a grounding terminal. The second terminal of transistor M4 is coupled to the second terminal of capacitor C1 and the first terminal 517 of the second current source 516. The second terminal 518 of the second current source 516 is coupled to ground or a grounding terminal. The third terminal 515 of the first current source 512 and the third terminal 519 of the second current source 516 receive a control signal CTL2 from a controller (not shown). The control signal CTL2 adjusts the current flow of the first current source 512 and the second current source 516 in response to the target impedance (e.g., 50Ω, 100Ω, or others) of the negative impedance unit 510.

[0077] Figure 5C The negative impedance unit 520 has a first terminal 521A and a second terminal 521B, wherein a negative impedance exists across the first terminal 521A and the second terminal 521B. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, the first terminal 521A and the second terminal 521B are coupled to an impedance line (e.g., Figure 4 Impedance line 404 in the middle.

[0078] The negative impedance unit 520 includes transistors M5 and M6, capacitor C2, resistor R1, first current source 522, and second current source 526. Figure 5C In this example, transistors M5 and M6 are NPN bipolar transistors. In other examples, MOS transistors may be used.

[0079] Transistor M5 has a first terminal, a second terminal, and a control terminal. Transistor M6 has a first terminal, a second terminal, and a control terminal. Capacitor C1 has a first terminal and a second terminal. Resistor R1 has a first terminal and a second terminal. First current source 522 has a first terminal 523, a second terminal 524, and a third terminal 525. Second current source 526 has a first terminal 527, a second terminal 528, and a third terminal 529.

[0080] The first terminal 521A of the negative impedance unit 520 is coupled to the first terminal of transistor M5 and the control terminal of transistor M6. The second terminal 521B of the negative impedance unit 520 is coupled to the first terminal of transistor M6 and the control terminal of transistor M5. The second terminal of transistor M5 is coupled to the first terminal of capacitor C2, the first terminal of resistor R1, and the first terminal 523 of the first current source 522. The second terminal 524 of the first current source 522 is coupled to ground or a grounding terminal. The second terminal of transistor M6 is coupled to the second terminal of capacitor C2, the second terminal of resistor R1, and the first terminal 527 of the second current source 526. The second terminal 528 of the second current source 526 is coupled to ground or a grounding terminal. The third terminal 525 of the first current source 522 and the third terminal 529 of the second current source 526 receive a control signal CTL3 from a controller (not shown). The control signal CTL3 adjusts the current flow of the first current source 522 and the second current source 526 in response to the target impedance (e.g., 50Ω, 100Ω, or others) of the negative impedance unit 520.

[0081] Figure 5D The negative impedance unit 530 has a first terminal 531A and a second terminal 531B, wherein a negative impedance exists across the first terminal 531A and the second terminal 531B. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, the first terminal 531A and the second terminal 531B are coupled to an impedance line (e.g., Figure 4 Impedance line 404 in the middle.

[0082] The negative impedance unit 530 includes transistors M7 to M10, capacitors C3 and C4, a first current source 532, a second current source 536, a third current source 540, and a fourth current source 544. Figure 5D In this example, transistors M7 through M10 are NPN bipolar transistors. In other examples, MOS transistors may be used.

[0083] Each of transistors M7 through M10 has a corresponding first terminal, a corresponding second terminal, and a corresponding control terminal. Capacitor C3 has a first terminal and a second terminal. Capacitor C4 has a first terminal and a second terminal. First current source 532 has a first terminal 533, a second terminal 534, and a third terminal 535. Second current source 536 has a first terminal 537, a second terminal 538, and a third terminal 539. Third current source 540 has a first terminal 541, a second terminal 542, and a third terminal 543. Fourth current source 544 has a first terminal 545, a second terminal 546, and a third terminal 547.

[0084] The first terminal 531A of the negative impedance unit 530 is coupled to the first terminal of transistor M7 and the control terminal of transistor M8. The second terminal 531B of the negative impedance unit 530 is coupled to the first terminal of transistor M8 and the control terminal of transistor M7. The second terminal of transistor M7 is coupled to the first terminal of capacitor C3 and the first terminal 533 of the first current source 532. The second terminal 534 of the first current source 532 is coupled to ground or a grounding terminal. The second terminal of transistor M8 is coupled to the second terminal of capacitor C3 and the first terminal 537 of the second current source 536. The second terminal 538 of the second current source 536 is coupled to ground or a grounding terminal. The third terminal 535 of the first current source 532 and the third terminal 539 of the second current source 536 receive a control signal CTL4 from a controller (not shown). The control signal CTL4 adjusts the current flow of the first current source 532 and the second current source 536 in response to the target impedance (e.g., 50Ω, 100Ω, or others) of the negative impedance unit 530.

[0085] As shown in the figure, the second terminal of transistor M7 is also coupled to the first terminal of transistor M9 and the control terminal of transistor M10. The second terminal of transistor M8 is also coupled to the first terminal of transistor M10 and the control terminal of transistor M9. The second terminal of transistor M9 is coupled to the first terminal of capacitor C4 and the first terminal 541 of the third current source 540. The second terminal 542 of the third current source 540 is coupled to ground or a grounded terminal. The second terminal of transistor M10 is coupled to the second terminal of capacitor C4 and the first terminal 545 of the fourth current source 544. The second terminal 546 of the fourth current source 544 is coupled to ground or a grounded terminal. The third terminal 543 of the third current source 540 and the third terminal 547 of the fourth current source 544 receive a control signal CTL5 from a controller (not shown). The control signal CTL5 adjusts the current flow of the third current source 540 and the fourth current source 544 in response to the target impedance (e.g., 50Ω, 100Ω, or others) of the negative impedance unit 530.

[0086] Figure 5E The negative impedance unit 550 has a first terminal 551A and a second terminal 551B, wherein a negative impedance exists across the first terminal 551A and the second terminal 551B. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, the first terminal 551A and the second terminal 551B are coupled to an impedance line (e.g., Figure 4 Impedance line 404 in the middle.

[0087] The negative impedance unit 550 includes transistors M11 to M14, inductors L1 and L2, capacitors C5 and C6, a first current source 552, a second current source 556, a third current source 560, and a fourth current source 564. Figure 5EIn this example, transistors M11 through M14 are NPN bipolar transistors. In other examples, MOS transistors may be used.

[0088] Each of transistors M11 to M14 has a corresponding first terminal, a corresponding second terminal, and a corresponding control terminal. Capacitor C5 has a first terminal and a second terminal. Capacitor C6 has a first terminal and a second terminal. First current source 552 has a first terminal 553, a second terminal 554, and a third terminal 555. Second current source 556 has a first terminal 557, a second terminal 558, and a third terminal 559. Third current source 560 has a first terminal 561, a second terminal 562, and a third terminal 563. Fourth current source 564 has a first terminal 565, a second terminal 566, and a third terminal 567.

[0089] The first terminal 551A of the negative impedance unit 550 is coupled to the first terminal of inductor L1. The second terminal of inductor L1 is coupled to the first terminal of transistor M11 and the control terminal of transistor M12. The second terminal 551B of the negative impedance unit 550 is coupled to the first terminal of inductor L2. The second terminal of inductor L2 is coupled to the first terminal of transistor M12 and the control terminal of transistor M11. The second terminal of transistor M11 is coupled to the first terminal of capacitor C5 and the first terminal 553 of the first current source 552. The second terminal 554 of the first current source 552 is coupled to ground or a grounded terminal. The second terminal of transistor M12 is coupled to the second terminal of capacitor C5 and the first terminal 557 of the second current source 556. The second terminal 558 of the second current source 556 is coupled to ground or a grounded terminal. The third terminal 555 of the first current source 552 and the third terminal 559 of the second current source 556 receive the control signal CTL4 from the controller (not shown). The control signal CTL4 adjusts the current flow of the first current source 552 and the second current source 556 in response to the target impedance (e.g., 50Ω, 100Ω or other) of the negative impedance unit 550.

[0090] As shown in the figure, the second terminal of transistor M11 is also coupled to the first terminal of transistor M13 and the control terminal of transistor M14. The second terminal of transistor M12 is also coupled to the first terminal of transistor M14 and the control terminal of transistor M13. The second terminal of transistor M13 is coupled to the first terminal of capacitor C6 and the first terminal 561 of the third current source 560. The second terminal 562 of the third current source 560 is coupled to ground or a grounded terminal. The second terminal of transistor M14 is coupled to the second terminal of capacitor C6 and the first terminal 565 of the fourth current source 564. The second terminal 566 of the fourth current source 564 is coupled to ground or a grounded terminal. The third terminal 563 of the third current source 560 and the third terminal 567 of the fourth current source 564 receive a control signal CTL6 from a controller (not shown). The control signal CTL6 adjusts the current flow of the third current source 560 and the fourth current source 564 in response to the target impedance (e.g., 50Ω, 100Ω, or others) of the negative impedance unit 550.

[0091] Figures 6A to 6F The diagram illustrates other examples of negative impedance units 600, 610, 620, 630, 640, and 650. Negative impedance units 600, 610, 620, 630, 640, and 650 are examples of active open-circuit switching circuits. Figure 6A The negative impedance unit 600 has a terminal 602, where a negative impedance exists. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, terminal 602 is coupled to an impedance line (e.g., in DRL 400). Figure 4 Impedance line 404 in the middle.

[0092] The negative impedance unit 600 includes a transistor M15, a capacitor C7, and a capacitor C8. Transistor M15 has a first terminal, a second terminal, and a control terminal. Capacitor C7 has a first terminal and a second terminal. Capacitor C8 has a first terminal and a second terminal. Figure 6A In this example, transistor M15 is an NPN bipolar transistor. In other examples, a MOS transistor may be used.

[0093] As shown in the figure, terminal 602 is coupled to the first terminal of capacitor C7 and the control terminal of transistor M15. The first terminal of transistor M15 is coupled to ground or a grounding terminal. The second terminal of capacitor C7 is coupled to the second terminal of transistor M15 and the first terminal of capacitor C8. The second terminal of capacitor C8 is coupled to ground or a grounding terminal.

[0094] Figure 6B The negative impedance unit 610 has a terminal 612, where a negative impedance exists. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, terminal 612 is coupled to an impedance line (e.g., in DRL 400). Figure 4 Impedance line 404 in the middle.

[0095] The negative impedance unit 610 includes a transistor M16, a capacitor C9, and a capacitor C10. Transistor M16 has a first terminal, a second terminal, and a control terminal. Capacitor C9 has a first terminal and a second terminal. Capacitor C10 has a first terminal and a second terminal. Figure 6B In this example, transistor M16 is an NPN bipolar transistor. In other examples, a MOS transistor may be used.

[0096] As shown in the figure, terminal 612 is coupled to the first terminal of capacitor C9 and the first terminal of transistor M16. The control terminal of transistor M16 is coupled to ground or a grounding terminal. The second terminal of transistor M16 is coupled to the second terminal of capacitor C9 and the first terminal of capacitor C10. The second terminal of capacitor C10 is coupled to ground or a grounding terminal.

[0097] Figure 6C The negative impedance unit 620 has a first terminal 622 and a second terminal 624, wherein a negative impedance exists at the first terminal 622. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, the first terminal 622 is coupled to an impedance line (e.g., in DRL 400). Figure 4 Impedance line 404 in the middle.

[0098] The negative impedance unit 620 includes a transistor M17 and an inductor L3. Transistor M17 has a first terminal, a second terminal, and a control terminal. Inductor L3 has a first terminal and a second terminal. Figure 6C In this example, transistor M17 is an NPN bipolar transistor. In other examples, a MOS transistor may be used.

[0099] As shown in the figure, the first terminal of inductor L3 is coupled to the second terminal 624, and the second terminal is... Figure 6C In this example, the terminals are power supply terminals. The second terminal of inductor L3 is coupled to the first terminal of transistor M17. The control terminal of transistor M17 is coupled to the first terminal 622. The second terminal of transistor M17 is coupled to ground or a grounding terminal.

[0100] Figure 6D The negative impedance unit 630 has a terminal 632, where a negative impedance exists. This is for use in DRLs (e.g.,...) Figure 4 Used in DRL 400), terminal 632 is coupled to an impedance line (e.g., Figure 4 Impedance line 404 in the middle.

[0101] The negative impedance unit 630 includes a transistor M18, a first inductor L4, and a second inductor L5. In some instances, inductors L4 and L5 function as transformers with a coupling factor K. Transistor M18 has a first terminal, a second terminal, and a control terminal. Inductor L4 has a first terminal and a second terminal. Inductor L5 has a first terminal and a second terminal. Figure 6D In this example, transistor M18 is an NPN bipolar transistor. In other examples, a MOS transistor may be used.

[0102] As shown in the figure, terminal 632 is coupled to the control terminal of transistor M18 and the first terminal of inductor L5. The first terminal of transistor M18 is coupled to the first terminal of inductor L4. The second terminals of transistor M18, inductor L4, and inductor L5 are coupled to ground or a grounding terminal.

[0103] Figure 6E The negative impedance unit 640 has a first terminal 642 and a second terminal 644, wherein a negative impedance exists at the first terminal 642. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, the first terminal 642 is coupled to an impedance line (e.g., in DRL 400). Figure 4 Impedance line 404 in the middle.

[0104] The negative impedance unit 640 includes a transistor M19 and an inductor L6. Transistor M19 has a first terminal, a second terminal, and a control terminal. Inductor L6 has a first terminal and a second terminal. Figure 6E In this example, transistor M19 is an NPN bipolar transistor. In other examples, a MOS transistor may be used.

[0105] As shown in the figure, the first terminal of inductor L6 is coupled to the second terminal 624, and the second terminal is... Figure 6E In this example, the terminals are power supply terminals. The second terminal of inductor L6 is coupled to the first terminal of transistor M19. The control terminal of transistor M19 is coupled to ground or grounding terminal. The second terminal of transistor M19 is coupled to the first terminal 642.

[0106] Figure 6F The negative impedance unit 650 has a first terminal 652A, a second terminal 652B, and a third terminal 654, wherein a negative impedance exists across the first terminal 652A and the second terminal 652B. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, the first terminal 652A and the second terminal 652B are coupled to an impedance line (e.g., Figure 4 Impedance line 404 in the middle.

[0107] The negative impedance unit 650 includes transistors M20 and M21, resistor R2, resistor R3, a first current source 656, and a second current source 660. Figure 6F In this example, transistors M20 and M21 are NPN bipolar transistors. In other examples, MOS transistors may be used.

[0108] Transistor M20 has a first terminal, a second terminal, and a control terminal. Transistor M21 has a first terminal, a second terminal, and a control terminal. Resistor R2 has a first terminal and a second terminal. Resistor R3 has a first terminal and a second terminal. First current source 656 has a first terminal 657, a second terminal 658, and a third terminal 659. Second current source 660 has a first terminal 661, a second terminal 662, and a third terminal 663.

[0109] The first terminal 652A of the negative impedance unit 650 is coupled to the second terminal of transistor M20 and the first terminal 657 of the first current source 656. The second terminal 658 of the first current source 656 is coupled to ground or a grounded terminal. The second terminal 652B of the negative impedance unit 650 is coupled to the second terminal of transistor M21 and the first terminal 661 of the second current source 660. The second terminal 662 of the second current source 660 is coupled to ground or a grounded terminal. The first terminal of transistor M20 is coupled to the control terminal of transistor M21 and the second terminal of resistor R2. The first terminal of resistor R2 is coupled to the third terminal 654, which is located at... Figure 6F In this example, the terminals are power supply terminals. The first terminal of transistor M21 is coupled to the control terminal of transistor M20 and the second terminal of resistor R3. The first terminal of resistor R3 is coupled to the third terminal 654. The third terminal 659 of the first current source 656 and the third terminal 663 of the second current source 660 receive a control signal CTL8 from a controller (not shown). The control signal CTL8 adjusts the current flow of the first current source 656 and the second current source 660 in response to the target impedance (e.g., 50Ω, 100Ω, or others) of the negative impedance unit 650.

[0110] Figure 7 This is a schematic diagram illustrating another example of a negative impedance unit 700. The negative impedance unit 700 is an active short-circuit switching circuit. The negative impedance unit 700 has a first terminal 701A and a second terminal 701B, wherein a short circuit (i.e., 0Ω) exists across the first terminal 701A and the second terminal 701B. This is for use in DRLs (e.g.,...) Figure 4 In DRL 400, the first terminal 701A and the second terminal 701B are coupled to an impedance line (e.g., in DRL 400). Figure 4 Impedance line 404 in the middle.

[0111] The negative impedance unit 700 includes transistors M22 to M25, a first current source 702, a second current source 706, a third current source 710, and a fourth current source 714. Figure 7 In this example, transistors M22 through M25 are NPN bipolar transistors. In other examples, MOS transistors may be used.

[0112] Each of transistors M22 to M25 has a corresponding first terminal, a corresponding second terminal, and a corresponding control terminal. First current source 702 has a first terminal 703, a second terminal 704, and a third terminal 705. Second current source 706 has a first terminal 707, a second terminal 708, and a third terminal 709. Third current source 710 has a first terminal 711, a second terminal 712, and a third terminal 713. Fourth current source 714 has a first terminal 715, a second terminal 716, and a third terminal 717.

[0113] The first terminal 701A of the negative impedance unit 700 is coupled to the first terminal of transistor M22 and the control terminal of transistor M23. The second terminal 701B of the negative impedance unit 700 is coupled to the first terminal of transistor M23 and the control terminal of transistor M22. The second terminal of transistor M22 is coupled to the first terminal 703 of the first current source 702. The second terminal 704 of the first current source 702 is coupled to ground or a grounded terminal. The second terminal of transistor M23 is coupled to the first terminal 707 of the second current source 706. The second terminal 708 of the second current source 706 is coupled to ground or a grounded terminal. The third terminal 705 of the first current source 702 and the third terminal 709 of the second current source 706 receive a control signal CTL9 from a controller (not shown). The control signal CTL9 adjusts the current flow of the first current source 702 and the second current source 706 in response to the target impedance (e.g., 50Ω, 100Ω, or others) of the negative impedance unit 700.

[0114] As shown in the figure, the second terminal of transistor M22 is also coupled to the first terminal of transistor M24 and the control terminal of transistor M25. The second terminal of transistor M23 is also coupled to the first terminal of transistor M25 and the control terminal of transistor M24. The second terminal of transistor M24 is coupled to the first terminal 711 of the third current source 710. The second terminal 712 of the third current source 710 is coupled to ground or a grounded terminal. The second terminal of transistor M25 is coupled to the first terminal 715 of the fourth current source 714. The second terminal 716 of the fourth current source 714 is coupled to ground or a grounded terminal. The third terminal 713 of the third current source 710 and the third terminal 717 of the fourth current source 714 receive a control signal CTL10 from a controller (not shown). The control signal CTL10 adjusts the current flow of the third current source 710 and the fourth current source 714 in response to the target impedance (e.g., 50Ω, 100Ω, or others) of the negative impedance unit 700.

[0115] Figures 8A to 8C This is a schematic diagram illustrating example transmission lines 800, 810, and 820. Transmission line 800 is a low-pass transmission line. As shown, transmission line 800 has a first terminal 802 and a second terminal 804. Transmission line 800 includes inductors L_A to L_N and capacitors C_A to C_N. Each of the inductors L_A to L_N has a corresponding first terminal and a corresponding second terminal. Each of the capacitors C_A to C_N has a corresponding first terminal and a corresponding second terminal.

[0116] exist Figure 8A In this example, inductors L_A to L_N are connected in series between the first terminal 802 and the second terminal 804. Specifically, the first terminal of inductor L_A is coupled to the first terminal 802. The second terminal of inductor L_A is coupled to the first terminal of inductor L_B, the second terminal of inductor L_B is coupled to the first terminal of inductor L_C, and so on. The first terminal of capacitor C_A is coupled to the first terminal 802 and the first terminal of inductor L_A, the first terminal of capacitor C_B is coupled to the second terminals of inductors L_A and L_B, and so on. The second terminals of capacitors C_A to C_N are coupled to ground or a ground terminal. In some examples, negative impedance units (e.g.) Figures 5A to 5E One of the negative impedance units in 6A to 6F and 7 is added in parallel with each of the corresponding capacitors in C_A to C_N to provide DRL functionality.

[0117] Figure 8BThe transmission line 810 is a bandpass transmission line. As shown, the transmission line 810 has a first terminal 812 and a second terminal 814. The transmission line 810 includes inductors L_AA to L_AN and L_BA to L_BN, and capacitors C_AA to C_AN and C_BA to C_BN. Each of the inductors L_AA to L_AN and L_BA to L_BN has a corresponding first terminal and a corresponding second terminal. Each of the capacitors C_AA to C_AN and C_BA to C_BN has a corresponding first terminal and a corresponding second terminal.

[0118] exist Figure 8B In some examples, inductors L_AA to L_AN and capacitors C_AA to C_AN are paired as series LC pairs and coupled between the first terminal 812 and the second terminal 814. Specifically, inductor L_AA and capacitor C_AA are series LC pairs, inductor L_AB and capacitor C_AB are series LC pairs, and so on. As shown, inductors L_BA to L_BN and capacitors C_BA to C_NN are paired as parallel LC pairs and coupled in parallel between series LC pairs. For example, the parallel LC pair C_BA and L_BA is coupled between the series LC pairs L_AA and C_AA and L_AB and C_AB, the parallel LC pair C_BB and L_BB is coupled between the series LC pairs L_AB and C_AB and the next series LC pair (e.g., L_AC and C_AC), and so on. In some instances, negative impedance units (e.g.) Figures 5A to 5E One of the negative impedance units in 6A to 6F and 7 is added in parallel with each corresponding LC pair to provide DRL functionality.

[0119] Figure 8C The transmission line 820 is a bandpass transmission line based on a double-tuned transformer. As shown, the transmission line 820 has a first terminal 822, a second terminal 824, a third terminal 826, and a fourth terminal 828. The transmission line 820 includes transformers C_CA to C_CN, transformers C_DA to C_DN, inductors L_CA to L_CN, and L_DA to L_DN. Each of the transformers C_CA to C_CN and C_DA to C_DN has a corresponding first terminal and a corresponding second terminal. Each of the inductors L_CA to L_CN and L_DA to L_DN has a corresponding first terminal and a corresponding second terminal.

[0120] exist Figure 8CIn the examples, transformers C_CA to C_CN, transformers C_DA to C_DN, and inductors L_CA to L_CN and L_DA to L_DN are grouped as bandpass components based on double-tuned transformers (sometimes simply referred to as "bandpass components" in this document). For example, transformer C_CA, inductor L_CA, inductor L_DA, and transformer C_DA are bandpass components based on double-tuned transformers, wherein inductors L_CA and L_DA form a transformer with a coupling factor K. Furthermore, transformer C_CB, inductor L_CB, inductor L_DB, and transformer C_DB are bandpass components based on double-tuned transformers, wherein inductors L_CB and L_DB form a transformer with a coupling factor K.

[0121] As shown in the figure, the first terminal 822 of transmission line 820 is coupled to the first terminals of transformer C_CA and inductor L_CA. The second terminal 824 of transmission line 820 is coupled to the second terminals of transformer C_CA and inductor L_CA. The first terminals of inductor L_DA, transformer C_DA, transformer C_CB, and inductor L_CB are coupled together. Furthermore, the second terminals of inductor L_DA, transformer C_DA, transformer C_CB, and inductor L_CB are coupled together, and so on.

[0122] For each bandpass component based on a dual-tuned transformer, the bandpass frequency is set by the inductor and capacitor values. Insertion loss is set by the transformer k-factor and Q-value. Furthermore, since the field is confined near each transformer, each bandpass component based on a dual-tuned transformer is anti-crosstalk. In some instances, negative impedance units (e.g.) Figures 5A to 5E One of the negative impedance units in 6A to 6F and 7 is added in parallel with each corresponding variable capacitor to provide DRL functionality.

[0123] Compared to CL-LC bandpass transmission lines, bandpass transmission lines based on dual-tuned transformers, such as Transmission Line 820, offer a variety of advantages. Examples of these advantages include: greater compactness due to the use of vertically stacked inductors for each transformer; wideband tuning behavior; no crosstalk between bandpass components based on dual-tuned transformers; improved capacitance absorption compared to low-pass transmission lines; ease of differential and single-ended implementation; operation of each transformer as a balun for differential-to-single-ended conversion; simplified biasing via a center tap on each transformer; ease of implementation at millimeter-wave frequencies; and ease of impedance transformation on both the source and load sides via transformers.

[0124] Figure 9 This is a diagram illustrating a bandpass component 900 based on a dual-tuned transformer. The bandpass component 900 based on a dual-tuned transformer is... Figure 8CThe text describes the replacement of each bandpass component based on a dual-tuned transformer (e.g., a bandpass component with a transformer C_CA, inductor L_CA, inductor L_DA, and transformer C_DA, etc.). As shown, the dual-tuned transformer-based bandpass component 900 has a first terminal 902, a second terminal 904, a third terminal 906, and a fourth terminal 908. Figure 9 In one example, the bandpass component 900 based on a dual-tuned transformer includes a first negative impedance unit 912A, a second negative impedance unit 912B, capacitors C11 to C14, transistors M26 to M29, and inductors L7 to L10. The first negative impedance unit 912A has a first terminal 914A and a second terminal 916A. The second negative impedance unit 912B has a first terminal 914B and a second terminal 916B. In some examples, the first negative impedance unit 912A is as follows: Figures 5A to 5E The active open circuits are shown in 6A to 6F. In other examples, the first negative impedance unit 912A is as follows: Figure 7 The active short circuit is shown. In some instances, the second negative impedance unit 912B is as follows: Figures 5A to 5E Active open circuits are shown as 6A to 6F. In other examples, the second negative impedance unit 912B is as follows: Figure 7 The active short circuit is shown. Although not required, the first negative impedance unit 912A and the second negative impedance unit 912B can have the same topology.

[0125] Each of capacitors C11 to C14 has a corresponding first terminal and a corresponding second terminal. Each of transistors M26 to M29 has a corresponding first terminal, a corresponding second terminal, and a corresponding control terminal. Each of inductors L7 to L10 has a first terminal and a second terminal. Inductors L7 and L9 form a first transformer. Inductors L8 and L10 form a second transformer. Figure 9 In this example, transistors M26 to M29 are NPN bipolar transistors. In other examples, MOS transistors may be used.

[0126] As shown in the figure, the first terminal 902 of the bandpass component 900 based on the dual-tuned transformer is coupled to the first terminal 914A of the first negative impedance unit 912A, the first terminal of capacitor C11, the control terminal of transistor M26, and the first terminal of inductor L7. The second terminal of capacitor C11 is coupled to the first terminal of capacitor C12. The first and second terminals of transistor M26 are coupled to each other and to the first and second terminals of transistor M27. The second terminal of inductor L7 and the first terminal of inductor L8 are coupled to the power supply (V). DDThe second terminal 916A of the first negative impedance unit 912A is coupled to the second terminal 904 of the bandpass component 900 based on the dual-tuned transformer, the second terminal of the capacitor C12, the control terminal of the transistor M27, and the second terminal of the inductor L8.

[0127] As shown in the figure, the third terminal 906 of the bandpass component 900 based on the dual-tuned transformer is coupled to the first terminal 914B of the second negative impedance unit 912B, the first terminal of capacitor C13, the control terminal of transistor M28, and the first terminal of inductor L9. The second terminal of capacitor C13 is coupled to the first terminal of capacitor C14. The first and second terminals of transistor M28 are coupled to each other and to the first and second terminals of transistor M29. The second terminal of inductor L9 and the first terminal of inductor L10 are coupled to the power supply (V). DD The second terminal 916B of the second negative impedance unit 912B is coupled to the fourth terminal 908 of the bandpass component 900 based on the dual-tuned transformer, the second terminal of the capacitor C14, the control terminal of the transistor M29, and the second terminal of the inductor L8.

[0128] exist Figure 9 In this example, the capacitance between the first terminal 902 and the second terminal 904 depends on capacitors C11 and C12 and transistors M26 and M27. To adjust the effective capacitance between the first terminal 902 and the second terminal 904 (e.g., to implement...), Figure 8C (As shown in the variable capacitor), control signal CTL11 is applied to the first and second terminals of transistors M26 and M27. Similarly, the capacitance between the third terminal 906 and the fourth terminal 908 depends on capacitors C13 and C14 and transistors M28 and M29. To adjust the effective capacitance between the third terminal 906 and the fourth terminal 908 (e.g., to implement...), Figure 8C The variable capacitor shown applies the control signal CTL11 to the first and second terminals of transistors M28 and M29.

[0129] For the bandpass component 900 based on a dual-tuned transformer, the bandpass frequency is set by the inductor and capacitor values. Insertion loss is set by the transformer k-factor and Q-value. Using transistors M26 to M29 and CTL11, a tunable parallel resistor can flatten Q, improving the consistency of different dual-tuned transformer-based components in the transmission line, DRL, or associated phase shifter. Furthermore, the dual-tuned transformer-based bandpass component 900 is anti-crosstalk because the field is confined near each transformer. In some instances, transistors M6 to M29 are high-voltage devices (e.g., above 5V) to meet voltage limits. The first negative impedance unit 912A and the second negative impedance unit 912B reduce the insertion loss of the dual-tuned transformer-based bandpass component 900. In some instances, the first negative impedance unit 912A and the second negative impedance unit 912B are degraded (i.e., using negative feedback) to improve linearity.

[0130] Figure 10 This is graph 1000 showing the S-parameters of the phase shifter as a function of frequency under different control settings. Figure 10 In the example, different values ​​of CTL11 represent the S21 waveform, including: CTL11 = 0V; CTL11 = 0.5V; CTL11 = 1.0V; CTL11 = 1.5V; CTL11 = 2.0V; and CTL11 = 2.5V. Adjusting CTL11 adjusts the effective frequency range of the phase shifter.

[0131] Figure 11 and 12 This is a diagram showing example phase shifters 1100 and 1200. Figure 11 The phase shifter 1100 is a single-ended RTPS and includes an I / Q generator 1102, a first balanced-unbalanced (balun) circuit 1120, a second balun circuit 1140, a first transmission line 1131, a second transmission line 1151, an AC source 1112, resistors R4 to R7, a first voltage source 1128, and a second voltage source 1148.

[0132] The I / Q generator 1102 has a first terminal 1104, a second terminal 1106, a third terminal 1108, and a fourth terminal 1110. Figure 11 In this example, the first terminal 1104 is the source terminal, and the fourth terminal 1110 is the load terminal. The second terminal 1106 and the third terminal 1108 are reflective load terminals. To support bidirectional operation, the source terminal and the load terminal can be switched as needed. Furthermore, the second terminal 1106 and the third terminal 1108 can be considered as internal terminals of the phase shifter, while the first terminal 1104 and the fourth terminal 1110 are external terminals.

[0133] The first balun circuit 1120 has a first terminal 1122, a second terminal 1124, a third terminal 1126, and a fourth terminal 1127. The second balun circuit 1140 has a first terminal 1142, a second terminal 1144, a third terminal 1146, and a fourth terminal 1147. The first transmission line 1131 includes a first impedance line 1132, a second impedance line 1134, and negative impedance units 1136A to 1136N. Figure 11 In this example, the first impedance line 1132 has an impedance of 50Ω, the second impedance line 1134 has an impedance of 50Ω, and the transmission line 1131 is matched with resistor R6, which may be 100Ω. The second transmission line 1151 includes the first impedance line 1152, the second impedance line 1154, and negative impedance units 1156A to 1156N coupled between the first impedance line 1152 and the second impedance line 1154. Figure 11 In this example, the first impedance line 1152 has an impedance of 50Ω, the second impedance line 1154 has an impedance of 50Ω, and the transmission line 1151 is matched with resistor R7, which may be 100Ω. The AC source 1112 has a first terminal and a second terminal. Each of resistors R4 to R7 has a corresponding first terminal and a corresponding second terminal. The first voltage source 1128 has a first terminal 1129 and a second terminal 1130. The second voltage source 1148 has a first terminal 1149 and a second terminal 1150.

[0134] exist Figure 11 In this example, the first terminal 1114 of AC source 1112 is coupled to the first terminal of resistor R4. The second terminal 1116 of AC source 1112 is coupled to ground or a grounded terminal. The second terminal of resistor R4 is coupled to the first terminal 1104 of I / Q generator 1102. The second terminal 1106 of I / Q generator 1102 is coupled to the first terminal 1122 of first balun circuit 1120. The second terminal 1124 of first balun circuit 1120 is coupled to the first impedance line 1132 of first transmission line 1131. The third terminal 1126 of first balun circuit 1120 is coupled to the second impedance line 1134 of first transmission line 1131. The fourth terminal 1127 of first balun circuit 1120 is coupled to the first terminal 1129 of first voltage source 1128. The second terminal 1130 of first voltage source 1128 is coupled to ground or a grounded terminal. The first terminal of resistor R6 is coupled to the first impedance line 1132 of first transmission line 1131. The second terminal of resistor R6 is coupled to the second impedance line 1134 of the first transmission line 1131. Negative impedance elements 1136A to 1136B of the first transmission line 1131 are distributed and coupled between the first impedance line 1132 and the second impedance line 1134. In different embodiments, the first transmission line 1131 may be a low-pass transmission line, a band-pass transmission line, or a band-pass transmission line based on a dual-tuned transformer.

[0135] The fourth terminal 1110 of I / Q generator 1102 is coupled to the first terminal of resistor R5. The second terminal of resistor R5 is coupled to ground or a grounding terminal. The third terminal 1108 of I / Q generator 1102 is coupled to the first terminal 1142 of the second balun circuit 1140. The second terminal 1144 of the second balun circuit 1140 is coupled to the first impedance line 1152 of the second transmission line 1151. The third terminal 1146 of the second balun circuit 1140 is coupled to the second impedance line 1154 of the second transmission line 1151. The fourth terminal 1127 of the second balun circuit 1140 is coupled to the first terminal 1149 of the second voltage source 1148. The second terminal 1150 of the second voltage source 1148 is coupled to ground or a grounding terminal. The first terminal of resistor R7 is coupled to the first impedance line 1152 of the second transmission line 1151. The second terminal of resistor R7 is coupled to the second impedance line 1154 of the second transmission line 1151. The negative impedance elements 1156A to 1156B of the second transmission line 1151 are distributed and coupled between the first impedance line 1152 and the second impedance line 1154. In different instances, the second transmission line 1151 may be a low-pass transmission line, a band-pass transmission line, or a band-pass transmission line based on a dual-tuned transformer.

[0136] exist Figure 11 In this example, phase shifter 1100 is used to: receive input voltage (V in Using I / Q generator 1102, first balun circuit 1120, second balun circuit 1140, first transmission line 1131 and second transmission line 1151 to V in Perform a phase shift operation; and respond to V in And phase shift operation to provide output voltage (V) OUT In some instances, the first voltage (V1+) at the first terminal 1104 of the I / Q generator 1102 is given as: V1+ = V in ∠Φ, where Φ is V in The phase. In some instances, the second voltage (V2+ or V2-) at the second terminal 1106 of the I / Q generator 1102 is given as: V2- = 0.5 * V in ∠(Φ+90) and V2+=0.5*Γ L V in ∠(Φ+90+θ), where θ is the phase shift caused by the first transmission line 1131 and the second transmission line 1151. In some instances, the third voltage (V3+ or V3-) at the third terminal 1108 of the I / Q generator 1102 is given as: V3-=0.5*V in ∠(Φ+180) and V3+=0.5*Γ L V in∠(Φ+180+θ). In some instances, V at the fourth terminal 1110 of the I / Q generator 1102. OUT Given as: V OUT =V² + ∠180 + V³ + ∠90 = V in *Γ L ∠(Φ+θ+270). In some instances, the bias voltages of the negative impedance units 1136A to 1136N are provided by a first voltage source 1128. Furthermore, the bias voltages of the negative impedance units 1156A to 1156N are provided by a second voltage source 1148. The cutoff capacitances (capacitors in the off state) of the negative impedance units 1136A to 1136N are absorbed into the first transmission line 1131, and the cutoff capacitances of the negative impedance units 1156A to 1156N are absorbed into the second transmission line 1151.

[0137] Compared to other phase shifters, phase shifter 1100 offers advantages including: bidirectional operation; real time delay; low insertion loss; low amplitude and phase changes; overcoming switching limitations using bipolar complementary metal-oxide-semiconductor (BiCMOS); and simple calibration. In some instances, calibration involves using a reference value, comparing the reference value with the impedance of the negative impedance cell, adjusting the control signal of the negative impedance cell (e.g., for a current source or other control circuitry) to match the impedance of the negative impedance cell to the reference value, and extending the control signal adjustment to other negative impedance cells.

[0138] Figure 12 Phase shifter 1200 contains the same components as phase shifter 1100, except that AC source 1112 is omitted and transformers T1 and T2 are added. Using transformers T1 and T2, phase shifter 1200 is a differential RTPS with differential input and differential output.

[0139] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0140] Furthermore, in this specification, the term "based on" means "at least partially based on". Therefore, if X is based on Y, then X can vary with Y and any number of other factors.

[0141] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0142] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components and / or conductors.

[0143] The circuits or devices described herein as containing certain components may be practically adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0144] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuit system. For example, field-effect transistors (“FETs”) (e.g., NFETs or PFETs), bipolar junction transistors (BJTs, such as NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0145] Reference may be made to the control terminal of the transistor, as well as its first and second terminals, in the claims. In the context of a FET, the control terminal is the gate, and the first and second terminals are the drain and source, respectively. In the context of a BJT, the control terminal is the base, and the first and second terminals are the collector and emitter, respectively.

[0146] In this article, the term "FET on" refers to the presence of a conduction channel in the FET and the flow of drain current through it. The term "FET off" refers to the absence of a conduction channel, therefore no drain current flows through the FET. However, a "off" FET may still have current flowing through the body diode of the transistor.

[0147] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0148] While some elements in the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as external to the integrated circuit may be contained within the integrated circuit, and / or some features shown as internal to the integrated circuit may be external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0149] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "generally" preceding a parameter means within + / - 10% of said parameter, or, if the parameter is zero, within a reasonable range of values ​​near zero.

[0150] Modifications to the described examples are possible within the scope of the claims, and other examples are also possible.

Claims

1. An integrated circuit, comprising: A transmission line comprising bandpass components, each bandpass component comprising: A first inductor having a first terminal and a second terminal; A second inductor has a first terminal and a second terminal, and the first inductor and the second inductor form a transformer; A first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the first terminal of the first inductor, and the second terminal of the first capacitor being coupled to the second terminal of the first inductor. as well as A second capacitor has a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the first terminal of the second inductor, and the second terminal of the second capacitor being coupled to the second terminal of the second inductor.

2. The integrated circuit of claim 1, wherein the transmission line is a first transmission line, and the integrated circuit further comprises: A second transmission line includes bandpass components, each bandpass component of the second transmission line comprising: A first inductor having a first terminal and a second terminal; A second inductor has a first terminal and a second terminal, and the first inductor and the second inductor form a transformer; A first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the first terminal of the first inductor, and the second terminal of the first capacitor being coupled to the second terminal of the first inductor. as well as A second capacitor has a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the first terminal of the second inductor, and the second terminal of the second capacitor being coupled to the second terminal of the second inductor.

3. The integrated circuit of claim 2, further comprising an I / Q generator having a first terminal, a second terminal, a third terminal and a fourth terminal, the second terminal of the I / Q generator being coupled to the first transmission line, and the third terminal of the I / Q generator being coupled to the second transmission line.

4. The integrated circuit according to claim 3, further comprising: A first transformer, which is coupled to the first terminal of the I / Q generator; as well as A second transformer is coupled to the second terminal of the I / Q generator.

5. The integrated circuit of claim 1, further comprising a bidirectional phase shifter circuit system, the transmission line coupled to the phase shifter circuit system, the transmission line comprising a negative impedance element.

6. The integrated circuit of claim 5, wherein the negative impedance unit comprises an active open-circuit switch circuit.

7. The integrated circuit of claim 5, wherein the negative impedance unit comprises an active short-circuit switch circuit.

8. A phase shifter comprising: A reflective phase shifter circuit system includes: The first distributed reflective load includes a first negative impedance unit; The second distributed reflective load includes a second negative impedance unit; as well as An I / Q generator having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the second terminal of the I / Q generator is coupled to the first distributed reflective load, and the third terminal of the I / Q generator is coupled to the second distributed reflective load.

9. The phase shifter of claim 8, wherein each of the first negative impedance unit and the second negative impedance unit comprises an active open-circuit switch circuit, each active open-circuit switch circuit comprising: A first transistor having a first terminal, a second terminal, and a control terminal; and The second transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the control terminal of the second transistor, and the first terminal of the second transistor is coupled to the control terminal of the first transistor.

10. The phase shifter of claim 9, wherein each active open-circuit switch circuit includes a current source having a first terminal and a second terminal, the first terminal of the current source being coupled to the second terminal of the first transistor and the second transistor.

11. The phase shifter of claim 9, wherein each active open-circuit switch circuit comprises: A first current source having a first terminal and a second terminal, wherein the first terminal of the first current source is coupled to the second terminal of the first transistor; A second current source having a first terminal and a second terminal, wherein the first terminal of the second current source is coupled to the second terminal of the second transistor; as well as A capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the first terminal of a first current source, and the second terminal of the capacitor being coupled to the first terminal of a second current source.

12. The phase shifter of claim 11, wherein each active open-circuit switch circuit includes a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first terminal of the first current source, and the second terminal of the resistor being coupled to the first terminal of the second current source.

13. The phase shifter of claim 11, wherein each active open-circuit switch circuit comprises: The third transistor has a first terminal, a second terminal, and a control terminal; A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the fourth transistor, and the first terminal of the fourth transistor is coupled to the control terminal of the third transistor; A third current source having a first terminal and a second terminal, wherein the first terminal of the third current source is coupled to the second terminal of the third transistor; as well as A fourth current source having a first terminal and a second terminal, wherein the first terminal of the fourth current source is coupled to the second terminal of the fourth transistor.

14. The phase shifter of claim 8, wherein each of the first negative impedance unit and the second negative impedance unit comprises an active short-circuit switch circuit, the active short-circuit switch circuit comprising: The first transistor has a first terminal, a second terminal, and a control terminal; The second transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the control terminal of the second transistor, and the first terminal of the second transistor is coupled to the control terminal of the first transistor. The third transistor has a first terminal, a second terminal, and a control terminal; A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the first transistor and the control terminal of the fourth transistor, and the first terminal of the fourth transistor is coupled to the second terminal of the second transistor and the control terminal of the third transistor; A first current source having a first terminal and a second terminal, wherein the first terminal of the first current source is coupled to the second terminal of the first transistor; A second current source having a first terminal and a second terminal, wherein the first terminal of the second current source is coupled to the second terminal of the second transistor; A third current source having a first terminal and a second terminal, wherein the first terminal of the third current source is coupled to the second terminal of the third transistor; as well as A fourth current source having a first terminal and a second terminal, wherein the first terminal of the fourth current source is coupled to the second terminal of the fourth transistor.

15. The phase shifter of claim 8, wherein each of the first negative impedance unit and the second negative impedance unit comprises an active open-circuit switch circuit, each active open-circuit switch circuit comprising: A transistor having a first terminal, a second terminal, and a control terminal; and A passive component coupled to either the first or second terminal of the transistor.

16. The phase shifter of claim 8, wherein the first distributed reflective load comprises a first bandpass transmission line based on a dual-tuned transformer, and the second distributed reflective load comprises a second bandpass transmission line based on a dual-tuned transformer, wherein the first bandpass transmission line based on a dual-tuned transformer and the second bandpass transmission line based on a dual-tuned transformer comprise bandpass components, each bandpass component comprising: A first inductor having a first terminal and a second terminal; A second inductor has a first terminal and a second terminal, and the first inductor and the second inductor form a transformer; A first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the first terminal of the first inductor, and the second terminal of the first capacitor being coupled to the second terminal of the first inductor. as well as A second capacitor has a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the first terminal of the second inductor, and the second terminal of the second capacitor being coupled to the second terminal of the second inductor.

17. An apparatus comprising: processor; A transceiver circuit system coupled to the processor; as well as An antenna array terminal, coupled to the transceiver circuitry, the transceiver circuitry comprising: A bidirectional phase shifter circuit system, the bidirectional phase shifter circuit system comprising: The first distributed reflective load includes a first negative impedance unit; The second distributed reflective load includes a second negative impedance unit; as well as An I / Q generator having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the second terminal of the I / Q generator is coupled to the first distributed reflective load, and the third terminal of the I / Q generator is coupled to the second distributed reflective load.

18. The device of claim 17, wherein each of the first negative impedance unit and the second negative impedance unit comprises an active open-circuit switch circuit, and each active open-circuit switch circuit comprises: A first transistor having a first terminal, a second terminal, and a control terminal; and The second transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the control terminal of the second transistor, and the first terminal of the second transistor is coupled to the control terminal of the first transistor.

19. The device of claim 17, wherein each of the first negative impedance unit and the second negative impedance unit comprises an active open-circuit switch circuit, and each active open-circuit switch circuit comprises: A transistor having a first terminal, a second terminal, and a control terminal; and A passive component coupled to either the first or second terminal of the transistor.

20. The device of claim 19, wherein each of the first negative impedance unit and the second negative impedance unit comprises an active short-circuit switch circuit, the active short-circuit switch circuit comprising: The first transistor has a first terminal, a second terminal, and a control terminal; The second transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the control terminal of the second transistor, and the first terminal of the second transistor is coupled to the control terminal of the first transistor. The third transistor has a first terminal, a second terminal, and a control terminal; A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the first transistor and the control terminal of the fourth transistor, and the first terminal of the fourth transistor is coupled to the second terminal of the second transistor and the control terminal of the third transistor; A first current source having a first terminal and a second terminal, wherein the first terminal of the first current source is coupled to the second terminal of the first transistor; A second current source having a first terminal and a second terminal, wherein the first terminal of the second current source is coupled to the second terminal of the second transistor; A third current source having a first terminal and a second terminal, wherein the first terminal of the third current source is coupled to the second terminal of the third transistor; as well as A fourth current source having a first terminal and a second terminal, wherein the first terminal of the fourth current source is coupled to the second terminal of the fourth transistor.

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