Decryption method, variable storage method and related device, equipment, medium and product

Abstract

Embodiments of the present disclosure provide a decryption method, a variable storage method, and related devices, equipment, media and products. The decryption method monitors the current signal of the chip through the current probe, monitors the electromagnetic signal of the SRAM through the electromagnetic probe, determines the key bit value corresponding to the coordinate value stored in the SRAM based on the signal change mode of the current signal and the electromagnetic signal, and then obtains the decryption result. Through the current-electromagnetic dual-channel acquisition and analysis scheme, the ability to obtain effective information in the decryption process is improved, the redundant information processing process is reduced, and the password cracking efficiency is improved. The variable storage method stores the coordinate values of at least two coordinate dimensions of at least one password intermediate variable in at least two SRAMs, or stores the coordinate values of at least one coordinate dimension of at least two password intermediate variables in the same SRAM, which can avoid local electromagnetic radiation analysis and the storage process does not affect the execution efficiency of the encryption algorithm.

Description

Technical Field

[0001] This disclosure belongs to the field of chip security technology, and in particular relates to a decryption method, a variable storage method, and related devices, equipment, media, and products. Background Technology

[0002] Taking elliptic curve cryptography (ECC) as an example, existing security chips randomly store intermediate variables during the ECC implementation process in SRAM memory cells to save cost and area. Specifically, random numbers are first generated, and then these random numbers are used to permutate the positions of intermediate variables in the ECC algorithm. After the permutation is complete, the ECC operation is performed.

[0003] However, the physical characteristics of SRAM make it vulnerable to attacks using localized electromagnetic radiation analysis (LEA). LEA is a type of side-channel analysis technique that utilizes the locality of electromagnetic radiation. During chip operation, a high-resolution electromagnetic probe is used to detect the chip's surface. By analyzing the intensity of the electromagnetic radiation signal at specific locations and times, sensitive information within the chip, such as the keys being processed, can be obtained, thereby cracking cryptographic algorithms. Furthermore, in the aforementioned defense scheme using randomized intermediate variable storage, position replacement requires a significant amount of time, increasing clock cycles and power consumption, making it unsuitable for low-power IoT edge scenarios. Summary of the Invention

[0004] This disclosure provides a decryption method, a variable storage method, and related devices, equipment, media, and products. The decryption method, devices, media, and products can solve the technical problem of low decryption efficiency, while the variable storage method, devices, media, and products can solve the problems of large computational load and low security in the encryption algorithm storage process.

[0005] In a first aspect, embodiments of this disclosure provide a decryption method, including:

[0006] The scalar multiplication process of the elliptic curve cryptography algorithm is performed on the target chip, and the current signal of the target chip is monitored by a current probe, and the electromagnetic signal of the SRAM on the target chip is monitored by an electromagnetic probe. The SRAM is used to store the coordinate values ​​of the cryptographic intermediate variables.

[0007] Based on the signal change patterns of current and electromagnetic signals, the key bit values ​​corresponding to the coordinate values ​​stored in SRAM are determined.

[0008] The corresponding private key is determined based on each key bit value;

[0009] The decryption result is determined based on the output of the private key and the scalar multiplication process.

[0010] In one feasible implementation, a current probe is connected to the target chip to monitor the overall current signal of the target chip; multiple electromagnetic probes are correspondingly positioned at each monitoring location of the SRAM of the target chip to monitor the electromagnetic signal of the corresponding SRAM; the method further includes:

[0011] The monitoring signals of the electromagnetic probe and the current probe are triggered by the same trigger signal, so that the time steps of the electromagnetic signal and the current signal are aligned.

[0012] In one feasible implementation, based on the signal change patterns of current and electromagnetic signals, the key bit values ​​corresponding to the coordinate values ​​stored in each SRAM are determined, including:

[0013] Analyze the intensity changes of the current signal to identify the point-addition operation stage and the point-doubling operation stage;

[0014] Analyze the intensity changes of electromagnetic signals and use the SRAM corresponding to electromagnetic signals with abrupt waveform changes as the target SRAM;

[0015] Based on the point-addition operation stage and the point-doubling operation stage, analyze the electromagnetic signals corresponding to at least one target SRAM to obtain the read-write operation sequence in at least one target SRAM.

[0016] The conditional operations of the cryptographic intermediate variables during the scalar multiplication process are restored from the read and write operation sequence, and the key bit values ​​corresponding to the coordinate values ​​stored in at least one target SRAM are determined based on the restoration result.

[0017] In one feasible implementation, the conditional operations of the cryptographic intermediate variables during the scalar multiplication process are restored from the read-write operation sequence, and the key bit values ​​corresponding to the coordinate values ​​stored in at least one target SRAM are determined based on the restoration result, including:

[0018] Identify the recurring read / write operation segments in the read / write operation sequence and match them with the conditional branches of the conditional operation;

[0019] After a successful match, the key bit value corresponding to the read / write operation segment is recorded as 1, and the remaining key bit value is recorded as 0.

[0020] In one feasible implementation, the scalar multiplication process includes:

[0021] Input the base point coordinates and the key value;

[0022] Initialize the coordinate values ​​of the intermediate password variables;

[0023] Update the coordinates of the intermediate cryptographic variables bit by bit according to the key bit value of the key value;

[0024] Output the scalar multiplication result of the base point coordinates and the key value.

[0025] In one feasible implementation, the coordinate system in which the intermediate cryptographic variables reside includes at least one of the Jacobian coordinate system, the standard coordinate system, and the affine coordinate system.

[0026] In addition, the SRAM storage method for cryptographic algorithm variables provided in this disclosure includes:

[0027] Obtain the coordinates of at least two dimensions of at least one cryptographic intermediate variable used in the scalar multiplication process of an elliptic curve cryptography algorithm;

[0028] The coordinate values ​​of at least two coordinate dimensions of at least one cryptographic intermediate variable are distributed and stored in at least two SRAMs; or, the coordinate values ​​of at least one coordinate dimension of at least two cryptographic intermediate variables are jointly stored in the same SRAM.

[0029] In one feasible implementation, the method further includes: when at least one cryptographic intermediate variable includes three coordinate dimensions that require simultaneous cryptographic computation, distributing and storing the coordinate values ​​of at least two coordinate dimensions of the at least one cryptographic intermediate variable in at least two SRAMs, including:

[0030] The coordinate values ​​of two coordinate dimensions of at least one cryptographic intermediate variable are stored in the same SRAM, and the coordinate values ​​of the other coordinate dimension of at least one cryptographic intermediate variable are stored in another SRAM.

[0031] Secondly, corresponding to the aforementioned decryption method, this disclosure provides a decryption apparatus, the apparatus comprising:

[0032] The signal acquisition module is used to perform the scalar multiplication process of the elliptic curve cryptography algorithm on the target chip, and to monitor the current signal of the target chip through a current probe, and to monitor the electromagnetic signal of the SRAM on the target chip through an electromagnetic probe. The SRAM is used to store the coordinate values ​​of the cryptographic intermediate variables.

[0033] The signal analysis module is used to determine the key bit values ​​corresponding to the coordinate values ​​stored in the SRAM based on the signal change patterns of current and electromagnetic signals.

[0034] The private key acquisition module is used to determine the corresponding private key based on each key bit value;

[0035] The decryption result output module is used to determine the decryption result based on the private key and the output of the scalar multiplication process.

[0036] Corresponding to the aforementioned SRAM storage method for cryptographic algorithm variables, this disclosure provides an SRAM storage device for cryptographic algorithm variables, the device comprising:

[0037] The coordinate value acquisition module is used to obtain the coordinate values ​​of at least two coordinate dimensions of at least one cryptographic intermediate variable used in the scalar multiplication process of the elliptic curve cryptography algorithm.

[0038] A coordinate value storage module is used to disperse and store the coordinate values ​​of at least two coordinate dimensions of at least one cryptographic intermediate variable in at least two SRAMs; or, to store the coordinate values ​​of at least one coordinate dimension of at least two cryptographic intermediate variables together in the same SRAM.

[0039] Thirdly, embodiments of this disclosure provide an apparatus comprising: a processor and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the aforementioned decryption method or the aforementioned SRAM storage method.

[0040] Fourthly, embodiments of this disclosure provide a computer storage medium storing computer program instructions, which, when executed by a processor, implement the aforementioned decryption method or the aforementioned SRAM storage method.

[0041] Fifthly, embodiments of this disclosure provide a computer program product, including a computer program that, when executed by a processor, implements the aforementioned decryption method or the aforementioned SRAM storage method.

[0042] The decryption method, apparatus, device, computer storage medium, and computer program product of this disclosure comprehensively analyze the changing patterns of the chip's current signal and the electromagnetic signal of the SRAM, obtain the key bit value stored in the SRAM during the scalar multiplication process, and thus obtain the decryption result. Compared to simply analyzing electromagnetic signals and determining the SRAM based on complex calculations, the local electromagnetic radiation method of this disclosure can efficiently extract effective information, complete decryption with fewer calculation steps and less computation time, and achieve higher decryption efficiency.

[0043] The SRAM storage method, apparatus, device, computer storage medium, and computer program product for cryptographic algorithm variables disclosed herein ensure that the storage location of the cryptographic intermediate variable for operations related to the key value cannot be distinguished by electromagnetic detection by setting the storage location of the cryptographic intermediate variable only by setting the coordinate dimension of the coordinate value during the entire encryption process. This avoids the situation where the analysis results of local electromagnetic radiation at a SRAM leakage point cannot obtain the coordinate value of the cryptographic intermediate variable, effectively defending against attacks. In addition, encryption is achieved without updating the storage location of the cryptographic intermediate variable, reducing a large amount of computation, saving computation time and power consumption, and making it more suitable for low-power scenarios of IoT edge chips. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments of this disclosure will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a flowchart illustrating a decryption method provided in an embodiment of this disclosure;

[0046] Figure 2 This is a schematic diagram illustrating a vulnerable method for storing intermediate cryptographic variables, as provided in an embodiment of this disclosure.

[0047] Figure 3 This is a schematic diagram of an electromagnetic signal curve and a current signal curve provided in an embodiment of this disclosure;

[0048] Figure 4 This is a schematic diagram of another vulnerable method for storing cryptographic intermediate variables provided in an embodiment of this disclosure;

[0049] Figure 5 This is a flowchart illustrating an SRAM storage method for cryptographic algorithm variables provided in an embodiment of this disclosure;

[0050] Figure 6 This is a schematic diagram illustrating a method for storing intermediate cryptographic variables according to an embodiment of this disclosure;

[0051] Figure 7 This is a schematic diagram illustrating another method for storing intermediate cryptographic variables provided in an embodiment of this disclosure;

[0052] Figure 8 This is a schematic diagram of the structure of a decryption device provided in an embodiment of this disclosure;

[0053] Figure 9 This is a schematic diagram of the structure of an SRAM storage device for cryptographic algorithm variables provided in an embodiment of this disclosure;

[0054] Figure 10 This is a schematic diagram of the structure of a device provided in an embodiment of this disclosure. Detailed Implementation

[0055] The features and exemplary embodiments of various aspects of this disclosure will now be described in detail. To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, will provide a further detailed description. It should be understood that the specific embodiments described herein are intended only to explain this disclosure and not to limit it. For those skilled in the art, this disclosure can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this disclosure by illustrating examples.

[0056] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0057] To better understand and explain the solutions provided in the embodiments of this application, some technical terms involved in the embodiments of this application will be briefly introduced below.

[0058] An elliptic curve is a mathematical object, a set of all points that satisfy a specific equation (such as y²=x³+ax+b). In cryptography, it serves as the mathematical foundation and framework for the entire cryptographic system, providing possibilities for cryptography by defining operational rules on it through cryptographic algorithms.

[0059] Elliptic Curve Cryptography (ECC) is a public-key cryptography algorithm based on the elliptic curve mathematical problem. It leverages the one-way nature of scalar multiplication in the Elliptic Curve Discrete Logarithm Problem (ECDLP) and employs point addition and doubling operations to implement the scalar multiplication process and achieve various security functions. Compared to traditional algorithms such as Simple Power Analysis (RSA), ECC achieves equal or even higher security strength due to its faster computation speed and smaller key and signature lengths, making it widely used in security chips. It is particularly useful for chips used in IoT edge applications, enabling optimal performance with limited hardware resources. The ECC algorithm defines fields including prime fields and binary extended fields; currently, most elliptic curve parameters are based on curves in the prime field. Elliptic curves of prime fields generally include Weierstrass curves, Montgomery curves, and Twisted Edwards curves. There is a one-to-one mapping between Montgomery and Twisted Edwards curves, and the mapping equation between point coordinates is easily expressed. The Commercial Elliptic Curve Public-Key Cryptography (SM2) algorithm is a type of ECC algorithm, and the scheme designed in this disclosure is also effective for the SM2 algorithm.

[0060] Localized electromagnetic radiation analysis is a type of side-channel analysis technique. This technique mainly utilizes the principle of locality of electromagnetic radiation. When the chip is working, a high-resolution electromagnetic probe (generally with a diameter of less than 100µm and a spatial resolution within 100µm) is used to probe the surface of the chip. By analyzing the intensity of the electromagnetic radiation signal at a specific location and time, sensitive information inside the chip, such as the key being processed on the chip, can be obtained, thereby cracking the cryptographic algorithm.

[0061] Static Random-Access Memory (SRAM) is an extremely fast type of memory. In public-key cryptography, SRAM is generally used as the storage unit in conjunction with logic circuits to implement cryptographic algorithms. Elliptic curve cryptography processes very large amounts of intermediate data, and storing this information in registers would increase the cost of the chip. Therefore, SRAM is often used, and multiple SRAM cells are arranged in the backend for better flexibility. Compared to registers, SRAM has a higher storage density and requires much less storage space under the same manufacturing process. However, SRAM cells should not be infinitely small. Each SRAM cell requires independent control logic. If SRAM is divided into smaller cells, the area per unit storage increases, leading to an increase in the overall cost of the chip. Therefore, the common SRAM cell size used in elliptic curve cryptography is 1KB, and approximately five SRAM cells are typically used. The size of the SRAM storage cell array varies depending on the manufacturing process. For example, in a security chip using a 40nm process, the array size of a 1KB SRAM is typically approximately 100um × 200um.

[0062] Current encryption methods, to defend against localized electromagnetic radiation analysis, randomize the intermediate cryptographic variables used in the elliptic curve cryptography (ECC) process. During randomization, random numbers are first generated, then used to permutate the positions of the intermediate cryptographic variables. After the permutation, the elliptic curve calculations are performed. Based on this randomness, when storing intermediate cryptographic variables in an ECC-based encryption process, a single SRAM may only store the coordinates of all dimensions of one intermediate variable. Reverse engineering this SRAM allows for rapid extraction of the key value. Furthermore, existing decryption methods generally rely solely on electromagnetic signal analysis. This process requires processing the electromagnetic signals into an easily analyzable form, which is highly complex and leads to low decryption efficiency.

[0063] To address the problems of existing technologies, embodiments of this disclosure provide a decryption method, apparatus, device, computer storage medium, and computer program product. The decryption method of this disclosure locates the target SRAM during reverse analysis. The target SRAM is at least one SRAM used by the encryptor to store the coordinate values ​​of intermediate cryptographic variables closely related to the key value, thus avoiding analysis and computation on non-target SRAMs and improving computational speed. Furthermore, the decryption method proposed in this disclosure introduces current signal analysis to perform reverse analysis of the chip based on electromagnetic signal analysis. This facilitates the differentiation of electromagnetic signal characteristics based on current signal features, thereby quickly identifying the SRAM related to key operations and improving the efficiency of key acquisition.

[0064] The embodiments disclosed herein can be applied to scenarios where keys stored in a physical carrier are obtained, and the physical carrier can be a chip.

[0065] The decryption method provided in the embodiments of this disclosure is described below.

[0066] Figure 1 A flowchart illustrating a decryption method provided in one embodiment of this disclosure is shown. Figure 1 As shown, the method may include steps S10, S20, S30, and S40. Specifically, it includes the following:

[0067] Step S10: Perform the scalar multiplication process of the elliptic curve cryptography algorithm on the target chip, and monitor the current signal of the target chip through a current probe and the electromagnetic signal of the SRAM on the target chip through an electromagnetic probe. The SRAM is used to store the coordinate values ​​of the intermediate cryptographic variables.

[0068] In the decryption method provided in this embodiment, to obtain the key value information, it is necessary to collect the signal fed back by the target chip when the encryption algorithm is executed to reconstruct the key storage process of the target chip. This facilitates subsequent analysis and processing of the signal to obtain the key value information. The target chip is designed by the encryptor and stores the key by executing the scalar multiplication process of the Elliptic Curve Cryptography (ECC) algorithm. The scalar multiplication process involves setting a cryptographic intermediate variable on the elliptic curve and combining point addition and doubling operations on this intermediate variable to store the key bit value in the target chip in an encrypted manner. Furthermore, since the coordinate system of the elliptic curve is different, the coordinate dimensions of the cryptographic intermediate variable also differ. In this embodiment, the coordinate system of the cryptographic intermediate variable includes at least one of the Jacobian coordinate system, the standard coordinate system, and the affine coordinate system. For example, when using the Jacobian coordinate system, the coordinates of the cryptographic intermediate variable on the elliptic curve are represented by (X, Y, Z). Taking a 256-bit elliptic curve as an example, the X, Y, and Z coordinate values ​​are all elements in the 256-bit Fp field (prime field). When using the standard coordinate system, the coordinates of the cryptographic intermediate variables on the elliptic curve are represented by (U,V), and each coordinate point is an element in the 256-bit Fp field.

[0069] To facilitate understanding of the subsequent steps, the scalar multiplication process is introduced first. In step S10, the scalar multiplication process is implemented based on an elliptic curve cryptography algorithm, which and the scalar multiplication process are known. The most important operation using elliptic curves in elliptic curve cryptography protocols is the calculation of the scalar multiplication [k] × G, where the key value k belongs to [0, n-1], and G is a point on the elliptic curve, which may be a base point or a random point. The scalar multiplication process may vary slightly for each encryption step, but it generally involves the following basic steps:

[0070] First, input the coordinates of the base point and the key value. This step is the starting point of the entire scalar multiplication calculation, defining the object and scale of the operation. Elliptic curves typically define a base point G, which is a public, standard parameter. Each elliptic curve has a recognized base point G. This base point has two coordinates, x and y, which are public values, elements in the prime field, and satisfy the elliptic curve equation. All users' public keys are obtained by performing a scalar multiplication of their respective private keys with the base point G. The key value k is a secret, randomly generated sequence of integers. The value of k ranges from 1 to n-1, where n is the order of the base point G. The key, or the encrypted version of the key, is the user's private key. The goal of the scalar multiplication calculation is to calculate k × G; the output is the user's public key, which is public.

[0071] Next, initialize the coordinate values ​​of the intermediate cryptographic variables. These intermediate variables store intermediate results during the scalar multiplication calculation. This step sets up an accumulator for subsequent iterative calculations. Ultimately, this variable will hold the final output result k×G.

[0072] Then, the coordinates of the intermediate cryptographic variables are updated bit-by-bit according to the key bit values. This is the core algorithm of the entire scalar multiplication process, which iterates from the most significant bit to the least significant bit of the key k, using dot addition and / or doubling operations. The algorithm includes a conditional operation process of updating the coordinates of the intermediate cryptographic variables based on the current bit values ​​of the key. Through efficient loops, the multiplication problem is transformed into an iteration related to the key bit length (e.g., 256 times), ultimately constructing the final result of the scalar multiplication in the intermediate cryptographic variables.

[0073] Finally, the scalar multiplication of the base point coordinates and the key value is output. This is the final step in the calculation, responsible for organizing and outputting the final result. At this point, the intermediate cryptographic variables store the result of the k×G scalar multiplication.

[0074] When reverse engineering a target chip using the decryption method provided in this embodiment, the scalar multiplication process of the ECC algorithm is first performed on the target chip, and signal acquisition is performed during this process. Specifically, the location of the SRAM memory array can be easily located through the target chip layout, as the SRAM memory array is formed by multiple SRAMs arranged in a regular pattern. Considering the size of the SRAM memory array and the current size of electromagnetic probes (100µm), an electromagnetic probe can be used to probe a specific SRAM block, observing in real time the physical implementation process of the encryption algorithm executed by that SRAM, i.e., whether data is being read or written to that SRAM; simultaneously, a current probe is used to detect the current of the entire target chip to identify the specific physical implementation stage of the physical implementation process, i.e., the computational operations contained in the data. Since the above observation results are related to the key value, the value of the entire key or part of the key can be derived, rendering the entire target chip's defense scheme ineffective.

[0075] It should be noted that the specific signal acquisition can be implemented according to the following steps. First, by simply unpacking the target chip, locate the SRAM memory array on the chip's layout. SRAM memory arrays are generally quite regular and adjacent to the digital logic area, making it easy to identify the location of each SRAM. After obtaining the location of each SRAM on the chip, perform an elliptic curve scalar multiplication process on the target chip. Connect a current probe to the target chip and use the current probe to monitor the current signal of the entire chip. Simultaneously, use multiple high-precision electromagnetic probes, one-to-one corresponding to the monitoring location of each SRAM on the target chip, to monitor the electromagnetic signal of the corresponding SRAM.

[0076] Furthermore, during signal acquisition, to improve the simplicity and correlation of subsequent joint analysis of electromagnetic and current signals, the current signals need to be precisely aligned in time. For example, the monitoring signals of both the electromagnetic and current probes can be triggered by the same trigger signal to align the time steps of the current and electromagnetic signals. In the above embodiment, the current signal comes from the entire chip, forming only one current change curve to identify the chip's working process and processed data content; while the electromagnetic signals come from each SRAM in the SRAM array, forming multiple electromagnetic change curves equivalent to the number of SRAMs. Combining the aforementioned current change curves, information such as the current SRAM's working process and processed data content can be obtained. Therefore, it is necessary to align the current and electromagnetic signals in time for comparative analysis, further improving the efficiency of the decryption method disclosed in this paper.

[0077] In step S10 of the above embodiments of this disclosure, in addition to monitoring electromagnetic signals, current signals are also monitored. This dual-channel signal acquisition method (current-electromagnetic) provides diverse data types. By combining the current signal with the current signal, the physical operation corresponding to the electromagnetic signal can be determined, greatly reducing the complex calculation process of decryption relying solely on electromagnetic signals (such as simplifying the calculation process of dividing the operation stages of electromagnetic signals), reducing decryption complexity, saving decryption time, and improving decryption efficiency. Simultaneously, the dual verification of electromagnetic and current characteristics ensures the accuracy of subsequent signal analysis.

[0078] Step S20: Based on the signal change patterns of the current signal and the electromagnetic signal, determine the key bit values ​​corresponding to the coordinate values ​​stored in the SRAM.

[0079] In the decryption method provided in this disclosure, to obtain the specific key bit value from the current signal and electromagnetic signal fed back by the chip, a signal analysis process is required. During the signal analysis process, a technical approach is provided that combines current signal analysis and electromagnetic signal analysis to infer the key bit value. That is, in addition to analyzing the change pattern of the electromagnetic signal, the change pattern of the current signal is also analyzed, and based on the correlation between the signal change patterns of the two, fast decryption is completed with fewer computations.

[0080] Specifically, step S20 can use channels other than the electromagnetic channel to acquire the chip's current signal, identify the timing of the ECC algorithm's point-addition and point-doubling operations, and simultaneously use the strength of the electromagnetic radiation signal at the corresponding timing position to indicate whether a read / write operation exists in the corresponding SRAM. Then, the key bit value is determined based on whether a read / write operation exists. The specific process is as follows.

[0081] First, the intensity changes of the current signal are analyzed to identify the point addition and point doubling operations. By monitoring the current signal across the entire chip using a current probe, the point addition and point doubling operations during the entire scalar multiplication calculation can be precisely observed. Since different operations cause changes in the current signal intensity, and the calculation processes of point addition and point doubling operations are clearly distinct, they can be easily differentiated from the current curves. The shape of the curve plotted from the current signal can be used for judgment.

[0082] Next, the intensity changes of the electromagnetic signal are analyzed, and the SRAM corresponding to the electromagnetic signal with abrupt waveforms is taken as the target SRAM. In the scalar multiplication process of elliptic curve cryptography, there are cryptographic intermediate variables unrelated to the key bit value storage; these are represented as the first cryptographic intermediate variable. Cryptographic intermediate variables related to the key bit value storage are represented as the second cryptographic intermediate variable. The main difference is that for the first cryptographic intermediate variable, its value remains the same regardless of whether the current key bit value is 0 or 1. However, the value of the second cryptographic intermediate variable differs depending on whether the current key bit value is 0 or 1. Applying this to the intensity changes of the electromagnetic signal, when the current key bit value changes, the electromagnetic signal corresponding to the SRAM storing the first cryptographic intermediate variable changes relatively smoothly, while the electromagnetic signal corresponding to the SRAM storing the second cryptographic intermediate variable exhibits abrupt waveforms; these are the focus of the analysis for the target SRAM. By analyzing only the electromagnetic signals related to key operations, the analysis process for non-target SRAMs is eliminated, allowing for rapid identification of the SRAM storing cryptographic intermediate variables related to the key bit value, significantly shortening decryption time and improving decryption efficiency.

[0083] Then, based on the dot-addition and doubling-point operation stages, the electromagnetic signals corresponding to at least one target SRAM are analyzed to obtain the read / write operation sequence in at least one target SRAM. The cryptographic intermediate variables stored in the SRAM are closely related to the key value. Therefore, when a dot-addition or doubling-point operation occurs during scalar multiplication, the SRAM storage will change accordingly. This change is the read / write operation change, which can be reflected in the electromagnetic signal. When a read / write operation occurs, the key bit value is either 0 or 1. The aforementioned dot-addition and doubling-point operation stages clearly indicate whether the current read / write operation corresponds to a dot-addition or doubling-point operation. Combining the dot-addition and doubling-point operations in the target SRAM yields the read / write operation sequence. Since the storage actions of the target SRAM are related to the key bit value, local electromagnetic radiation applied to a target SRAM can obtain the key value. Multiple SRAMs can also be used to verify whether there are errors in the analysis process or whether the key bit value is correct.

[0084] Finally, the conditional operations of the cryptographic intermediate variables during the scalar multiplication process are reconstructed from the read / write operation sequence. Based on the reconstruction result, the key bit values ​​corresponding to the coordinate values ​​stored in at least one target SRAM are determined. The calculations directly related to the key bit values ​​during scalar multiplication are implemented based on conditional operations. Specifically, when the current key bit value is 1, the first instruction of the first conditional branch of the conditional operation is executed. This first instruction includes a combination of addition and / or doubling operations on the cryptographic intermediate variables. When the current key bit value is 0, the second instruction of the second conditional branch of the conditional operation is executed. This second instruction also performs a combination of addition and / or doubling operations on the cryptographic intermediate variables, but it is different from the first instruction. This step mainly establishes an association between the previously identified read / write operation sequence and the first or second instruction of the conditional operation, i.e., which read / write operation segments in the read / write operation sequence the first instruction corresponds to, and which read / write operation segments in the read / write operation sequence the second instruction corresponds to. Specifically, this is achieved through the following process: identify the recurring read / write operation segments in the read / write operation sequence and match them with the conditional branches of the conditional operation; after a successful match, record the key bit value corresponding to the read / write operation segment as 1 and the remaining key bit value as 0.

[0085] The above embodiment matches the read / write operation sequence with the conditional operations performed during scalar multiplication when storing the key bit value. This identifies which read / write operation segments correspond to the conditional operation instructions, thus accurately determining the read / write operation segments directly related to the key bit value from the complex operations in the target SRAM. Specifically, a read / write operation segment exists only when the key bit value is 0 or 1. The key bit value is then derived by working backward from the read / write operation segments, further improving the accuracy and efficiency of decryption.

[0086] In the above embodiments, point-addition and point-doubling operations serve as the link between current and electromagnetic signals. Based on changes in the current signal, the point-addition and point-doubling stages of the entire SRAM array can be quickly identified. Then, at least one read / write operation sequence (i.e., a combination of point-addition and point-doubling operations) within the changing electromagnetic signal of the SRAM is determined. Finally, the read / write operation sequence is correlated with the conditional operations performed during scalar multiplication to obtain the key bit value. The entire process does not require complex calculations; by combining current signal analysis, the physical operation corresponding to a specific electromagnetic signal can be determined, simplifying the calculation process of dividing the SRAM storage operation stages. This allows for the rapid acquisition of the target SRAM associated with the key value. Then, based on the read / write operations fed back during decryption and the actual read / write operations, the key value can be quickly obtained. This entire process further improves decryption efficiency.

[0087] Step S30: Determine the corresponding private key based on each key bit value.

[0088] A key value is constructed from the key bit values, and then the private key is reconstructed from the key value. In asymmetric encryption, the key is the same as the private key.

[0089] Step S40: Determine the decryption result based on the private key and the output of the scalar multiplication process.

[0090] The key is reconstructed based on the key bit values ​​obtained from the aforementioned signal analysis steps, and the private key is derived from the key. At this point, the private key is the private key deduced earlier, not the actual private key. Therefore, it is necessary to verify the private key by combining it with the output of the actual scalar multiplication process until the true and correct private key is obtained.

[0091] The decryption method disclosed herein improves the ability to obtain effective information during the decryption process and reduces redundant information processing by using a dual-channel acquisition scheme of current and electromagnetic fields and a correlation analysis scheme. At the same time, based on the matching of point addition operation, doubling operation and scalar multiplication algorithm, it can quickly decrypt the code and improve processing efficiency.

[0092] To explain the decryption method proposed in this disclosure in detail, the following description is based on the implementation scheme of the elliptic curve cryptography algorithm on a chip over a prime field, using the Weier-Strass curve and the Montgomery curve as two examples, and in conjunction with steps S10 to S40.

[0093] Example 1

[0094] The equation of the WeierStrass elliptic curve is defined as shown in formula (1):

[0095] (1)

[0096] in, These are characteristics of the prime field Fp; a and b are elements in the prime field; x and y form the coordinates of a point on the curve. In order to seek and The operation of obtaining the remainder after division.

[0097] There are many side-channel attack methods targeting the Weier-Strass equation, such as Simple Power Analysis (SPA), Differential Power Analysis (DPA), Correlation Power Analysis (CPA), Refined Power Analysis (RPA), and Zero-value Power Analysis (ZPA). The Bit-Replacement Insertion Permutation (BRIP) algorithm is used to defend against these attacks. The BRIP algorithm takes d and P as inputs and outputs [d] × P. The input d is typically a random number or a private key d. Knowing d allows direct derivation of the corresponding key value. The steps of the BRIP algorithm are as follows:

[0098] Step 1: Generate a random point R. This can generally be generated by multiplying the base point by a scalar of the random number.

[0099] Step 2: Determine at least one point on the Weier-Strass elliptic curve, which is the intermediate cipher variable. When point T is the intermediate cipher variable, its coordinates are represented as (X, Y, Z). Taking a 256-bit elliptic curve as an example, the X, Y, and Z coordinates are all 256 bits, and T is a 96-byte variable.

[0100] Step 3: Perform conditional operations based on the key bit value. Iterate through the bits of the key in sequence and perform corresponding operations based on the key bit value of the current bit. For example, when the key bit value is 1, the conditional branch is a dot addition operation of T0=T0+T2; when the key bit value is 0, the conditional branch is a dot addition operation of T0=T0+T1; and regardless of whether the key bit value is 0 or 1, a doubling operation of T0=[2]×T0 is performed.

[0101] Step 4: Output the result of the scalar multiplication.

[0102] Figure 2 This is a vulnerability in existing technologies for storing intermediate cryptographic variables. For example... Figure 2 Suppose that in implementing the BRIP algorithm on a chip, three SRAMs are used to store the variable values ​​of T0, T1, and T2 respectively, and these variables are stored in SRAMs numbered 0, 1, and 2. In the Weier-Strass curve, the X and Y dimensions are involved in calculations far more frequently than the Z dimension. Therefore, as long as the X and Y dimensions of the same intermediate cryptographic variable are obtained from the same SRAM, the aforementioned BRIP-based encryption method can be decrypted.

[0103] The decryption method disclosed herein is used to decrypt the above-mentioned... Figure 2 When a chip designed to implement the BRIP algorithm by storing intermediate cryptographic variables undergoes decryption, the following process occurs:

[0104] First, the time-step precisely aligned current signal and electromagnetic signal are obtained through step S10, and they are plotted as current signal curve and electromagnetic signal curve respectively according to the waveform. Figure 3 This is a schematic diagram of an electromagnetic signal curve and a current signal curve provided in an embodiment of this disclosure. Figure 3 The diagram shows the aligned current signal and electromagnetic signal curves, including one current signal curve and two electromagnetic signal curves from different SRAMs, namely electromagnetic curve 0 and electromagnetic curve 1. However, it is not possible to distinguish which SRAM the electromagnetic signal curve corresponds to at this time.

[0105] Next, the current curve and electromagnetic curve are analyzed in step S20. From Figure 3 The current curves clearly distinguish between the point-addition and point-doubling operation stages. From electromagnetic curve 1, it can be seen that during the point-addition stage, the electromagnetic signal exhibits abrupt waveform changes, sometimes showing read / write signals and sometimes lacking significant radiation. During the point-doubling stage, there is no significant read / write signal radiation, and the electromagnetic probe only collects noise signals. It is known that during the point-addition stage, electromagnetic curve 1 is related to the key storage operation, and its corresponding SRAM is taken as the target SRAM. Specifically, combining this with step 3 of the BRIP algorithm's conditional operation, it can be determined that this SRAM stores either the cryptographic intermediate variable T1 or T2. Similarly, from electromagnetic curve 0, it can be seen that regardless of whether it's the point-addition or point-doubling stage, the SRAM corresponding to electromagnetic curve 0 continuously performs read / write operations throughout the entire operation. It is known that electromagnetic curve 0 is unrelated to the key storage operation. Combining this with step 3 of the BRIP algorithm, it can be determined that the SRAM corresponding to electromagnetic curve 0 stores the cryptographic intermediate variable T0, i.e., the corresponding SRAM is SRAM0, and therefore no further analysis is needed. Next, the implicit read / write operation sequence of electromagnetic curve 1 is analyzed: During the doubling operation phase, read / write operations exist, denoted as the doubling read / write operation segment; during the point addition operation phase, read / write operations exist, denoted as the point addition read / write operation segment, thus obtaining the entire read / write operation sequence. The read / write operation segments in this sequence are matched with the conditional branches of step 3 of the BRIP algorithm to determine the read / write operation segments (i.e., combinations of read / write operations) corresponding to the conditional branch steps. The following assumption is made: if the key bit value corresponding to a read / write operation segment is 0, then there is no key bit value corresponding to that read / write operation segment that is 1.

[0106] Then, the corresponding private key d is obtained from the key bit value in step S30. Since elliptic curve cryptography uses an asymmetric algorithm, the key is the private key. At this time, the private key d is obtained based on the assumption in step S20. Therefore, the private key d is not necessarily the real private key. The private key is only correct if this assumption is true. When the aforementioned assumption "if the key bit value corresponding to the read / write operation segment is 0, then there is no key bit value corresponding to the read / write operation segment" is incorrect, it means that the opposite assumption "if the key bit value corresponding to the read / write operation segment is 1, then there is no key bit value corresponding to the read / write operation segment" is true. In this case, the private key should be inverted.

[0107] Finally, in step S40, the scalar multiplication of the private key d from step S30 and the public base point P is calculated. The calculation result is compared with the output result of [d]×P in the BRIP algorithm. If they match, it means that electromagnetic curve 1 corresponds to SRAM1, which reflects the operation and storage of the cryptographic intermediate variable; otherwise, it means that electromagnetic curve 1 corresponds to SRAM2, which reflects the operation and storage of the cryptographic intermediate variable. The correct key can be obtained by inverting the entire private key d obtained in step S30 according to the bit values.

[0108] Example 2

[0109] Besides the Weier-Strass equation, another type of curve commonly used in elliptic curve cryptography is the Montgomery curve. Among Montgomery curves, the Curve 25519 curve is relatively common. Compared to the Weier-Strass curve, this type of curve can omit the Y-dimensional coordinates and use a standard coordinate system to represent the points on the curve as (U, V). Therefore, it is often used in key negotiation scenarios, such as the Elliptic Curve Diffie-Hellman (ECDH) key negotiation based on Transport Layer Security (TLS), which generally uses this type of curve. Therefore, the Curve 25519 curve must be supported when designing IoT edge chips. The equation of the Curve 25519 curve is shown in formula (2):

[0110] (2)

[0111] Where B is a parameter and B=1; u and v constitute the coordinates of a point on the curve; a represents a constant.

[0112] When the Curve25519 algorithm is implemented using the Montgomery ladder, it is also called the X25519 algorithm, which calls the point addition and doubling points. In this case, the input to the Montgomery ladder algorithm is the base point P = (U...P V P ), key k = (k n-1 =1,k n-2 (,…,k1,k0) and a 24 =(a-2) / 4; the output is U Q =[k]P. The Montgomery ladder algorithm for the Curve 25519 curve is implemented based on two cryptographic intermediate variables R0 and R1, which exist on the X25519 curve. The coordinates of R0 are (U... R0 V R0 The coordinates of R1 are (U R1 V R1 Each coordinate point's value is an element in a 256-bit Fp field. The Montgomery ladder algorithm includes the following steps:

[0113] Step 1: Assign values ​​to intermediate password variables.

[0114] Step 2: Perform conditional operations based on the key bit values. Iterate through the key bits in sequence and perform corresponding operations based on the key bit value of the current bit. For example, when the key bit value is 1, the conditional branches are a dotted addition operation (R0 = R0 + R1) and a doubling operation (R1 = 2 × R1); while when the key bit value is 0, the conditional branches are a dotted addition operation (R1 = R0 + R1) and a doubling operation (R0 = 2 × R0).

[0115] Step 3: Perform subsequent calculations and output the result of the scalar multiplication.

[0116] Figure 4 This is another vulnerable method for storing intermediate cryptographic variables. For example... Figure 4 Assuming that when implementing the Montgomery ladder algorithm in the chip, two SRAMs are used to store the variable values ​​of R0 and R1 respectively, and the variables of R0 and R1 are stored in SRAMs numbered 0 and 1 respectively.

[0117] Similar to the decryption process in Example 1, an electromagnetic probe is placed at SRAM0, and the scalar multiplication process of the Montgomery ladder algorithm is executed simultaneously. It can be observed that significant electromagnetic radiation is present at SRAM0 during point addition. During elliptic curve doubling, if the bit value corresponding to scalar k is 0, significant electromagnetic radiation is present in SRAM0 corresponding to the variable R0 of the doubling operation. However, if the bit value corresponding to scalar k is 1, no read / write operation occurs in SRAM0, and no significant electromagnetic radiation is observed. Therefore, according to steps S10-S40 of the decryption method of this disclosure, as long as the U-dimensional coordinates and V-dimensional coordinates of the same cryptographic intermediate variable are obtained in the same SRAM, the aforementioned encryption method based on the Montgomery ladder algorithm can be decrypted, thereby obtaining the key.

[0118] Furthermore, from an encryption perspective, the random storage in existing encryption methods presents the following drawbacks. First, position permutation requires a significant amount of time. Taking an elliptic curve cryptography algorithm with 256-bit length and using Jacobian or standard coordinate systems to identify coordinate points as an example, the Jacobian coordinate system requires three 256-bit variables, totaling 768 bits, or 24 words. Assuming one clock cycle for reading or writing one word to the SRAM, 24 words require 24 clock cycles. Since three separate read / write operations are needed for each of the three variables, the entire clock cycle requires 24 × 3 = 72 clock cycles, significantly increasing the computation time of the elliptic curve cryptography algorithm. Second, besides increasing clock cycles, data permutation also introduces additional power consumption. The 72 clock cycles of SRAM read / write operations during data permutation consume a large amount of current, increasing battery consumption and reducing battery life for IoT devices or SIM chips used in mobile devices. Additionally, random storage allows attackers to directly obtain the coordinate values ​​of all dimensions of a cryptographic intermediate variable from a single SRAM, thus quickly obtaining the key value, indicating poor security.

[0119] To address the problems of existing technologies, embodiments of this disclosure provide a method, apparatus, device, computer storage medium, and computer program product for storing SRAM variables in cryptographic algorithms. Throughout the cryptographic encryption process, this disclosure cleverly sets the storage rules for intermediate cryptographic variables so that an attacker cannot directly obtain the coordinate values ​​of all dimensions of an intermediate cryptographic variable from an SRAM, thus avoiding the aforementioned drawbacks. Compared to existing random storage, it requires less computation and significantly improves security, especially in defending against the decryption methods proposed in this disclosure.

[0120] The embodiments disclosed herein can be applied to scenarios where keys are stored within a physical carrier, which can be a chip.

[0121] The SRAM storage method for cryptographic algorithm variables provided in the embodiments of this disclosure is described below.

[0122] Figure 5 A flowchart illustrating an embodiment of the SRAM storage method for cryptographic algorithm variables provided in this disclosure is shown. Figure 5 As shown, the method includes steps S1 and S2. Specifically, it includes the following:

[0123] Step S1: Obtain the coordinate values ​​of at least two coordinate dimensions of at least one cryptographic intermediate variable used in the scalar multiplication process of the elliptic curve cryptography algorithm.

[0124] In the scalar multiplication process of elliptic curve cryptography, intermediate cryptographic variables are used as accumulators for iterative updates of key-related intermediate variables. Depending on the elliptic curve cryptography algorithm, multiple different intermediate cryptographic variables can be set. Furthermore, the coordinate dimensions of the intermediate cryptographic variables will differ for different elliptic curves.

[0125] Step S2: Distribute the coordinate values ​​of at least two coordinate dimensions of at least one cryptographic intermediate variable into at least two SRAMs; or, jointly store the coordinate values ​​of at least one coordinate dimension of at least two cryptographic intermediate variables into the same SRAM.

[0126] Step S2 sets two selectable storage strategies for cryptographic intermediate variables. Strategy one is distributed storage, where the coordinate values ​​of at least two coordinate dimensions of at least one cryptographic intermediate variable are distributed across at least two SRAMs. The core principle is to ensure that during operations related to the key value, the coordinate values ​​of the corresponding coordinate dimensions of the cryptographic intermediate variable are stored in the same SRAM. When at least one cryptographic intermediate variable is related to the key bit value, the at least two coordinate dimensions of that cryptographic intermediate variable, determined in step S1, are stored in different SRAMs. For example, when there are three coordinate dimensions, three SRAMs are set up to store one of the three coordinate dimensions. When there are two coordinate dimensions, at least two SRAMs are set up to store one of the two coordinate dimensions. Specifically, the X-dimensional coordinate value of the cryptographic intermediate variable T(X, Y, Z) is stored in SRAM0, the Y-dimensional coordinate value in SRAM1, and the Z-dimensional coordinate value in SRAM2. Strategy two is joint storage, where the coordinate values ​​of at least two coordinate dimensions of at least two cryptographic intermediate variables are jointly stored in the same SRAM. The core principle is to ensure that, during operations related to the key value, at least two cryptographic intermediate variables corresponding to different coordinate dimensions are stored in a single SRAM. For example, for two cryptographic intermediate variables T0(X0,Y0,Z0) and T1(X1,Y1,Z1), the X-dimensional coordinate values ​​X0 and X1 are stored in SRAM 0, while the Y-dimensional coordinate values ​​Y0 and Y1 and the Z-dimensional coordinate values ​​Z0 and Z1 are stored in SRAM 1. Of course, this is not limited to other situations that can achieve the above approach; other similar storage strategies can be set based on this strategy.

[0127] This disclosure presents an SRAM storage method for cryptographic algorithm variables, providing a key consideration for how variables are stored in SRAM during chip hardware implementation of encryption algorithms to prevent local electromagnetic radiation attacks. During point addition and multiplication point calculations, it prevents attackers from obtaining the coordinates of the same intermediate cryptographic variable from a single SRAM, effectively avoiding attackers using local electromagnetic radiation analysis to deduce the key and improving chip security. Furthermore, it ensures that storing the point addition and multiplication point calculation process does not increase computational burden or affect the execution efficiency of the encryption algorithm, significantly reducing execution time. Compared to previous randomized storage of intermediate variables, this method saves computation time and power consumption, making it more suitable for low-power scenarios in IoT edge chips. It achieves elliptic curve cryptography defense against local electromagnetic radiation analysis at a very low cost, demonstrating strong practicality.

[0128] The storage method disclosed herein is still based on the implementation scheme of elliptic curve cryptography algorithm on chip over prime field, and is described in conjunction with the specific steps of S1 to S2 using Weier-Strass curves and Montgomery curves as examples.

[0129] In the Weier-Strass curve of Example 1, the intermediate cryptographic variables are T0(X0,Y0,Z0), T1(X1,Y1,Z1), and T2(X2,Y2,Z2). However, since changes in the bit values ​​of the key do not affect T0(X0,Y0,Z0), T1(X1,Y1,Z1) and T2(X2,Y2,Z2) are identified as the key intermediate cryptographic variables to focus on in step S1. Considering that the X-dimensional and Y-dimensional coordinate values ​​are involved in calculations far more frequently than the Z-dimensional coordinate value in the Weier-Strass curve, decryption can be performed as long as the X-dimensional and Y-dimensional coordinate values ​​of the same intermediate cryptographic variable are obtained in the same SRAM block.

[0130] Therefore, in step S1, at least the coordinate values ​​of T1(X1,Y1,Z1) and T2(X2,Y2,Z2) in the X and Y dimensions should be identified. Figure 6 This is a cryptographic intermediate variable storage method based on the disclosed variable storage method. In step S2, as... Figure 6 As shown, three SRAMs can be configured. SRAM 0 stores the X-dimensional coordinates X0, X1, and X2; SRAM 1 stores the Y-dimensional coordinates Y0, Y1, and Y2; and SRAM 2 stores the Z-dimensional coordinates Z0, Z1, and Z2. Considering that the X-dimensional and Y-dimensional coordinates are used in calculations far more frequently than the Z-dimensional coordinates, and decryption can be performed as long as the X-dimensional and Y-dimensional coordinates of the same intermediate password variable are obtained from the same SRAM, the following configuration can also be used: Two SRAMs are configured, with SRAM 0 storing the X-dimensional coordinates X0, X1, and X2, SRAM 1 storing the Y-dimensional coordinates Y0, Y1, and Y2, and the Z-dimensional coordinates Z0, Z1, and Z2 randomly stored in SRAM 0 and SRAM 1. After adopting this protection scheme, the BRIP algorithm calculation is then performed. Regardless of whether the current key bit value is 0 or 1, when performing the dot addition operation in step 3, the coordinate values ​​of T2 or T1 need to be loaded from the same SRAM. The coordinate values ​​cannot be distinguished solely by the SRAM cell array, thus achieving the goal of defending against localized electromagnetic radiation analysis. Furthermore, if the SRAM cell size is 1KB and the maximum number of bits for the coordinate value is 512 bits (64 bytes), then the six sets of variables X1, X2, Y1, Y2, Z1, and Z2 can simultaneously exist in the same SRAM.

[0131] In the X25519 curve form of the Montgomery curve in Example 2, changes in the bit value of the key value will affect R0(U). R0 V R0 ) and R1(U R1 V R1Therefore, the intermediate password variable is determined to be R0(U). R0 V R0 ) and R1(U R1 V R1 In step S1, at least R0(U) should be identified. R0 V R0 ) and R1(U R1 V R1 The coordinate values ​​in the U and V dimensions. Figure 7 The diagram shows another method for storing cryptographic intermediate variables based on the variable storage method proposed in this disclosure. In step S2, as... Figure 7 As shown, two SRAMs are set up. SRAM 0 stores the coordinate values ​​of dimension U. R0 U R1 SRAM 1 stores the coordinate values ​​of dimension V. R1 V R0 This ensures that during the calculation of point addition and multiplication points in scalar multiplication, there is no process where the U-dimensional coordinate values ​​and V-dimensional coordinate values ​​need to be simultaneously input into a certain hardware operator, thus providing excellent defense.

[0132] In one embodiment, when at least one cryptographic intermediate variable includes three coordinate dimensions that need to be encrypted simultaneously, storing the coordinate values ​​of at least two coordinate dimensions of at least one cryptographic intermediate variable in at least two SRAMs includes: storing the coordinate values ​​of two coordinate dimensions of the at least one cryptographic intermediate variable in the same SRAM, and storing the coordinate value of the other coordinate dimension of the at least one cryptographic intermediate variable in another SRAM.

[0133] In the above embodiments, the scenario of simultaneous computation of intermediate cryptographic variables was considered, and the coordinate dimensions to be computed simultaneously were distributed and stored in different SRAMs. This is because if the simultaneously computed intermediate cryptographic variables were stored in the same SRAM, since the general technology of SRAM does not support two data read ports, and an SRAM has only one data read port, the two variables would need to be read sequentially. One of the variables would need to be latched using a register, which wastes both clock cycles and the register space used for latching to store the intermediate variable, ultimately resulting in slow data reading and hindering the improvement of computation speed. Therefore, when calculating the values ​​of intermediate cryptographic variables in different dimensions, it is necessary to ensure that there are no conflicts in simultaneous reading or writing to the SRAM.

[0134] For example, in the Weier-Strass curve of Example 1, there are cases where the X and Z coordinates, and the Y and Z coordinates are calculated simultaneously during point addition and doubling operations. According to Strategy 1, the X and Y coordinates of the corresponding intermediate cryptographic variable T can be stored in the same SRAM, while the Z coordinate is stored in another SRAM, to ensure that variables that need to be accessed simultaneously during the entire algorithm execution process are stored in different SRAM units.

[0135] Figure 8 This is a schematic diagram of a decryption device provided in an embodiment of this disclosure. Figure 8 As shown, the device may include a signal acquisition module 210, a signal analysis module 220, a private key acquisition module 230, and a decryption result output module 240.

[0136] The signal acquisition module 210 is used to perform the scalar multiplication process of the elliptic curve cryptography algorithm on the target chip, and to monitor the current signal of the target chip through a current probe, and to monitor the electromagnetic signal of the SRAM on the target chip through an electromagnetic probe. The SRAM is used to store the coordinate values ​​of the cryptographic intermediate variables.

[0137] The signal analysis module 220 is used to determine the key bit values ​​corresponding to the coordinate values ​​stored in the SRAM based on the signal change patterns of the current signal and the electromagnetic signal.

[0138] Private key acquisition module 230 is used to determine the corresponding private key based on each key bit value;

[0139] The decryption result output module 240 is used to determine the decryption result based on the output of the private key and the scalar multiplication process.

[0140] Optionally, the signal acquisition module 210 is also used for:

[0141] A current probe is connected to the target chip to monitor the overall current signal of the target chip; multiple electromagnetic probes are correspondingly positioned at each monitoring location of each SRAM on the target chip to monitor the electromagnetic signal of the corresponding SRAM; the signal acquisition module is also used for:

[0142] The monitoring signals of the electromagnetic probe and the current probe are triggered by the same trigger signal, so that the time steps of the electromagnetic signal and the current signal are aligned.

[0143] Optionally, the signal analysis module 220 is also used for:

[0144] Analyze the intensity changes of the current signal to identify the point-addition operation stage and the point-doubling operation stage;

[0145] Analyze the intensity changes of electromagnetic signals and use the SRAM corresponding to electromagnetic signals with abrupt waveform changes as the target SRAM;

[0146] Based on the point-addition operation stage and the point-doubling operation stage, analyze the electromagnetic signals corresponding to at least one target SRAM to obtain the read-write operation sequence in at least one target SRAM.

[0147] The conditional operations of the cryptographic intermediate variables during the scalar multiplication process are restored from the read and write operation sequence, and the key bit values ​​corresponding to the coordinate values ​​stored in at least one target SRAM are determined based on the restoration result.

[0148] Optionally, the signal analysis module 220 is also used for:

[0149] Identify the recurring read / write operation segments in the read / write operation sequence and match them with the conditional branches of the conditional operation;

[0150] After a successful match, the key bit value corresponding to the read / write operation segment is recorded as 1, and the remaining key bit value is recorded as 0.

[0151] Optionally, the signal acquisition module 210 is also used to perform the following scalar multiplication process:

[0152] Input the base point coordinates and the key value;

[0153] Initialize the coordinate values ​​of the intermediate password variables;

[0154] Update the coordinates of the intermediate cryptographic variables bit by bit according to the key bit value of the key value;

[0155] Output the scalar multiplication result of the base point coordinates and the key value.

[0156] Optionally, the signal acquisition module 210 is also used to handle the following situations:

[0157] The coordinate system in which the intermediate variables of the password reside includes at least one of the Jacobian coordinate system, the standard coordinate system, and the affine coordinate system.

[0158] Figure 9 This is a schematic diagram of an SRAM storage device structure for cryptographic algorithm variables provided in an embodiment of this disclosure. Figure 9 As shown, the device may include a coordinate value acquisition module 1 and a coordinate value storage module 2.

[0159] The coordinate value acquisition module 1 is used to obtain the coordinate values ​​of at least two coordinate dimensions of at least one cryptographic intermediate variable used in the scalar multiplication process of the elliptic curve cryptography algorithm.

[0160] The coordinate value storage module 2 is used to disperse and store the coordinate values ​​of at least two coordinate dimensions of at least one cryptographic intermediate variable in at least two SRAMs; or, to store the coordinate values ​​of at least one coordinate dimension of at least two cryptographic intermediate variables together in the same SRAM.

[0161] Optionally, the coordinate value storage module 2 is also used for:

[0162] When at least two cryptographic intermediate variables include three coordinate dimensions that need to be encrypted simultaneously, the coordinate values ​​of at least one coordinate dimension of the at least two cryptographic intermediate variables are stored together in the same SRAM: the coordinate values ​​of two coordinate dimensions of the at least one cryptographic intermediate variable are stored in the same SRAM, and the coordinate value of the other coordinate dimension is stored in another SRAM.

[0163] Figure 10 A schematic diagram of the hardware structure of the device provided in an embodiment of this disclosure is shown.

[0164] The device may include a processor 301 and a memory 302 storing computer program instructions.

[0165] Specifically, the processor 301 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this disclosure.

[0166] Memory 302 may include mass storage for data or instructions. For example, and not limitingly, memory 302 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. In one instance, memory 302 may include removable or non-removable (or fixed) media, or memory 302 may be non-volatile solid-state memory. Memory 302 may be internal or external to the integrated gateway disaster recovery device.

[0167] In one instance, memory 302 may be read-only memory (ROM). In one instance, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0168] Memory 302 may include read-only memory (ROM), random access memory (RAM), disk storage media device, optical storage media device, flash memory device, electrical, optical, or other physical / tangible memory storage device. Therefore, generally, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to one aspect of this disclosure.

[0169] The processor 301 reads and executes computer program instructions stored in the memory 302 to achieve... Figure 1 The decryption method in the illustrated embodiment, and / or, Figure 5 The SRAM storage method for cryptographic algorithm variables shown in the embodiment.

[0170] In one example, the device may also include a communication interface 303 and a bus 304. Wherein, for example... Figure 10 As shown, the processor 301, memory 302, and communication interface 303 are connected through bus 304 and complete communication with each other.

[0171] The communication interface 303 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this disclosure.

[0172] Bus 304 includes hardware, software, or both, that couples components of a device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 304 may include one or more buses. Although specific buses are described and illustrated in embodiments of this disclosure, this disclosure contemplates any suitable bus or interconnect.

[0173] Furthermore, in conjunction with the decryption methods in the above embodiments, and / or the SRAM storage method for cryptographic algorithm variables, this disclosure can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the decryption methods in the above embodiments, and / or the SRAM storage method for cryptographic algorithm variables.

[0174] This application also provides a computer program product, including a computer program that, when executed by a processor, implements any of the decryption methods described in the above embodiments, and / or a method for storing cryptographic algorithm variables in SRAM.

[0175] It should be clarified that this disclosure is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this disclosure is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this disclosure.

[0176] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this disclosure are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, read-only memory (ROM), flash memory, erasable read-only memory (EROM), floppy disks, compact disc read-only memory (CD-ROM), optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0177] It should also be noted that the exemplary embodiments mentioned in this disclosure describe methods or systems based on a series of steps or apparatus. However, this disclosure is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0178] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0179] The above description is merely a specific embodiment of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this disclosure, and these modifications or substitutions should all be covered within the protection scope of this disclosure.

Claims

1. A decryption method characterized by, include: The scalar multiplication process of the elliptic curve cryptography algorithm is executed on the target chip, and the current signal of the target chip is monitored by a current probe, and the electromagnetic signal of the SRAM on the target chip is monitored by an electromagnetic probe. The SRAM is used to store the coordinate values ​​of the cryptographic intermediate variables. The scalar multiplication process is implemented based on conditional operations, which include a first conditional branch and a second conditional branch. Based on the signal change patterns of the current signal and the electromagnetic signal, determine the key bit values ​​corresponding to the coordinate values ​​stored in the SRAM; The corresponding private key is determined based on each of the key bit values; The decryption result is determined based on the private key and the output of the scalar multiplication process; The step of determining the key bit value corresponding to each coordinate value stored in the SRAM based on the signal change patterns of the current signal and the electromagnetic signal includes: Analyze the intensity changes of the current signal to identify the point-addition operation stage and the point-doubling operation stage; Analyze the intensity changes of the electromagnetic signal, and take the SRAM corresponding to the electromagnetic signal with abrupt waveforms as the target SRAM; Based on the point addition operation stage and the point doubling operation stage, the electromagnetic signal corresponding to at least one of the target SRAMs is analyzed to obtain the read and write operation sequence in at least one of the target SRAMs, and the read and write operation sequence includes multiple read and write operation segments. The multiple read / write operation segments are correlated with the first instruction of the first conditional branch and the second instruction of the second conditional branch to determine the key bit values ​​corresponding to the coordinate values ​​stored in at least one of the target SRAMs; the first instruction represents a combination of operations that perform point addition and / or doubling operations on the cryptographic intermediate variable based on the first conditional branch; the second instruction represents a combination of operations that perform point addition and / or doubling operations on the cryptographic intermediate variable based on the second conditional branch. Determining the decryption result based on the private key and the output of the scalar multiplication process includes: if the scalar multiplication of the private key and the public base point is consistent with the output result, the private key is taken as the correct private key; otherwise, the bit values ​​of the private key are inverted to obtain the correct private key.

2. The decryption method according to claim 1, characterized in that, The current probe is connected to the target chip and is used to monitor the overall current signal of the target chip; Multiple electromagnetic probes are respectively set at the monitoring positions of each SRAM of the target chip to monitor the electromagnetic signals of the corresponding SRAM; The method further includes: The monitoring signals of the electromagnetic probe and the current probe are triggered by the same trigger signal, so that the time steps of the electromagnetic signal and the current signal are aligned.

3. The decryption method of claim 1, wherein, The step of performing correlation analysis between the plurality of read / write operation segments and the first instruction of the first conditional branch and the second instruction of the second conditional branch to determine the key bit values ​​corresponding to at least one of the coordinate values ​​stored in the target SRAM includes: Identify the recurring read / write operation segments in the read / write operation sequence and match them with the conditional branches of the conditional operation; After a successful match, the key bit value corresponding to the read / write operation segment is recorded as 1, and the remaining key bit values ​​are recorded as 0.

4. The decryption method of claim 1, wherein, The scalar multiplication process includes: Input the base point coordinates and the key value; Initialize the coordinate values ​​of the intermediate password variable; The coordinate values ​​of the cryptographic intermediate variable are updated bit by bit according to the key bit values ​​of the key value; Output the scalar multiplication result of the base point coordinates and the key value.

5. The decryption method of claim 1, wherein, The coordinate system in which the intermediate cryptographic variables are located includes at least one of the Jacobian coordinate system, the standard coordinate system, and the affine coordinate system.

6. A decryption device, characterized by The device includes: The signal acquisition module is used to execute the scalar multiplication process of the elliptic curve cryptography algorithm on the target chip, and to monitor the current signal of the target chip through a current probe and the electromagnetic signal of the SRAM on the target chip through an electromagnetic probe. The SRAM is used to store the coordinate values ​​of the cryptographic intermediate variables. The scalar multiplication process is implemented based on conditional operations, which include a first conditional branch and a second conditional branch. The signal analysis module is used to determine the key bit values ​​corresponding to the coordinate values ​​stored in the SRAM based on the signal change patterns of the current signal and the electromagnetic signal. The private key acquisition module is used to determine the corresponding private key based on each of the key bit values; The decryption result output module is used to determine the decryption result based on the private key and the output of the scalar multiplication process; The step of determining the key bit value corresponding to each coordinate value stored in the SRAM based on the signal change patterns of the current signal and the electromagnetic signal includes: Analyze the intensity changes of the current signal to identify the point-addition operation stage and the point-doubling operation stage; Analyze the intensity changes of the electromagnetic signal, and take the SRAM corresponding to the electromagnetic signal with abrupt waveforms as the target SRAM; Based on the point addition operation stage and the point doubling operation stage, the electromagnetic signal corresponding to at least one of the target SRAMs is analyzed to obtain the read and write operation sequence in at least one of the target SRAMs, and the read and write operation sequence includes multiple read and write operation segments. The multiple read / write operation segments are correlated with the first instruction of the first conditional branch and the second instruction of the second conditional branch to determine the key bit values ​​corresponding to the coordinate values ​​stored in at least one of the target SRAMs; the first instruction represents a combination of operations that perform point addition and / or doubling operations on the cryptographic intermediate variable based on the first conditional branch; the second instruction represents a combination of operations that perform point addition and / or doubling operations on the cryptographic intermediate variable based on the second conditional branch. Determining the decryption result based on the private key and the output of the scalar multiplication process includes: if the scalar multiplication of the private key and the public base point is consistent with the output result, the private key is taken as the correct private key; otherwise, the bit values ​​of the private key are inverted to obtain the correct private key.

7. An apparatus, comprising: The device includes: a processor and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the decryption method as described in any one of claims 1-5.

8. A computer storage medium, characterized in that The computer storage medium stores computer program instructions, and the computer program instructions are executed by a processor to implement the decryption method in any one of claims 1-5.

9. A computer program product, characterised in that, The computer program is executed by a processor to implement the decryption method in any one of claims 1-5.

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