Equipment delay determination method and device, equipment and medium

Abstract

The embodiment of the invention provides an equipment delay determination method and device, equipment and a medium. The method comprises the steps of generating a target trigger signal based on a preset signal trigger in a test process of to-be-tested equipment; distributing the target trigger signal to a plurality of measuring devices so as to synchronously trigger data acquisition of the plurality of measuring devices; determining a plurality of effective test signals collected by the plurality of measuring devices, and performing time domain resampling processing on the plurality of effective test signals to generate a test signal sequence on a unified time axis based on the plurality of test signals after time domain resampling; and determining the total delay of the to-be-tested equipment and the multi-level delay corresponding to the to-be-tested equipment based on the test signal sequence on the unified time axis. According to the method, through hardware synchronization and time axis calibration, time alignment of multiple devices is achieved, end-to-end and inter-module delay of the devices is accurately quantified, and the requirement for high-precision device delay testing is met.

Description

Technical Field

[0001] This application relates to the field of communication testing technology, and in particular to a method, apparatus, device and medium for determining device delay. Background Technology

[0002] In fields with stringent real-time requirements, such as industrial automation, collaborative robotic operations, and precise control of medical equipment, signal transmission latency between multiple devices within a system is a core indicator directly impacting overall performance, synchronization accuracy, and operational safety. Taking collaborative robotic operations as an example, uncontrollable delays in command responses between the master control device and slave actuators can lead to multi-axis motion synchronization failure, increased trajectory tracking errors, and even task failure. In complex industrial automation production lines composed of sensors, controllers, and actuators connected in series, signals undergo multiple stages of transmission and processing. Without accurately quantifying the latency percentage of each stage, it is difficult to effectively pinpoint system bottlenecks and perform targeted optimizations. Furthermore, in high-end medical equipment such as surgical robots, even minute delays between master and slave operations can be amplified into clinical risks, threatening surgical safety and outcomes.

[0003] In related technologies, conventional techniques for delay measurement across devices and signal types are often limited by the measurement range of a single instrument or rely on the software synchronization of the built-in clocks of each device. This results in problems such as inconsistent time bases, single measurement dimensions, and insufficient synchronization accuracy, making it difficult to achieve full-link, high-precision, and traceable multi-dimensional delay analysis and bottleneck diagnosis. This restricts the optimization and verification of high-performance real-time systems and leads to inaccurate device delay measurement results. Summary of the Invention

[0004] This application provides a method, apparatus, device, and medium for determining device delay, as well as a computer program product, to achieve time alignment of multiple devices, accurately quantify end-to-end and inter-module delays of devices, and meet the requirements for high-precision device delay testing.

[0005] In a first aspect, embodiments of this application provide a method for determining device delay, comprising: during the testing of a device under test, generating a target trigger signal based on a preset signal trigger; distributing the target trigger signal to multiple measuring devices to synchronously trigger data acquisition by the multiple measuring devices; determining multiple valid test signals acquired by the multiple measuring devices, and performing time-domain resampling processing on the multiple valid test signals to generate a test signal sequence on a unified time axis based on the multiple test signals after time-domain resampling; and determining the delay of the device under test and the multi-level delay corresponding to the device under test based on the test signal sequence on the unified time axis.

[0006] In one possible implementation, determining the multiple valid test signals acquired by the multiple measuring devices includes: determining a unified time origin for the multiple measuring devices based on the target trigger signal, wherein the unified time origin includes the test signal acquisition time origin; acquiring the multiple test signals acquired by the multiple measuring devices, and determining multiple valid test signals corresponding to the multiple test signals based on the unified time origin.

[0007] In one possible implementation, the step of performing time-domain resampling processing on the plurality of valid test signals to generate a test signal sequence on a unified time axis based on the multiple time-domain resampled test signals includes: determining multiple acquisition frequencies corresponding to the plurality of measurement devices, and determining a common multiple of sampling frequencies; determining time-domain resampling processing on the plurality of valid test signals based on the common multiple of sampling frequencies to obtain multiple time-domain resampled valid test signals; and generating a test signal sequence on a unified time axis based on the multiple time-domain resampled valid test signals.

[0008] In one possible implementation, the step of performing time-domain resampling processing on the plurality of test signals based on the common multiple of sampling includes: determining a sliding window corresponding to the measuring device, and determining signal characteristics corresponding to the measuring device based on the sliding window; determining a time-domain resampling strategy for the test signals corresponding to the measuring device based on the signal characteristics, and performing time-domain resampling processing on the valid test signals based on the time-domain resampling strategy.

[0009] In one possible implementation, determining the total delay of the device under test based on the test signal sequence on the unified time axis includes: determining the key event timestamps corresponding to the plurality of measuring devices in the test signal sequence on the unified time axis, the key event timestamps including input excitation feature point timestamps and output response feature point timestamps; determining the end-to-end response delay corresponding to the device under test based on the output response feature point timestamps and the output excitation feature point timestamps; and determining the total delay of the device under test based on the response delay.

[0010] In one possible implementation, the method further includes: if the test signal sequence on the unified time axis is a series signal chain, then determining the transmission delay between any two measuring devices based on the key event timestamp; determining the multi-level delay of the device under test based on the transmission delay, and generating a corresponding visual delay analysis report based on the multi-level delay.

[0011] Secondly, embodiments of this application provide a device for determining device delay. The device includes: a triggering module, used to generate a target trigger signal based on a preset signal trigger during the testing process of the device under test; a distribution module, used to distribute the target trigger signal to multiple measuring devices to synchronously trigger data acquisition by the multiple measuring devices; an alignment module, used to determine multiple valid test signals acquired by the multiple measuring devices and perform time-domain resampling processing on the multiple valid test signals to generate a test signal sequence on a unified time axis based on the multiple test signals after time-domain resampling; and a determination module, used to determine the total delay of the device under test and the multi-level delay corresponding to the device under test based on the test signal sequence on the unified time axis.

[0012] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0013] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0014] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0015] The device delay determination method, apparatus, device, and medium provided in this application generate a target trigger signal by pre-set a signal trigger and distribute it to multiple measuring devices, achieving hardware-level synchronous startup of data acquisition. This fundamentally avoids time misalignment caused by instruction transmission delays or system scheduling differences. By resampling the acquired multiple signals in the time domain and mapping them to a unified time axis, not only is the problem of inconsistent sampling frequencies of different measuring devices solved, but strict alignment of signals in the time dimension is also ensured. This allows subsequent analysis to accurately capture microsecond-level or even nanosecond-level delays generated by the device under test at different stages. Moreover, the combination of this synchronization mechanism and time axis calibration technology can simultaneously reveal the overall end-to-end total delay of the device and the delay distribution of the signal transmission path between internal multiple modules. This provides a highly reliable quantitative basis for system performance optimization, fault location, and timing constraint design, and is particularly suitable for real-time control systems, high-speed communication equipment, or precision instrument testing scenarios with stringent time accuracy requirements. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] Figure 1 A schematic diagram illustrating the scenario for determining the device delay provided in this application;

[0018] Figure 2 Flowchart of the device delay determination method provided in this application Figure 1 ;

[0019] Figure 3 Flowchart of the device delay determination method provided in this application Figure 2 ;

[0020] Figure 4 A schematic diagram of the device delay determination apparatus provided in this application;

[0021] Figure 5 A schematic diagram of the structure of the electronic device provided in this application.

[0022] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0024] First, let me explain the terms used in this application:

[0025] Device latency refers to the time interval between receiving a valid signal at the input and generating a corresponding response at the output during the processing, transmission, or conversion of a signal or data within a device. This time difference can be caused by a combination of factors, including physical delays in hardware circuits (such as the speed limit of signal propagation within a chip), processing time of software algorithms (such as data parsing, calculation, or scheduling overhead), communication buffering between modules (such as queuing during bus transmission), or system-level synchronization errors (such as clock drift during multi-device collaboration). Device latency is a key indicator for measuring the real-time performance of a system, directly affecting the response speed of the control system, the transmission efficiency of communication equipment, and the accuracy of measuring instruments. Especially in scenarios requiring strict timing coordination (such as industrial automation, collaborative robot operations, and precise control of medical equipment), excessive latency can lead to functional failures or even safety hazards.

[0026] Time-domain resampling is a signal processing technique that adjusts the signal sampling rate to maintain data consistency across different time resolutions. Its core lies in interpolation or decimation of the original sampled signal: when a low-sampling-rate signal needs to be boosted to a higher frequency, algorithms (such as linear interpolation or spline interpolation) generate new data points between the original sampling points to fill the time intervals; conversely, when the sampling rate needs to be reduced, some original data points are decimated according to rules, while anti-aliasing filtering avoids high-frequency noise distortion. This process ensures that signals with different sampling frequencies are aligned on the time axis, providing a unified time reference for multi-device synchronous analysis, frequency domain conversion, or system modeling. It is widely used in fields such as communication, audio processing, and measurement testing.

[0027] Please see Figure 1 , Figure 1 A schematic diagram of the scenario for determining the device delay provided in this application, such as Figure 1 As shown, this scenario includes a device under test (DUT) 110, multiple measuring devices 120, and a server 130. Specifically, during the testing of the DUT 110, the server 130 generates a corresponding target trigger signal based on a preset signal trigger and distributes this target trigger signal to the multiple measuring devices 120 to synchronously trigger data acquisition by the multiple measuring devices. Then, the server 130 determines the multiple valid test signals acquired by the multiple measuring devices and performs time-domain resampling processing on these multiple valid test signals to generate a test signal sequence on a unified time axis based on the time-domain resampled test signals. Finally, the server 130 can determine the total delay of the DUT 110 and the corresponding multi-level delay of the DUT based on the test signal sequence on the unified time axis. This achieves accurate measurement of the delay of the DUT.

[0028] The device under test 110, the measuring device 120 and the server 130 can communicate with each other via wired or wireless means, and this application does not impose any restrictions on this.

[0029] In high-real-time fields such as industrial automation, collaborative robot operations, and precise control of medical equipment, signal transmission delay between multiple devices has become a core bottleneck restricting system performance, synchronization accuracy, and operational safety. Taking multi-robot collaborative operation scenarios as an example, the instruction transmission between the master control device and the slave actuators must meet the microsecond-level response requirement. If there is uncontrollable delay, it will directly lead to multi-axis motion loss of synchronization, accumulation of trajectory tracking errors, and even mechanical collisions or task interruptions, seriously affecting production efficiency and equipment lifespan.

[0030] For example, in complex industrial automated production lines, sensors, controllers, and actuators are connected in series through multi-level networks. Signals must undergo analog-to-digital conversion, protocol encapsulation, bus transmission, and processing scheduling. The hardware circuit delays, software algorithm time consumption, and communication protocol overhead of each stage add up to form a complex delay chain that is difficult to quantify. Existing technologies mostly rely on rough estimations or offline calibration of delays in a single stage, failing to dynamically track the real-time delay distribution of signals throughout the entire chain. This results in a lack of accurate data support for system optimization and low efficiency in bottleneck location. Crucially, in high-end medical equipment such as surgical robots, signal delays at the master and slave operating ends are further amplified by the mechanical feedback of human tissue. Even sub-millisecond delays can cause operational jitter and force feedback distortion, directly threatening surgical accuracy and patient safety. Therefore, how to achieve real-time quantification, dynamic compensation, and synchronous optimization of signal transmission delays across multiple devices has become a key technical challenge for improving the reliability, security, and intelligence of high real-time systems.

[0031] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0032] Figure 2 Flowchart of the device delay determination method provided in this application Figure 1 ,like Figure 2 As shown, the process of determining the device delay includes at least steps S201 to S204, which are described in detail below:

[0033] Step S201: During the testing process of the device under test, a target trigger signal is generated based on a preset signal trigger.

[0034] For example, a preset signal trigger can be carefully designed and configured according to the test requirements, and the type of its output signal can be determined, such as an electrical pulse signal, an optical signal, or a waveform signal of a specific frequency. At the same time, the key parameters of the signal, such as the amplitude, duration, and steepness of the rising and falling edges, should be determined. The settings of these parameters should closely match the triggering requirements of the device under test to ensure that the device can be accurately driven to start the test action.

[0035] Optionally, a reliable connection is established between the preset signal trigger and the device under test. If the trigger signal is an electrical signal, the output port of the trigger is connected to the corresponding trigger input interface on the device using a suitable wire. Good contact must be ensured during the connection to avoid signal transmission interruption or distortion due to poor contact. If it is an optical signal, a suitable optical transmission medium such as optical fiber is required for the connection. After completing the hardware connection, the preset signal trigger is initialized. The timing of trigger signal generation is set according to the test scenario. This can be time-based triggering, such as setting the trigger signal to be generated a specific number of seconds after the start of the test, or conditional triggering based on external events, such as the trigger generating a signal only when a sensor detects a specific physical quantity reaching a preset threshold. When the preset trigger conditions are met, the internal circuit of the preset signal trigger starts working, generating a target trigger signal according to the previously set parameters. This signal is shaped and amplified by the signal conditioning circuit inside the trigger to enhance the signal's stability and driving capability, ensuring that the signal maintains its characteristics during transmission. The generated target trigger signal is transmitted to the device under test through the connection line. The trigger receiving module on the device identifies and parses the signal. Once a trigger signal that meets the requirements is detected, the control system inside the device immediately responds, starts the preset test process, and begins recording relevant data or executing specific test actions, thereby completing the entire process of generating a target trigger signal based on the preset signal trigger and driving the device under test to perform the test.

[0036] Step S202: Distribute the target trigger signal to multiple measuring devices to synchronously trigger data acquisition from multiple measuring devices.

[0037] For example, after the target trigger signal is generated by a preset signal trigger, it needs to be distributed to each measuring device through a physical connection method (such as an equal-length cable, optical fiber, or dedicated signal bus). During the connection process, impedance matching and anti-interference design of the signal transmission path must be ensured to reduce signal attenuation, reflection, and external noise interference. At the same time, equal-length cables or precise compensation for transmission delay should be used to ensure that the time difference between the signal arrival at each measuring device is controlled within the nanosecond range or even smaller. In addition, corresponding signal conditioning and interface conversion modules need to be adapted to the trigger interface characteristics of different measuring devices (such as hardware trigger ports or software trigger interfaces). For devices that support direct hardware triggering, the signal can be directly connected to its physical trigger interface. For devices that require software triggering, the physical signal must be converted into software instructions that the device can recognize (such as trigger pulse to trigger interrupt or network message to trigger acquisition command) through a host computer or dedicated interface module. Finally, after receiving the synchronization trigger signal, each measuring device must immediately start the data acquisition process and use a built-in high-precision clock source or an external time synchronization module (such as PPS signal or IEEE 1588 protocol) to accurately timestamp the acquired data, ensuring that the first data point acquired by all devices corresponds to the same absolute moment in the physical world.

[0038] Step S203: Determine multiple valid test signals acquired by multiple measuring devices, and perform time-domain resampling processing on the multiple valid test signals to generate a test signal sequence on a unified time axis based on the multiple test signals after time-domain resampling.

[0039] For example, for the raw signals collected by each measuring device, valid test signals need to be determined through signal quality assessment. This process includes checking the integrity of the signal, the signal-to-noise ratio, and whether there is abnormal interference or missing data. For instance, threshold judgment can be used to exclude glitches caused by electromagnetic interference, or correlation analysis can be used to screen out valid data segments that highly match the actual operating state of the device under test, ensuring that the selected signals can truly reflect the physical characteristics of the test scenario. Subsequently, to address the issue of inconsistent signal time resolution caused by differences in sampling frequencies among different measuring devices, time-domain resampling processing is required. For signals with low sampling rates, new data points can be generated between the original sampling points using interpolation algorithms (such as linear interpolation, spline interpolation, or frequency-domain interpolation based on Fourier transform), improving their time resolution to a unified target frequency. For signals with high sampling rates, the number of data points is reduced through decimation operations (such as equal-interval decimation or downsampling based on anti-aliasing filtering) to avoid reducing subsequent processing efficiency due to excessive data volume, while ensuring that key information is not lost during the decimation process. During the resampling process, the time-domain characteristics of the signal must be strictly maintained to avoid signal distortion introduced by interpolation or decimation. Finally, by using timestamp alignment technology, all resampled signals are mapped onto a unified time axis. The arrival time of the synchronous trigger signal is taken as the absolute time zero point. Combined with the timestamp information of the data collected by each device, the time position of each signal point is adjusted to ensure that the first data point of all signals corresponds to the same physical time. Subsequent data points are arranged at a unified time interval, thus forming a test signal sequence that is strictly aligned in the time dimension.

[0040] Step S204: Determine the total delay of the device under test and the corresponding multi-level delay of the device under test based on the test signal sequence on a unified time axis.

[0041] For example, for a test signal sequence on a unified time axis, key event points in each signal need to be identified through feature extraction algorithms, such as the start time, peak time, and specific threshold crossover points of the signal. These event points serve as benchmarks for delay calculation to ensure the accuracy of subsequent analysis. Subsequently, time alignment technology is used to map the key event points in the signals collected by each measuring device onto a unified time axis. By comparing the time differences of corresponding event points in different signals, the signal transmission delay between different functional modules inside the device under test can be determined. For example, by comparing the start time difference between the input signal and the output signal, the total delay from receiving the input signal to generating an output response can be preliminarily estimated.

[0042] Optionally, to further refine the delay analysis, a multi-level delay model of the device under test needs to be constructed. The device is divided into several functional levels or modules (such as signal preprocessing layer, core processing layer, post-processing layer, etc.). For each level or module, key event points in its input and output signal sequences are extracted, and the signal transmission delay between levels is calculated, thus obtaining the delay distribution of the device at different functional levels. During the delay calculation process, the impact of factors such as the signal propagation path within the device, the complexity of the processing algorithm, and hardware characteristics on the delay needs to be considered. Statistical analysis or simulation modeling methods are used to correct and optimize the measured delay data to improve the accuracy and reliability of the delay calculation. Finally, based on the test signal sequence on a unified time axis and the constructed multi-level delay model, the total delay of the device under test and the specific delay of each functional module or level can be comprehensively determined, providing strong data support for device performance evaluation, optimization, and fault diagnosis.

[0043] In the embodiments provided in this application, a target trigger signal is generated and synchronously distributed to multiple measuring devices based on a preset signal trigger, thereby achieving precise synchronization of data acquisition. After time-domain resampling processing, a test signal sequence with a unified time axis is generated. Finally, the total delay of the device under test and its multi-level delay distribution can be accurately quantified, providing a highly reliable time synchronization measurement solution for device performance evaluation and optimization.

[0044] Based on the above embodiments, in one exemplary embodiment provided in this application, the specific implementation process of determining multiple valid test signals collected by multiple measuring devices may further include steps S301 and S302, which are described in detail below:

[0045] Step S301: Determine the unified time origin of multiple measuring devices based on the target trigger signal. The unified time origin includes the test signal acquisition time origin.

[0046] Step S302: Acquire multiple test signals collected by multiple measuring devices, and determine multiple valid test signals corresponding to the multiple test signals based on a unified time origin.

[0047] For example, after a target trigger signal is generated by a preset signal trigger, the signal is synchronously distributed to the trigger input ports of each measuring device via an equal-length cable or a synchronous transmission network. The physical time when the trigger signal arrives at each device is accurately recorded as a unified time origin (i.e., the test signal acquisition time origin). This origin serves as the time reference for all subsequent signals. Subsequently, each measuring device starts the data acquisition process. During continuous acquisition, the original test signal may contain invalid parts such as interference noise, missing data, or abnormal fluctuations. The original signal needs to be screened using signal quality assessment algorithms (such as signal-to-noise ratio threshold screening, outlier detection, or correlation verification) to remove invalid data segments caused by electromagnetic interference, equipment failure, or environmental disturbances, and retain valid test signals that can truly reflect the operating status of the device under test. During the screening process, the signal needs to be time-aligned in conjunction with the unified time origin. Using the arrival time of the trigger signal as the absolute zero point, a precise timestamp is assigned to each data point to ensure that the first valid data point collected by all measuring devices corresponds to the same physical time. Subsequent data points are arranged according to a uniform sampling interval, thereby mapping the test signals collected by each device onto a time axis with a unified time origin as the reference, and finally obtaining multiple valid test signals based on a unified time origin.

[0048] In the embodiments provided in this application, by establishing a unified time origin based on the target trigger signal, the test signal acquisition time of multiple measuring devices is strictly aligned, thereby accurately extracting the effective test signal with a unified time reference from the raw data, providing a highly consistent data foundation for subsequent time domain analysis and delay calculation.

[0049] Based on the above embodiments, in one exemplary embodiment provided in this application, the specific implementation process of performing time-domain resampling processing on multiple valid test signals to generate a test signal sequence on a unified time axis based on the multiple time-domain resampled test signals may further include steps S401 to S403, which are described in detail below:

[0050] Step S401: Determine multiple sampling frequencies corresponding to multiple measuring devices, and determine the common multiple of sampling frequencies;

[0051] Step S402: Based on the common multiple of sampling, determine the time-domain resampling process for multiple valid test signals to obtain multiple time-domain resampled valid test signals;

[0052] Step S403: Generate a test signal sequence on a unified time axis based on the valid test signals after multiple time-domain resampling.

[0053] For example, after determining multiple sampling frequencies corresponding to multiple measuring devices, the least common multiple of these frequencies can be calculated as a unified sampling reference frequency. For instance, if device A has a sampling frequency of 1kHz, device B has 2kHz, and device C has 1.5kHz, then their least common multiple is 6kHz. Subsequently, time-domain resampling processing is performed on the original sampling signals of each device. For signals with sampling rates lower than the least common multiple (such as 1kHz for device A), new data points are generated between the original sampling points using interpolation algorithms (such as linear interpolation, spline interpolation, or frequency-domain interpolation based on Fourier transform) to increase the sampling rate to 6kHz, while ensuring that the interpolation process does not introduce signal distortion. For signals with sampling rates higher than the least common multiple (such as 2kHz for device B), the number of data points is reduced to 6kHz through decimation operations (such as equal-interval decimation or downsampling after anti-aliasing filtering) to avoid data redundancy and preserve key signal characteristics. For sampling rates that are not integer multiples (such as 1.5kHz for device C), a hybrid operation of interpolation and decimation is required to achieve precise matching. During resampling, the temporal characteristics of the signals must be strictly maintained to ensure uniform temporal resolution across all signals. Finally, based on the aforementioned unified time origin (such as the physical time when the target trigger signal arrives at each device), all resampled signals are mapped onto a unified time axis referenced to this origin. Timestamp alignment technology ensures that the first valid data point of each signal corresponds to the same absolute time, and subsequent data points are arranged at a uniform sampling interval of 6kHz. This forms a strictly aligned test signal sequence in the time dimension, providing a precise time synchronization data foundation for subsequent delay analysis, performance evaluation, and system optimization.

[0054] In the embodiments provided in this application, by determining the common multiple of the sampling frequencies of multiple measuring devices and implementing time-domain resampling, test signals of different frequencies are unified to a high-precision time reference, and finally a seamlessly aligned test signal sequence is generated, providing highly consistent time-domain data support for cross-device delay analysis and dynamic characteristic research.

[0055] Based on the above embodiments, in one exemplary embodiment provided in this application, the specific implementation process of performing time-domain resampling processing on multiple test signals based on the least common multiple of sampling may further include steps S501 and S502, which are described in detail below:

[0056] Step S501: Determine the sliding window corresponding to the measuring device, and determine the signal characteristics corresponding to the measuring device based on the sliding window.

[0057] For example, when determining the sliding window corresponding to the measuring device, the window length, step size, and type need to be comprehensively set based on signal characteristics and test requirements. For instance, a rectangular window of fixed length can be selected based on the signal fluctuation frequency to capture transient changes, or an adaptively adjusted Hanning window can be used to suppress frequency domain leakage. The window length needs to balance time resolution and frequency domain resolution. Too short a window may lose low-frequency characteristics, while too long a window may blur transient details. The step size determines the time interval for window sliding and needs to be adjusted according to the signal change rate to avoid missing key information or accumulating redundant data. Then, when performing segment-by-segment analysis of the effective test signal based on the sliding window, the statistical characteristics of the signal within the window (such as the mean reflecting the signal baseline level, variance measuring the fluctuation amplitude, peak capturing the location of the maximum value, and rising edge slope quantifying the rate of change) or frequency domain characteristics (such as power spectral density revealing energy distribution and dominant frequency components identifying the dominant frequency) can be calculated. These characteristics can accurately characterize the signal's fluctuation characteristics, energy distribution, and changing trends at different time periods. For example, during the rapid rise phase of a signal, a high slope value within the window can indicate a steep change in the signal, while during the steady-state phase, a low variance value reflects the smooth state of the signal, thus providing a key basis for subsequent time-domain resampling strategy formulation or delay analysis.

[0058] Step S502: Determine the time-domain resampling strategy for the test signal corresponding to the measuring device based on the signal characteristics, and perform time-domain resampling processing on the valid test signal based on the time-domain resampling strategy.

[0059] For example, based on the above embodiments, the time-domain and frequency-domain characteristics of the signal are analyzed, such as the mean, variance, peak value, rising slope, power spectral density, and dominant frequency components extracted through a sliding window. These characteristics reveal the fluctuation amplitude, rate of change, energy distribution, and dominant frequency of the signal in different time periods, thereby guiding the formulation of resampling strategies. For signal segments with large variance, steep slope, or significant high-frequency components, a dense sampling point insertion strategy is adopted, such as generating new points between the original sampling points through cubic spline interpolation, to improve time resolution and accurately capture rapidly changing details, avoiding signal distortion caused by insufficient sampling rate. For signal segments with small variance, gentle slope, or predominantly low-frequency components, an appropriate sampling point extraction strategy is adopted, such as performing equal-interval downsampling after anti-aliasing filtering, reducing data redundancy while maintaining key signal information, and improving subsequent analysis efficiency.

[0060] Furthermore, the resampling strategy needs to dynamically adapt to changes in signal characteristics. For example, by monitoring the variance or spectral changes of the signal within the window in real time, the sampling rate can be automatically adjusted to ensure high resolution in areas where signal characteristics change drastically and to reduce the amount of data in stable areas. Finally, based on this strategy, the effective test signal is resampled in the time domain. Through precise control of interpolation and decimation, the balance between signal time resolution and data volume is achieved, ensuring that the resampled signal can not only fully retain the key features of the original signal, but also meet the accuracy and efficiency requirements of synchronous analysis by multiple devices.

[0061] In the embodiments provided in this application, by accurately extracting the signal features of the measuring device based on a sliding window and dynamically adapting to the time-domain resampling strategy, a personalized time-scale transformation of the effective test signal is realized. This generates a high-resolution and time-aligned unified signal sequence while retaining key features, providing a reliable data foundation for the time-domain collaborative analysis of complex systems.

[0062] Based on the above embodiments, in one exemplary embodiment provided in this application, the specific implementation process of determining the total delay of the device under test based on the test signal sequence on a unified time axis may further include steps S601 to S603, which are described in detail below:

[0063] Step S601: Determine the key event timestamps corresponding to the test signal sequence of multiple measuring devices on a unified time axis. The key event timestamps include the input excitation feature point timestamps and the output response feature point timestamps.

[0064] Step S602: Determine the end-to-end response delay of the device under test based on the timestamp of the output response feature point and the timestamp of the output excitation feature point;

[0065] Step S603: Determine the total delay of the device under test based on the response delay.

[0066] For example, when determining the key event timestamps of multiple measuring devices in a test signal sequence on a unified time axis, signal feature extraction algorithms such as peak detection, threshold cross-identification, or slope change analysis are needed to accurately locate the feature points of the input stimulus and output response. For instance, the start time of the input stimulus can be determined by detecting the moment when the signal first exceeds a preset threshold, and the peak time is obtained by finding the maximum value point or local extremum point of the signal. The feature points of the output response are extracted using a similar method. For example, the start time of the response corresponds to the moment when the signal deviates significantly from the baseline, and the peak time reflects the position of the maximum amplitude of the response. The timestamps of these feature points are accurately recorded as key event timestamps on a unified time axis.

[0067] Subsequently, the end-to-end response delay is calculated based on the timestamps of the output response feature points and the corresponding input stimulus feature points. Specifically, the timestamp of the input stimulus start time is subtracted from the timestamp of the output response start time to obtain the direct time difference from the application of the input stimulus to the start of the output response. This difference is the end-to-end response delay, reflecting the overall delay characteristics of the device under test from receiving the input signal to generating the output response. Finally, the total delay of the device under test is determined based on the calculated response delay. Since the end-to-end response delay integrates the delay of the entire process of signal transmission, processing, and response generation within the device, the total delay can be directly characterized by this response delay, or the stability and reliability of the total delay can be further quantified by statistically analyzing parameters such as the average and maximum response delays over multiple test cycles. This provides an accurate quantitative basis for device performance evaluation, delay optimization, and fault diagnosis.

[0068] In the embodiments provided in this application, by accurately extracting the key event timestamps of input stimulus and output response under a unified time axis, and quantifying the end-to-end response delay based on the difference between the two, the accurate measurement of the total delay of the device under test and the dynamic characteristic analysis are finally realized, providing a high-confidence time synchronization quantification basis for system performance evaluation and optimization.

[0069] Based on the above embodiments, in one exemplary embodiment provided in this application, the specific implementation process of the above device delay determination method may further include steps S701 and S702, which are described in detail below:

[0070] Step S701: If the test signal sequence on the unified time axis is a series signal chain, then determine the transmission delay between any two measuring devices based on the key event timestamp.

[0071] Step S702: Determine the multi-level delay of the device under test based on the transmission delay, and generate a corresponding visual delay analysis report based on the multi-level delay.

[0072] For example, in a scenario where the test signal sequence on a unified time axis is a series signal chain, the transmission delay between any two measuring devices can be determined. This can be achieved by accurately calculating the time difference using key event timestamps such as the input excitation feature point timestamp and the output response feature point timestamp. Specifically, for the signal sequences of adjacent measuring devices, the output response feature point timestamps of the preceding device (such as the signal peak time or a specific threshold crossover point) and the input excitation feature point timestamps of the following device (such as the signal start time or the rising edge start time) are extracted. Then, by calculating the difference between the subsequent input excitation timestamp and the preceding output response timestamp, the signal transmission delay between the two devices is obtained. This delay reflects the time delay characteristics of the signal along the transmission path between the devices.

[0073] Optionally, based on the quantitative results of the transmission delay between various devices, and combined with the internal structure or functional module division of the device under test, the total delay can be decomposed into multi-level delays. For example, if the device consists of a signal preprocessing layer, a core processing layer, and a post-processing layer connected in series, the specific delay contribution of each functional layer can be determined by accumulating the transmission delays of measurement devices between adjacent layers, thereby obtaining the multi-level delay distribution of the device on the signal processing link. Finally, a visualized delay analysis report is generated based on the quantitative data of multi-level delays. This report should include the statistical characteristics of the delay data (such as average, maximum, and minimum values), the delay distribution trend (such as the change law with time or signal strength), and the visualization of key delay nodes. The visualization content includes, for example, comparing the delay ratio of each level through bar charts, showing the change of delay along the signal chain transmission path through line charts, and presenting the transmission delay intensity between different modules through heat maps. In this way, through the intuitive combination of charts and data, clear quantitative basis and visualization support are provided for device performance optimization, fault location, and delay characteristic analysis.

[0074] Optionally, in some feasible embodiments, taking a robot collaborative operation scenario as an example, a unified time origin can be established through hardware synchronization trigger signals (such as pulse signals when the master control device sends commands) to ensure strict alignment of the time bases of the master and slave devices. Subsequently, the command signals of the master control device (such as PWM control signals, CAN bus commands) and the execution status signals of the slave actuators (such as motor current, joint angles, and end-effector position feedback) are synchronously acquired, and key event timestamps are extracted using sliding window analysis. For command signals, the command start time is determined by threshold cross-detection (such as the voltage first exceeding the static friction threshold), and the command peak time is located by peak detection. For execution signals, the moment when the actuator begins to move is captured by slope change analysis (such as the sudden change point of velocity from zero to non-zero), and the execution completion time is determined by error threshold judgment (such as the position error being less than a set value).

[0075] Next, the difference between the timestamp of the key event in the execution signal and the corresponding timestamp of the instruction signal is calculated to obtain the response delay of a single instruction. Furthermore, to improve accuracy, multiple tests are conducted, and the average, maximum, minimum, and standard deviation of the delay are statistically analyzed to identify sources of delay fluctuations (such as communication delay, mechanical inertia, and control algorithm execution time). Finally, considering the hierarchical structure of the robot system (such as the communication layer, control layer, and drive layer), the total delay is decomposed into multi-level delays. Specifically, the communication layer delay is determined by the time difference between instruction transmission between the master and slave devices; the control layer delay is analyzed by the time difference between the generation of the master device instruction and the initiation of the slave device control algorithm; and the drive layer delay is quantified by the time difference between the output of the slave device control signal and the action of the actuator. Ultimately, a visual analysis report containing the delay distribution of each level is generated, providing accurate quantitative evidence for performance optimization and fault diagnosis in robot collaborative operations.

[0076] In the embodiments provided in this application, the transmission delay between any two measuring devices is accurately calculated based on the timestamps of key events in the serial signal chain, and a multi-level delay model is constructed by decomposing it layer by layer, and finally a visual analysis report is generated, thus realizing the full-link transparent analysis of the timing characteristics of complex systems.

[0077] Based on the above embodiments, in one exemplary embodiment provided in this application, the specific implementation process of the above device delay determination method may further include steps S801 and S802, which are described in detail below:

[0078] Step S801: If the measuring device includes a hardware interface, then the target trigger signal is distributed by connecting to the hardware interface based on a preset distributor.

[0079] For example, if the measuring device includes a hardware interface, a physical or logical connection must be established with the hardware interface through a preset distributor to distribute the target trigger signal. Specifically, an appropriate connection method should be selected based on the type of the measuring device's hardware interface (such as GPIO, serial port, Ethernet interface, or dedicated bus interface). For example, a direct cable connection or an interface conversion module can be used to ensure compatibility between the distributor and the hardware interfaces of each measuring device. Secondly, the signal generation parameters of the preset distributor should be configured, including the type of trigger signal (such as level trigger, edge trigger, pulse sequence, or specific coded signal), frequency, amplitude, and duration, to ensure that the trigger signal meets the triggering conditions of the measuring device. Next, the target trigger signal is transmitted in parallel or serially to the hardware interface of each measuring device through the distributor's signal output channel. Signal integrity must be considered during transmission; for example, impedance matching, shielded cables, or signal amplifiers can be used to reduce signal attenuation and interference.

[0080] In step S802, if the measuring device does not include a hardware interface, the communication protocol corresponding to the measuring device is determined, and the target trigger signal is converted into a control command based on the communication protocol, so as to send the control command to the measuring device.

[0081] For example, if the measuring device does not include a hardware interface, the supported communication protocol type (such as TCP / IP, UDP, Modbus, CAN bus, SPI, I2C, or proprietary protocol) must first be identified through device documentation, protocol analysis tools, or known communication behavior. Then, based on the characteristics of the target trigger signal (such as level change pattern, pulse sequence characteristics, or specific encoding format), it is converted into a control command conforming to that protocol format. For instance, if the protocol is Modbus RTU, the start or stop condition of the trigger signal needs to be mapped to a combination of function code and register address, and a CRC checksum needs to be added. If the protocol is TCP / IP, the signal needs to be converted into a byte stream containing a specific command identifier, parameter values, and checksum, and sent via socket communication. Furthermore, during command transmission, a reliable communication connection must be established, correct network parameters (such as IP address and port number) or bus parameters (such as baud rate and slave address) must be configured, and synchronization mechanisms (such as timestamps and handshake signals) must be used to ensure that the command arrives at the measuring device within the correct time window. Finally, the control command is confirmed to have successfully triggered the expected action through response feedback from the measuring device, such as status register updates, response signal returns, or execution result verification. This enables remote transmission and precise control of the target trigger signal without a hardware interface, providing a flexible and reliable signal distribution solution for multi-device collaborative work or distributed measurement systems.

[0082] In the embodiments provided in this application, by adopting a flexible triggering method of direct connection to a preset distributor or communication protocol conversion for measurement devices with or without hardware interfaces, the seamless adaptation and accurate synchronous distribution of the target trigger signal in the heterogeneous measurement system are realized, providing a highly compatible signal triggering solution for multi-device collaborative testing.

[0083] Please see Figure 3 , Figure 3 Flowchart of the device delay determination method provided in this application Figure 2 ,like Figure 3As shown, during the testing process of the device under test, a target trigger signal is generated based on a preset signal trigger; the target trigger signal is distributed to multiple measuring devices to synchronously trigger data acquisition by the multiple measuring devices; multiple test signals acquired by the multiple measuring devices are acquired, and multiple valid test signals corresponding to the multiple test signals are determined based on a unified time origin. Multiple acquisition frequencies corresponding to the multiple measuring devices are determined, and the common multiple of the sampling frequencies is determined; based on the common multiple of the sampling, time-domain resampling processing is performed on the multiple valid test signals to obtain multiple time-domain resampled valid test signals; a test signal sequence on a unified time axis is generated based on the multiple time-domain resampled valid test signals. Key event timestamps corresponding to the multiple measuring devices in the test signal sequence on the unified time axis are determined, including input excitation feature point timestamps and output response feature point timestamps; the end-to-end response delay corresponding to the device under test is determined based on the output response feature point timestamps and the output excitation feature point timestamps; the total delay of the device under test is determined based on the response delay. For detailed implementation processes, please refer to the descriptions in the aforementioned embodiments, which will not be repeated here.

[0084] Figure 4 A schematic diagram of the device delay determination apparatus provided in this application is shown below. Figure 4 As shown, the device delay determination device 40 provided in this embodiment includes: a trigger module 410, used to generate a target trigger signal based on a preset signal trigger during the testing process of the device under test; a distribution module 420, used to distribute the target trigger signal to multiple measuring devices to synchronously trigger the data acquisition of multiple measuring devices; an alignment module 430, used to determine multiple valid test signals acquired by multiple measuring devices, and perform time-domain resampling processing on the multiple valid test signals to generate a test signal sequence on a unified time axis based on the multiple test signals after time-domain resampling; and a determination module 440, used to determine the total delay of the device under test and the multi-level delay corresponding to the device under test based on the test signal sequence on the unified time axis.

[0085] In one possible implementation, the alignment module 430 is further configured to: determine a unified time origin for multiple measuring devices based on a target trigger signal, the unified time origin including a test signal acquisition time origin; acquire multiple test signals acquired by multiple measuring devices; and determine multiple valid test signals corresponding to the multiple test signals based on the unified time origin.

[0086] In one possible implementation, the alignment module 430 is further configured to: determine multiple acquisition frequencies corresponding to multiple measurement devices, and determine the common multiple of sampling frequencies; determine time-domain resampling processing of multiple valid test signals based on the common multiple of sampling to obtain multiple time-domain resampled valid test signals; and generate a test signal sequence on a unified time axis based on the multiple time-domain resampled valid test signals.

[0087] In one possible implementation, the alignment module 430 is further configured to: determine a sliding window corresponding to the measuring device, and determine the signal characteristics corresponding to the measuring device based on the sliding window; determine the time-domain resampling strategy of the test signal corresponding to the measuring device based on the signal characteristics, and perform time-domain resampling processing on the valid test signal based on the time-domain resampling strategy.

[0088] In one possible implementation, the determining module 440 is further configured to: determine key event timestamps corresponding to multiple measuring devices in a test signal sequence on a unified time axis, the key event timestamps including input excitation feature point timestamps and output response feature point timestamps; determine the end-to-end response delay corresponding to the device under test based on the output response feature point timestamps and the output excitation feature point timestamps; and determine the total delay of the device under test based on the response delay.

[0089] In one possible implementation, the determination module 440 is further configured to: if the test signal sequence on the unified time axis is a series signal chain, determine the transmission delay between any two measuring devices based on the key event timestamp; determine the multi-level delay of the device under test based on the transmission delay; and generate a corresponding visual delay analysis report based on the multi-level delay.

[0090] In one possible implementation, the distribution module 420 is further configured to: if the measuring device includes a hardware interface, connect to the hardware interface based on a preset distributor to distribute the target trigger signal; if the measuring device does not include a hardware interface, determine the communication protocol corresponding to the measuring device, and convert the target trigger signal into a control command based on the communication protocol to send the control command to the measuring device.

[0091] The device delay determination device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0092] Figure 5 A schematic diagram of the structure of the electronic device provided in this application. Figure 5 As shown, the electronic device 50 provided in this embodiment includes at least one processor 510 and a memory 520. Optionally, the device 50 further includes a communication component 530. The processor 510, memory 520, and communication component 530 are connected via a bus 540.

[0093] In a specific implementation, at least one processor 510 executes computer execution instructions stored in memory 520, causing at least one processor 510 to perform the above-described method.

[0094] The specific implementation process of processor 510 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0095] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0096] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0097] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0098] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0099] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0100] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0101] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0102] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0103] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0104] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0105] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0106] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0107] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method of device latency determination, the method comprising: The method comprises: generating a target trigger signal based on a preset signal trigger during a test process of a device to be tested; distributing the target trigger signal to a plurality of measuring devices to synchronously trigger data acquisition of the plurality of measuring devices; determining a plurality of effective test signals collected by the plurality of measuring devices, and performing time domain resampling processing on the plurality of effective test signals to generate a test signal sequence on a unified time axis based on the plurality of test signals after time domain resampling; determining a total delay of the device to be tested and a multi-level delay corresponding to the device to be tested based on the test signal sequence on the unified time axis.

2. The method of claim 1, wherein, The determining of the plurality of effective test signals collected by the plurality of measuring devices comprises: determining a unified time origin of the plurality of measuring devices based on the target trigger signal, the unified time origin comprising a test signal acquisition time origin; acquiring a plurality of test signals collected by the plurality of measuring devices, and determining a plurality of effective test signals corresponding to the plurality of test signals based on the unified time origin.

3. The method of claim 1, wherein, The time domain resampling processing on the plurality of effective test signals to generate the test signal sequence on the unified time axis based on the plurality of test signals after time domain resampling comprises: determining a plurality of acquisition frequencies corresponding to the plurality of measuring devices, and determining a sampling common multiple corresponding to the plurality of acquisition frequencies; determining the time domain resampling processing on the plurality of effective test signals based on the sampling common multiple to obtain a plurality of effective test signals after time domain resampling; generating the test signal sequence on the unified time axis based on the plurality of effective test signals after time domain resampling.

4. The method of claim 3, wherein, The time domain resampling processing on the plurality of test signals based on the sampling common multiple comprises: determining a sliding window corresponding to the measuring device, and determining a signal feature corresponding to the measuring device based on the sliding window; determining a time domain resampling strategy of the test signal corresponding to the measuring device based on the signal feature, and performing the time domain resampling processing on the effective test signal based on the time domain resampling strategy.

5. The method according to any one of claims 1 to 4, characterized in that, The determination of the total delay of the device to be tested based on the test signal sequence on the unified time axis comprises: determining a key event timestamp corresponding to the measuring device in the test signal sequence on the unified time axis, the key event timestamp comprising an input excitation feature point timestamp and an output response feature point timestamp; determining a response delay of an end-to-end corresponding to the device to be tested based on the output response feature point timestamp and the output excitation feature point timestamp; determining the total delay of the device to be tested based on the response delay.

6. The method of claim 5, wherein, The method further comprises: if the test signal sequence on the unified time axis is a signal chain in series, determining a transmission delay between any two measuring devices based on the key event timestamp; determining a multi-level delay of the device to be tested based on the transmission delay, and generating a corresponding visual delay analysis report based on the multi-level delay.

7. The method according to any one of claims 1 to 4, wherein The method further comprises: if the measuring device comprises a hardware interface, connecting a preset distributor to the hardware interface to distribute the target trigger signal; If the measuring device does not include a hardware interface, a communication protocol corresponding to the measuring device is determined, and the target trigger signal is converted into a control instruction based on the communication protocol, so as to send the control instruction to the measuring device.

8. An apparatus delay determination device, comprising: The method comprises the steps of: generating a target trigger signal based on a preset signal trigger during a test process of a device to be tested; distributing the target trigger signal to a plurality of measuring devices to synchronously trigger data collection of the plurality of measuring devices; determining a plurality of valid test signals collected by the plurality of measuring devices, and performing time domain resampling processing on the plurality of valid test signals to generate a test signal sequence on a unified time axis based on the plurality of test signals after time domain resampling; determining a total delay of the device to be tested and a plurality of levels of delays corresponding to the device to be tested based on the test signal sequence on the unified time axis.

9. An electronic device, comprising: The method comprises the steps of: a memory and a processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory, so that the processor executes the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement the method according to any one of claims 1 to 7.

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