Power semiconductor device, gate commutated thyristor chip and thyristor

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and discloses a power semiconductor device, a gate commutated thyristor chip and a thyristor. The power semiconductor device comprises: an N-base region; the first stacking structure is located on the first surface of the N-base region and comprises an N + + emitter region, a P base region and a P + base region, and the P base region and the P + base region are sequentially stacked on the first surface; the gate metal layer is located on the P + base region and connected with the P + base region; the cathode metal layer is located on the N + + emitter region and connected with the N + + emitter region; the isolation groove is located between the P + base region and the N + + emitter region, and the isolation groove surrounds the N + + emitter region and does not surround the P + base region. According to the power semiconductor device provided by the invention, the core contradiction that the on-state loss and the turn-off capability cannot be considered at the same time in the prior art is broken, and the problem of balancing the on-state loss and the turn-off capability is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power semiconductor device, a gate-commutated thyristor chip, and a thyristor. Background Technology

[0002] IGCT is an abbreviation for Integrated Gate-Commutated Thyristor, a semiconductor device specifically designed for medium- and high-voltage, high-power power electronics applications. As a core component of power devices, the loss characteristics of the gate-commutated thyristor chip (GCT) are closely related to the energy transfer efficiency of the power device.

[0003] Existing trench-type GCTs suffer from a core contradiction stemming from the strong binding between trench structural parameters and performance parameters, resulting in an inability to simultaneously address on-state losses and turn-off capabilities, thus limiting improvements in turn-off capability. Summary of the Invention

[0004] The purpose of this application is to provide at least one power semiconductor device, gate-commutated thyristor chip and thyristor, which can at least solve the core contradiction of the inability to balance on-state loss and turn-off capability, and improve turn-off capability.

[0005] To address the aforementioned technical problems, at least one embodiment of this application provides a power semiconductor device, comprising: N-base region; A first stacked structure is located on the first surface of the N-base region. The first stacked structure includes an N++ emitter region and a P-base region and a P+ base region stacked sequentially on the first surface. A gate metal layer is located on the P+ base region and is connected to the P+ base region; A cathode metal layer is located on and connected to the N++ emission region; An isolation trench is located between the P+ base region and the N++ emitter region, the isolation trench surrounds the N++ emitter region but does not surround the P+ base region.

[0006] In some alternative embodiments, the contact surface between the N++ emitter region and the cathode metal layer is coplanar with the contact surface between the P+ base region and the gate metal layer.

[0007] In some alternative embodiments, the depth of the isolation trench is 0.8 to 1.3 times the junction depth of the N++ emitter region.

[0008] In some alternative embodiments, a passivation layer is also included, which at least covers the surface of the isolation trench.

[0009] In some alternative embodiments, a second stacked structure and an anode metal layer are further included, the second stacked structure and the anode metal layer being stacked sequentially in a direction away from the second surface of the N-base region, the first surface and the second surface being opposite to each other.

[0010] In some alternative embodiments, the second stacked structure includes an N-buffer layer and a P+ transparent anode emission region sequentially located away from the second surface; or, the second stacked structure includes a P emission region and a P+ anode emission region sequentially located away from the second surface.

[0011] In some alternative embodiments, the P-base region has a protruding structure on the contact surface with the N-base region, the protruding structure protruding toward the N++ emitter region and located in the region below the N++ emitter region.

[0012] At least one embodiment of this application also provides a gate-commutated thyristor chip, including the power semiconductor device described above.

[0013] At least one embodiment of this application also provides a thyristor, characterized in that it includes the gate-commutated thyristor chip described above.

[0014] In some alternative embodiments, the thyristor further includes a fast recovery diode chip, wherein the gate-commutated thyristor chip and the fast recovery diode chip are connected in anti-parallel.

[0015] The power semiconductor device, gate-commutated thyristor chip, and thyristor provided in the embodiments of this application have an annular isolation trench between the P+ base region and the N++ emitter region. Compared with the trench-type GCT device of the prior art, the isolation trench only surrounds the N++ emitter region but not the P+ base region. At this time, the carrier injection efficiency and transmission efficiency during the operation of the GCT are no longer determined by the concentration of the P+ base region, but are dominated by the size of the isolation trench, such as the depth and width. This achieves the decoupling of the current gain α2 of the npn transistor T2 and the current gain α1 of the pnp transistor T1 from the parameters of the P+ base region, breaking the core contradiction of the prior art that the on-state loss and turn-off capability cannot be taken into account, and effectively improving the turn-off capability of the device. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 This is a schematic diagram of the structure of a trench-type GCT device in the prior art; Figure 2This is a schematic diagram of the relationship between the trench and the gate and emitter in a trench-type GCT device in the prior art; Figure 3 This is a schematic diagram of the structure of a power semiconductor device according to an embodiment of this application; Figure 4 This is a schematic diagram of the structural relationship between the isolation trench and the N++ emitter region and the P+ base region in a power semiconductor device according to an embodiment of this application; Figure 5 This is a structural schematic diagram of the cross-sectional shape of an isolation trench in a power semiconductor device according to another embodiment of this application; Figure 6 This is a structural schematic diagram of the cross-sectional shape of an isolation trench in a power semiconductor device according to another embodiment of this application; Figure 7 This is a schematic diagram of the structure of a power semiconductor device according to an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a power semiconductor device according to another embodiment of this application; Figures 9-10 This is a schematic diagram illustrating the influence of the isolation width and isolation depth of the isolation trench of a power semiconductor device on its turn-off capability according to another embodiment of this application; Figure 11 This is a schematic diagram of the structure of a power semiconductor device according to another embodiment of this application; Figure 12 This is a schematic diagram of the structure of a power semiconductor device according to another embodiment of this application; Figure 13 This is a schematic diagram of the structure of a thyristor provided according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0019] To facilitate understanding of the embodiments of this application, relevant information about existing trench-type GCT devices will be introduced first.

[0020] like Figure 1As shown, an exemplary structural schematic diagram of a conventional trench-type GCT device is illustrated. The main vertical structure comprises a PNPN four-layer structure, equivalent to a positive feedback combination of "pnp transistor (T1) and npn transistor (T2)". The conduction of the GCT (or IGCT chip) depends on the pnp transistor (anode side P region → N). - Base region → P-base region) and npn transistor (N + Cathode → P-based region → N - The positive feedback of the base region (i.e., the current gain α1 of pnp transistor T1 + the current gain α2 of npn transistor T2 > 1). Based on the degree of doping, it can be further subdivided from bottom to top into P+, N′, N... The six regions, P, P+, and N+, correspond to the P+ anode emitter region, the N′ buffer layer, and the N′ emissive layer, respectively. The device consists of a base region, a P-base region, a P+ short base region, and an N+ emitter region (also known as a cathode comb). It is evident that the GCT device contains three PN junctions, which, from the anode to the cathode, are the J1 junction (anode transparent junction), the J2 junction (blocking voltage main junction), and the J3 junction (gate cathode junction).

[0021] For grooved GCTs, such as Figure 1 and Figure 2 As shown, trench 10' surrounds the P+ short base region and the N+ emitter region, so that the cathode 30' and the gate 20' form a step 40' through trench 10'. Since trench 10' surrounding the gate 20' is formed by the P+ short base region, the isolation between the gate 20' and the cathode 30' depends on the P+ short base region (gate side) and the depth of trench 10'. These two parameters directly determine the current gain α2 of the npn transistor (T2).

[0022] Specifically, when the concentration of P+ in the short base region is high (e.g., greater than 1e), 18 cm -3 When the trench depth is shallow (10'), the current gain α2 of the npn transistor T2 decreases, the conduction loss increases, and the turn-off capability decreases. Specifically, for example... Figure 1As shown, the P+ short base region is the core region of the gate, adjacent to the N+ emitter region on the cathode side. The N+ emitter region is the emitter of the npn transistor T2. If the concentration of the P+ short base region is high, when the N+ emitter region injects electrons into the P base region (T2 emits carriers), the electrons will be largely recombinated by the high concentration of holes in the P+ short base region (more holes → easier for electrons to collide and disappear), resulting in a significant decrease in the "emission efficiency" of the N+ emitter region. If the trench is shallow, and the trench is the isolation region between the gate and the cathode, a shallow trench means a thin effective thickness of the P base region, and the electrons will travel a shorter distance in the P base region, which will also increase the recombination probability and further reduce the N+ emission efficiency. The low N+ emission efficiency will lead to a decrease in the current gain α2 of the npn transistor T2 (α2 = emission efficiency × base region transfer coefficient). When the GCT is turned on, a positive feedback of α1 + α2 > 1 needs to be maintained. After the current gain α2 of the npn transistor T2 decreases, a higher anode-cathode forward voltage V is required. AK This is necessary to compensate for the insufficient carriers, which leads to through-state losses (P=V). AK ×I A I A The current gain α2 of the npn transistor T2 increases significantly. When the gate injects reverse current (turn-off command) to extract carriers from the P-base region, the npn transistor T2 will quickly exit the conduction state, resulting in a sharp decrease in the number of carriers between the gate and cathode, a sudden increase in the local electric field strength, and a tendency to induce a positive anode-cathode voltage V. GK Avalanche (gate-cathode voltage breakdown); at the same time, the decrease in the current gain α2 of the npn transistor T2 will cause the positive feedback to break prematurely, the carriers will not be completely extracted, and the residual carriers will easily lead to "re-triggering". Therefore, the turn-off capability is greatly reduced.

[0023] For example, when the concentration of P+ in the short base region is low (e.g., less than 2e), 17 cm -3 When the trench depth is 10', the current gain α2 of the npn transistor T2 increases, the conduction loss decreases, and the turn-off capability decreases significantly. This process is the opposite of the above: a low concentration in the P+ short base region results in a low hole concentration, leading to less recombination of electrons injected into the N+ emitter region, thus increasing emission efficiency; a deep trench means a thicker effective P-base region, resulting in a longer electron transport distance and a lower recombination probability, further improving emission efficiency. High N+ emission efficiency leads to a significant increase in the current gain α2 of the npn transistor T2. When the current gain α2 of the npn transistor T2 is high, α1+α2 more easily satisfies the conduction condition greater than 1, requiring V... AKThe low current gain (α2) optimizes conduction losses. However, it leads to severely insufficient turn-off capability. This is because the core of turn-off is breaking the positive feedback where α1+α2>1. A high current gain (α2) in the npn transistor T2 means stronger positive feedback (α1+α2 is closer to or even exceeds 1), requiring a larger reverse current injection at the gate to pump out the carriers from the P-base region. Especially at high temperatures, the increased temperature prolongs carrier lifetime (slower carrier recombination), further increasing α1 and α2 (the current gain (α1) of the pnp transistor T1 also increases due to the longer carrier lifetime). The gate reverse current is insufficient to quickly pump out the carriers, making it difficult to break the positive feedback. The device cannot quickly exit the conduction state, resulting in "difficulty in high-temperature hard-drive turn-off" or even turn-off failure. Therefore, as... Figure 2 As shown, the trench 10' of the existing trench-type GCT is a shared isolation structure between the gate 20' and the cathode 30'. The depth of the trench 10' simultaneously affects the thickness of the P-base region and the boundary of the N+ emitter region (forming a step). Therefore, the existing trench-type GCT cannot resolve the above contradiction by adjusting the turn-off capability through the above two methods.

[0024] To address the aforementioned technical problems, this application proposes a power semiconductor device that utilizes an annular isolation trench surrounding only the N++ emitter. This fundamentally breaks the core contradiction in existing trench-type GCTs where the P+ short base region parameters are strongly bound to the current gain α2 of the npn transistor T2. It achieves independent control of the current gain α1 of the pnp transistor T1 and the current gain α2 of the npn transistor T2, resolving the core contradiction of the inability to balance conduction loss and turn-off capability, thereby solving the problem of balancing conduction loss and turn-off capability.

[0025] Example 1: The embodiments of this application relate to a power semiconductor device. The implementation details of the power semiconductor device of this embodiment are described in detail below. The following implementation details are provided for ease of understanding and are not necessary for implementing this solution.

[0026] like Figure 3 As shown, an embodiment of this application provides a power semiconductor device, which can be a GCT device, and the power semiconductor device includes: N-base region 100; a first stacked structure 200 located on the first surface of the N-base region 100, the first stacked structure 200 including an N++ emitter region 230 and a P-base region 210 and a P+ base region 220 sequentially stacked on the first surface; a gate metal layer 400 located on and connected to the P+ base region 220; a cathode metal layer 500 located on and connected to the N++ emitter region 230; an isolation trench 600 located between the P+ base region 220 and the N++ emitter region 230, the isolation trench 600 surrounding the N++ emitter region 230 but not surrounding the P+ base region 220.

[0027] Specifically, the N-base region 100 can be an N-substrate, and its doping concentration and width depend on the blocking voltage design. A first stacked structure 200 is present on the first surface of the N-base region 100. The first stacked structure 200 is composed of a P-base region 210 and a P+ base region 220 sequentially stacked on the first surface of the N-base region 100. An N++ emitter region 230 (cathode comb) is also disposed within the P+ base region 220. A cathode metal layer 500 is disposed on the N++ emitter region 230, and a gate metal layer 400 is disposed on the P+ base region 220. The P+ base region 220 is led out through the gate metal layer 400. The total thickness of the gate metal layer 400, Wg, can be lower than the total thickness of the cathode metal layer 500, Wk, where Wk-Wg≥10μm, facilitating the isolation and lead-out of the gate and cathode, allowing them to be wired separately and not interfere with each other.

[0028] In one embodiment, the gate metal layer 400 and the cathode metal layer 500 are typically formed by one or more layers stacked together.

[0029] In this embodiment, such as Figure 4 As shown, an annular isolation trench 600 is provided between the P+ base region 220 and the N++ emitter region 230. Compared with the trench-type GCT devices of the prior art, the isolation trench 600 in this embodiment only surrounds the N++ emitter region 230, but not the P+ base region 220. This is equivalent to adding a "physical isolation band" between the N++ emitter region 230 (the emitter of T2) and the P+ base region 220 (the base of T2). Electrons must "cross" this trench to enter the P+ base region 210 from the N++ emitter region 230. At this time, the electron injection efficiency and transport efficiency are no longer determined by the concentration of the P+ base region 220, but are dominated by the dimensions of the isolation trench 600, such as its width and depth. The width and depth of the isolation trench 600 can be designed independently and do not depend on the concentration of the P+ base region 220.

[0030] Specifically, the size of the isolation trench 600 directly controls the amount of electrons injected from the N++ emitter region 230 to the P base region 210 (the source of carriers for T2). If the isolation trench 600 is wide or deep, electrons need to travel a longer distance from the N++ emitter region 230 to the P base region 210. During this journey, the probability of electron-hole recombination is high, so the amount of electron injection will decrease, resulting in low injection efficiency. This reduces the current gain α2 of the npn transistor T2, which is beneficial for turn-off. When the isolation trench 600 is narrow or shallow, the distance electrons travel from the N++ emitter region 230 to the P base region 210 is short, and the probability of electron-hole recombination is low. This increases the amount of electron injection, resulting in high injection efficiency. This increases the current gain α2 of the npn transistor T2, which is beneficial for reducing conduction losses. The above regulation is achieved entirely by changing the structural size of the isolation trench 600 and is independent of the concentration of the P+ base region 220. The concentration of the P+ base region 220 can be independently optimized to control the current gain α1 of the pnp transistor T1. This is like adding a controllable "gate" between the "emitter" and the "base". The size of the isolation trench 600 structure directly controls the current gain α1 of the pnp transistor T1 and the current gain α2 of the npn transistor T2, without depending on the doping concentration of the P+ base 220 and the width of the base region.

[0031] Compared to existing trench-type GCTs, the power semiconductor device provided in this embodiment, where the electron emission efficiency from the N+ emitter region to the P-base region 210 and the electron transport factor (base region transport coefficient) in the P-base region 210 are entirely determined by the concentration and width of the P+ short base region / P+ base region, this embodiment transfers the control of the current gain α2 of the npn transistor T2 from the structural parameters dependent on the P+ short base region / P-base region to independent trench structural parameters, thus achieving decoupling of the current gain α2 of the npn transistor T2 from the parameters of the P+ base region 220.

[0032] In the power semiconductor device provided in this embodiment, the current gain α2 of the npn transistor T2 is independently adjustable by the size of the isolation trench 600. The concentration of the P+ base region 220 only needs to focus on optimizing its gate contact performance, such as reducing contact resistance and improving drive signal response speed. At the same time, the concentration of the P+ base region 220, as the base edge of the pnp transistor T1, can independently optimize the current gain α1 of the pnp transistor T1. For example, by adjusting the concentration and width of the P+ base region 220, the hole injection efficiency of the pnp transistor T1 can be controlled, achieving precise control of the current gain α1 of the pnp transistor T1, without having to worry about compromises in the design of the current gain α2 of the npn transistor T2. In this way, the P+ base region 220 controls the current gain α1 of the pnp transistor T1, and the isolation trench 600 controls the current gain α2 of the npn transistor T2. Each performs its own function and no longer interferes with the other.

[0033] In this embodiment, the annular isolation trench 600 is an "independent isolation structure" that surrounds only the N++ emitter region (cathode) and does not affect the contact distance between the P+ base region 220 and the gate (the gate metal layer 400 directly covers the P+ base region 220), ensuring efficient transmission of the gate drive signal and reverse current. The depth and width of the isolation trench 600 are designed solely for the electron injection path of the N++ emitter region 230, completely decoupled from parameters such as the thickness of the P base region 210 and the gate contact performance. Therefore, this "partitioned isolation" design physically severs the chain reaction between various design parameters, allowing each structural parameter to independently serve its target performance. Specifically, the P+ base region 220 controls the current gain α1 of the pnp transistor T1, and the isolation trench 600 controls the current gain α2 of the npn transistor T2, breaking the core contradiction in existing technologies where conduction loss and turn-off capability cannot be simultaneously addressed, effectively improving turn-off capability.

[0034] In one embodiment, the doping concentration of the N++ emitter region 230 can be 1E22~5E17 cm⁻¹. -3 Its junction depth ranges from approximately 10 μm to 40 μm.

[0035] In one embodiment, the peak doping concentration of the P-base region 210 can be 2E16~1E13 cm⁻¹. -3 The depth of the P-base region 210 can be 20μm to 200μm, depending on the trade-off design of device characteristics such as blocking voltage and reverse loss.

[0036] In one embodiment, such as Figure 4 As shown, the isolation width W of the isolation trench 600 ranges from 10μm to 80μm.

[0037] In one embodiment, such as Figure 5 and Figure 6 As shown, the cross-sectional shape of the isolation trench 600 can be a "U" shape or a "U"-shaped polygon.

[0038] In one embodiment, such as Figure 3 and Figure 7 As shown, the depth of the isolation trench 600 is 0.6 to 1.3 times the junction depth of the N++ emitter region 230, such as 0.7, 0.8, 1.1, or 1.3 times. For example, the depth of the isolation trench 600 ranges from 10 μm to 45 μm.

[0039] In one embodiment, such as Figure 3 , Figure 7 and Figure 8As shown, the power semiconductor device also includes a passivation layer 610, which at least covers the surface of the isolation trench 600. Exemplarily, the surface of the isolation trench 600 may be coated with an oxide layer or a silicon nitride layer for isolation to prevent leakage. Exemplarily, the thickness of the passivation layer 610 can be 0.5 μm to 2 μm, and the length of the passivation layer 610 along the surface of the isolation trench 600 ranges from 30 μm to 80 μm. In this embodiment, the passivation layer 610 is designed along the trench surface, reducing the lateral proportion of the passivation layer 610, increasing the effective area ratio of the cathode to the gate, and improving the current handling capability.

[0040] Example 2: According to an exemplary embodiment, most of the power semiconductor device in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, in this embodiment, as... Figure 8 As shown, the contact surface between the N++ emitter region 230 and the cathode metal layer 500 of the power semiconductor device is coplanar with the contact surface between the P+ base region 220 and the gate metal layer 400.

[0041] In this embodiment, to address the issues of uneven carrier distribution and "re-triggering" during turn-off, a planar coplanar structure is designed for the N++ emitter region 230 and the P+ base region 220. This is because in existing technologies, such as... Figure 1 As shown, in existing trench-type GCTs, the cathode and gate form a step through the trench. On the one hand, this causes carriers to accumulate at the step, resulting in an excessively high current gain α2 in the local npn transistor T2. Consequently, carrier extraction is incomplete during turn-off, leading to easy re-triggering failure. On the other hand, the gate reverse current is unevenly distributed at the step, resulting in slow turn-off speed and high losses. Therefore, in this embodiment, the N++ emitter region 230 and the P+ base region 220 are coplanar, structurally solving this problem.

[0042] Specifically, because the coplanar structure of the N++ emitter region 230 and the P+ base region 220 eliminates the "edge effect" caused by the step, the electrons injected into the N++ emitter region 230 diffuse uniformly in the P base region 210, making the current gain α2 of the npn transistor T2 uniformly distributed in the lateral direction of the power semiconductor device, thereby avoiding the turn-off residue caused by excessively high current gain α2 in some local npn transistors T2. Since the gate metal layer 400 directly covers the P+ base region 220, and the isolation trench 600 surrounds the N++ emitter region 230 to form a "closed boundary", the reverse current injected by the gate can uniformly surround the N++ emitter region 230 along the inner side of the isolation trench 600, which can efficiently remove the carriers from the P base region 210, significantly improving the turn-off speed, thereby solving the problem of incomplete removal of local carriers in the existing structure.

[0043] In one embodiment, the isolation trench 600 can be matched to the J3 junction (gate-cathode junction) through depth design. The depth of the isolation trench 600 is 0.8 to 1.3 times the depth of the gate-cathode junction, which can effectively isolate the N++ emitter region 230 and the P+ base region 220, thereby limiting the temperature-dependent current gain α2 of the npn transistor T2 and preventing excessive weakening of the injection capability of the N++ emitter region 230. This ensures that the current gain α2 of the npn transistor T2 is sufficiently high at low temperatures to reduce conduction losses. This matching design makes the current gain α2 of the npn transistor T2 change gradually over a wide temperature range, such as -40℃ to 125℃, avoiding turn-off failure caused by a sudden increase in the current gain α2 of the npn transistor T2 at high temperatures, thus solving the problem of "difficulty in high-temperature hard turn-off" in existing structures.

[0044] For example, when the power semiconductor device of this application is used in a power grid device under a 4500V high-voltage scenario, assuming the isolation width W of the isolation trench is 20μm, the influence of the depth of the isolation trench on the device's turn-off capability is as follows: Figure 9 As shown. By Figure 9 It can be concluded that, compared to the existing standard 4500V GCT (reference) technology Figure 1 The design of the junction depth Xj3 of the J3 junction (as shown in the diagram) is as follows: Figure 8 As shown, the turn-off capability improvement reaches its maximum when the trench depth is in the range of 0.9~1.3×j3. Compared with the standard 4500V GCT design, the power semiconductor device (GCT) structure proposed in this application improves the turn-off capability by approximately 14%.

[0045] When Figure 7 As shown, when the trench depth is 0.7×j3, the effect of the isolation width of the isolation trench on the device's turn-off capability is as follows. Figure 10 As shown. By Figure 10 It can be concluded that, relative to the standard 4500V GCT design, the shutdown capability reaches its maximum when the isolation width W of the isolation trench is 80μm. (This is in contrast to the standard 4500V GCT scheme.) Figure 1 The power semiconductor device (GCT) structure proposed in this application, as shown in the diagram, improves the turn-off capability by approximately 21%.

[0046] Example 3: According to an exemplary embodiment, most of the power semiconductor device in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, Figure 3 , Figure 7 and Figure 8As shown, the power semiconductor device further includes a second stacked structure 300 and an anode metal layer 700, which are sequentially stacked in a direction away from the second surface of the N-base region 100, with the first surface and the second surface being opposite to each other. Figure 3 As shown, the second stacked structure 300 includes an N-buffer layer 310 and a P+ transparent anode emission region 320, which are sequentially located away from the second surface.

[0047] like Figure 11 and Figure 12 As shown, in one embodiment, the second stacked structure 300 may also be the P-emission region 330 and the P+ anode emission region 340 that are sequentially located away from the second surface.

[0048] Example 4: According to an exemplary embodiment, most of the power semiconductor device in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, Figure 12 As shown, the P-base region 210 has a protrusion structure 211 on the contact surface with the N-base region 100. The protrusion structure 211 protrudes toward the N++ emission region 230 and is located in the region below the N++ emission region 230.

[0049] In this embodiment, the P-base region 210 is provided with a protrusion structure 211, thereby forming a corrugated P-base region 210. The protrusion structure 211 protrudes toward the N++ emitter region 230, causing the N-base region 100 to be recessed into the P-base region 210.

[0050] When the power semiconductor device is turned on, the corrugated P-base region 210 enables a uniform distribution of charge carriers, reducing on-state losses. Specifically, when the power semiconductor device is turned on, the N++ emitter region 230 (cathode side) injects a large number of electrons into the P-base region 210 (this process is the carrier transport process of an npn transistor). The protruding structure 211 of the corrugated P-base region 210 increases the contact area between the P-base region 210 and the N-base region 100, resulting in a decrease in current density and promoting a more uniform dispersion of injected electrons in the P-base region 210, thereby reducing carrier recombination losses and thus reducing on-state losses.

[0051] When the power semiconductor device is turned off, the corrugated P-base region 210 can also accelerate carrier extraction, suppress re-triggering, and improve turn-off capability. This is because the core of power semiconductor device turn-off is the reverse extraction of carriers from the P-base region 210 by the gate, making the current gain α1+α2 < 1 of the npn / pnp transistor. The protruding structure 211 of the corrugated P-base region 210 is equivalent to adding a carrier extraction path inside the P-base region 210, allowing the reverse current from the gate to penetrate into all areas of the P-base region 210 more quickly and uniformly, thereby removing residual carriers. Reducing the residual carriers in the P-base region 210 after turn-off can avoid re-triggering caused by residual carriers, and can especially improve turn-off reliability at high temperatures.

[0052] In this embodiment, the peak electric field and carrier density distribution are optimized by setting a protrusion structure 211 in the P-base region 210. This solves the problems of high on-state loss, large turn-off residue, and difficulty in turning off at high temperature affecting reliability in traditional GCT, and ultimately achieves a better balance between turn-on and turn-off performance.

[0053] Example 5: The embodiments of this application also provide a gate-commutated thyristor chip, including the power semiconductor device as described in any of the above embodiments. In this embodiment, the gate-commutated thyristor chip includes a power semiconductor device, and the annular isolation trench 600 in the power semiconductor device is an "independent isolation structure" that only surrounds the N++ emitter region (cathode) and does not affect the contact distance between the P+ base region 220 and the gate (the gate metal layer 400 directly covers the P+ base region 220), ensuring efficient transmission of the gate drive signal and reverse current. The depth and width of the isolation trench 600 are designed only for the electron injection path of the N++ emitter region 230 and are completely decoupled from parameters such as the thickness of the P base region 210 and the gate contact performance. Therefore, this "partition isolation" design physically cuts off the chain reaction between parameters, allowing each structural parameter to independently serve its target performance. That is, the P+ base region 220 controls the current gain α1 of the pnp transistor T1, and the isolation trench 600 controls the current gain α2 of the npn transistor T2, breaking the core contradiction of the existing technology that cannot balance on-state loss and turn-off capability.

[0054] Example 6: This application also provides a thyristor, including a gate-commutated thyristor chip as described in the above embodiments. The power semiconductor device of this application can be applied to a reverse-conducting gate-commutated thyristor (GCT), such as... Figure 13As shown, the structure formed by the anti-parallel integration of the gate commutated thyristor (GCT) and the fast recovery diode (FRD) constitutes a planar GCT chip structure with an integrated fast recovery diode (FRD), which is the core part of the trench IGCT (integrated gate commutated thyristor) device. The anti-parallel integration refers to the reverse connection of the gate commutated thyristor (GCT) and the fast recovery diode (FRD) on the same chip, with their anode-cathode connections reversed. The fast recovery diode (FRD) is used to achieve rapid recovery of reverse current. The annular isolation trench design in the power semiconductor device only affects the gate-cathode region of the GCT structure, without interfering with the electric field distribution and carrier transport in the RED region. This ensures the optimized and coordinated operation of the "GCT on / off" and "RED reverse recovery" functions in the integrated device, solving the problem of mutual interference between functional regions in the integrated structure.

[0055] It should be understood that the terms "mechanism," "device," "component," etc., used in this application are merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.

[0056] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application. In practical applications, the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A power semiconductor device, characterized by, The power semiconductor device comprises: an N-base region; a first stack structure located on a first surface of the N-base region, the first stack structure comprising an N++ emitter region and a P-base region and a P+-base region stacked in sequence on the first surface; a gate metal layer located on the P+-base region and connected to the P+-base region; a cathode metal layer located on the N++ emitter region and connected to the N++ emitter region; an isolation trench located between the P+-base region and the N++ emitter region, the isolation trench surrounding the N++ emitter region and not surrounding the P+-base region.

2. The power semiconductor device according to claim 1, characterized in that, A contact surface of the N++ emitter region and the cathode metal layer is arranged in a coplanar manner with a contact surface of the P+-base region and the gate metal layer.

3. The power semiconductor device of claim 1, wherein, A depth of the isolation trench is 0.8-1.3 times a junction depth of the N++ emitter region.

4. The power semiconductor device according to any one of claims 1 to 3, characterized in that, The power semiconductor device further comprises a passivation layer covering at least a surface of the isolation trench.

5. The power semiconductor device according to claim 1 or 2, characterized in that, The power semiconductor device further comprises a second stack structure and an anode metal layer, the second stack structure and the anode metal layer being arranged in sequence in a direction away from a second surface of the N-base region, the first surface and the second surface being opposite surfaces.

6. The power semiconductor device according to claim 5, characterized in that, The second stack structure comprises an N-buffer layer and a P+ transparent anode emitter region in sequence away from the second surface, or the second stack structure comprises a P emitter region and a P+ anode emitter region in sequence away from the second surface.

7. The power semiconductor device of claim 1, wherein, The P-base region is provided with a protruding structure on a contact surface with the N-base region, the protruding structure protruding towards the N++ emitter region and being located below the N++ emitter region.

8. A gate-commutated thyristor chip, characterized by The power semiconductor device comprises the power semiconductor device as claimed in any one of claims 1-7.

9. A thyristor, characterized by The power semiconductor device is characterized in that, The power semiconductor device comprises the gate-commutated thyristor chip as claimed in claim 8.

10. A thyristor according to claim 9, characterized in that The power semiconductor device further comprises a fast recovery diode chip, the gate-commutated thyristor chip and the fast recovery diode chip being connected in anti-parallel.

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