A diode and packaging method for use in negative ion generators and igniters.

Abstract

This invention relates to the field of electronic device packaging technology, and more particularly to a diode and packaging method for packaging negative ion generators and igniters. The method uses an image recognition system to detect the assembled die after dispensing, generating die defect data including overall offset, relative misalignment, and height deviation. Based on the comparison of the defect data with corresponding preset thresholds, the compensability of the defect is determined, and if compensability is achieved, the corresponding stress defect type and stress defect factor are further determined. Then, differentiated compensation instructions are generated according to different stress defect types, thereby dynamically adjusting the injection molding parameters according to the compensation instructions and stress defect factor to complete the packaging and obtain the diode. This invention achieves accurate diagnosis and proactive process compensation for dual-chip-specific packaging defects, effectively improving packaging yield and product reliability.

Description

Technical Field

[0001] This invention relates to the field of electronic device packaging technology, and in particular to a diode and packaging method for packaging negative ion generators and igniters. Background Technology

[0002] In the field of semiconductor power devices and high-voltage small-signal devices, integrating multiple semiconductor chips into a single package has become an important technological trend in order to achieve higher current capability, power density, and reliability. However, the inherent, minute, and random chip mounting deviations during the packaging process directly lead to variations in the electrical performance of the finished product and a decline in long-term reliability. Existing technologies mainly seek solutions by optimizing the structure of the packaging hardware itself.

[0003] Chinese Patent Publication No. CN120882072A discloses a parallel half-bridge power module with dual-ended power supply and double-sided heat dissipation packaging. The related technical solution uses upper and lower ceramic copper-clad laminates as the main carrier, and bridges and interconnects multiple independent molybdenum and copper conductive sheets in three-dimensional space to construct a complex electrical and heat conduction path. It also symmetrically arranges DC positive and negative power terminals on both sides of the module, and strictly alternates and equidistantly arranges multiple SiC MOSFET chips and diode chips on the substrate to achieve physical balance of parasitic inductance and resistance in each parallel branch, thereby improving dynamic current distribution. However, the above solution still has the following problems:

[0004] The performance of existing technical solutions is highly dependent on the ideal state of the initial design and the absolute precision of manufacturing, and lacks any online sensing and compensation mechanism. Once a micron-level offset, tilt or height deviation occurs in the chip mounting process, this tiny deviation will be amplified step by step in the subsequent packaging and curing process, resulting in uneven stress distribution between chips and unbalanced lead tension.

[0005] Therefore, there is an urgent need for a packaging method that can sense and compensate for minute deviations in the packaging process in real time, so as to achieve high consistency and high reliability of dual-chip micro-packaging. Summary of the Invention

[0006] Therefore, the present invention provides a diode and its packaging method for use in negative ion generators and igniters, in order to overcome the problems of poor consistency and insufficient reliability of dual-chip packaged products caused by the lack of online detection and real-time compensation capabilities in the prior art.

[0007] To achieve the above objectives, the present invention provides a diode packaging method, comprising:

[0008] Step S1: Perform dispensing and dual-chip die mounting operations to obtain a die assembly. Use an image recognition system to detect the actual mounting positions of the first chip and the second chip in the die assembly to obtain pose information and calculate the corresponding die mounting defect data. The die mounting defect data includes overall offset, relative misalignment, and height deviation.

[0009] Step S2: The die assembly is cured or heat-welded, and wire bonding is performed to form an electrically interconnected packaged body.

[0010] Step S3: Determine the corresponding stress defect type based on the mounting defect data, wherein the stress defect type includes main channel deflection stress defect and local shear stress concentration defect.

[0011] Step S4: Determine the corresponding stress defect factor and compensation instructions for adjusting different injection molding parameters based on the stress defect type. The compensation instructions include a first compensation instruction and a second compensation instruction. The injection molding parameters include injection speed, injection temperature and holding time.

[0012] Step S5: Adjust the injection speed and injection temperature based on the first compensation command and the corresponding stress defect factor, or adjust the injection speed, injection temperature and holding time based on the second compensation command and the corresponding stress defect factor, so as to perform injection molding on the body to be packaged.

[0013] Step S6 involves performing post-curing, electroplating, bead cutting and molding, and electrical performance testing on the injection-molded body to be packaged to obtain the packaged diode.

[0014] Further, step S1 includes:

[0015] Step S11: Calculate the relative pose offset set based on the pose information, wherein the relative pose offset set includes the first offset of the first chip corresponding to the first actual mounting position, the second offset of the second chip corresponding to the second actual mounting position, and the direction angle of the connection between the first chip and the second chip.

[0016] Step S12: Determine the corresponding mounting defect data based on the first offset, the second offset, and the connection direction angle.

[0017] Further, step S3 includes:

[0018] Step S31: Determine whether to perform compensation based on the comparison result between the corresponding mounting defect data and the corresponding preset pose threshold.

[0019] Step S32: If the overall offset, the relative misalignment, and the height deviation are all less than or equal to the corresponding preset pose threshold, a compensation defect is determined.

[0020] Alternatively, if any one of the overall offset, the relative misalignment, and the height deviation exceeds the corresponding preset pose threshold, it is determined that the defect cannot be compensated.

[0021] The preset pose threshold includes a preset overall offset, a preset relative misalignment, and a preset height deviation.

[0022] Further, step S32 includes:

[0023] Step S321: When determining the compensation defect, the corresponding stress defect type is determined based on the comparison result between the corresponding mounting defect data and the corresponding preset pose threshold, and the corresponding stress defect factor is determined based on the stress defect type.

[0024] Alternatively, if it is determined that the defect cannot be compensated, an exception notification will be issued.

[0025] Furthermore, based on the comparison results where the overall offset, the relative misalignment, and the height deviation are all less than or equal to the corresponding preset pose threshold, the stress defect type is determined based on the maximum value among the overall offset, the relative misalignment, and the height deviation.

[0026] When determining the type of stress defect, if the overall offset is greater than the relative misalignment and the height deviation, the stress defect type is determined to be the main channel deflection stress defect.

[0027] If the overall offset is less than or equal to either the relative misalignment or the height deviation, the stress defect type is determined to be the local shear stress concentration defect.

[0028] Furthermore, the stress defect factor is determined as the first stress defect factor based on the main channel deflection stress defect.

[0029] The stress defect factor is determined as the second stress defect factor based on the local shear stress concentration defect.

[0030] Furthermore, the compensation instruction is determined to be the first compensation instruction based on the deflection stress defect of the main channel;

[0031] Alternatively, the compensation instruction may be determined as the second compensation instruction based on the local shear stress concentration defect.

[0032] Furthermore, when performing step S4, the injection speed is reduced and the injection temperature is increased based on the first compensation command and the first stress defect factor.

[0033] Alternatively, based on the second compensation command and the second stress defect factor, the injection speed can be reduced, the injection temperature increased, and the holding time extended.

[0034] Furthermore, the magnitude of the reduction in injection speed, the increase in injection temperature, and the holding time are positively correlated with the magnitude of the stress defect factor.

[0035] On the other hand, the present invention also provides a diode for use in the packaging of a negative ion generator and an igniter, comprising:

[0036] First pin, second pin and third pin, and first conductive part, second conductive part and third conductive part respectively disposed on the corresponding pin;

[0037] The first chip is connected to the first conductive part and connected to the third conductive part via a lead wire;

[0038] The second chip is connected to the third conductive part and connected to the second conductive part via a lead.

[0039] Compared with existing technologies, the advantages of the diode packaging method of the present invention are as follows: by acquiring the precise pose information of the dual chips after packaging in real time, the packaging error is quantified into packaging defect data including overall offset, relative misalignment, and height deviation; subsequently, based on the comparison results of the packaging defect data and the preset pose threshold, the compensability of the defect is determined, and further, based on the defect type and defect degree, the stress risk type and stress defect factor of the subsequent injection molding process are predicted, and the corresponding process compensation instructions are generated; in the subsequent injection molding process, the corresponding parameter adjustments are executed based on the process compensation instructions to actively compensate for the defect impact caused by the previous process. Thus, without changing the standard packaging hardware, active suppression of process fluctuations and precise control of the product's intrinsic quality are achieved, significantly improving the overall performance and production yield of the dual-chip micro-package.

[0040] Furthermore, this invention transforms the chip pose information acquired by the image recognition system into a quantified defect dataset including overall offset, relative misalignment, and height deviation, and compares it with a preset pose threshold to determine the corresponding stress defect type. Based on the stress defect type, the corresponding stress defect factor is determined to quantify the severity of the defect and the intensity of compensation required for the injection molding process, thereby providing a reliable data foundation for subsequent defect compensation.

[0041] Furthermore, this invention distinguishes between different defects based on their physical causes and failure mechanisms. For defects that affect flow uniformity, the solution focuses on adjusting the parameters during the injection filling stage to guide the flow of the injection melt. For defects that cause local high stress, the parameters during the filling and holding stages are optimized simultaneously to alleviate stress, ensuring the efficiency and effectiveness of the compensation measures and avoiding the limitations of adjusting a single parameter.

[0042] Furthermore, this invention achieves precise matching of process adjustments by quantitatively linking compensation commands with stress defect factors, ensuring that the adjustment range of injection molding parameters is adapted to the severity of defects, thus avoiding overcompensation or undercompensation. Attached Figure Description

[0043] Figure 1 This is an axial view of the body to be packaged in the packaged diode in an embodiment of the present invention;

[0044] Figure 2 This is a top view of the device to be packaged in the diode packaged in an embodiment of the present invention;

[0045] Figure 3 This is a top view of another form of the device to be packaged in the packaged diode according to an embodiment of the present invention;

[0046] Figure 4 This is a schematic flowchart of the diode packaging method in an embodiment of the present invention;

[0047] Figure 5 This is a logic decision diagram of the diode packaging method in an embodiment of the present invention;

[0048] In the diagram, 1 is the first pin; 2 is the second pin; 3 is the third pin; 4 is the first chip; 5 is the second chip; and 6 is the lead wire. Detailed Implementation

[0049] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0050] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0051] It should be noted that in the description of this invention, the terms "upper", "lower", "left", "right", "inner", "outer", etc., which indicate directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. This is only for the convenience of description and is not intended to indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0052] Furthermore, it should be noted that, in the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0053] Please see Figures 1 to 3 As shown, Figure 1 This is an axial view of the device to be packaged in the diode packaged according to an embodiment of the present invention. Figure 2 This is a top view of the device to be packaged in the diode packaged according to an embodiment of the present invention. Figure 3 This is a top view of another form of the device to be packaged in an embodiment of the present invention. Please refer to [link / reference]. Figure 2 As shown, in this embodiment of the invention, the diode has three conductive connection portions, and each conductive connection portion is connected to a corresponding outwardly extending pin. The anode terminals of the first chip 4 and the second chip 5 are fixedly connected to the first conductive connection portion and the third conductive connection portion, respectively, by dispensing or soldering. The cathode terminal of the first chip 4 is connected to the third conductive connection portion via a lead 6, and the cathode terminal of the second chip 5 is connected to the second conductive connection portion via a lead 6. According to... Figure 3 As shown, in this embodiment of the invention, the anodes of the first chip 4 and the second chip 5 are fixedly connected to the second conductive connection part and the third conductive connection part respectively by dispensing or soldering; the cathode of the first chip 4 is connected to the third conductive connection part by a lead 6, and the cathode of the second chip 5 is connected to the first conductive connection part by a lead 6.

[0054] Please see Figure 4 and Figure 5 As shown, Figure 4 This is a schematic flowchart of the diode packaging method in an embodiment of the present invention. Figure 5 This is a logic decision diagram for a diode packaging method in an embodiment of the present invention. This embodiment includes at least the following steps:

[0055] Step S1: Perform dispensing and dual-chip die mounting operations to obtain a die assembly. Use an image recognition system to detect the actual mounting positions of the first chip 4 and the second chip 5 in the die assembly to obtain pose information and calculate the corresponding die mounting defect data. The die mounting defect data includes overall offset, relative misalignment, and height deviation.

[0056] Step S2: The die assembly is cured or heat-welded, and wire bonding is performed to form an electrically interconnected packaged body.

[0057] Step S3: Determine the corresponding stress defect type based on the mounting defect data. The stress defect types include main channel deflection stress defects and local shear stress concentration defects.

[0058] Step S4: Determine the corresponding stress defect factor and compensation instructions for adjusting different injection parameters based on the stress defect type. The compensation instructions include a first compensation instruction and a second compensation instruction. The injection parameters include injection speed, injection temperature and holding time.

[0059] Step S5: Adjust the injection speed and injection temperature based on the first compensation command and the corresponding stress defect factor, or adjust the injection speed, injection temperature and holding time based on the second compensation command and the corresponding stress defect factor, so as to perform injection molding on the body to be packaged.

[0060] Step S6 involves performing post-curing, electroplating, bead cutting and molding, and electrical performance testing on the injection-molded body to be packaged to obtain the packaged diode.

[0061] In one specific embodiment, the present invention provides a packaging method for manufacturing the above-mentioned diode. Preferably, a low-temperature curing conductive adhesive is applied to a designated position on a first conductive portion on a first pin 1 and a third conductive portion on a third pin 3. Subsequently, the first chip 4 and the second chip 5 are respectively fixed to the corresponding conductive portions by the low-temperature curing conductive adhesive to obtain a die assembly.

[0062] The present invention also provides another preferred embodiment in which pre-made solder is applied to a designated position on a first conductive portion on a first pin 1 and a third conductive portion on a third pin 3. Subsequently, the first chip 4 and the second chip 5 are respectively fixed to the corresponding conductive portions by the pre-made solder to obtain another form of die assembly.

[0063] The control system uses an image recognition system to detect the actual mounting positions of the first chip 4 and the second chip 5 in the die assembly, generates position information, and identifies the corresponding die assembly defect data.

[0064] In this embodiment, after the die-mounting system attaches the first chip 4 and the second chip 5 to designated positions on the first pin 1 and the third pin 3 respectively using conductive adhesive, a die-mounting assembly is formed. Subsequently, the die-mounting assembly is identified by an image recognition system to obtain the spatial coordinates (X1, Y1, Z1) and (X2, Y2, Z2) of the geometric centers of the first chip 4 and the second chip 5 in the X, Y, and Z directions, as well as the pose information of the direction angle φ of the line connecting the first chip 4 and the second chip 5. For example, the X-axis can be set to be perpendicular to the pin direction, and the Y-axis can be set to be parallel to the pin direction. The line connecting the design center of the first chip 4 and the design center of the second chip 5 is denoted as the first line, and the line connecting the geometric center of the first chip 4 and the geometric center of the second chip 5 is denoted as the second line. The angle between the first line and the second line is calculated and denoted as the line direction angle φ. Here, the geometric center is determined by the actual placement after chip dispensing, and the design center is determined by the expected placement position. The counterclockwise direction is positive. The control system calculates the relative pose offset set of the first chip 4 and the second chip 5 based on the pose information. This includes the first offset (ΔX1, ΔY1, ΔZ1) of the first chip 4 corresponding to the first actual placement position and the second offset (ΔX2, ΔY2, ΔZ2) of the second chip 5 corresponding to the second actual placement position, as well as the line direction angle φ of the first chip 4 and the second chip 5.

[0065] In this embodiment, the corresponding die-mounting defect data is calculated based on the relative pose offset set of the first chip 4 and the second chip 5, including the overall offset ΔG, the relative misalignment ΔR, and the height deviation ΔC.

[0066] Specifically, the control system uses the midpoint of the line connecting the geometric centers of the first chip 4 and the second chip 5 to form the overall graphic center, and calculates the deviation of the overall graphic center relative to the design center to determine the overall offset ΔG. The calculation formula is ΔG=√[((X1+X2) / 2-X0)²+((Y1+Y2) / 2-Y0)²], where (X0,Y0) are the center coordinates of the first chip 4 and the second chip 5 at the design center, determined by the expected mounting position; the overall offset ΔG characterizes the offset error between the first chip 4 and the second chip 5 as a whole and the design center on the substrate plane.

[0067] The control system calculates the absolute difference between the actual planar distance and the theoretical design distance between the geometric center coordinates of the first chip 4 and the geometric center coordinates of the second chip 5, and combines this with the change in the direction angle of the line connecting the first chip 4 and the second chip 5 to comprehensively evaluate and determine the relative misalignment ΔR. The calculation formula is ΔR=|√[(X2-X1)²+(Y2-Y1)²]-D0|+ζ·|φ|, where D0 is the straight-line distance between the design center of the first chip 4 and the design midpoint of the second chip 5, and ζ is a preset weighting coefficient in mm / °. The setting of ζ is determined based on process experiments and historical packaging data analysis. The relative misalignment ΔR characterizes the spacing error and relative orientation error between the first chip 4 and the second chip 5 after dispensing.

[0068] The control system calculates the first height difference between the actual installation height of the first chip 4 and the preset installation height, and the second height difference between the actual installation height of the second chip 5 and the preset installation height. It also calculates the absolute difference between the arithmetic mean of the first height difference and the second height difference and the preset limit value to determine the height deviation ΔC. The calculation formula is ΔC=|(Z1+Z2) / 2-Z0|, where Z0 is the preset limit value set with the pin horizontal plane as the reference.

[0069] In one specific embodiment, the die assembly after identifying die defects is sent to a curing device to cure the conductive adhesive or heat-weld the pre-made solder. Then, a wire bonding machine is used to perform a wire bonding operation to obtain an electrically interconnected body to be packaged.

[0070] In one specific embodiment, the control system compares the calculated die-mount defect data with the corresponding preset pose threshold to determine whether the current packaged assembly can be compensated. The preset pose thresholds are determined based on process experiments and historical packaging data. When any error in the die-mount defect data of the packaged assembly is less than or equal to the corresponding preset error in the preset pose threshold, it indicates that although the current packaged assembly has defects, it has not yet reached a scrapped state. The corresponding stress defect risk can be effectively compensated or prevented from occurring through subsequent injection molding processes to compensate for the diode's die-mount defects. The preset pose threshold includes a preset overall offset Gth, a preset relative misalignment Rth, and a preset height deviation Cth. For example, Gth = 20 μm, Rth = 15 μm, and Cth = 10 μm.

[0071] In this embodiment, ΔG, ΔR, and ΔC are compared with preset pose thresholds Gth, Rth, and Cth, respectively. If ΔG≤Gth, ΔR≤Rth, and ΔC≤Cth, it is determined that the defect of the body to be packaged can be compensated. If any one of them is not satisfied, it is determined that it cannot be compensated, and an abnormal notification is generated, so that the body to be packaged is marked and removed from the main production line to avoid wasting subsequent packaging materials and time, thereby directly improving the overall production efficiency and economic benefits.

[0072] In this embodiment, the control system executes a corresponding compensation strategy based on the comparison result that the die-mount defect data is less than or equal to a preset pose threshold. Specifically, if the overall offset ΔG is the maximum value in the die-mount defect data or the ratio of the overall offset ΔG to the preset overall offset Gth is the largest compared to other ratios, it indicates that the first chip 4 and the second chip 5 as a whole are offset on the pin horizontal plane, and the stress defect type of the current body to be packaged is determined to be a main channel deflection stress defect. If the relative misalignment ΔR is the maximum value in the die-mount defect data or the ratio of the relative misalignment ΔR to the preset relative misalignment Rth is the largest compared to other ratios, or the height deviation ΔC is the maximum value in the die-mount defect data or the ratio of the height deviation ΔC to the preset height deviation Cth is the largest compared to other ratios, or ΔG / Gth is equal to ΔR / Rth or ΔC / Cth, it indicates that there is a narrow and uneven gap or a large height difference between the first chip 4 and the second chip 5, and the stress defect type of the current body to be packaged is determined to be a local shear stress concentration defect.

[0073] If ΔG / Gth > ΔR / Rth and ΔG / Gth > ΔC / Cth, then the stress defect type is determined to be a main channel deflection stress defect. If ΔG / Gth < ΔR / Rth or ΔG / Gth < ΔC / Cth, then the stress defect type is determined to be a local shear stress concentration defect.

[0074] In this embodiment, exemplarily, the specific design parameters can be selected as follows: from D0=1.2mm, φ0=0°, the preset pose thresholds are: Gth=0.05mm, Rth=0.10mm, Cth=0.03mm. The preset weighting coefficient ζ=0.01mm / °. The following two calculation examples illustrate the defect compensation determination process.

[0075] Example 1: The geometric center of the first chip 1 after dispensing is set to (X1,Y1,Z1)=(0.02,0.01,0.001), and the geometric center of the second chip 2 after dispensing is set to (X2,Y2,Z2)=(1.22,0.01,0.002), with the connecting angle φ=0.5°.

[0076] Therefore, we can obtain: ΔG≈0.015mm, ΔR≈0.005mm, ΔC≈0.001mm.

[0077] ΔG, ΔR, and ΔC are compared with preset pose thresholds Gth, Rth, and Cth, respectively. When ΔG < Gth, ΔR < Rth, and ΔC < Cth, it can be determined that the defect of the body to be packaged can be compensated. Furthermore, ΔG / Gth is the largest ratio compared to other values. Therefore, the control system determines that the stress defect type of the body to be packaged is the main channel deflection stress defect.

[0078] Example 2: The geometric center of the first chip 1 after dispensing is set to (X1,Y1,Z1)=(0.01,0.00,0.000), and the geometric center of the second chip 2 after dispensing is set to (X2,Y2,Z2)=(1.21,0.10,0.020), with a connecting angle φ=5.0°.

[0079] Therefore, we can obtain: ΔG≈0.055mm, ΔR≈0.058mm, ΔC≈0.020mm.

[0080] ΔG, ΔR, and ΔC are calculated and compared with preset pose thresholds Gth, Rth, and Cth, respectively. The results show that ΔG > Gth, ΔR < Rth, and ΔC < Cth. Therefore, it can be determined that the defect of the body to be packaged cannot be compensated, and an abnormal notification is generated.

[0081] Specifically, regarding the main channel deflection stress defect, the diode packaging method provided in this embodiment of the invention differs from the single-chip packaging layout. According to the principles of fluid dynamics, the overall offset of the first chip 4 and the second chip 5 will disrupt the geometric symmetry of the mold cavity. When the encapsulated melt flows in the asymmetrical cavity, it will naturally tend to the side with less resistance, generating an asymmetrical flow field and pressure field. When the first chip 4 and the second chip 5 are offset relative to the design center, it will cause non-uniform residual stress inside the diode after injection molding and solidification, causing internal warping and making the chip bear unilateral stress, affecting long-term reliability. The injection molding system reduces the initial momentum of the injection melt when it enters the cavity by reducing the injection speed, thereby weakening the biased flow tendency of the injection melt caused by the cavity asymmetry. The injection molding system also increases the injection temperature to reduce the viscosity of the injection melt to enhance the fluidity of the injection melt, so that the injection melt can fully fill the area of ​​flow resistance difference caused by the overall offset of the first chip 4 and the second chip 5.

[0082] For local shear stress concentration defects, the height difference or abnormal gap between the first chip 4 and the second chip 5 will cause abrupt changes in the flow cross section. When the molding melt flows through this abrupt change area, the local shear stress will increase accordingly, which will lead to a decrease in the interfacial bonding strength between the chip and the molding compound or damage to the passivation layer on the chip surface. In addition to reducing the injection speed of the injection melt and increasing the injection temperature, the injection system also ensures that the injection melt has more time to continuously replenish the melt to areas with large shrinkage, such as the back of the chip and the gap, by extending the holding time, thereby reducing voids or interfacial separation caused by shrinkage differences and enhancing the integrity of the interfacial bonding.

[0083] In one specific embodiment, the control system determines the corresponding stress defect factor and compensation instruction based on the corresponding stress defect type. The stress defect factor K includes a first stress defect factor K1 and a second stress defect factor K2, which are used to quantify the severity of the defect and the intensity of compensation required for the injection molding process. The compensation instruction includes a first compensation instruction and a second compensation instruction, which are determined based on the corresponding first stress defect factor K1 and the second stress defect factor K2, respectively, thereby determining the injection temperature, injection speed and / or holding time in the injection molding process.

[0084] Specifically, in response to the overall offset disrupting the geometric symmetry of the injection mold cavity, the control system reduces the injection speed through the first compensation command, making the flow easier to be guided by the mold geometry; and enhances the fluidity of the injection melt by increasing the temperature.

[0085] To address the extremely high shear rates generated by the melt flow due to relative misalignment or excessive height, the control system reduces the injection speed and increases the injection temperature through a second compensation command. At the same time, it extends the holding time to provide sufficient stress relaxation time for the molecular chains and ensures that the melt can fully compensate for the shrinkage of local areas, preventing interface delamination or voids caused by uneven shrinkage.

[0086] In this embodiment, the control system determines the first stress defect factor K1 corresponding to the injection molding process based on the determination result of the main channel deflection stress defect. The calculation formula is K1=α1·(ΔG / Gth), where α1 is a weighting coefficient calibrated through experiments, which can be set to α1=1.2 for example. At the same time, a first compensation command is generated to adjust the injection molding process parameters to generate compensatory hydrodynamics. The specific parameter adjustment amount of the injection molding process parameters is determined by K1: the injection speed adjustment amount ΔV1=V0 / (1+β1·K1), where β1 is the speed adjustment coefficient, which can be set to β1=0.1 for example; the injection temperature adjustment amount ΔT1=T0 / (1+σ1·K1), where σ1 is the temperature adjustment coefficient, which can be set to σ1=0.03 for example; V0 and T0 are standard process parameters set according to the rheological characteristics of the packaging material and the mold design, which can be set to V0=80mm / s and T0=175℃ for example.

[0087] In this embodiment, if the control system determines that the stress defect type is a local shear stress concentration defect, it determines the corresponding second stress defect factor K2, which is calculated by the formula K2=max[α2·(ΔR / Rth),α3·(ΔC / Cth)], where α2 and α3 are weighting coefficients calibrated through experiments. For example, α2=1.0 and α3=1.5. At the same time, based on the determination result of the local shear stress concentration defect, a second compensation command is generated to adjust the injection molding process parameters to reduce the local shear rate during the filling stage and extend the holding time during the injection molding holding stage. To promote stress relaxation and shrinkage compensation, the specific adjustment amounts of the injection molding process parameters are determined by K2. The injection speed adjustment amount ΔV2 = V0 / (1 + β2·K2), where β2 is the speed adjustment coefficient, and can be set to 0.2 for example; the injection temperature adjustment amount ΔT2 = T0 / (1 + σ2·K2), where σ2 is the temperature adjustment coefficient, and can be set to 0.05 for example; and the holding time adjustment amount Δt = t0·(1 + γ·K2), where γ is the holding time adjustment coefficient, and can be set to 0.15 for example, and t0 is the standard holding time, and can be set to 6s for example. Since the calculation results of the first stress defect factor K1 and the second stress defect factor K2 are different, the reduction in injection speed and the increase in injection temperature under the first compensation command and the second compensation command are different.

[0088] In one specific embodiment, the control system responds to the corresponding compensation command and the process parameters calculated based on the corresponding stress defect factor K to execute the injection molding process. After injection molding is completed, the injection-molded product is placed in a specific temperature environment for a period of time to allow the encapsulating resin material to fully cure, thereby eliminating the instantaneous thermal stress generated during injection molding and stabilizing the material properties of the encapsulation. Then, an electroplating process is sequentially performed to improve the solderability and corrosion resistance of the product pins, thereby obtaining the assemblies to be cut. Subsequently, multiple assemblies to be cut are cut and separated. Finally, each individual diode is subjected to electrical testing to obtain qualified diode finished products.

[0089] In this embodiment, when packaging a diode according to the diode packaging method of the present invention, a uniformly packaged diode is obtained by stress compensation control. The uniformly packaged diode is suitable for application scenarios that require high voltage, high frequency and high reliability, such as negative ion generators and igniters, and shows significant advantages.

[0090] Specifically, compared to traditional single-chip SOT-23 diodes, this product integrates two high-voltage diode chips within the package while maintaining a standard shape, thereby nearly doubling the diode's forward current carrying capacity and power density.

[0091] This invention's diode packaging method uses an image recognition system to identify wafer defect data online and, based on a preset pose threshold, instantly determines the type of stress defect. Simultaneously, it implements differentiated injection molding compensation schemes for different stress defect types, effectively suppressing potential defects such as internal stress concentration, uneven filling, or poor interface bonding caused by process fluctuations. This results in the final diode product exhibiting higher consistency in key electrical parameters such as reverse breakdown voltage (VRRM) and forward voltage drop (VF), and demonstrating superior reliability and lifespan under long-term high-voltage, high-frequency operating conditions.

[0092] Specifically, the diode provided in this embodiment integrates and optimizes the functions that originally required two discrete devices into a single compact package, greatly improving space utilization. At the same time, the optimization of the number of devices reduces the total area occupied by the original two devices to the area occupied by a single package. This lays the foundation for the miniaturization design requirements of the diode in this embodiment for negative ion generators and igniters.

[0093] Furthermore, the reduced number of components and increased integration freed up circuit board space and layout constraints, allowing the high-voltage silicon stack to be upgraded from the traditional DO-205 through-hole package to a more advanced SMA surface mount package. This enables the entire negative ion generator to be designed to be thinner and flatter, making it easier to integrate into chip modules.

[0094] Furthermore, the number of placement steps was reduced from 2 to 1, and the number of solder joints was reduced from 4 to 3, thereby improving production efficiency while reducing the complexity of the placement process, the amount of solder paste used, and manufacturing costs.

[0095] All technologies not mentioned in the above embodiments are existing technologies. It is understood that no specific limitation is made to any preset parameter or critical parameter in the embodiments of the present invention, and the above values ​​are not limited thereto. Those skilled in the art can adjust the preset parameters or critical parameters accordingly based on actual needs, analysis of historical data, or equipment usage.

[0096] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

Claims

1. A diode packaging method, characterized in that, include: Step S1: Perform dispensing and dual-chip die mounting operations to obtain a die assembly. Use an image recognition system to detect the actual mounting positions of the first chip and the second chip in the die assembly to obtain pose information and calculate the corresponding die mounting defect data. The die mounting defect data includes overall offset, relative misalignment, and height deviation. Step S2: The die assembly is cured or heat-welded, and wire bonding is performed to form an electrically interconnected packaged body. Step S3: Determine the corresponding stress defect type based on the mounting defect data, wherein the stress defect type includes main channel deflection stress defect and local shear stress concentration defect. Step S31: Determine whether to perform compensation based on the comparison result between the corresponding mounting defect data and the corresponding preset pose threshold. Step S32: If the overall offset, the relative misalignment, and the height deviation are all less than or equal to the corresponding preset pose threshold, a compensation defect is determined. Alternatively, if any one of the overall offset, the relative misalignment, and the height deviation exceeds the corresponding preset pose threshold, it is determined that the defect cannot be compensated. The preset pose threshold includes a preset overall offset, a preset relative misalignment, and a preset height deviation. Step S4: Determine the corresponding stress defect factor and compensation instructions for adjusting different injection molding parameters based on the stress defect type. The compensation instructions include a first compensation instruction and a second compensation instruction. The injection molding parameters include injection speed, injection temperature and holding time. Step S5: Adjust the injection speed and injection temperature based on the first compensation command and the corresponding stress defect factor, or adjust the injection speed, injection temperature and holding time based on the second compensation command and the corresponding stress defect factor, so as to perform injection molding on the body to be packaged. Step S6 involves performing post-curing, electroplating, bead cutting and molding, and electrical performance testing on the injection-molded body to be packaged to obtain the packaged diode.

2. The diode packaging method according to claim 1, characterized in that, Step S1 includes: Step S11: Calculate the relative pose offset set based on the pose information, wherein the relative pose offset set includes the first offset of the first chip corresponding to the first actual mounting position, the second offset of the second chip corresponding to the second actual mounting position, and the direction angle of the connection between the first chip and the second chip. Step S12: Determine the corresponding mounting defect data based on the first offset, the second offset, and the connection direction angle.

3. The diode packaging method according to claim 2, characterized in that, Step S32 includes: Step S321: When determining the compensation defect, the corresponding stress defect type is determined based on the comparison result between the corresponding mounting defect data and the corresponding preset pose threshold, and the corresponding stress defect factor is determined based on the stress defect type. Alternatively, if it is determined that the defect cannot be compensated, an exception notification will be issued.

4. The diode packaging method according to claim 3, characterized in that, Based on the comparison results where the overall offset, the relative misalignment, and the height deviation are all less than or equal to the corresponding preset pose threshold, the stress defect type is determined based on the maximum value among the overall offset, the relative misalignment, and the height deviation. When determining the type of stress defect, if the overall offset is greater than the relative misalignment and the height deviation, the stress defect type is determined to be the main channel deflection stress defect. If the overall offset is less than or equal to either the relative misalignment or the height deviation, the stress defect type is determined to be the local shear stress concentration defect.

5. The diode packaging method according to claim 4, characterized in that, The stress defect factor is determined as the first stress defect factor based on the deflection stress defect of the main channel. The stress defect factor is determined as the second stress defect factor based on the local shear stress concentration defect.

6. The diode packaging method according to claim 5, characterized in that, Based on the aforementioned main channel deflection stress defect, the compensation instruction is determined to be the first compensation instruction. Alternatively, the compensation instruction may be determined as the second compensation instruction based on the local shear stress concentration defect.

7. The diode packaging method according to claim 6, characterized in that, When performing step S4, the injection speed is reduced and the injection temperature is increased based on the first compensation command and the first stress defect factor. Alternatively, based on the second compensation command and the second stress defect factor, the injection speed can be reduced, the injection temperature increased, and the holding time extended.

8. The diode packaging method according to claim 7, characterized in that, The magnitude of the decrease in injection speed, the increase in injection temperature, and the holding time are positively correlated with the magnitude of the stress defect factor.

9. A diode for packaging a negative ion generator and an igniter, obtained by the diode packaging method according to any one of claims 1-8, characterized in that, include: First pin, second pin and third pin, and first conductive part, second conductive part and third conductive part respectively disposed on the corresponding pin; The first chip is connected to the first conductive part and connected to the third conductive part via a lead wire; The second chip is connected to the third conductive part and connected to the second conductive part via a lead.

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