Copper-plated circuit board and copper plating process thereof

Abstract

The invention discloses a copper-plated circuit board and a copper plating process thereof, and relates to the technical field of circuit board manufacturing. The copper plating process of the circuit board comprises the following steps: after carrying out surface cleaning pretreatment on a dielectric substrate, injecting metal particles by adopting a high-energy ion beam to form a metal seed layer; performing magnetic filtering arc deposition treatment on the surface of the metal seed layer to form a metal bottom layer; and performing copper plating on the surface of the metal bottom layer through pulse magnetron sputtering treatment to form a copper foil layer combined with the dielectric substrate. According to the method, the metal particles are injected through the high-energy ion beam, then the metal layer is deposited on the surface in an electric arc mode, then copper plating is conducted through pulse magnetron sputtering, high-strength combination of the metal copper foil and the base material is achieved by combining physical vapor deposition and the ion injection technology, meanwhile, the surface roughness of the copper foil is low, and the requirements for reliability and low loss of the circuit board are met.

Description

Technical Field

[0001] This invention relates to the field of circuit board manufacturing technology, and more specifically, to a copper-plated circuit board and its copper plating process. Background Technology

[0002] Low-loss printed circuit boards (PCBs) are designed to reduce attenuation and loss caused by the electrical, thermal, and mechanical characteristics of the PCB. These PCBs are used in telecommunications, medical, aerospace, automotive, and other fields. Low-loss PCBs typically require reduced surface roughness of the copper foil to reduce signal loss at the interface layer. However, using low-roughness copper foil makes it difficult to achieve a high-strength bond with the dielectric substrate, leading to decreased reliability and making it difficult to simultaneously meet the requirements of reliability and reduced loss.

[0003] The conventional process for manufacturing high-precision printed circuit boards (PCBs) typically includes the following steps: material preparation, drilling, copper plating, pattern transfer, pattern electroplating, etching, and post-processing. The copper plating process generally employs chemical copper plating (PTH), the main purpose of which is to deposit a thin, uniform copper layer on the non-conductive surfaces of the PCB, such as insulating hole walls and certain specific non-copper foil areas, through a chemical reaction. This imparts conductivity to the originally non-conductive areas, laying the foundation for subsequent copper plating processes and ultimately achieving interlayer electrical interconnection on the PCB. However, using chemical reaction to deposit a thin copper layer on the substrate material only results in an electrostatic adsorption composite structure and chemical bonding. The peel strength between the copper foil and the substrate material is extremely low, making it easy for the copper foil traces to separate from the substrate under external force, increasing the risk of flyaway lines and reducing the overall reliability of the PCB product. Therefore, it is necessary to research a new copper plating process that can replace the conventional chemical copper plating process to prepare a conductive copper layer for interlayer electrical interconnection on the PCB, while achieving a high-strength bond between the copper foil and the substrate material and reducing the surface roughness of the copper foil, thus meeting the requirements of PCB reliability and low loss. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a copper plating process for circuit boards that can form copper foil with low surface roughness and can bond with the substrate material with high strength, thereby meeting the requirements of reliability and low loss of circuit boards.

[0005] One of the objectives of this invention is to provide a copper-plated circuit board.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A copper plating process for circuit boards is provided, including the following steps: S1, after the dielectric substrate is pretreated by surface cleaning, metal particles are implanted using a high-energy ion beam to form a metal seed layer; the metal particles are selected from at least one of Ni / Cu, Ni / Cr and Ni alloy, and the implantation dose is 10-100 keV. S2, magnetic filtering arc deposition is performed on the surface of the metal seed layer to form a metal underlayer; The magnetic filtering arc deposition process employs two deposition processes. The plasma for the first deposition is selected from at least one of Ni, Ni / Cu alloy, Ni / Ti alloy, and Ni / V alloy, while the plasma for the second deposition is selected from Cu. The process parameters for the magnetically filtered arc deposition are: vacuum degree ≤ 9 × 10⁻⁶. -3 Pa, generating current 60-160A, voltage 600-1500V, magnetic field strength 0.005-0.02T, bias voltage +20V~+50V; S3, copper is plated on the surface of the metal substrate by pulsed magnetron sputtering to form a copper foil layer bonded to the dielectric substrate.

[0007] The present invention does not impose any particular restrictions on the material of the dielectric substrate, and substrate materials with low dielectric constant (Dk) and dielectric loss factor (Df) in this technical field can be used; optionally, the dielectric substrate material includes, but is not limited to, bismaleimide triazine resin (BT), ABF, polytetrafluoroethylene (PTFE) and modified polyimide (PI).

[0008] In some embodiments, in step S1, the molar content of Ni in the metal particles is ≥60%; preferably, the molar ratio of the two elements in Ni / Cu or Ni / Cr is (7-9):(1-3).

[0009] In some embodiments, the process parameters for high-energy ion beam implantation of metal particles in step S1 are: pulse source voltage of 20-80kV and beam current intensity of 1-100eV.

[0010] In some embodiments, the high-energy ion beam implantation depth is 10-50 nm.

[0011] In some embodiments, in step S1, the surface cleaning pretreatment is plasma treatment, wherein the plasma is N2 and / or Ar, and the process parameters are: gas ion source voltage 400-1000V, duty cycle 10-40%, vacuum degree ≤5×10 -2 Pa.

[0012] In some embodiments, in step S2, the molar content of Ni in the plasma seed of the first deposition of the magnetically filtered arc deposition is ≥10%; this is beneficial to improving the bonding performance with the metal seed layer; preferably, the molar content of Ni in the Ni / Cu alloy, Ni / Ti alloy or Ni / V alloy is 20-60%.

[0013] In some embodiments, the process parameters for the magnetically filtered arc deposition in step S2 are: vacuum degree 1×10⁻⁶. -3 -9×10 -3 Pa, generating current 80-140A, voltage 800-1200V, magnetic field strength 0.008-0.15T, bias voltage +25V to +45V.

[0014] In some embodiments, the thickness of the metal substrate is 1-100 nm.

[0015] In some embodiments, in the pulsed magnetron sputtering process of step S3, the target material is Cu, the sputtering gas is N2 and / or Ar, and the process parameters are: pulse voltage of 400-1500V, pulse frequency of 20-200kHz, pulse width of 50-200μs, bias voltage of -100V to -600V, and bias frequency of 20-40kHz.

[0016] In some embodiments, the thickness of the copper foil layer is 0.1-1 μm.

[0017] The present invention also provides a copper-plated circuit board, which is manufactured using the copper plating process described above.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention discloses a copper plating process for circuit boards. First, metal particles are implanted using a high-energy ion beam. Then, a metal layer is deposited on the surface by electric arc and the process parameters are optimized. Next, copper is plated by pulsed magnetron sputtering. By combining physical vapor deposition and ion implantation technology, a high-strength bond is achieved between the copper foil and the substrate material. At the same time, the surface roughness of the copper foil is low, which meets the requirements of reliability and low loss of the circuit board. Detailed Implementation

[0019] To better illustrate the purpose, technical solution, and advantages of the present invention, the present invention will be further described below in conjunction with specific embodiments.

[0020] Example 1 A copper plating process for circuit boards includes the following steps: S1. After the dielectric substrate is pretreated by surface cleaning, metal particles are implanted using a high-energy ion beam to form a metal seed layer. Specifically, the surface cleaning pretreatment involves plasma treatment of the BT dielectric substrate to achieve surface cleaning and roughening. The plasma is Ar, and the process parameters are: gas ion source voltage 700V, duty cycle 25%, and vacuum degree 5×10⁻⁶. -2 Pa.

[0021] The high-energy ion beam implantation is performed as follows: the metal particles are selected from Ni / Cu, the molar ratio of Ni to Cu ions is 8:2, and the process parameters are: pulse source voltage is 40kV, beam current intensity is 40keV, implantation dose is 60keV, and implantation depth is 50nm below the surface.

[0022] S2, magnetic filtering arc deposition is performed on the surface of the metal seed layer to form a metal underlayer with a thickness of 50 nm. Specifically, the magnetic filtering arc deposition process employs two deposition processes. The first deposition uses a Ni / Cu plasma (molar ratio of 3:7), and the second deposition uses a Cu plasma. The process parameters are: vacuum degree 1×10⁻⁶. -3 Pa, generating current 100A, voltage 900V, magnetic field strength 0.01T, bias voltage +35V.

[0023] S3, copper is plated on the surface of the metal substrate by pulsed magnetron sputtering to form a copper foil layer with a thickness of 1µm that is bonded to the dielectric substrate.

[0024] Specifically, the pulsed magnetron sputtering process is as follows: the target material is Cu, the sputtering gas is Ar, and the process parameters are: pulse voltage is 800V, pulse frequency is 80kHz, pulse width is 100μs, bias voltage is -200V, and bias frequency is 25kHz.

[0025] Example 2 A copper plating process for circuit boards differs from Example 1 in that: the high-energy ion beam implantation conditions in this example are: the metal particles are selected from Ni / Cr, and the molar ratio of Ni to Cr ions is 8:2; the process parameters are: the pulse source voltage is 70kV, the beam current intensity is 70keV, the implantation dose is 70keV, and the implantation depth is 50nm below the surface layer.

[0026] Example 3 A copper plating process for circuit boards differs from Example 1 in that: the magnetically filtered arc deposition conditions in this example are as follows: the plasma for the first deposition is a Ni / Cu alloy (molar ratio of 3:7), and the plasma for the second deposition is selected from Cu; the process parameters are: vacuum degree 4×10 -3 Pa, generating current 130A, voltage 1300V, magnetic field strength 0.015T, bias voltage +45V.

[0027] Example 4 A copper plating process for circuit boards differs from Example 1 in that: the pulse magnetron sputtering conditions in this example are: the target material is Cu, the sputtering gas is N2; the process parameters are: pulse voltage is 1200V, pulse frequency is 150kHz, pulse width is 150μs, bias voltage is -500V, and bias frequency is 35kHz.

[0028] Comparative Example 1 A copper plating process for circuit boards differs from Example 1 in that this comparative example does not employ high-energy ion beam implantation of metal particles.

[0029] Comparative Example 2 A copper plating process for circuit boards differs from Example 1 in that this comparative example does not involve magnetic filtering arc deposition treatment.

[0030] Comparative Example 3 A copper plating process for circuit boards is described. In this comparative example, a copper plating layer with a thickness of 1 μm is prepared using a chemical copper plating process.

[0031] Performance testing The products of the copper plating process for circuit boards in the above embodiments and comparative examples were subjected to the following performance tests, and the results are shown in Table 1.

[0032] Peel strength: Tested according to the method of standard IPC-TM-650 2.4.8C. The copper thickness of the test sample is 12um. Test requirements: copper foil length is greater than 75mm, width is 3mm, test is not less than three times, and 90-degree tensile test is used.

[0033] Dielectric loss: Referencing standard IPC-TM-650 2.5.5.13, the transmission line method (microstrip / stripline) of a vector network analyzer (VNA) was used for testing. Specifically, a microstrip line was fabricated on the PCB, and the insertion loss and return loss of the microstrip line were measured using a network analyzer. Then, the dielectric loss Df was calculated based on transmission line theory and tested at a frequency of 10 GHz.

[0034] Table 1

[0035] As shown in Table 1, the copper-plated structure prepared by the copper plating process of the present invention has high peel strength and low dielectric loss, with peel strength ≥0.76N / mm and dielectric loss ≤0.007.

[0036] Compared to Example 1, Comparative Example 1 did not use high-energy ion beam implantation of metal particles, resulting in a significant decrease in its peel strength; Comparative Example 2 did not use magnetic filtering arc deposition, resulting in a significant decrease in its dielectric loss; while Comparative Example 3, prepared using chemical copper plating, had a lower peel strength and excessive dielectric loss.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A copper plating process for circuit boards, characterized in that, Includes the following steps: S1, after the dielectric substrate is pretreated by surface cleaning, metal particles are implanted using a high-energy ion beam to form a metal seed layer; the metal particles are selected from at least one of Ni / Cu, Ni / Cr and Ni alloy, and the implantation dose is 10-100 keV. S2, magnetic filtering arc deposition is performed on the surface of the metal seed layer to form a metal underlayer; The magnetic filtering arc deposition process employs two deposition processes. The plasma for the first deposition is selected from at least one of Ni, Ni / Cu alloy, Ni / Ti alloy, and Ni / V alloy, while the plasma for the second deposition is selected from Cu. The process parameters for the magnetically filtered arc deposition are: vacuum degree ≤ 9 × 10⁻⁶. -3 Pa, generating current 60-160A, voltage 600-1500V, magnetic field strength 0.005-0.02T, bias voltage +20V~+50V; S3, copper is plated on the surface of the metal substrate by pulsed magnetron sputtering to form a copper foil layer bonded to the dielectric substrate.

2. The circuit board copper plating process according to claim 1, characterized in that, The process parameters for high-energy ion beam implantation of metal particles in step S1 are: pulse source voltage of 20-80kV and beam current intensity of 1-100eV.

3. The circuit board copper plating process according to claim 1 or 2, characterized in that, The high-energy ion beam implantation depth is 10-50 nm.

4. The copper plating process for circuit boards according to claim 1, characterized in that, In step S1, the surface cleaning pretreatment is plasma treatment, in which the plasma is N2 and / or Ar, and the process parameters are: gas ion source voltage 400-1000V, duty cycle 10-40%, vacuum degree ≤5×10 -2 Pa.

5. The copper plating process for circuit boards according to claim 1, characterized in that, The process parameters for magnetically filtered arc deposition in step S2 are: vacuum degree 1×10⁻⁶. -3 -9×10 -3 Pa, generating current 80-140A, voltage 800-1200V, magnetic field strength 0.008-0.15T, bias voltage +25V to +45V.

6. The copper plating process for circuit boards according to claim 1, characterized in that, The thickness of the metal substrate is 1-100 nm.

7. The copper plating process for circuit boards according to claim 1, characterized in that, In the pulsed magnetron sputtering process of step S3, the target material is Cu, the sputtering gas is N2 and / or Ar, and the process parameters are: pulse voltage of 400-1500V, pulse frequency of 20-200kHz, pulse width of 50-200μs, bias voltage of -100V to -600V, and bias frequency of 20-40kHz.

8. The copper plating process for circuit boards according to claim 1, characterized in that, The thickness of the copper foil layer is 0.1-1 μm.

9. The circuit board copper plating process according to claim 1, characterized in that, The dielectric substrate is made of any one of PI, PET, ABF, and BT.

10. A copper-plated circuit board, characterized in that, The circuit board is manufactured using the copper plating process described in any one of claims 1-9.

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