Silicon carbide epitaxial wafer and preparation method thereof
By using segmented cooling and heat preservation methods, the problem of strong electrostatic force on the surface of silicon carbide epitaxial wafers was solved, which improved the accuracy of performance testing and production efficiency, and reduced costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-04-03
AI Technical Summary
Traditional silicon carbide epitaxial wafers have many dangling silicon bonds on their surface during the cooling process, resulting in strong electrostatic forces that affect the accuracy and yield of performance testing and increase costs.
By employing segmented cooling and heat preservation methods, the cooling rate and temperature are controlled. Through multiple cooling steps and heat preservation platforms, defects introduced by thermal stress are reduced, surface electrostatic forces are eliminated, and charge dissipation is promoted.
It improves the accuracy of performance testing of silicon carbide epitaxial wafers, reduces testing errors, increases production yield and efficiency, and reduces additional equipment costs.
Smart Images
Figure CN121781278A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to silicon carbide epitaxial wafers and methods for their preparation. Background Technology
[0002] Silicon carbide, as a third-generation semiconductor material, possesses advantages such as high thermal conductivity, high breakdown field strength, high saturated electron drift velocity, and high bonding energy. It effectively meets the application requirements of modern electronic technology under harsh conditions such as high temperature, high power, high voltage, high frequency, and high radiation, and plays a crucial role in next-generation high-voltage power electronic semiconductor devices. Silicon carbide devices are formed through a series of processes on silicon carbide epitaxial wafers. A silicon carbide epitaxial wafer consists of a silicon carbide substrate and a silicon carbide epitaxial layer.
[0003] In traditional silicon carbide epitaxial wafer fabrication methods, after the silicon carbide epitaxial layer has grown and cooled, the presence of numerous dangling silicon bonds on the surface results in strong surface electrostatic forces. This reduces the reliability of performance testing results, leading to inaccurate assessments of silicon carbide epitaxial wafer performance. For example, AFM testing may show morphological distortions, with images displaying stripes, bright or dark lines parallel to the scanning direction, or false bumps or depressions. Two scans of the same area may yield completely different results, making effective comparison impossible and directly causing misjudgments of epitaxial performance. Inaccurate performance assessments of silicon carbide epitaxial wafers directly result in decreased yield and increased costs. Summary of the Invention
[0004] Therefore, it is necessary to provide silicon carbide epitaxial wafers and their preparation methods. The silicon carbide epitaxial wafer preparation method of this application can effectively eliminate the electrostatic force on the surface of the silicon carbide epitaxial wafer, thereby improving the accuracy of the performance test results of the silicon carbide epitaxial wafer and achieving stable and reliable quality control and high-yield production.
[0005] In a first aspect, this application provides a method for preparing a silicon carbide epitaxial wafer, comprising the following steps:
[0006] A silicon carbide epitaxial layer is epitaxially grown on a silicon carbide substrate at a growth temperature to obtain a wafer to be cooled;
[0007] The cooling rate is controlled to a first cooling rate to cool the wafer to be cooled from the growth temperature to the first temperature.
[0008] The cooling rate is controlled to be a second cooling rate, and the wafer to be cooled is cooled from the first temperature to the second temperature and held at that temperature for a first preset time; the second cooling rate is lower than the first cooling rate.
[0009] The cooling rate is controlled to be a third cooling rate, and the wafer to be cooled is cooled from the second temperature to the wafer exit temperature and held at that temperature for a second preset time; the third cooling rate is lower than the second cooling rate.
[0010] In some embodiments, the first temperature is 200°C to 350°C lower than the growth temperature.
[0011] In some embodiments, the second temperature is 200°C to 400°C lower than the first temperature.
[0012] In some embodiments, the output temperature is 100°C to 300°C lower than the second temperature.
[0013] In some embodiments, the first temperature is 1300°C to 1400°C.
[0014] In some embodiments, the second temperature is 1000°C to 1100°C.
[0015] In some embodiments, the growth temperature is 1600℃~1650℃.
[0016] In some embodiments, the film output temperature is 800°C to 900°C.
[0017] In some embodiments, the second cooling rate is 15°C / min to 35°C / min lower than the first cooling rate.
[0018] In some embodiments, the third cooling rate is 5°C / min to 20°C / min lower than the second cooling rate.
[0019] In some embodiments, the first cooling rate is 30°C / min to 100°C / min.
[0020] In some embodiments, the second cooling rate is 15°C / min to 85°C / min.
[0021] In some embodiments, the third cooling rate is 10°C / min to 80°C / min.
[0022] In some implementations, the second preset time is shorter than the first preset time.
[0023] In some implementations, the first preset time is 3 to 8 minutes.
[0024] In some embodiments, the second preset time is 2 min to 6 min.
[0025] In some embodiments, the time to cool the wafer to be cooled from the first temperature to the second temperature is greater than the time to cool the wafer to be cooled from the growth temperature to the first temperature.
[0026] In some embodiments, the time for cooling the wafer to be cooled from the growth temperature to the first temperature is 2 min to 10 min.
[0027] In some embodiments, the time for cooling the wafer to be cooled from the first temperature to the second temperature is 3 min to 25 min.
[0028] In some embodiments, the time for cooling the wafer to be cooled from the second temperature to the wafer exit temperature is 2 min to 30 min.
[0029] Secondly, this application provides a silicon carbide epitaxial wafer, which is prepared by the above-described method for preparing a silicon carbide epitaxial wafer, including a silicon carbide substrate and a silicon carbide epitaxial layer located on the surface of the silicon carbide substrate.
[0030] Compared to traditional silicon carbide epitaxial wafer fabrication methods that involve rapid cooling from the growth temperature to the wafer exit temperature, the method described in this application incorporates multiple cooling steps and a holding platform for segmented cooling and holding after silicon carbide epitaxial growth. First, a relatively rapid first cooling rate is used to cool from the growth temperature. In the high-temperature region, the yield strength of the silicon carbide crystal is high, making it less prone to plastic deformation, allowing for safe and rapid cooling and saving process time. Then, a slower second cooling rate, lower than the first, is used to gradually cool to an intermediate temperature, the second temperature, and hold at this temperature for a first preset time. This slow cooling allows the lattice to relax through atomic diffusion, significantly reducing defects such as new dislocations and stacking faults introduced by thermal stress. Fewer defects mean fewer charge traps, thus reducing the "nests" that can fix charges at the source. During the holding period, surface atoms have sufficient energy to rearrange into a more stable structure, reducing surface dangling bonds. Subsequently, the wafer is cooled to the unwinding temperature at a third cooling rate lower than the second cooling rate and held at that temperature for a second preset time. Upon reaching the unwinding temperature, the silicon carbide epitaxial wafer surface reaches a dynamic equilibrium state, representing the optimal window for balance between surface state energy and thermal energy, effectively promoting charge dissipation. At this point, the rate of hydrogen atom desorption and the rate of re-adsorption passivation are equal, and the migration of surface atoms reaches the lowest energy stable configuration. The aforementioned cooling process provides conditions for the recombination and dissipation of surface charges, thereby eliminating electrostatic forces, which are then transferred to the wafer. Therefore, the silicon carbide epitaxial wafer preparation method of this application effectively eliminates and reduces electrostatic forces on the silicon carbide epitaxial wafer surface, thereby improving the accuracy of the test results for the epitaxial performance of the silicon carbide epitaxial wafer. Attached Figure Description
[0031] Figure 1This is a schematic diagram of the cooling process in a method for preparing a silicon carbide epitaxial wafer according to an embodiment of this application.
[0032] Figure 2 This is a schematic diagram of the cooling process in the traditional silicon carbide epitaxial wafer fabrication method.
[0033] Figure 3 The image shows the atomic force microscopy test results of the silicon carbide epitaxial wafer in Example 1.
[0034] Figure 4 The image shows the atomic force microscopy test results of the silicon carbide epitaxial wafer in Comparative Example 1. Detailed Implementation
[0035] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, a detailed description of specific embodiments of this application is provided below. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0037] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0039] The inventors discovered that in the current process of growing silicon carbide epitaxial layers via chemical vapor deposition, the reactant gases (SiH4 / SiHCl3, C3H8 / C2H4) react at high temperatures (typically >1600℃) to grow a silicon carbide epitaxial layer on the substrate. The high-temperature growth process (1600℃~1650℃) is generally carried out in a hydrogen atmosphere. Hydrogen (H2) decomposes into hydrogen atoms (H), which combine with dangling bonds on the silicon carbide surface to form Si-H and CH bonds. This "hydrogen termination" makes the surface very stable at the growth temperature, passivates the dangling bonds, and results in a low surface state density. After epitaxial growth is complete, the equipment is cooled to the wafer exit temperature, and the wafer begins to cool. Because the bond energy of the CH bond (~413 kJ / mol) is stronger than that of the Si-H bond (~318 kJ / mol), the Si-H bond first becomes unstable and undergoes breakage and desorption, while the CH bond is more stably retained. After cooling to the wafer exit temperature, the surface of the silicon carbide epitaxial layer mainly consists of stable CH bonds and a large number of unsaturated, re-exposed silicon dangling bonds. These dangling bonds introduce a high density of surface states (referred to as "surface state density") within the band gap. Due to the high surface state density of the silicon carbide epitaxial wafer, the surface silicon dangling bonds capture or release charge carriers, forming a fixed surface charge. Therefore, the surface exhibits significant electrostatic charge, and is strongly attracted to external objects when they approach.
[0040] Currently, the traditional method is to eliminate static electricity through external means. A common approach is to use ion blowers in all working areas to blow positive and negative ions onto the surface of the silicon carbide epitaxial wafer, neutralizing the static charge. However, ion blowers increase equipment costs. Besides this, changing epitaxial process parameters, such as temperature and silicon-to-carbon ratio, can improve surface charge to some extent; however, altering the process window can worsen other defects and reduce the quality of the silicon carbide epitaxial wafer.
[0041] This application provides a method for preparing silicon carbide epitaxial wafers that can eliminate surface electrostatic forces. The process is simple and easy to control. While improving the surface electrostatic forces of silicon carbide epitaxial wafers, it can also reduce production costs and improve production efficiency.
[0042] Reference Figure 1 As shown, based on this, one embodiment of this application provides a method for preparing a silicon carbide epitaxial wafer, comprising the following steps:
[0043] A silicon carbide epitaxial layer is epitaxially grown on a silicon carbide substrate at a growth temperature to obtain a wafer to be cooled;
[0044] The cooling rate is controlled to be the first cooling rate, and the wafer to be cooled is cooled from the growth temperature to the first temperature.
[0045] The cooling rate is controlled to be a second cooling rate, and the wafer to be cooled is cooled from a first temperature to a second temperature and held at that temperature for a first preset time; the second cooling rate is lower than the first cooling rate.
[0046] The cooling rate is controlled at a third cooling rate to cool the wafer from the second temperature to the wafer exit temperature and hold it at that temperature for a second preset time; the third cooling rate is lower than the second cooling rate.
[0047] Compared to traditional silicon carbide epitaxial wafer fabrication methods that directly cool from the growth temperature to the wafer exit temperature at a relatively fast cooling rate, the silicon carbide epitaxial wafer fabrication method of this application incorporates multiple cooling steps during the cooling stage after silicon carbide epitaxial growth, and includes a heat preservation platform for segmented cooling and heat preservation. (Refer to...) Figure 2 As shown, Figure 2 This is a schematic diagram of the cooling process in a traditional silicon carbide epitaxial wafer fabrication method, where the wafer is directly cooled from the growth temperature (T1) to the wafer exit temperature (T2). It is understood that after cooling to the exit temperature, the silicon carbide epitaxial wafer is transferred from the growth chamber to the sample placement chamber for further cooling, such as purging. In this application, the wafer to be cooled is cooled from the second temperature to the exit temperature and held at that temperature for a second preset time, followed by the wafer exit process. Subsequent cooling can be any cooling method available in the art, and is not limited in this application. Similarly, the silicon carbide epitaxial layer growth method in this application can also be selected from any growth method available in the art, and is not limited in this application.
[0048] Refer again Figure 1 As shown, exemplarily, Figure 1 In this diagram, T1 represents the growth temperature, T2 represents the wafer exit temperature, and T3 and T4 correspond to the first and second temperatures, respectively. Meanwhile, t1 to t3 represents the time from the growth temperature to the first temperature, t3 to t4 represents the time from the first temperature to the second temperature, t4 to t5 represents the first preset time for holding the wafer at the second temperature, t5 to t6 represents the time from the second temperature to the wafer exit temperature, and t6 to t2 represents the second preset time for holding the wafer at the wafer exit temperature. After t2 is reached, the wafer is exited.
[0049] First, a relatively fast initial cooling rate is used to cool the silicon carbide from the growth temperature. In the high-temperature region, the silicon carbide crystal has a high yield strength and is not prone to plastic deformation, allowing for safe and rapid cooling, saving process time. Then, a slower second cooling rate, lower than the initial rate, is used to cool the silicon carbide to an intermediate temperature (the second temperature), and this temperature is held for a first preset time. Slow cooling allows the lattice to relax through atomic diffusion, significantly reducing defects such as new dislocations and stacking faults introduced by thermal stress. Fewer defects mean fewer charge traps, thus reducing the "nests" that can fix charges at the source. During the holding period, surface atoms have sufficient energy to rearrange into a more stable structure, reducing dangling bonds on the surface. Subsequently, a third cooling rate, lower than the second rate, is used to cool the silicon carbide epitaxial wafer to the wafer exit temperature and held for a second preset time. When the wafer exit temperature is reached, the silicon carbide epitaxial wafer surface reaches a dynamic equilibrium state—the optimal window for surface state energy and thermal energy to balance, effectively promoting charge dissipation. At this point, the rate of hydrogen atom desorption and the rate of re-adsorption passivation are equal, and the migration of surface atoms reaches the stable configuration with the lowest energy. The aforementioned cooling process provides conditions for the recombination and dissipation of surface charges, thereby eliminating electrostatic forces, which are then transferred out of the wafer. In other words, the silicon carbide epitaxial wafer preparation method of this application effectively eliminates and reduces electrostatic forces on the surface of the silicon carbide epitaxial wafer, thereby improving the accuracy of the test results for the epitaxial performance of the silicon carbide epitaxial wafer.
[0050] In some embodiments, the first temperature is 200°C to 350°C lower than the growth temperature.
[0051] Optionally, the first temperature is 200°C, 225°C, 250°C, 275°C, 300°C, 325°C, or 350°C lower than the growth temperature, or the difference between the first temperature and the growth temperature can be within the range of any two of the above temperatures.
[0052] In some embodiments, the second temperature is 200°C to 400°C lower than the first temperature.
[0053] Optionally, the second temperature is 200°C, 220°C, 240°C, 260°C, 280°C, 300°C, 320°C, 340°C, 360°C, 380°C, or 400°C lower than the first temperature, or the difference between the second temperature and the first temperature can be within the range of any two of the above temperatures.
[0054] In some embodiments, the output temperature is 100°C to 300°C lower than the second temperature.
[0055] Optionally, the film output temperature is 100°C, 120°C, 140°C, 160°C, 180°C, 200°C, 220°C, 240°C, 260°C, 280°C, or 300°C lower than the second temperature, or the difference between the film output temperature and the second temperature can be within the range of any two of the above temperatures.
[0056] In some of these embodiments, the first temperature is 1300°C to 1400°C.
[0057] Optionally, the first temperature is 1300℃, 1320℃, 1340℃, 1360℃, 1380℃ or 1400℃, or the first temperature may be within the range of any two of the above temperatures.
[0058] In some embodiments, the second temperature is 1000°C to 1100°C.
[0059] By maintaining the temperature within the aforementioned second temperature range, the surface atoms of the silicon carbide epitaxial wafer have sufficient energy to rearrange into a more stable structure, effectively reducing surface dangling bonds. Optionally, the second temperature is 1000℃, 1020℃, 1040℃, 1060℃, 1080℃, or 1100℃, or it can be within any two of the aforementioned temperatures.
[0060] In some of these embodiments, the growth temperature is 1600°C to 1650°C.
[0061] Optionally, the growth temperature is 1600℃, 1610℃, 1620℃, 1630℃, 1640℃ or 1650℃, or the growth temperature may be within any two of the above temperatures.
[0062] In some embodiments, the output temperature is 800°C to 900°C.
[0063] Within the aforementioned wafer exit temperature range, when the wafer exit temperature is maintained, the surface of the silicon carbide epitaxial wafer reaches a "dynamic equilibrium" state, an optimal window for balancing surface state energy and thermal energy, effectively promoting charge dissipation. At this point, the rate of hydrogen atom desorption and the rate of re-adsorption passivation are equal, and the migration of surface atoms reaches the lowest energy stable configuration. Optionally, the wafer exit temperature is 800℃, 820℃, 840℃, 860℃, 880℃, or 900℃, or the wafer exit temperature can be within any two of the aforementioned temperatures.
[0064] In some embodiments, the second cooling rate is 15°C / min to 35°C / min lower than the first cooling rate.
[0065] Optionally, the second cooling rate may be lower than the first cooling rate by 15℃ / min, 18℃ / min, 20℃ / min, 22℃ / min, 25℃ / min, 28℃ / min, 30℃ / min, 32℃ / min, or 35℃ / min. Alternatively, the difference between the second cooling rate and the first cooling rate may be within the range of any two of the above cooling rates.
[0066] In some embodiments, the third cooling rate is 5°C / min to 20°C / min lower than the second cooling rate.
[0067] Optionally, the third cooling rate may be 5°C / min, 8°C / min, 10°C / min, 12°C / min, 15°C / min, 18°C / min, or 20°C / min lower than the second cooling rate, or the difference between the third cooling rate and the second cooling rate may be within the range of any two of the above cooling rates.
[0068] In some embodiments, the first cooling rate is 30°C / min to 100°C / min.
[0069] In the high-temperature region, silicon carbide crystals have high yield strength and are not prone to plastic deformation, thus allowing for safe and rapid cooling. Within the range of the aforementioned first cooling rate, process time can be saved. Optionally, the first cooling rate is 30℃ / min, 40℃ / min, 50℃ / min, 60℃ / min, 70℃ / min, 80℃ / min, 90℃ / min, or 100℃ / min; alternatively, the first cooling rate can be within the range of any two of the aforementioned cooling rates.
[0070] In some embodiments, the second cooling rate is 15°C / min to 85°C / min.
[0071] Within the range of the aforementioned second cooling rate, the lattice is allowed to relax through atomic diffusion, which can greatly reduce defects such as new dislocations and stacking faults introduced by thermal stress. Fewer defects mean fewer charge traps, thus reducing the number of holes that can fix charges at the source. This results in a better effect on eliminating electrostatic forces on the surface of the silicon carbide epitaxial wafer. Optionally, the second cooling rate is 15℃ / min, 25℃ / min, 35℃ / min, 45℃ / min, 55℃ / min, 65℃ / min, 75℃ / min, or 85℃ / min, or the second cooling rate can be within the range of any two of the above cooling rates.
[0072] In some embodiments, the third cooling rate is 10°C / min to 80°C / min.
[0073] Within the range of the aforementioned third cooling rate, the effect of eliminating electrostatic forces on the surface of the silicon carbide epitaxial wafer is better. Optionally, the third cooling rate is 10℃ / min, 20℃ / min, 30℃ / min, 40℃ / min, 50℃ / min, 60℃ / min, 70℃ / min, or 80℃ / min, or the third cooling rate may be within the range between any two of the aforementioned cooling rates.
[0074] In some implementations, the second preset time is shorter than the first preset time.
[0075] In some implementations, the first preset time is 3 to 8 minutes.
[0076] Optionally, the first preset time is 3 min, 4 min, 5 min, 6 min, 7 min or 8 min, or the first preset time can be within the range of any two of the above times.
[0077] In some implementations, the second preset time is 2 min to 6 min.
[0078] Optionally, the second preset time is 2 min, 3 min, 4 min, 5 min or 6 min, or the second preset time can be within the range of any two of the above times.
[0079] Within the range of the first and second preset times mentioned above, sufficient conditions can be provided for surface charge recombination and dissipation, while taking into account production costs and efficiency, and the effect of eliminating electrostatic forces on the surface of silicon carbide epitaxial wafers is good.
[0080] In some embodiments, the time to cool the wafer from the first temperature to the second temperature is longer than the time to cool the wafer from the growth temperature to the first temperature.
[0081] In some embodiments, the time for cooling the wafer from the growth temperature to the first temperature is 2 min to 10 min.
[0082] Optionally, the time for cooling the wafer from the growth temperature to the first temperature is 4 min to 7 min. More preferably, the time for cooling the wafer from the growth temperature to the first temperature is 2 min, 3 min, 4 min, 5 min, 6 min, 7 min, 8 min, 9 min, or 10 min, or the time for cooling the wafer from the growth temperature to the first temperature can also be within any two of the above-mentioned time ranges.
[0083] In some embodiments, the time for cooling the wafer from the first temperature to the second temperature is 3 min to 25 min.
[0084] Optionally, the time for cooling the wafer from the first temperature to the second temperature is 7 min to 15 min. More preferably, the time for cooling the wafer from the first temperature to the second temperature is 3 min, 5 min, 7 min, 10 min, 12 min, 15 min, 18 min, 20 min, 22 min, or 25 min, or the time for cooling the wafer from the first temperature to the second temperature can also be within any two of the above-mentioned time ranges.
[0085] In some embodiments, the time for cooling the wafer to be cooled from the second temperature to the wafer exit temperature is 2 min to 30 min.
[0086] Optionally, the time for cooling the wafer from the second temperature to the wafer exit temperature is 5 min to 10 min. More optionally, the time for cooling the wafer from the second temperature to the wafer exit temperature is 2 min, 5 min, 8 min, 10 min, 12 min, 15 min, 18 min, 20 min, 25 min, or 30 min, or the time for cooling the wafer from the second temperature to the wafer exit temperature can also be within any two of the above-mentioned time ranges.
[0087] Another embodiment of this application provides a silicon carbide epitaxial wafer, which is prepared by the above-described method for preparing a silicon carbide epitaxial wafer, and includes a silicon carbide substrate and a silicon carbide epitaxial layer located on the surface of the silicon carbide substrate.
[0088] The following are specific examples:
[0089] Example 1
[0090] Methods for preparing silicon carbide epitaxial wafers:
[0091] (1) A silicon carbide epitaxial layer is grown on a silicon carbide substrate at a growth temperature of 1650℃ to obtain a wafer to be cooled.
[0092] (2) Control the first cooling rate to 60℃ / min, and after 4.2min of cooling, the wafer to be cooled will be cooled to the first temperature of 1400℃.
[0093] (3) Control the second cooling rate to 40℃ / min, and slowly cool the wafer to be cooled to the second temperature of 1100℃ after 7.5min, and keep it at the second temperature for the first preset time of 5min.
[0094] (4) Control the third cooling rate to 32℃ / min, slowly cool down to the wafer exit temperature of 900℃ after 6.3min, and keep the wafer at the exit temperature for the second preset time of 5min to exit the silicon carbide epitaxial wafer.
[0095] Example 2
[0096] Methods for preparing silicon carbide epitaxial wafers:
[0097] (1) A silicon carbide epitaxial layer is grown on a silicon carbide substrate at a growth temperature of 1620℃ to obtain a wafer to be cooled.
[0098] (2) Control the first cooling rate to 50℃ / min, and after 6.4min of cooling, the wafer to be cooled will be cooled to the first temperature of 1300℃.
[0099] (3) Control the second cooling rate to 30℃ / min, slowly cool down to the second temperature of 1000℃ after 10min, and keep warm at the second temperature for the first preset time of 4min.
[0100] (4) Control the third cooling rate to 25℃ / min, slowly cool down to the wafer temperature of 800℃ after 8min, and keep the wafer at the wafer temperature for 3min for the preset time before wafering.
[0101] Comparative Example 1
[0102] Methods for preparing silicon carbide epitaxial wafers:
[0103] (1) A silicon carbide epitaxial layer is grown on a silicon carbide substrate at a growth temperature of 1600~1650℃ to obtain a wafer to be cooled.
[0104] (2) Cool the wafer to be cooled to 800℃~900℃, take 12min~18min, and cool at a rate of 50℃ / min~65℃ / min to unload the silicon carbide epitaxial wafer.
[0105] The silicon carbide epitaxial wafers prepared in Example 1 and Comparative Example 1 were subjected to atomic force microscopy (AFM) testing, referring to... Figure 3 and Figure 4 As can be seen, the AFM test results of the silicon carbide epitaxial wafer in Comparative Example 1 show a large number of obvious transverse stripes (appearing as white or black stripes), while the AFM test results of the silicon carbide epitaxial wafer in Example 1 show that the transverse stripe morphology completely disappears, exhibiting a continuous and uniform longitudinal texture. This is because the cooling method in Comparative Example 1 results in a strong surface electrostatic force on the silicon carbide epitaxial wafer. On the one hand, this force adsorbs impurities, causing interference with the test results; on the other hand, the strong surface electrostatic force interferes with the AFM probe, thus causing distortion of the test morphology. In contrast, the silicon carbide epitaxial wafer preparation method of this application in Example 1 can effectively eliminate the electrostatic force on the surface of the silicon carbide epitaxial wafer, reduce the test errors of characterization techniques such as AFM, and thus clearly present the intrinsic morphology of the sample.
[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0107] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims, and the specification and drawings can be used to interpret the content of the claims.
Claims
1. A method for preparing a silicon carbide epitaxial wafer, characterized in that, Includes the following steps: A silicon carbide epitaxial layer is epitaxially grown on a silicon carbide substrate at a growth temperature to obtain a wafer to be cooled; The cooling rate is controlled to a first cooling rate to cool the wafer to be cooled from the growth temperature to the first temperature. The cooling rate is controlled to be a second cooling rate, and the wafer to be cooled is cooled from the first temperature to the second temperature and held at that temperature for a first preset time; the second cooling rate is lower than the first cooling rate. The cooling rate is controlled to be a third cooling rate, and the wafer to be cooled is cooled from the second temperature to the wafer exit temperature and held at that temperature for a second preset time; the third cooling rate is lower than the second cooling rate.
2. The method for preparing a silicon carbide epitaxial wafer according to claim 1, characterized in that, The first temperature is 200°C to 350°C lower than the growth temperature; and / or, The second temperature is 200°C to 400°C lower than the first temperature; and / or, The output temperature is 100℃~300℃ lower than the second temperature.
3. The method for preparing a silicon carbide epitaxial wafer according to claim 1, characterized in that, The first temperature is 1300℃~1400℃; and / or, The second temperature is 1000℃~1100℃; and / or, The growth temperature is 1600℃~1650℃; and / or, The output temperature is 800℃~900℃.
4. The method for preparing a silicon carbide epitaxial wafer according to claim 1, characterized in that, The second cooling rate is 15°C / min to 35°C / min lower than the first cooling rate; and / or, The third cooling rate is 5°C / min to 20°C / min lower than the second cooling rate.
5. The method for preparing a silicon carbide epitaxial wafer according to claim 1, characterized in that, The first cooling rate is 30℃ / min to 100℃ / min; and / or, The second cooling rate is 15℃ / min to 85℃ / min; and / or, The third cooling rate is 10℃ / min to 80℃ / min.
6. The method for preparing a silicon carbide epitaxial wafer according to claim 1, characterized in that, The second preset time is less than the first preset time.
7. The method for preparing a silicon carbide epitaxial wafer according to claim 1, characterized in that, The first preset time is 3 min to 8 min; and / or, The second preset time is 2 min to 6 min.
8. The method for preparing a silicon carbide epitaxial wafer according to any one of claims 1 to 7, characterized in that, The time required to cool the wafer from the first temperature to the second temperature is greater than the time required to cool the wafer from the growth temperature to the first temperature.
9. The method for preparing a silicon carbide epitaxial wafer according to any one of claims 1 to 7, characterized in that, The time for cooling the wafer to be cooled from the growth temperature to the first temperature is 2 min to 10 min; and / or, The time for cooling the wafer from the first temperature to the second temperature is 3 min to 25 min; and / or, The time for cooling the wafer to be cooled from the second temperature to the wafer exit temperature is 2 min to 30 min.
10. A silicon carbide epitaxial wafer, characterized in that, The silicon carbide epitaxial wafer is prepared by the method of claim 9, comprising a silicon carbide substrate and a silicon carbide epitaxial layer located on the surface of the silicon carbide substrate.