Analysis method and device for determining distribution of two defects along channel of semiconductor device

Abstract

The invention discloses an analysis method and device for determining distribution of two defects of a semiconductor device along a channel, relates to the technical field of semiconductors, and aims to solve the problems that two defects cannot be positioned simultaneously and an analysis result is distorted in a traditional method. The method comprises the following steps: receiving pulse IV rapid test data of a target semiconductor device; extracting a first threshold voltage difference degradation amount between the linear region and the saturation region under the forward-scanning bias from the corresponding forward-scanning IV data before and after the stress, and extracting a second threshold voltage difference degradation amount between the linear region and the saturation region under the reverse-scanning bias from the corresponding reverse-scanning IV data before and after the stress; and determining distribution positions of interface defects and oxide layer defects in the target semiconductor device along a channel according to a magnitude relationship between the first threshold voltage difference degradation amount and the second threshold voltage difference degradation amount. The method is used for positioning the two defects of the semiconductor device distributed along the channel and improving the fidelity of an analysis result.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an analytical method and apparatus for determining the distribution of two types of defects along the channel of a semiconductor device. Background Technology

[0002] As semiconductor device dimensions continue to shrink, the mechanism of hot carrier degradation (HCD) also changes. In the stage of larger device sizes and higher operating voltages, the industry generally used the Lucky Electron model, which posits that hot carriers only generate interface defects at the drain, and that these interface defects are the sole critical factor leading to device degradation. During this stage, research focused on optimizing methods for extracting these interface defects.

[0003] However, as device operating voltage decreases and device size shrinks, the impact of cold carriers far from the drain on degradation becomes increasingly prominent, and oxide layer defects also become a significant factor that cannot be ignored. At this point, the limitations of traditional methods for extracting interface defects are fully exposed: on the one hand, they can only extract a single interface defect and cannot simultaneously determine the location of both types of defects; on the other hand, traditional methods require constantly interrupting the stress process to scan the target semiconductor device to obtain the relationship between drain current and gate voltage. - Due to technological limitations, early testing equipment required 500-1000 seconds to scan a curve. Without interrupting the stress, prolonged testing would cause additional defects in the device. However, after interrupting the stress, the difference between the scanning voltage and the stress voltage would introduce additional stress or a defect recovery process, severely affecting the accuracy of the test and ultimately leading to distorted defect location analysis results. Summary of the Invention

[0004] The purpose of this invention is to provide an analytical method and apparatus for determining the distribution of two types of defects along the channel in a semiconductor device. Based on pulse IV rapid test data, the method accurately determines the distribution location of interface defects and oxide layer defects along the channel in a target semiconductor device, thereby solving the problem that traditional methods cannot simultaneously locate two types of defects and result in distorted analysis results.

[0005] To achieve the above objectives, in a first aspect, the present invention provides an analytical method for determining the distribution of two types of defects along the channel in a semiconductor device, comprising: first, receiving pulse IV rapid test data of a target semiconductor device, the data covering forward and reverse scan IV data corresponding to the target semiconductor device before and after stress; next, extracting a first threshold voltage difference degradation amount between the linear region and the saturation region under forward bias from the forward scan IV data corresponding to the period before and after stress, and extracting a second threshold voltage difference degradation amount between the linear region and the saturation region under reverse scan bias from the reverse scan IV data corresponding to the period before and after stress; finally, determining the distribution positions of interface defects and oxide layer defects along the channel in the target semiconductor device based on the magnitude relationship between the first threshold voltage difference degradation amount and the second threshold voltage difference degradation amount.

[0006] Using the above technical solution, the analysis method provided by this invention first receives pulsed IV test data. This data is acquired using pulsed IV rapid testing technology and includes full-dimensional information on forward and reverse scans before and after stress, as well as linear and saturation regions. It retains significant signals sensitive to interface defects and also covers subtle current fluctuations caused by oxide layer defects, thus comprehensively characterizing the defect-related responses of the device under different states. Next, by extracting the first threshold voltage difference degradation and the second threshold voltage difference degradation, the two types of defect signals are effectively separated. Finally, a judgment is made based on the magnitude relationship between the two degradation values: if the first threshold voltage difference degradation is greater than the second threshold voltage difference degradation, the interface defect is determined to be close to the device drain; if the first threshold voltage difference degradation is less than the second threshold voltage difference degradation, the oxide layer defect is determined to be close to the device source. This is because defects at the separation interface and oxide layer are caused by hot and cold carriers. Oxide layer defects are generally considered to be contributed by cold carriers, while interface defects can be contributed by both hot and cold carriers. By analyzing the location of these defects, the dominant type of degradation defect can be inferred. Under the influence of the transverse electric field in the channel, carriers undergo an acceleration process from source to drain, with energy gradually increasing. Therefore, hot carriers are usually concentrated at the drain, and cold carriers are usually concentrated at the source. If the separated defect is close to the drain, it indicates that hot carriers play a major role in degradation, and the defect distribution is dominated by interface defects. Conversely, if the separated defect is close to the source, it indicates that cold carriers play a major role in degradation, and the defect distribution is dominated by oxide layer defects. This judgment logic directly adapts to the distribution characteristics and response patterns of both types of defects, achieving simultaneous localization of interface and oxide layer defects while avoiding the defect state distortion problem caused by interrupted stress in traditional methods. It provides precise guidance for process developers to optimize device structure and improve device reliability, helping to quickly locate the root cause of problems and accelerate the research and development iteration process of target semiconductor devices.

[0007] In one example, before receiving the test data, the method further includes: scanning the target semiconductor device to obtain the pulse IV rapid test data; Scanning the target semiconductor device to obtain the pulse IV rapid test data includes: Before and after stress is applied to the target semiconductor device, a voltage within a preset scanning voltage range is applied to the gate of the target semiconductor device based on the pulse IV rapid testing method. Forward and reverse scanning are performed on the linear and saturation regions of the target semiconductor device, respectively, to obtain the pulse IV rapid testing data between the drain current and the gate voltage. The upper limit of the preset scanning voltage range is the sum of the threshold voltage of the target semiconductor device and a preset voltage value, and the lower limit of the preset scanning voltage range is the difference between the threshold voltage of the target semiconductor device and the preset voltage value.

[0008] In one example, before scanning the target semiconductor device to obtain the pulse IV rapid test data, the method further includes: A reference device of the same type as the target semiconductor device is scanned to obtain the threshold voltage of the reference device before and after stress. The threshold voltage of the reference device is determined as the threshold voltage of the target semiconductor device.

[0009] In one example, the upper limit of the preset scan voltage range is less than the gate stress voltage during the stress application process.

[0010] In one example, determining the distribution location of interface defects and oxide layer defects along the channel in the target semiconductor device based on the relationship between the first threshold voltage difference degradation and the second threshold voltage difference degradation includes: If the degradation amount of the first threshold voltage difference is greater than the degradation amount of the second threshold voltage difference, it is determined that the interface defect is close to the drain terminal of the target semiconductor device; If the degradation amount of the first threshold voltage difference is less than the degradation amount of the second threshold voltage difference, then it is determined that the oxide layer defect is close to the source end of the target semiconductor device.

[0011] In one example, the degradation of the first threshold voltage difference between the linear region and the saturation region under forward bias is extracted from the forward scan IV data corresponding to the stress before and after, and the degradation of the second threshold voltage difference between the linear region and the saturation region under reverse scan bias is extracted from the reverse scan IV data corresponding to the stress before and after, including: The positive and negative IV data of the target semiconductor device before and after stress are fitted to the corresponding drain current versus gate voltage curves to obtain the positive scan data before and after stress. - Curves and reverse scans - curve; Positive scan before and after stress extraction - Threshold voltage of the curve and back scan - The threshold voltage of the curve is used to obtain the threshold voltage of the forward scan linear region, the threshold voltage of the forward scan saturation region, the threshold voltage of the reverse scan linear region, and the threshold voltage of the reverse scan saturation region before and after stress. Based on the threshold voltage of the linear region and the threshold voltage of the saturation region before and after stress, the degradation amount of the first threshold voltage difference is determined. The degradation amount of the second threshold voltage difference is determined based on the threshold voltage of the linear region and the threshold voltage of the saturation region before and after stress.

[0012] In one example, the degradation amount of the first threshold voltage difference is determined based on the threshold voltages of the linear region and the saturation region before and after stress, including: Formula used: The degradation amount of the first threshold voltage difference is calculated; where, This is the degradation amount of the first threshold voltage difference; The threshold voltage of the positive sweep linear region before stress; The threshold voltage of the positive sweep saturation region before stress; This is the threshold voltage of the positive scan linear region after stress. This is the threshold voltage of the positive sweep saturation region after stress. Based on the threshold voltages of the linear region and the saturation region before and after stress, the degradation amount of the second threshold voltage difference is determined, including: Formula used: The degradation amount of the second threshold voltage difference is calculated; where, This is the degradation amount of the second threshold voltage difference; The threshold voltage of the linear region before stress is the reverse scan. The threshold voltage of the reverse sweep saturation region before stress; The threshold voltage of the linear region after stress is the reverse scan. This is the threshold voltage of the saturation region after stress.

[0013] In one example, a positive scan is performed on the linear region and saturation region of the target semiconductor device, including: A preset first voltage is applied to the drain of the target semiconductor device in the linear region to perform a positive scan; A preset second voltage is applied to the drain of the target semiconductor device in the saturation region to perform a positive scan; Performing reverse scanning on the linear and saturation regions of the target semiconductor device, respectively, includes: The first voltage is applied to the source of the target semiconductor device in the linear region to perform a reverse scan; The second voltage is applied to the source of the target semiconductor device in the saturation region to perform a reverse scan.

[0014] In one example, the first voltage is less than the second voltage.

[0015] In a second aspect, the present invention also provides an analytical apparatus for determining the distribution of two types of defects along a channel in a semiconductor device, comprising: A receiving module is used to receive pulse IV rapid test data of a target semiconductor device; the pulse IV rapid test data includes forward scan IV data and reverse scan IV data of the target semiconductor device before and after stress. The extraction module is used to extract the first threshold voltage difference degradation amount between the linear region and the saturation region under forward bias from the forward scan IV data corresponding before and after the stress, and to extract the second threshold voltage difference degradation amount between the linear region and the saturation region under reverse bias from the reverse scan IV data corresponding before and after the stress. The determination module is used to determine the distribution location of interface defects and oxide layer defects along the channel in the target semiconductor device based on the relationship between the first threshold voltage difference degradation amount and the second threshold voltage difference degradation amount. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 One of the flowcharts of an analytical method for determining the distribution of two types of defects along the channel in a semiconductor device according to an embodiment of the present invention; Figure 2 A schematic diagram of a test waveform provided for one embodiment of the present invention; Figure 3 A schematic diagram illustrating parameter extraction using a constant current method under positive sweep bias, provided as an embodiment of the present invention; Figure 4 A second schematic flowchart of an analytical method for determining the distribution of two types of defects along the channel in a semiconductor device, provided as an embodiment of the present invention; Figure 5 To and Figure 4 A diagram showing the corresponding results; Figure 6A schematic diagram of the structure of an analytical apparatus for determining the distribution of two types of defects along a channel in a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0017] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0018] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0019] In the context of this invention, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if one layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] First, we analyze the scanning process of semiconductor devices using traditional methods. The scanning process of traditional methods is a periodic dynamic loop system based on early device characteristics and equipment limitations. Its core understanding comes from the physical mechanism of the drain-induced barrier lowering (DIBL) effect: when the drain voltage increases, the energy band peak near the drain terminal is suppressed, resulting in a decrease in the threshold voltage of the device. This effect causes a difference in the threshold voltage between the saturation region and the linear region of the device, which becomes a key electrical feature for analyzing interface defects near the drain terminal.

[0023] Based on this, the scanning process of traditional methods unfolds in the following stages.

[0024] Stage 1: Stress Induction.

[0025] Traditional methods for understanding defects are as follows: Interface defects refer to defects at the interface between the gate and channel in a semiconductor device, caused by factors such as hot carrier impacts. These defects significantly interfere with the drain current and can substantially change the threshold voltage of the device. They were considered the only degradation factor in early Lucky Electron models and are usually concentrated at the drain end.

[0026] Early devices were large (e.g., micrometer-scale) and operated at high voltages. The field followed the lucky electron model, assuming that hot carriers only generated interface defects at the drain, and that these defects were the sole cause of device degradation. Therefore, stress application was designed solely to excite drain interface defects. Typically, a positive voltage was applied to N-type devices and a negative voltage to P-type devices. This sustained stress for 500-10000 seconds ensured detectable interface defects at the drain. At this stage, oxide layer defects were considered negligible; therefore, only drain interface defects were considered, and there was no need to consider oxide layer defects that might be generated by low-energy, cold carriers concentrated at the source.

[0027] Of course, as technology advances and semiconductor devices become smaller, the impact of oxide layer defects has gradually gained attention.

[0028] Phase 2: Interruption and Testing.

[0029] (1) The previous method for extracting defect locations required constant interruption of the stress process due to factors such as slope fitting. - Multiple scans of the curve. Because of stress voltage and - The voltage during the scanning process varies. If the scanning voltage is greater than the stress voltage, additional electron trapping will occur. If the scanning voltage is less than the stress voltage, the trapped electrons will be released. This will have an additional impact on the extraction of post-stress defect locations, and it cannot be guaranteed that the obtained defect distribution is the result of stress. Therefore, the stress process should be shortened and simplified as much as possible to reduce additional electron trapping and release.

[0030] (2) Traditional methods - Curve scanning core logic.

[0031] Traditional scanning methods only focus on determining the location of interface defects, such as comparing the saturation current in forward and reverse scans, or comparing the current degradation in the linear and saturation regions. These methods can only characterize the spatial distribution of interface defects. This is because interface defects can significantly interfere with the current.

[0032] Phase 3: Result Judgment.

[0033] (1) Judgment logic has a singleness.

[0034] Because interface defects were initially considered to be the only factor in device degradation, traditional methods only focused on interface defects in their result judgments: after scanning, only the difference in operating current between the linear region and the saturation region during forward and reverse scanning was calculated, and the location of the interface defect was output based on the magnitude of the difference. If the difference was greater in forward scanning than in reverse scanning, the defect was determined to be at the drain end, and vice versa, without considering the existence of oxide layer defects at all.

[0035] The interference intensity of oxide layer defects on current is much smaller than that of interface defects. The threshold voltage change that they may cause can be completely masked by the signal of interface defects. Even if the scan data contains information about oxide layer defects, traditional methods do not have corresponding detection indicators and separation algorithms and cannot identify them. The reason is that the test logic does not match the defect type, rather than the fact that oxide layer defects did not exist in early devices.

[0036] (2) Latent causes of result deviation.

[0037] Traditional methods fail to recognize the problem of "scanning voltage interference after stress interruption": the scanning voltage differs from the original stress voltage. When the scanning voltage is higher than the stress voltage, the device will trap additional electrons; when the scanning voltage is lower than the stress voltage, the trapped electrons will be released. Both situations alter the original state of the defect, but early testing only focused on whether interface defects were detected, without verifying whether the defects were solely caused by the initial stress. This led to test results deviating from the true defect state, although this deviation was not highlighted in the early qualitative testing requirements of devices.

[0038] Phase 4: Iterative cycles lead to a vicious cycle of defect accumulation.

[0039] To obtain the "defect evolution law under different stress times", it is necessary to repeat the cycle of "stress application (extended time) - interruption - scan", for example, interrupt the test at stress of 1000s, 3000s and 5000s respectively, and compare the changes in threshold voltage difference at each stage.

[0040] Cyclic cycles have negative effects. The "scanning voltage interference" after each interruption accumulates. The first interruption leads to additional electron capture, and the second interruption may release electrons on top of that. The final measured defect distribution is the result of the superposition of "initial stress defects and multiple test interference defects", which deviates more and more from the true "stress-defect evolution law". Especially after the device size is reduced (the proportion of cold carrier defects increases), this deviation will completely mask the signal of oxide layer defects.

[0041] The invention will now be described in detail. In recent years, high-precision fast pulse generators, high-speed current sensors, and other equipment have matured, enabling the realization of Pulse IV rapid testing technology (also known as Pulse IV rapid testing). Its testing time is only 1ns to 2s, providing a possibility to overcome traditional limitations. This technology can rapidly scan a small range near the threshold voltage, avoiding interference from long-term testing and eliminating the need to interrupt the stress process. It is precisely because those in the art have realized that, driven by three factors—the importance of both types of defects, technological maturity, and the need for precise testing due to device miniaturization—there is an urgent need for new defect location analysis methods that can simultaneously analyze and determine how interface defects and oxide layer defects are distributed along the channel.

[0042] Specifically, such as Figure 1 As shown, this embodiment of the invention provides an analytical method for determining the distribution of two types of defects along the channel in a semiconductor device. This method can simultaneously analyze and locate the distribution positions of interface defects and oxide layer defects along the channel in a target semiconductor device. The method may include: Step 100: Receive the pulse IV rapid test data of the target semiconductor device; the pulse IV rapid test data includes the forward scan IV data and reverse scan IV data of the target semiconductor device before and after stress.

[0043] Understandably, the target semiconductor device needs to be scanned before receiving the pulse IV fast test data to obtain the aforementioned pulse IV fast test data.

[0044] Combination Figure 2 It is known that scanning the target semiconductor device to obtain pulse IV rapid test data includes: Before and after stress is applied to the target semiconductor device, a voltage within a preset scanning voltage range is applied to the gate of the target semiconductor device using a pulse IV rapid testing method. Forward and reverse scans are performed on the linear and saturation regions of the target semiconductor device, respectively, to obtain the drain current. With gate voltage The pulse IV rapid test data between; wherein, the upper limit of the preset scan voltage range is the sum of the threshold voltage of the target semiconductor device and the preset voltage value, and the lower limit of the preset scan voltage range is the difference between the threshold voltage of the target semiconductor device and the preset voltage value; in other words, The threshold voltage is the threshold voltage corresponding to the gate of the target semiconductor device.

[0045] A positive scan is performed on the linear and saturation regions of the target semiconductor device, including: A preset first voltage is applied to the drain of the target semiconductor device in the linear region to perform a positive scan; A preset second voltage is applied to the drain of the target semiconductor device in the saturation region to perform a positive scan; the first voltage is less than the second voltage. The linear and saturation regions of the target semiconductor device are scanned in reverse, including: A first voltage is applied to the source of the target semiconductor device in the linear region to perform a reverse scan; A second voltage is applied to the source of the target semiconductor device in the saturation region to perform a reverse scan.

[0046] Specifically, the test time for the pulse IV rapid test method is 1 ns to 2 s.

[0047] For example, the first voltage is 0.05V~0.1V.

[0048] For example, the second voltage is 0.7V~1V.

[0049] For example, the preset voltage value is 0.1V~0.4V.

[0050] Preferably, the preset voltage value is 0.2V.

[0051] It should be noted that in the analytical method for determining the distribution of two types of defects along the channel in semiconductor devices according to the present invention, the upper limit of the preset scanning voltage range based on pulse IV rapid testing is the sum of the threshold voltage of the target semiconductor device and the preset voltage value. Under the conventional parameter configuration of the target semiconductor device, that is, when the device threshold voltage is in the typical operating range, the preset voltage value is usually 0.1V~0.4V, while the upper limit of the preset scanning voltage range is (always) less than the gate stress voltage during the stress application process, and the gate-source stress voltage is usually 1~4V. This voltage relationship design can avoid additional electron trapping or releasing caused by the test voltage, ensuring that the pulse IV testing process does not change the original state of the stress-induced defects, and providing a high-fidelity data basis for the subsequent accurate analysis of the two types of defects.

[0052] In one specific implementation, combined with Figure 2 The process of acquiring pulse IV rapid test data, which is also the scanning process of the target semiconductor device, is illustrated in chronological order and includes the following stages.

[0053] Phase 1: First forward scan, also known as the forward scan before stress.

[0054] Referring to Figure 2, during the pre-stress scanning phase, a preset scanning voltage range is applied to the gate. The voltage.

[0055] Positive scan in the linear region: Apply the first voltage to the drain. (For example Figure 2 The 0.05V in the figure is the drain voltage. At this time, the target semiconductor device is operating in the linear region. When the gate scanning voltage varies within the range, the drain current is recorded. With gate voltage The corresponding relationship was used to obtain the positive scan IV data of the linear region before stress.

[0056] Forward scan in the saturation region: Apply a second voltage to the drain. (For example Figure 2 In That is, the drain voltage. At this time, the target semiconductor device is operating in the saturation region. Similarly, as the gate scanning voltage range changes, the drain current is recorded. With gate voltage The corresponding relationship was used to obtain the positive scan IV data of the pre-stress saturation region.

[0057] Phase Two: First backscan, also known as pre-stress backscan.

[0058] During the first reverse scan phase, a preset scan voltage range is still applied to the gate. The voltage.

[0059] Reverse scanning in the linear region: Apply a first voltage to the source. That is, the source voltage At this time, the target semiconductor device is operating in the linear region. When the gate scanning voltage varies within the range, the drain current is recorded. With gate voltage The corresponding relationship was used to obtain the inverse scan IV data of the linear region before stress.

[0060] Reverse scanning in the saturation region: Apply a second voltage to the source. That is, the source voltage At this time, the target semiconductor device is operating in the saturation region. Similarly, as the gate scanning voltage range changes, the drain current is recorded. With gate voltage The corresponding relationship was used to obtain the back-scan IV data of the pre-stress saturation region.

[0061] Phase 3: Stress application process.

[0062] refer to Figure 2 During the stress phase, the same stress voltage is applied to both the gate and drain. That is, gate voltage ,in, The value is set to 1~4V as mentioned above. The target semiconductor device is subjected to this stress condition for 500~10000s to complete the stress process. Specifically, a positive voltage is applied to the N-type target semiconductor device to capture electrons, and a negative voltage is applied to the P-type target semiconductor device to capture holes.

[0063] Stage 4: Second forward scan, also known as post-stress forward scan.

[0064] Referring to Figure 2, a preset scan voltage range is applied to the gate. The voltage.

[0065] Positive scan in the linear region: Apply the first voltage to the drain. (For example Figure 2 The 0.05V in the figure is the drain voltage. At this time, the target semiconductor device is operating in the linear region. When the gate scanning voltage varies within the range, the drain current is recorded. With gate voltage The corresponding relationship was used to obtain the positive scan IV data of the linear region after stress.

[0066] Forward scan in the saturation region: Apply a second voltage to the drain. (For example Figure 2 In That is, the drain voltage. At this time, the target semiconductor device is operating in the saturation region. Similarly, as the gate scanning voltage range changes, the drain current is recorded. With gate voltage The corresponding relationship was used to obtain the positive scan IV data of the post-stress saturation region.

[0067] Phase 5: Second back-scan, also known as post-stress back-scan.

[0068] See Figure 2 During the second reverse scan phase, a preset scan voltage range is still applied to the gate. The voltage.

[0069] Reverse scanning in the linear region: Apply a first voltage to the source. That is, the source voltage At this time, the target semiconductor device is operating in the linear region. When the gate scanning voltage varies within the range, the drain current is recorded. With gate voltage The corresponding relationship was used to obtain the inverse scan IV data of the linear region after stress.

[0070] Reverse scanning in the saturation region: Apply a second voltage to the source. That is, the source voltage At this time, the target semiconductor device is operating in the saturation region. Similarly, as the gate scanning voltage range changes, the drain current is recorded. With gate voltage The corresponding relationship was used to obtain the inverse scan IV data of the post-stress saturation region.

[0071] By performing the above five stages in sequence, the forward and reverse IV data of the target semiconductor device before and after stress can be obtained completely, which is the required pulse IV rapid test data.

[0072] It should be further noted that, in the process of acquiring pulse IV rapid test data in this invention, the core equipment for achieving rapid testing of 1ns~2s consists of a pulse signal generation system and a high-speed current acquisition system. The two work together to meet the requirements of short-time, low-interference data acquisition, and their specific functions are as follows: The core function of a pulse signal generation system is to precisely apply a preset voltage signal to the gate, drain, and source of a target semiconductor device. A pulse signal generation system consists of two key components: a pulse generator and a precision voltage control module.

[0073] The pulse generator can generate a fast scanning voltage within the range of "threshold voltage ± preset voltage value" with a voltage switching speed of nanoseconds. It can complete the full range scanning of the gate voltage in a very short time, avoiding the problem of excessive time consumption caused by point-by-point acquisition in traditional equipment. The precision voltage control module can apply the first voltage in the linear region and the second voltage in the saturation region to the drain and source respectively, and the voltage output has high stability, ensuring that the voltage deviation in different test stages is controllable and reducing interference to defect signals.

[0074] The core function of the high-speed current acquisition system is to synchronously record the changes in drain current Id during the gate voltage scan.

[0075] The high-speed current acquisition system has the following key characteristics: High-speed sampling rate. The sampling rate can reach the gigahertz (GHz) level, which can capture the subtle current fluctuations caused by oxide layer defects. These fluctuations have short time scales and small amplitudes, and are easily missed by traditional low-sampling-rate devices;

[0076] It features low-noise amplification. It can accurately amplify weak current signals (such as nA or even pA level) and convert them into digital signals, avoiding signal distortion and ensuring the accuracy of subsequent threshold voltage extraction.

[0077] Using the above technical solution, in this embodiment of the invention, the target semiconductor device is first scanned to obtain pulse IV rapid test data, and then the computer device receives the pulse IV rapid test data for subsequent analysis and positioning. The process of acquiring pulse IV rapid test data has the following technical advantages.

[0078] 1) Traditional forward and reverse scanning methods suffer from limited testing logic and conditions, making them unable to capture oxide layer defect information and only applicable to interface defects. The design of traditional forward and reverse scanning methods focuses solely on determining the location of interface defects. The core principle is to extract the threshold voltages of the linear and saturation regions, using the difference to determine the location of interface defects at the drain and source ends. The testing logic is entirely geared towards interface defects, lacking specific design for oxide layer defects. Furthermore, traditional methods are time-consuming, with single scans lasting 500-1000 seconds, requiring stress interruption before testing. During this interruption, oxide layer defects may recover naturally due to the disappearance of stress, masking subtle current fluctuations. The scanning voltage range is large. Because the difference between the scanning voltage and the stress voltage is large after the interruption, the subtle current fluctuations of oxide layer defects will be completely masked by the electron capture or release signals caused by the scanning voltage interference, and cannot be effectively identified.

[0079] The embodiments of the present invention have made breakthroughs in both forward and reverse scanning in terms of testing timing and voltage control, thereby achieving comprehensive capture of information on both types of defects.

[0080] From the perspective of uninterrupted testing, based on pulse IV rapid testing technology, the forward and reverse scans of this invention can be completed quickly before and after stress application without interrupting the stress. The state of oxide layer defects remains stable under continuous stress, and its minute current fluctuations will not be recovered or distorted due to stress interruption, ensuring the authenticity of the signal.

[0081] From the perspective of precise voltage control and minimal interference, the preset scanning voltage range is strictly limited to "threshold voltage ± preset voltage value". This means that the scanning voltage always revolves around the core operating range of the device, and the difference between it and the stress voltage is controllable, which greatly reduces the masking of subtle signals of oxide layer defects by scanning voltage interference. The forward and reverse scan voltages (such as the first voltage in the linear region and the second voltage in the saturation region) in the linear region and saturation region are designed in a reasonable way, so that the current response differences of oxide layer defects in different working regions can be accurately captured. For example, the current fluctuation pattern of oxide layer defects in the saturation region is significantly different from that of interface defects.

[0082] In short, the forward and reverse scanning process of traditional methods is a local operation with a single purpose and limited conditions, which can only serve interface defects; while the forward and reverse scanning of this invention is a systematic data acquisition under full-scene and precise control, which comprehensively adapts to the detection of two types of defects in terms of test timing and test voltage, thus obtaining more comprehensive information.

[0083] 2) This invention solves the problems of excessively long testing time and stress interruption in traditional methods. Traditional testing requires 500-1000 seconds for a single scan, forcing stress interruption and resulting in scanning voltage interference and unstable defect states after the interruption. The data acquisition process in this embodiment is based on pulse IV rapid testing technology, with an extremely short testing time of 1ns~2s. Testing can be quickly inserted before and after stress without interrupting the stress, avoiding the additional defect generation caused by long scanning time and the change in defect state caused by stress interruption. At the same time, the preset scanning voltage range is "threshold voltage ± preset voltage value". The scanning voltage surrounds the core working range of the device, and the difference with the stress voltage is controllable, which greatly reduces the risk of electron trapping and electron release caused by scanning voltage interference and ensures the authenticity of the defect state.

[0084] 3) Solving the problem of defect accumulation caused by iterative cycles in traditional methods. Traditional IV testing requires repeating a "stress application-interruption-scan" cycle. Each interruption in the scan voltage causes accumulated interference, resulting in a measured defect distribution that is a superposition of initial stress defects and multiple test-interference defects, deviating significantly from the true stress and defect evolution patterns. In this embodiment, the IV data acquisition process, due to the absence of stress interruption in pulsed IV testing, allows for rapid data acquisition multiple times at preset time intervals during a single continuous stress application. For example, within a stress period of 5000 seconds, data acquisition is completed in 2-second intervals at 1000s, 3000s, and 5000s, without interruption. This avoids the accumulation of interference caused by multiple interruptions, thus accurately restoring the true correspondence between stress time and defect evolution.

[0085] Next, step 200 is performed: extract the first threshold voltage difference degradation amount between the linear region and the saturation region under forward bias from the forward scan IV data corresponding before and after stress, and extract the second threshold voltage difference degradation amount between the linear region and the saturation region under reverse bias from the reverse scan IV data corresponding before and after stress.

[0086] Finally, step 300 is performed: based on the relationship between the first threshold voltage difference degradation amount and the second threshold voltage difference degradation amount, the distribution location of interface defects and oxide layer defects along the channel in the target semiconductor device is determined.

[0087] Using the above technical solution, this invention, through its three core processes of receiving pulse IV rapid test data, extracting threshold voltage difference degradation, and determining defect distribution locations, not only achieves simultaneous determination of two types of defects but also improves measurement accuracy. The advantages of the pulse IV rapid test data testing process have already been analyzed and will not be repeated here. This embodiment of the invention specifically extracts the first threshold voltage difference degradation in the linear and saturation regions under forward bias and the second threshold voltage difference degradation under reverse bias from the pulse IV rapid test data. By comparing the stress before and after and the differences between forward and reverse scans, the signals of interface defects and oxide layer defects are distinguished. The influence of interface defects on the threshold voltage difference is more significant in forward scans, while the influence of oxide layer defects is more prominent in reverse scans. The signal characteristics of the two types of defects are separated by the difference in degradation, overcoming the shortcomings of traditional methods that can only calculate a single threshold voltage difference, cannot distinguish between two defect types, and result in distorted defect analysis results.

[0088] In one example, it is understood that the method further includes, prior to scanning the target semiconductor device to obtain pulse IV rapid test data: Scan a reference device of the same type as the target semiconductor device to obtain the threshold voltage of the reference device before and after stress. The threshold voltage of the reference device is determined as the threshold voltage of the target semiconductor device.

[0089] In practice, a reference device of the same type as the target semiconductor device is scanned using the same pulse IV rapid test method to obtain the threshold voltage of the reference device before and after stress.

[0090] The beneficial technical effects of this embodiment are as follows: 1) It avoids introducing additional defects into the target semiconductor device due to threshold voltage testing. If the target semiconductor device is directly scanned across the entire voltage range to obtain the threshold voltage, it will trigger the non-stress voltage interference problem analyzed above. That is, there is a difference between the scan voltage and the stress voltage, which may lead to additional electron capture or release of captured electrons, changing the original defect state of the target semiconductor device. This would prevent the subsequent pulse IV rapid test data from reflecting the purely stress-induced defect signal. In this embodiment, the threshold voltage is obtained through a reference device of the same type. Therefore, the target semiconductor device does not need to undergo a full voltage range scan. It only needs to be scanned within a small range of ±0.1~0.4V of the reference device threshold voltage. This completely avoids the additional electrical stress caused by the full voltage scan and ensures that the defect state of the target semiconductor device is always the original stress-induced state, providing a high-fidelity data basis for determining the accurate separation and location of the two types of defects.

[0091] 2) Improved testing efficiency. The threshold voltages of similar semiconductor devices have good consistency, eliminating the need for a separate full voltage threshold scan for each target semiconductor device. Threshold voltage data can be reused by testing only a small number of reference devices, reducing repetitive testing steps. Especially in batch testing scenarios, this can significantly shorten the overall testing time, which aligns with the efficient design logic of pulse IV rapid testing.

[0092] The reference device is of the same type as the target semiconductor device, and its threshold voltage can accurately reflect the typical operating voltage range of the target semiconductor device. The ±0.1~0.4V scanning range set based on this threshold voltage can cover the defect-sensitive area without introducing redundant signals or interference due to an excessively large scanning range, ensuring the relevance and effectiveness of the pulse IV rapid test data, and further improving the identification of defect signals.

[0093] 3) Reduce target semiconductor device losses and testing costs. Full-voltage range scanning can cause electrical stress losses to semiconductor devices, especially for high-precision, high-value semiconductor devices, where frequent full-voltage scanning may affect their performance stability. Using a reference device as a substitute can reduce unnecessary electrical stress exposure to the target semiconductor device, reduce losses, and protect the original performance state of the target semiconductor device.

[0094] In one example, step 200: extracting the first threshold voltage difference degradation amount between the linear region and the saturation region under forward bias from the forward scan IV data corresponding before and after stress, and extracting the second threshold voltage difference degradation amount between the linear region and the saturation region under reverse bias from the reverse scan IV data corresponding before and after stress, including: Step 1: Fit the forward and reverse scan IV data of the target semiconductor device before and after stress to the corresponding drain current versus gate voltage curves, thus obtaining the forward scan data before and after stress. - Curves and reverse scans - curve; In practice, step 1 includes: The linear region data in the pre-stress forward scan IV data is fitted to the pre-stress forward scan linear region. - curve; The saturation region data in the pre-stress forward scan IV data is fitted to the pre-stress forward scan saturation region. - curve; The linear region data in the pre-stress back-scan IV data is fitted to the pre-stress back-scan linear region. - curve; The saturation region data in the pre-stress back-scan IV data is fitted to the pre-stress back-scan saturation region. - curve; The linear region data in the post-stress forward scan IV data is fitted to the post-stress forward scan linear region. - curve; The saturation region data in the post-stress forward scan IV data are fitted to the post-stress forward scan saturation region. - curve; The linear region data in the post-stress scan IV data is fitted to the post-stress scan linear region. - curve; The saturation region data in the post-stress scanned IV data are fitted to the post-stress scanned saturation region. - curve.

[0095] Step 2: Extract the corresponding forward scan before and after stress. - Threshold voltage of the curve and back scan - The threshold voltage of the curve is used to obtain the threshold voltage of the forward scan linear region, the threshold voltage of the forward scan saturation region, the threshold voltage of the reverse scan linear region, and the threshold voltage of the reverse scan saturation region before and after stress. Corresponding to the first step, the second step is essentially to extract the linear region before stress scanning. - Curve, pre-stress positive sweep saturation region - Curves, pre-stress reverse scan linear region - Curves, pre-stress back-scan saturation region - Curves, post-stress forward scan linear region - Curve, post-stress positive sweep saturation region - Curves, post-stress backscan linear region - Curves, post-stress backscan saturation region - These 8 curves - Each of the curves - The threshold voltage of the curve itself is used to obtain the threshold voltage of the positive sweep linear region before stress. Threshold voltage of the positive sweep saturation region before stress Threshold voltage in the positive scan linear region after stress Threshold voltage of the positive sweep saturation region after stress Threshold voltage in the linear region before stress scan Threshold voltage of the saturation region before stress scan Threshold voltage in the linear region after stress scan Threshold voltage of the saturation region after stress scan .

[0096] The second step is as follows: scan from the forward scan... - Curves and reverse scans - Extract the corresponding threshold voltage from the curve.

[0097] See Figure 3 To use the constant current method from the positive scan - Taking the extraction of the threshold voltage corresponding to the curve as an example, for each curve... - The process of extracting the threshold voltage of the curve is illustrated by way of example.

[0098] Figure 3 The horizontal axis represents the gate voltage. The vertical axis represents the drain current. The diagram contains 4 core lines. - Curve: Linear region before stress scanning - Curve, pre-stress positive sweep saturation region - Curves, post-stress forward scan linear region - Curves, post-stress forward scan linear region - The curve and a blue reference current line, with "fresh" and "aged" being key labels used to distinguish the device's state before and after stress application, are shown below. The extraction process using the constant current method is as follows: Setting a fixed reference current: Based on the device type (N-type or P-type) and the test standard, a fixed reference current value is set, i.e. Figure 3 The blue horizontal curve represents the current value, which is typically the characteristic current of the device in the on-state and is used to define the critical state of the target semiconductor device from cutoff to conduction.

[0099] Positioning the curve intersection point: Place the blue reference current line (current value is...) ) and the 8 lines generated in step 1 - The curves intersect one by one, and the x-coordinate of each intersection point is the threshold voltage corresponding to that curve. Figure 4 The annotation: Blue reference line and stress pre-scan linear region - curve( Figure 3 The intersection of the two black curves on the left and right sides → (Threshold voltage in the linear region before stress scanning, simplified in the figure) ); Blue reference line and pre-stress saturation region - curve( Figure 3 The intersection of the leftmost black curve in the middle → (Threshold voltage of the saturation region before stress scanning, simplified in the figure) ); Blue reference line and post-stress scanning linear region - curve( Figure 3 The intersection of the two red curves on the right side of the middle section → (The threshold voltage in the linear region after stress scanning is simplified in the figure as follows) ); Blue reference line and post-stress scan saturation region - curve( Figure 3Intersection of the red curve on the right side of the middle line → (The threshold voltage of the saturation region after stress scanning is simplified in the figure as follows) ).

[0100] The core advantage of the constant current method is the unified judgment standard: by fixing the reference current, the threshold voltage extraction deviation caused by the difference in curve slope is avoided, ensuring the comparability of the eight threshold voltages.

[0101] It should be noted that the present invention can extract the threshold voltage not only using the constant current method, but also using other methods, and there is no limitation on this.

[0102] Step 3: Determine the degradation amount of the first threshold voltage difference based on the threshold voltage of the linear region and the threshold voltage of the saturation region before and after stress. The degradation amount of the second threshold voltage difference is determined based on the threshold voltage of the linear region and the threshold voltage of the saturation region before and after stress.

[0103] In the third step, based on the threshold voltages of the linear region and the saturation region before and after stress, the degradation amount of the first threshold voltage difference is determined, including: Formula used: (1) The degradation amount of the first threshold voltage difference is calculated; where, This represents the degradation amount of the first threshold voltage difference; The threshold voltage of the positive sweep linear region before stress; The threshold voltage of the positive sweep saturation region before stress; This is the threshold voltage of the positive scan linear region after stress. This is the threshold voltage of the positive sweep saturation region after stress. Based on the threshold voltages of the linear region and the saturation region before and after stress, the degradation amount of the second threshold voltage difference is determined, including: Formula used: (2) The degradation amount of the second threshold voltage difference is calculated; where, This represents the degradation amount of the second threshold voltage difference. The threshold voltage of the linear region before stress is the reverse scan. The threshold voltage of the reverse sweep saturation region before stress; The threshold voltage of the linear region after stress is the reverse scan. This is the threshold voltage of the saturation region after stress.

[0104] Finally, based on the degradation amount of the first threshold voltage difference Difference from the second threshold voltage The size relationship is used to determine the distribution location of interface defects and oxide layer defects along the channel in the target semiconductor device, including: If the degradation amount of the first threshold voltage difference is greater than the degradation amount of the second threshold voltage difference, that is... If the interface defect is close to the drain of the target semiconductor device, then it is determined that the interface defect is close to the drain of the target semiconductor device. If the degradation amount of the first threshold voltage difference is less than the degradation amount of the second threshold voltage difference, that is... If the oxide layer defect is located near the source end of the target semiconductor device, then it is determined that the defect is close to the source end of the target semiconductor device.

[0105] In one specific embodiment, combined with Figure 4 and Figure 5 This paper provides a flowchart of the analytical method for determining the distribution of two types of defects along the channel in semiconductor devices.

[0106] See Figure 4 By performing pre-stress, stressed, and post-stress scans on the target semiconductor device, the linear region and saturation region of the pre-stress scan can be obtained. - Curves, linear region and saturation region before stress scan - Curves, linear region and saturation region after stress positive sweep - Curves and post-stress backscan linear and saturation regions - curve.

[0107] From the linear region and saturation region before stress scanning - Curve extraction forward scan and .

[0108] From the pre-stress back scan linear region and saturation region - Curve extraction reverse scan and .

[0109] From the linear region and saturation region after stress scanning - Curve extraction forward scan and .

[0110] From the post-stress scan linear region and saturation region - Curve extraction reverse scan and .

[0111] Calculated according to formula (1) Calculated according to formula (2) .

[0112] See Figure 5 ,Compare ,like If the defect peak is close to the source end, then The defect peak is close to the drain end.

[0113] The analytical apparatus for determining the distribution of two types of defects along the channel in a semiconductor device provided by the present invention is described below. of The analytical apparatus for determining the distribution of two types of defects along the channel in semiconductor devices can be used in conjunction with the analytical method for determining the distribution of two types of defects along the channel in semiconductor devices described above.

[0114] See Figure 6 The present invention also provides an analytical apparatus for determining the distribution of two types of defects along a channel in a semiconductor device, comprising: The receiving module 610 is used to receive pulse IV rapid test data of the target semiconductor device; the pulse IV rapid test data includes forward scan IV data and reverse scan IV data of the target semiconductor device before and after stress; The extraction module 620 is used to extract the first threshold voltage difference degradation amount between the linear region and the saturation region under the forward scan bias from the forward scan IV data corresponding before and after stress, and to extract the second threshold voltage difference degradation amount between the linear region and the saturation region under the reverse scan bias from the reverse scan IV data corresponding before and after stress. The determination module 630 is used to determine the distribution location of interface defects and oxide layer defects along the channel in the target semiconductor device based on the relationship between the first threshold voltage difference degradation amount and the second threshold voltage difference degradation amount.

[0115] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0116] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. An analytical method for determining the distribution of two types of defects along the channel in a semiconductor device, characterized in that, include: Receive pulse IV rapid test data of the target semiconductor device; the pulse IV rapid test data includes the forward scan IV data and reverse scan IV data of the target semiconductor device before and after stress. Extract the first threshold voltage difference degradation amount between the linear region and the saturation region under forward bias from the forward scan IV data corresponding before and after the stress, and extract the second threshold voltage difference degradation amount between the linear region and the saturation region under reverse scan bias from the reverse scan IV data corresponding before and after the stress. Based on the relationship between the first threshold voltage difference degradation amount and the second threshold voltage difference degradation amount, the distribution location of interface defects and oxide layer defects along the channel in the target semiconductor device is determined.

2. The analytical method for determining the distribution of two types of defects along the channel in a semiconductor device according to claim 1, characterized in that, Before receiving the test data, the method further includes: scanning the target semiconductor device to obtain the pulse IV rapid test data; Scanning the target semiconductor device to obtain the pulse IV rapid test data includes: Before and after stress is applied to the target semiconductor device, a voltage within a preset scanning voltage range is applied to the gate of the target semiconductor device based on the pulse IV rapid testing method. Forward and reverse scanning are performed on the linear and saturation regions of the target semiconductor device, respectively, to obtain the pulse IV rapid testing data between the drain current and the gate voltage. The upper limit of the preset scanning voltage range is the sum of the threshold voltage of the target semiconductor device and a preset voltage value, and the lower limit of the preset scanning voltage range is the difference between the threshold voltage of the target semiconductor device and the preset voltage value.

3. The analytical method for determining the distribution of two types of defects along the channel in a semiconductor device according to claim 2, characterized in that, Before scanning the target semiconductor device to obtain the pulse IV rapid test data, the method further includes: A reference device of the same type as the target semiconductor device is scanned to obtain the threshold voltage of the reference device before and after stress. The threshold voltage of the reference device is determined as the threshold voltage of the target semiconductor device.

4. The analytical method for determining the distribution of two types of defects along the channel in a semiconductor device according to claim 2, characterized in that, The upper limit of the preset scanning voltage range is less than the gate stress voltage during the stress application process.

5. The analytical method for determining the distribution of two types of defects along the channel in a semiconductor device according to claim 1, characterized in that, Based on the relationship between the first threshold voltage difference degradation and the second threshold voltage difference degradation, the distribution locations of interface defects and oxide layer defects along the channel in the target semiconductor device are determined, including: If the degradation amount of the first threshold voltage difference is greater than the degradation amount of the second threshold voltage difference, it is determined that the interface defect is close to the drain terminal of the target semiconductor device; If the degradation amount of the first threshold voltage difference is less than the degradation amount of the second threshold voltage difference, then it is determined that the oxide layer defect is close to the source end of the target semiconductor device.

6. The analytical method for determining the distribution of two types of defects along the channel in a semiconductor device according to claim 1, characterized in that, Extract the first threshold voltage difference degradation amount between the linear region and the saturation region under forward bias from the forward scan IV data corresponding to the stress before and after, and extract the second threshold voltage difference degradation amount between the linear region and the saturation region under reverse scan bias from the reverse scan IV data corresponding to the stress before and after, including: The positive and negative IV data of the target semiconductor device before and after stress are fitted to the corresponding drain current versus gate voltage curves to obtain the positive scan data before and after stress. - Curves and reverse scan - curve; Positive scan before and after stress extraction - Threshold voltage of the curve and reverse scan - The threshold voltage of the curve is used to obtain the threshold voltage of the forward scan linear region, the threshold voltage of the forward scan saturation region, the threshold voltage of the reverse scan linear region, and the threshold voltage of the reverse scan saturation region before and after stress. Based on the threshold voltage of the linear region and the threshold voltage of the saturation region before and after stress, the degradation amount of the first threshold voltage difference is determined. The degradation amount of the second threshold voltage difference is determined based on the threshold voltage of the linear region and the threshold voltage of the saturation region before and after stress.

7. The analytical method for determining the distribution of two types of defects along the channel in a semiconductor device according to claim 6, characterized in that, Based on the threshold voltages of the linear region and the saturation region before and after stress, the degradation amount of the first threshold voltage difference is determined, including: Formula used: ； The degradation amount of the first threshold voltage difference is calculated; where, This is the degradation amount of the first threshold voltage difference; The threshold voltage of the positive sweep linear region before stress; This is the threshold voltage of the positive sweep saturation region before stress. This is the threshold voltage of the positive scan linear region after stress. This is the threshold voltage of the positive sweep saturation region after stress. Based on the threshold voltages of the linear region and the saturation region before and after stress, the degradation amount of the second threshold voltage difference is determined, including: Formula used: ； The degradation amount of the second threshold voltage difference is calculated; where, This is the degradation amount of the second threshold voltage difference; The threshold voltage of the linear region before stress is the reverse scan. The threshold voltage of the reverse sweep saturation region before stress; The threshold voltage of the linear region after stress is the reverse scan. This is the threshold voltage of the saturation region after stress.

8. The analytical method for determining the distribution of two types of defects along the channel in a semiconductor device according to claim 2, characterized in that, Performing a positive scan on the linear and saturation regions of the target semiconductor device, respectively, includes: A preset first voltage is applied to the drain of the target semiconductor device in the linear region to perform a positive scan; A preset second voltage is applied to the drain of the target semiconductor device in the saturation region to perform a positive scan; Performing reverse scanning on the linear and saturation regions of the target semiconductor device, respectively, includes: The first voltage is applied to the source of the target semiconductor device in the linear region to perform a reverse scan; The second voltage is applied to the source of the target semiconductor device in the saturation region to perform a reverse scan.

9. The analytical method for determining the distribution of two types of defects along the channel in a semiconductor device according to claim 2, characterized in that, The first voltage is less than the second voltage.

10. An analytical apparatus for determining the distribution of two types of defects along a channel in a semiconductor device, characterized in that, include: A receiving module is used to receive pulse IV rapid test data of a target semiconductor device; the pulse IV rapid test data includes forward scan IV data and reverse scan IV data of the target semiconductor device before and after stress. The extraction module is used to extract the first threshold voltage difference degradation amount between the linear region and the saturation region under forward bias from the forward scan IV data corresponding before and after the stress, and to extract the second threshold voltage difference degradation amount between the linear region and the saturation region under reverse bias from the reverse scan IV data corresponding before and after the stress. The determination module is used to determine the distribution location of interface defects and oxide layer defects along the channel in the target semiconductor device based on the relationship between the first threshold voltage difference degradation amount and the second threshold voltage difference degradation amount.

Images