Manufacturing method of waveguide

Abstract

The invention discloses a method for manufacturing a waveguide. The method comprises the following steps of: transferring a full-etching pattern formed on a first hard mask layer to the surface of a waveguide material layer below through a first filling material layer; transferring a part of the etching pattern formed on the second hard mask layer to the surface of the first filling material layer through the second filling material layer and the first hard mask layer in sequence; and correspondingly carrying out full etching and partial etching on the waveguide material layer through the transmitted full etching pattern and partial etching pattern. According to the method, the waveguide morphology after full etching can be remarkably improved, and the device performance is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a method for fabricating a waveguide. Background Technology

[0002] Silicon nitride waveguides are important passive devices. Fabricating silicon nitride waveguides typically requires two different etching depths on the silicon nitride substrate: partial etching and full etching, to form the desired complete device structure. Full etching involves completely etching through the silicon nitride substrate, while partial etching generally reaches about half the depth of full etching.

[0003] Currently, the common process flow for fabricating silicon nitride waveguides generally involves sequentially performing partial and full etching on the silicon nitride substrate. Partial etching produces a good silicon nitride morphology. However, before the subsequent full etching, the front-layer step created by partial etching on the silicon nitride substrate needs to be filled. This requires a very thick spin-coated material layer (usually a SOC) (greater than the thickness of the silicon nitride substrate) to planarize the front layer and ensure a stable focal plane during photolithography. However, this results in a severe shading effect during the full etching step. Furthermore, the high aspect ratio of the etching in the fill material layer amplifies the etching tilt angle generated in the fill material layer, which is then amplified in the main etching step on the silicon nitride substrate. This leads to a slanted silicon nitride morphology after full etching, with a standing angle at the bottom, thus negatively impacting device performance.

[0004] Therefore, it is necessary to provide a new waveguide fabrication method to solve the aforementioned problems existing in the prior art. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide a method for manufacturing a waveguide.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] This invention provides a method for fabricating a waveguide, comprising:

[0008] The fully etched pattern formed on the first hard mask layer is transferred to the surface of the underlying waveguide material layer through the first filler material layer;

[0009] The partial etch pattern formed on the second hard mask layer is sequentially transferred to the surface of the first hard mask layer through the second filler material layer and the first hard mask layer.

[0010] The waveguide material layer is subjected to full and partial etching respectively by transmitting the full etching pattern and the partial etching pattern.

[0011] Furthermore, the process of transferring the fully etched pattern formed on the first hard mask layer to the surface of the underlying waveguide material layer through the first filler material layer, and the process of transferring the partially etched pattern formed on the second hard mask layer sequentially through the second filler material layer and the first hard mask layer to the surface of the first filler material layer, specifically includes:

[0012] The full etch pattern is formed on the first hard mask layer, exposing the surface of the first filler material layer below;

[0013] Partial etching patterns are formed on the second hard mask layer, exposing the surface of the second filler material layer that fills the space between the first hard mask layer and the second hard mask layer;

[0014] The partially etched pattern is then transferred through the second filler material layer to the surface of the first hard mask layer on one side of the fully etched pattern;

[0015] The fully etched pattern is then transferred through the first filler material layer to the surface of the underlying waveguide material layer, while the partially etched pattern is also transferred through the first hard mask layer to the surface of the first filler material layer.

[0016] The process of performing full and partial etching on the waveguide material layer using the transmitted full and partial etching patterns specifically includes:

[0017] The waveguide material layer is fully etched by transferring the full etch pattern to the surface of the waveguide material layer. At the same time, after the partial etch pattern is further transferred to the surface of the waveguide material layer by the first leveling material layer, the waveguide material layer is further partially etched.

[0018] Further, by sequentially forming the first filler material layer and the first hard mask layer on the surface of the waveguide material layer, and by photolithography and etching, a first opening as the fully etched pattern is formed on the first hard mask layer, exposing the surface of the first filler material layer below the first opening; by sequentially forming the second filler material layer and the second hard mask layer on the surface of the first hard mask layer, the second filler material layer fills the first opening, and by photolithography and etching, a second opening as the partially etched pattern is formed on the second hard mask layer, exposing the surface of the second filler material layer below the second opening; by using the second hard mask layer as a hard mask and etching through the second opening, the partially etched pattern is further transferred to the first hard mask layer through a third opening formed on the second filler material layer. On the surface of the mask layer; by etching back the second filler material layer, and using the first hard mask layer as a hard mask, the first filler material layer is further etched through the first opening, and the fully etched pattern is further transferred to the surface of the waveguide material layer through the fourth opening formed on the first filler material layer, while etching is performed through the third opening, and the partially etched pattern is further transferred to the surface of the first filler material layer through the fifth opening formed on the first hard mask layer; the waveguide material layer is fully etched through the fourth opening, and the first filler material layer is etched through the fifth opening, and after the partially etched pattern is further transferred to the surface of the waveguide material layer through the sixth opening formed on the first filler layer, the waveguide material layer is further partially etched.

[0019] Furthermore, during etching through the second opening, when the surface of the first hard mask layer is exposed below the third opening, the second hard mask layer is completely etched away; during back etching of the second filler material layer and continued etching of the first filler material layer through the first opening, when the surface of the waveguide material layer is exposed below the fourth opening, the surface of the first filler material layer is also exposed below the fifth opening; during full etching of the waveguide material layer, the full etching and the partial etching are completed simultaneously.

[0020] Furthermore, the materials of the first and second leveling material layers include SOC, and the materials of the first and second hard mask layers include SiARC.

[0021] Furthermore, the thickness of the first hard mask layer and the second hard mask layer is less than the thickness of the first flattening material layer and the second flattening material layer, the thickness of the first flattening material layer and the second flattening material layer is less than half the thickness of the waveguide material layer, and the thickness of the first hard mask layer and the second hard mask layer does not exceed one-tenth of the thickness of the waveguide material layer.

[0022] Further, the thickness of the first leveling material layer and / or the second leveling material layer is 100-160 nm; and / or, the thickness of the first hard mask layer and / or the second hard mask layer is 20-40 nm; and / or, the thickness of the waveguide material layer is 380-420 nm.

[0023] Furthermore, when etching to form the first opening and the second opening, an etching gas containing F ions is used; and / or, when etching through the second opening, an etching process with an etching rate for the second hard mask layer lower than that for the second filler material layer is used, and an etching gas containing O ions is used; and / or, when performing back etching on the second filler material layer and continuing etching on the first filler material layer through the first opening, an etching process with an etching rate for the first hard mask layer lower than that for the second filler material layer and the first filler material layer is used, and an etching gas containing O ions is used; and / or, when performing full etching on the waveguide material layer, an etching process with an etching rate for the first filler material layer lower than that for the waveguide material layer is used, and an etching gas containing F ions is used.

[0024] Furthermore, the full etching penetrates the waveguide material layer, and the bottom of the partial etching remains within the waveguide material layer; and / or, the full etching penetrates the waveguide material layer, and the bottom of the partial etching remains at half the thickness of the waveguide material layer.

[0025] Furthermore, the waveguide material layer material includes silicon nitride.

[0026] As can be seen from the above technical solution, the present invention forms the fully etched pattern and the partially etched pattern for forming waveguides with two different etching depths on two hard mask layers (the first hard mask layer and the second hard mask layer), respectively. By adjusting the etching selectivity of each step, the etching of the two planarization material layers (the second planarization material layer and the first planarization material layer) and the main etching of the waveguide material layer are performed sequentially. This avoids the difficult front-layer planarization step in the existing silicon nitride waveguide patterning scheme and eliminates the fatal shadowing effect caused by it. Therefore, it greatly improves the waveguide morphology after full etching and enhances the device performance. Attached Figure Description

[0027] Figure 1 This is a flowchart illustrating a waveguide fabrication method according to the present invention.

[0028] Figure 2 This is a flowchart illustrating a preferred embodiment of the waveguide fabrication method of the present invention.

[0029] Figure 3 This is a schematic diagram illustrating the steps of a preferred embodiment of the present invention for completing the full etching photolithography process.

[0030] Figure 4 This is a schematic diagram illustrating the etching process steps of the first hard mask layer according to a preferred embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram of the completed etching and photolithography process steps in a preferred embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram illustrating the etching process steps for completing the second hard mask layer according to a preferred embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram illustrating the etching process steps for completing the second leveling material layer according to a preferred embodiment of the present invention.

[0034] Figure 8 This is a schematic diagram of the etching process steps for the first leveling material layer on the fully etched side, according to a preferred embodiment of the present invention.

[0035] Figure 9 This is a schematic diagram of the etching process steps of the first filler material layer on the etched side of the completed portion in a preferred embodiment of the present invention.

[0036] Figure 10 This is a schematic diagram illustrating the completion of the main etching of the waveguide material layer and the formation of the final waveguide morphology with two etching depths, according to a preferred embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0038] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0039] refer to Figure 1 The present invention provides a method for fabricating a waveguide, comprising:

[0040] The fully etched pattern formed on the first hard mask layer is transferred to the surface of the underlying waveguide material layer through the first filler material layer;

[0041] The partial etch pattern formed on the second hard mask layer is sequentially transferred to the surface of the first hard mask layer through the second filler material layer and the first hard mask layer.

[0042] By transmitting the full etch pattern and the partial etch pattern, the waveguide material layer is subjected to full etch and partial etch respectively.

[0043] refer to Figure 2 In some embodiments, a method for fabricating a waveguide according to the present invention, further implemented according to the above method, specifically includes the following steps:

[0044] Step S1: Form a full etch pattern on the first hard mask layer, exposing the surface of the underlying first filler material layer.

[0045] like Figure 3 As shown, a waveguide material layer 11 is provided as a substrate. First, a first leveling material layer 12 and a first hard mask layer 13 are sequentially formed on the surface of the waveguide material layer 11.

[0046] In some embodiments, the waveguide material layer 11 comprises silicon nitride. That is, the waveguide material layer 11 includes a silicon nitride layer 111, used to fabricate a silicon nitride waveguide with two different etching depths on the silicon nitride layer 111 by performing partial and full etching, so as to form the desired device through partial and full etching. It is understood that the waveguide material layer 11 may also include other suitable materials besides silicon nitride. The following describes a method for fabricating a waveguide according to the present invention in further detail, using the fabrication of a silicon nitride waveguide as an example and in conjunction with the accompanying drawings.

[0047] In some embodiments, the thickness of the silicon nitride layer 111 (waveguide material layer 11) is 380–420 nm. In this embodiment, the thickness of the silicon nitride layer 111 is 400 nm. The etching process menu employs partial etching at a depth of 200 nm and full etching at a depth of 400 nm on the silicon nitride layer 111. That is, during full etching, the silicon nitride layer 111 is completely etched through; during partial etching, the etch bottom remains within the waveguide material layer 11, and the etch bottom of the partial etching stops at half the thickness of the silicon nitride layer 111. In other words, the etching depth of the partial etching is half the etching depth of the full etching. However, it is understood that the etching depth of the partial etching can be any other etching depth value smaller than the full etching depth.

[0048] In some embodiments, the first leveling material layer 12 comprises a SOC (spin-on carbon material). The first hard mask layer 13 comprises a SiARC (silicon-containing anti-reflective layer material). That is, the first leveling material layer 12 comprises a first SOC layer 121. The first hard mask layer 13 comprises a first SiARC layer 131. It should be noted that, in order to form a good full-etch morphology of the silicon nitride waveguide, it is better to use a Si-containing hard mask material, while a thinner SOC can be used for ground plane leveling.

[0049] In some embodiments, a spin coating process is used to sequentially form a first SOC layer 121 and a first SiARC layer 131 on the surface of the silicon nitride layer 111.

[0050] In some other embodiments, a spin coating process is used to form a first SOC layer 121 on the surface of the silicon nitride layer 111. Then, a PVD process is used to form a first SiARC layer 131 on the surface of the first SOC layer 121.

[0051] In some embodiments, the thickness of the first SOC layer 121 (first planarizing material layer 12) is 100–160 nm. However, in existing full etching processes, the 200 nm step in the front layer caused by partial etching needs to be filled during photolithography, resulting in the SOC requiring spin coating up to 600 nm to complete the front layer planarization. The thickness of the first SOC layer 121 in this invention is effectively reduced compared to the thickness of the SOC in the aforementioned existing full etching processes, thus eliminating the fatal shadowing effect caused by excessive thickness, thereby greatly improving the waveguide morphology after full etching.

[0052] The thickness of the first SiARC layer 131 (first hard mask layer 13) can be determined based on reflectivity simulation. The thickness of the first SiARC layer 131 is generally no greater than 40 nm, for example, 20–40 nm.

[0053] In this embodiment, the thickness of the first SOC layer 121 is 150 nm. The thickness of the first SiARC layer 131 is 40 nm.

[0054] Then, a first photoresist layer 21 is formed on the surface of the first SiARC layer 131, and a first photolithography process is used to form a first photolithographic opening 31 as a full etch pattern on the first photoresist layer 21, exposing the surface of the underlying first SiARC layer 131.

[0055] like Figure 4 As shown, next, an etching process is used to transfer the fully etched pattern formed on the first photoresist layer 21 by photolithography and form it on the first SiARC layer 131. A first opening 32 is formed on the first SiARC layer 131 as the transferred fully etched pattern, exposing the surface of the first SOC layer 121 below the first opening 32. In other words, the fully etched pattern is stored on the first SiARC layer 131 and transferred to the surface of the first SOC layer 121.

[0056] In some embodiments, an etching gas containing F ions is used to etch the first SiARC layer 131 and form the first opening 32. Etching the first SiARC layer 131 with an etching gas containing F ions can produce an etching selectivity higher than the state of charge (SOC).

[0057] It should be noted that when etching the first hard mask layer 13, since the pattern of fully etched silicon nitride (fully etched pattern) needs to be formed on the relatively thin first hard mask layer 13, SiARC is preferred as the front-end hard mask material because SiARC can meet the requirements of front-end process for contamination control, can achieve a high selectivity, and is easy to remove in subsequent processes.

[0058] Step S2: Partial etched pattern is formed on the second hard mask layer, exposing the surface of the second filler material layer that fills the space between the first hard mask layer 13 and the second hard mask layer.

[0059] like Figure 5 As shown, a second filler material layer 14 and a second hard mask layer 15 are then sequentially formed on the surface of the first SiARC layer 131, and the second filler material layer 14 fills the first opening 32.

[0060] In some embodiments, the second filler layer 14 is made of SOC. The second hard mask layer 15 is made of SiARC. That is, the second filler layer 14 includes a second SOC layer 141. The second hard mask layer 15 includes a second SiARC layer 151.

[0061] In some embodiments, a spin coating process is used to sequentially form a second SOC layer 141 and a second SiARC layer 151 on the surface of a first SiARC layer 131. The spin-coated second SOC layer 141 completely fills the first opening 32, so that the second SOC layer 141 is tightly connected to the surface of the second SOC layer 141 through the first opening 32.

[0062] In some other embodiments, a spin coating process is used to form a second SOC layer 141 on the surface of the first SiARC layer 131. Then, a PVD process is used to form a second SiARC layer 151 on the surface of the second SOC layer 141.

[0063] In some embodiments, the thickness of the second SOC layer 141 (second leveling material layer 14) is 100–160 nm. The thickness of the second SiARC layer 151 can be determined based on reflectivity simulation. The thickness of the second SiARC layer 151 is generally no greater than 40 nm, for example, 20–40 nm. In this embodiment, the thickness of the second SOC layer 141 is 150 nm. The thickness of the second SiARC layer 151 is 40 nm.

[0064] As can be seen, the thickness of the first SiARC layer 131 and the second SiARC layer 151 is less than the thickness of the first SOC layer 121 and the second SOC layer 141. The thickness of the first SOC layer 121 and the second SOC layer 141 is less than half the thickness of the silicon nitride layer 111. The thickness of the first SiARC layer 131 and the second SiARC layer 151 is no more than one-tenth the thickness of the silicon nitride layer 111.

[0065] It should be noted that since the thickness of the first SiARC layer 131 is generally less than 40nm, the photolithography process used for partially etching silicon nitride waveguides does not need to consider the planarization of the front layer, so a thinner second SOC layer 141 can be used.

[0066] Then, a second photoresist layer 22 is formed on the surface of the second SiARC layer 151, and a second photolithography process is used to form a second photolithographic opening 41 as a partial etching pattern on the second photoresist layer 22, exposing the surface of the underlying second SiARC layer 151.

[0067] like Figure 6As shown, next, an etching process is used to transfer a portion of the etched pattern formed on the second photoresist layer 22 by photolithography and form it on the second SiARC layer 151. A second opening 42, which is the transferred portion of the etched pattern, is formed on the second SiARC layer 151, exposing the surface of the second SOC layer 141 below the second opening 42. In other words, the portion of the etched pattern is stored on the second SiARC layer 151 and transferred to the surface of the second SOC layer 141. The second opening 42, which is the transferred portion of the etched pattern, is located on the second SiARC layer 151 to one side of the first opening 32, which is formed on the first SiARC layer 131 and is the transferred full etched pattern. The vertical projection of the second opening 42 on the first SiARC layer 131 needs to be a certain design distance from the first opening 32.

[0068] In some embodiments, an etching gas containing F ions is used to etch the second SiARC layer 151 and form a second opening 42 to produce an etching selectivity higher than SOC.

[0069] Step S3: The partial etched pattern is then transferred through the second filler material layer 14 to the surface of the first hard mask layer 13 on the side of the fully etched pattern.

[0070] like Figure 7 As shown, next, using the second SiARC layer 151 as a hard mask, the second SOC layer 141 below is etched through the second opening 42. A third opening 43 is formed on the second SOC layer 141 below the second opening 42 to transfer part of the etched pattern, exposing the surface of the first SiARC layer 131 below the third opening 43. Thus, part of the etched pattern continues to be transferred downwards to the surface of the first SiARC layer 131 through the second opening 42 and the third opening 43.

[0071] In some embodiments, when etching the second SOC layer 141 through the second opening 42, an etching process with a lower etching rate for the second SiARC layer 151 than for the second SOC layer 141 is used; that is, a process menu with a high etching selectivity for the second SOC layer 141 and the second SiARC layer 151 is selected for etching. Furthermore, by adjusting the etching selectivity, the second SiARC layer 151 is completely etched away and removed when the surface of the first SiARC layer 131 is exposed below the third opening 43.

[0072] In some embodiments, the etching process described above, in which the etching rate of the second SiARC layer 151 is less than the etching rate of the second SOC layer 141, uses an etching gas containing O ions for etching.

[0073] Step S4: The fully etched pattern is continued to be transferred through the first filler material layer 12 to the surface of the underlying waveguide material layer 11, while the partially etched pattern is continued to be transferred through the first hard mask layer 13 to the surface of the first filler material layer 12.

[0074] like Figure 8 As shown, a maskless etching process is then used to etch back (push-back removal) the second SOC layer 141. After removing the last portion of the second SOC layer 141 located in the first opening 32, the first SiARC layer 131 is used as a hard mask, and etching continues on the lower first SOC layer 121 through the first opening 32. A fourth opening 33 is formed on the first SOC layer 121 below the first opening 32 to transfer the full etch pattern, exposing the surface of the silicon nitride layer 111 below the fourth opening 33. Thus, the full etch pattern is transferred downwards through the first opening 32 and the fourth opening 33 to the surface of the silicon nitride layer 111 where full etching is required. Simultaneously, during the back etching process of the second SOC layer 141, the second SOC layer 141 itself is used as a mask. Before the second SOC layer 141 is completely consumed, the first SiARC layer 131 below it is etched through the third opening 43 located on the second SOC layer 141. A fifth opening 44 is formed on the first SiARC layer 131 below the third opening 43 to transfer part of the etched pattern, exposing the surface of the first SOC layer 121 below the fifth opening 44. Thus, part of the etched pattern is transferred to the surface of the first SOC layer 121 through the fifth opening 44 formed on the first SiARC layer 131. This eliminates the need for a photomask to etch the first SiARC layer 131, thereby avoiding registration errors.

[0075] In some embodiments, when the second SOC layer 141 is etched back and the first SOC layer 121 is etched through the first opening 32, an etching process with a lower etching rate for the first SiARC layer 131 than for the second SOC layer 141 and the first SOC layer 121 is used. Specifically, a process menu with a high etching selectivity for the second SOC layer 141 and the first SOC layer 121 compared to the first SiARC layer 131 is selected for etching. Furthermore, by adjusting the etching selectivity, when the surface of the silicon nitride layer 111 is exposed below the fourth opening 33, the surface of the first SOC layer 121 is also exposed below the fifth opening 44.

[0076] In some embodiments, the etching process described above, in which the etching rate of the first SiARC layer 131 is less than the etching rate of the second SOC layer 141 and the first SOC layer 121, uses an etching gas containing O ions for etching.

[0077] Step S5: The waveguide material layer 11 is fully etched by transferring the full etch pattern to the surface of the waveguide material layer 11. At the same time, after transferring the partial etch pattern to the surface of the waveguide material layer 11 through the first leveling material layer 12, the waveguide material layer 11 is partially etched.

[0078] Next, using the first SiARC layer 131 as a hard mask, and through the fourth opening 33 and the fifth opening 44, the silicon nitride layer 111 exposed below the fourth opening 33 is fully etched, and the first SOC layer 121 and the silicon nitride layer 111 exposed below the fifth opening 44 are etched simultaneously, so as to achieve the final partial etching of the silicon nitride layer 111 below the fifth opening 44. That is, the first SOC layer 121 located on the silicon nitride layer 111 is used as a pre-consumption layer for the partial etching of the silicon nitride layer 111, so that the partial etching of the silicon nitride layer 111 can be completed simultaneously when the full etching of the silicon nitride layer 111 is completed.

[0079] In some embodiments, when performing full etching on the silicon nitride layer 111, an etching process is used in which the etching rate of the first SOC layer 121 is less than the etching rate of the silicon nitride layer 111, so that full etching and partial etching are completed simultaneously.

[0080] In some embodiments, the etching process described above, in which the etching rate of the first SOC layer 121 is less than the etching rate of the silicon nitride layer 111, uses an etching gas containing F ions for etching.

[0081] like Figure 9 As shown, in some embodiments, during the etching process of the first exposed SOC layer 121 through the fifth opening 44, a sixth opening 45 for transferring a portion of the etched pattern is formed on the first SOC layer 121 below the fifth opening 44, exposing the surface of the silicon nitride layer 111 below the sixth opening 45. Thus, the partial etched pattern is ultimately transferred through the sixth opening 45 formed on the first SOC layer 121 to the surface of the silicon nitride layer 111 at the location where partial etching is required.

[0082] In some embodiments, by adjusting the etching selectivity, when a portion of the etched pattern is transferred to the surface of the silicon nitride layer 111 through the sixth opening 45 formed on the first leveling material layer 12, the full etching of the exposed silicon nitride layer 111 below through the fourth opening 33 is just halfway completed, forming a transition step structure 51 on the silicon nitride layer 111 during the full etching process. For example, when the thickness of the silicon nitride layer 111 is 400 nm, the etching depth at this point in the full etching process is 200 nm.

[0083] like Figure 10As shown, finally, through the fourth opening 33, the remaining half of the silicon nitride layer 111, which has already undergone half of full etching, continues to be fully etched. Simultaneously, through the sixth opening 45, partial etching begins on the exposed silicon nitride layer 111. Thus, when the set partial etching depth is half the full etching depth (200nm), when the full etching of the silicon nitride layer 111 below the fourth opening 33 is completed, that is, the silicon nitride layer 111 is etched through through the full etching (generally, a waveguide cladding layer and a device substrate layer are located below the waveguide cladding layer). Figures 3-10 (The details are omitted here). At the same time, the partial etching of the silicon nitride layer 111 below the sixth opening 45 is also completed, forming a partially etched step structure 61 on the silicon nitride layer 111. This results in the final morphology of the silicon nitride waveguide 71 with two etching depths.

[0084] In this step, the first SiARC layer 131 will be completely etched away. The first SOC layer 121 is as follows: Figure 10 If there is any residue, it does not need to be removed and can be used as an etching stop layer in subsequent processes.

[0085] The number of the partially etched pattern (second photolithographic opening 41) and the fully etched pattern (first photolithographic opening 31) mentioned above is set according to design requirements. The above embodiments are only examples used to illustrate a method for fabricating a silicon nitride waveguide 71 according to the present invention.

[0086] In summary, this invention forms the fully etched pattern and the partially etched pattern for waveguides with two different etching depths on two hard mask layers (first hard mask layer 13 and second hard mask layer 15), respectively. By adjusting the etching selectivity of each step, the etching of the two planarization material layers (second planarization material layer 14 and first planarization material layer 12) and the main etching of the waveguide material layer 11 are performed sequentially. This avoids the difficult front-layer planarization step in existing silicon nitride waveguide patterning schemes and eliminates the fatal shadowing effect caused by it. Therefore, it greatly improves the waveguide morphology after full etching and enhances the device performance.

[0087] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A method for fabricating a waveguide, characterized in that, include: The fully etched pattern formed on the first hard mask layer is transferred to the surface of the underlying waveguide material layer through the first filler material layer; The partial etch pattern formed on the second hard mask layer is sequentially transferred to the surface of the first hard mask layer through the second filler material layer and the first hard mask layer. The waveguide material layer is subjected to full and partial etching respectively by transmitting the full etching pattern and the partial etching pattern.

2. The waveguide fabrication method according to claim 1, characterized in that, The process of transferring the fully etched pattern formed on the first hard mask layer to the surface of the underlying waveguide material layer through the first filler material layer, and transferring the partially etched pattern formed on the second hard mask layer sequentially through the second filler material layer and the first hard mask layer to the surface of the first filler material layer, specifically includes: The full etch pattern is formed on the first hard mask layer, exposing the surface of the first filler material layer below; Partial etching patterns are formed on the second hard mask layer, exposing the surface of the second filler material layer that fills the space between the first hard mask layer and the second hard mask layer; The partially etched pattern is then transferred through the second filler material layer to the surface of the first hard mask layer on one side of the fully etched pattern; The fully etched pattern is then transferred through the first filler material layer to the surface of the underlying waveguide material layer, while the partially etched pattern is also transferred through the first hard mask layer to the surface of the first filler material layer. The process of performing full and partial etching on the waveguide material layer using the transmitted full and partial etching patterns specifically includes: The waveguide material layer is fully etched by transferring the full etch pattern to the surface of the waveguide material layer. At the same time, after the partial etch pattern is further transferred to the surface of the waveguide material layer by the first leveling material layer, the waveguide material layer is further partially etched.

3. The waveguide fabrication method according to claim 2, characterized in that, By sequentially forming the first filler material layer and the first hard mask layer on the surface of the waveguide material layer, and by photolithography and etching, a first opening as the full etch pattern is formed on the first hard mask layer, exposing the surface of the first filler material layer below the first opening. By sequentially forming the second filler material layer and the second hard mask layer on the surface of the first hard mask layer, the second filler material layer fills the first opening, and by photolithography and etching, a second opening as the partial etched pattern is formed on the second hard mask layer, exposing the surface of the second filler material layer below the second opening; By using the second hard mask layer as a hard mask and etching through the second opening, the partially etched pattern is transferred to the surface of the first hard mask layer through the third opening formed on the second filler material layer; by performing back etching on the second filler material layer and using the first hard mask layer as a hard mask, the first filler material layer is etched through the first opening, and the fully etched pattern is transferred to the surface of the waveguide material layer through the fourth opening formed on the first filler material layer, while simultaneously etching through the third opening, the partially etched pattern is transferred to the surface of the first filler material layer through the fifth opening formed on the first hard mask layer; The waveguide material layer is fully etched through the fourth opening, while the first filler material layer is etched through the fifth opening. After the partial etched pattern is further transferred to the surface of the waveguide material layer through the sixth opening formed on the first filler material layer, the waveguide material layer is partially etched.

4. The waveguide fabrication method according to claim 3, characterized in that, When etching is performed through the second opening, the second hard mask layer is completely etched away when the surface of the first hard mask layer is exposed below the third opening; when the second filler material layer is etched back and the first filler material layer is etched through the first opening, the surface of the first filler material layer is also exposed below the fifth opening when the surface of the waveguide material layer is exposed below the fourth opening. When performing full etching on the waveguide material layer, the full etching and the partial etching are completed simultaneously.

5. The waveguide fabrication method according to claim 4, characterized in that, The first and second filler layers are made of SOC material, and the first and second hard mask layers are made of SiARC material.

6. The method for fabricating a waveguide according to claim 5, characterized in that, The thickness of the first hard mask layer and the second hard mask layer is less than the thickness of the first filler material layer and the second filler material layer, the thickness of the first filler material layer and the second filler material layer is less than half the thickness of the waveguide material layer, and the thickness of the first hard mask layer and the second hard mask layer does not exceed one-tenth of the thickness of the waveguide material layer.

7. The method for fabricating a waveguide according to claim 5, characterized in that, The thickness of the first leveling material layer and / or the second leveling material layer is 100-160 nm; and / or the thickness of the first hard mask layer and / or the second hard mask layer is 20-40 nm; and / or the thickness of the waveguide material layer is 380-420 nm.

8. The method for fabricating a waveguide according to claim 5, characterized in that, When etching to form the first opening and the second opening, an etching gas containing F ions is used; and / or, when etching through the second opening, an etching process with an etching rate for the second hard mask layer lower than that for the second filler material layer is used, and an etching gas containing O ions is used; and / or, when performing back etching of the second filler material layer and continuing etching of the first filler material layer through the first opening, an etching process with an etching rate for the first hard mask layer lower than that for the second filler material layer and the first filler material layer is used, and an etching gas containing O ions is used; and / or, when performing full etching of the waveguide material layer, an etching process with an etching rate for the first filler material layer lower than that for the waveguide material layer is used, and an etching gas containing F ions is used.

9. The method for fabricating a waveguide according to claim 1, characterized in that, The full etching etches through the waveguide material layer, and the bottom of the partial etching remains within the waveguide material layer; and / or, the full etching etches through the waveguide material layer, and the bottom of the partial etching remains at half the thickness of the waveguide material layer.

10. The method for fabricating a waveguide according to claim 1, characterized in that, The waveguide material layer material includes silicon nitride.

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