HBF chip intelligent cache prefetching and replacement strategy method and system

Abstract

The invention relates to an HBF chip intelligent cache prefetching and replacement strategy method and system, and the method comprises the following steps: carrying out the access frequency statistics of cache prefetching data, obtaining a data access sequence table, and carrying out the time access analysis of the cache prefetching data based on the data access sequence table, and obtaining a data heat distribution diagram; performing priority ranking analysis on the cached prefetched data based on the data popularity distribution diagram to obtain a cache priority list; performing partition management on a cache space of the HBF chip based on the cache priority list to obtain a cache partition mapping table; according to the cache partition mapping table, replacement position selection is carried out on the data blocks newly entering the cache, so that preferential residence of the high-heat data blocks and directional replacement of the low-heat data blocks are achieved, and the technical problems that in the prior art, the cache hit rate is decreased, and bandwidth is wasted are solved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method and system for intelligent cache prefetching and replacement strategy for HBF chips. Background Technology

[0002] With the rapid development of fields such as artificial intelligence, big data, and high-performance computing, higher demands are being placed on the access efficiency of storage systems. As a key component connecting computing and storage units, the cache management strategy of HBF (High Bandwidth Fabric) chips directly impacts the overall system performance. Traditional cache replacement algorithms (such as LRU and FIFO) primarily make decisions based on simple access time or order, making it difficult to effectively capture the complex and dynamically changing data access patterns in modern applications. Especially when facing non-uniform, highly bursty, or long-tailed access requests, this often leads to problems such as decreased cache hit rate, wasted bandwidth, and increased latency. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a method for intelligent cache prefetching and replacement strategy in HBF chips, comprising the following steps: Access frequency statistics are performed on cached prefetched data to obtain a data access sequence list, and time access analysis is performed on cached prefetched data based on the data access sequence list to obtain a data heat distribution map. Based on the data heat distribution map, the cache prefetched data is prioritized and analyzed to obtain a cache priority list; The cache space of the HBF chip is partitioned and managed based on the cache priority list to obtain a cache partition mapping table; The replacement location of newly entered data blocks is selected according to the cache partition mapping table, so as to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks.

[0004] Furthermore, the access frequency of cached prefetched data is statistically analyzed to obtain a data access sequence list, including: The cache prefetch data is extracted by the cache prefetch data reading unit of the HBF chip to obtain the cache prefetch data fields; The cached prefetch data fields are sorted according to access time, and the number of accesses to the same data block address is accumulated to obtain a data access sequence table.

[0005] Furthermore, based on the data access sequence list, time access analysis is performed on the cached prefetched data to obtain a data heat distribution map, including: For each data block in the data access sequence list, multiple time windows are divided according to the time axis, and the number of accesses to the data block in each time window is counted to obtain access count information; Based on the access frequency information, the access popularity of each data block in different time windows is calculated, and a data popularity distribution map is drawn based on the access popularity.

[0006] Furthermore, based on the cache priority list, the cache space of the HBF chip is partitioned for management, resulting in a cache partition mapping table, including: The data blocks in the cache priority list are divided into groups based on their number of groups, resulting in the number of groups for each partition. Based on the quantity information, the cache space of the HBF chip is divided proportionally to obtain initial cache partitions. Then, based on the priority sorted data blocks, the data blocks in each initial cache partition are matched and mapped to obtain a cache partition mapping table.

[0007] Furthermore, based on the aforementioned quantity information, the cache space of the HBF chip is divided proportionally to obtain an initial cache partition, including: The quantity information is parsed to obtain the number of partitions, and the total cache space size is obtained through the cache space management unit of the HBF chip. The total cache space is proportionally divided based on the number of partitions to obtain the space size of each partition. The cache space of the HBF chip is then divided according to the space size to obtain the initial cache partitions.

[0008] Furthermore, the replacement location for newly entered data blocks is selected according to the cache partition mapping table to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks, including: The cache partition mapping table is parsed to obtain the cache priority and space usage status of each partition; Based on the cache priority and space usage status of each partition, priority matching and space adaptation analysis are performed on newly entered data blocks to obtain a list of adapted partitions. The partitions in the adaptation partition list are sorted by priority and remaining space, and the optimal partition in the initial cache partition is selected as the replacement position to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks.

[0009] Furthermore, based on the cache priority and space usage status corresponding to each partition, priority matching and space adaptation analysis are performed on newly entered data blocks to obtain a list of adapted partitions, including: The cache priority corresponding to each partition is parsed to obtain the priority level of each partition, and the priority attribute of the newly entered data block is obtained through the data block attribute reading unit of the HBF chip. The priority attribute of newly entered data blocks is compared with the priority level of each partition one by one to obtain priority-matching partitions; The space usage status corresponding to the priority matching partition is extracted to obtain the used space size and remaining space size of each matching partition, and the space size required for the newly entered data block is calculated by the space calculation unit of the HBF chip. The space required for the new data block entering the cache is compared with the remaining space of each matching partition to filter out partitions with enough remaining space to accommodate the new data block, thus obtaining a list of suitable partitions.

[0010] This invention also provides an intelligent cache prefetching and replacement strategy system for HBF chips, comprising: The statistics module is used to count the access frequency of cached prefetched data, obtain a data access sequence list, and perform time access analysis on the cached prefetched data based on the data access sequence list to obtain a data heat distribution map. The analysis module is used to perform priority sorting analysis on the cached prefetched data based on the data heat distribution map to obtain a cache priority list; The management module is used to partition the cache space of the HBF chip based on the cache priority list to obtain a cache partition mapping table; The selection module is used to select the replacement location for newly entered data blocks according to the cache partition mapping table, so as to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks.

[0011] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.

[0012] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any of the above methods.

[0013] This invention provides an intelligent cache prefetching and replacement strategy method for HBF chips, comprising the following steps: statistically analyzing the access frequency of cache prefetched data to obtain a data access sequence list, and performing time access analysis on the cache prefetched data based on the data access sequence list to obtain a data heat distribution map; performing priority sorting analysis on the cache prefetched data based on the data heat distribution map to obtain a cache priority list; performing partition management on the cache space of the HBF chip based on the cache priority list to obtain a cache partition mapping table; and selecting the replacement location for newly entered data blocks according to the cache partition mapping table to achieve priority residence of high-heat data blocks and targeted replacement of low-heat data blocks. This solves the technical problems that traditional technologies often lead to decreased cache hit rate and wasted bandwidth. It achieves targeted replacement of low-heat data blocks and reserves suitable locations for newly entered high-potential data, reducing the residence time of invalid or redundant data in the cache, effectively alleviating memory bandwidth contention, reducing average data access latency, and improving system response speed. Attached Figure Description

[0014] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart illustrating the steps of the HBF chip intelligent cache prefetching and replacement strategy method in an embodiment of the present invention. Figure 2 This is a structural block diagram of the HBF chip intelligent cache prefetch and replacement strategy system in an embodiment of the present invention; Figure 3 This is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0015] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0016] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0017] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0018] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0019] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0020] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0021] Reference Figure 1 This invention provides a method for intelligent cache prefetching and replacement strategy of HBF chip, including the following steps: Step S1: Statistical analysis of access frequency of cached prefetched data is performed to obtain a data access sequence list. Based on the data access sequence list, time access analysis is performed on cached prefetched data to obtain a data heat distribution map.

[0022] Specifically, when counting the access frequency of cached prefetched data, a counter needs to be set for each data block. The counter is incremented each time the data block is accessed, gradually building a data access sequence list. During this process, whenever a new data block enters the cache or an existing data block is accessed, the system automatically updates the corresponding access count, ensuring the sequence list accurately reflects the access frequency of each data block. Based on this continuously updated data access sequence list, the next task is to perform temporal access analysis on the cached prefetched data to obtain a data heat map. In this step, a sliding window technique is used to observe the access patterns of each data block over a period of time, calculating the access density and interval of each data block in different time periods, thereby evaluating its temporal locality characteristics. For example, when the HBF chip processes AI training tasks, frequently accessed weight parameter data blocks will show a high access density in a short period because these data are repeatedly used during model training iterations, indicating good temporal locality. Input sample data that is only used occasionally may show a lower access density and a larger access interval, reflecting lower temporal locality. Combining this information creates a clear data heatmap, which guides subsequent adjustments to cache management strategies. Continuously monitoring and updating access frequency and temporal locality is crucial in this process. This ensures the heatmap always reflects the latest cache usage, providing a reliable basis for optimizing cache performance.

[0023] Step S2: Based on the data heat distribution map, perform priority sorting analysis on the cache prefetched data to obtain a cache priority list.

[0024] Specifically, prioritizing cached prefetched data based on a data heatmap first requires defining a metric to evaluate the heat level of each data block. This metric can be determined by considering factors such as access frequency, recent access time, and access density. In practice, an algorithm can be set up to traverse the entire data heatmap, extracting the corresponding heat information for each data block. For example, data blocks with high access frequency and recent frequent access are assigned higher weight values. Then, these weight values ​​are used as the sorting criteria. By comparing the weights of each data block, all data blocks are arranged in descending order to form a cache priority list. Throughout this process, to ensure that the priority list accurately reflects the current workload characteristics, the sorting process needs to be re-executed after each update of the data heatmap. For example, when the HBF chip processes AI training tasks, suppose there is a set of model parameters and a batch of training samples. The model parameters have a high access frequency and a short recent access interval because they are repeatedly called throughout the training process, so they will be at the top of the priority ranking. Conversely, some input samples specific to a certain iteration may receive a lower priority because they are only used once. This cache priority list not only helps to identify the most valuable data blocks so that they can be given a longer cache residency opportunity, but also facilitates more reasonable allocation and management of cache space based on this list, further improving the overall performance of the caching system.

[0025] Step S3: Based on the cache priority list, the cache space of the HBF chip is partitioned and managed to obtain a cache partition mapping table.

[0026] Specifically, the cache space of the HBF chip is partitioned and managed based on a cache priority list. First, the proportion of cache space allocated to data blocks of different popularity levels needs to be determined according to the popularity levels of the data blocks in the priority list. This process involves dividing the entire cache space into several regions, each corresponding to data blocks of a specific popularity level. In practice, an algorithm can be set up to calculate the required space size for each popularity level based on the weight values ​​in the priority list, and allocate cache space sequentially from high to low popularity levels, ensuring that high-popularity data blocks receive more cache resources. After the initial partitioning is completed, a mapping table, namely the cache partition mapping table, needs to be established to record the correspondence between each data block and its respective partition. This step is crucial for quickly locating and accessing specific data blocks later. For example, when processing AI training tasks, considering that model parameters usually have a high access frequency and temporal locality, these parameters are given a higher priority, and a larger proportion of cache space will be allocated to these high-popularity data blocks during cache partitioning management. Conversely, training samples used only occasionally may be allocated only a small amount or even no dedicated cache space. This approach not only achieves efficient utilization of cache space but also significantly improves system access efficiency. In actual operation, when new data blocks enter the cache or the state of existing data blocks changes, the partitioning scheme can be dynamically adjusted and the cache partition mapping table updated based on the latest cache priority list. This ensures that the cache management strategy remains optimal to adapt to ever-changing workload demands. Throughout this process, continuously monitoring and adjusting the cache partition mapping table is a crucial step in guaranteeing cache performance, helping to ensure that all data blocks receive the most appropriate cache resource allocation throughout their lifecycle.

[0027] Step S4: Select the replacement location for newly entered data blocks according to the cache partition mapping table, so as to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks.

[0028] Specifically, when selecting a replacement location for a newly entered data block in the cache based on the cache partition mapping table, the system first queries the data block's popularity level and then locates the corresponding cache partition range in the cache partition mapping table according to its popularity level. If there is free space in the target partition, the data block is directly loaded into that free location. If the target partition is full, a replacement operation must be performed within that partition. At this point, the system iterates through all data blocks in the partition, combines their specific priority ranking in the cache priority list, selects the lowest priority (i.e., the lowest popularity) data block as a candidate replacement object, and removes it from the cache to free up space for the new data block. Throughout the process, replacement decisions are strictly limited to partitions with the same or lower popularity level to avoid mistakenly replacing high-popularity data blocks. For example, when the HBF chip processes AI training tasks, if a newly generated block of intermediate activation values ​​needs to be loaded into the cache, the system first evaluates its access characteristics and assigns an initial popularity level. Assuming it belongs to medium popularity, it is allocated to the medium popularity zone according to the cache partitioning mapping table. If the zone is full, the system searches for the lowest priority old activation value or temporary gradient data in that zone to replace it, without touching the long-term resident model weight parameters in the high popularity zone. In this way, the continuous residence of high popularity data blocks is ensured, and the targeted cleaning of low popularity data blocks is achieved. This ensures that the cache replacement process is always consistent with the actual use value of the data, thereby maintaining high cache utilization and access performance under dynamic load.

[0029] In a specific embodiment, the access frequency of cached prefetched data is statistically analyzed to obtain a data access sequence list, including: The cache prefetch data is extracted by the cache prefetch data reading unit of the HBF chip to obtain the cache prefetch data fields; The cached prefetch data fields are sorted according to access time, and the number of accesses to the same data block address is accumulated to obtain a data access sequence table.

[0030] Specifically, the process of statistically analyzing the access frequency of cache prefetched data to obtain a data access sequence list first involves the cache prefetch data reading unit of the HBF chip extracting fields from the cache prefetch data. This unit captures the metadata of the accessed data block each time a cache access occurs, including the data block address, access timestamp, and related identification fields, thereby generating cache prefetch data fields. Subsequently, these cache prefetch data fields are arranged sequentially according to the access time, forming a raw access record sequence organized along a time axis. Based on this sequence, the system traverses all fields and identifies and merges entries with the same data block address, while accumulating the corresponding access count. That is, whenever a data block address is found to appear again, its counter is incremented by one, and key information such as its first and most recent access times is retained. Finally, a structured data access sequence list is output, in which each entry contains a unique data block address and its cumulative access count and timing information. For example, during the AI ​​training task performed by the HBF chip, when the model weight parameters are repeatedly loaded for forward and backward propagation calculations, the cache prefetch data reading unit continuously records each access to the same weight address. After field extraction and sorting, the weight address will show a high cumulative access count in the data access sequence table, while temporary intermediate results used only once or a few times. In this way, the data access sequence table can truly and completely reflect the access behavior of different data blocks in actual operation, providing accurate input for subsequent time access analysis and heat modeling.

[0031] In a specific embodiment, time access analysis is performed on the cached prefetched data based on the data access sequence list to obtain a data heat distribution map, including: For each data block in the data access sequence list, multiple time windows are divided according to the time axis, and the number of accesses to the data block in each time window is counted to obtain access count information; Based on the access frequency information, the access popularity of each data block in different time windows is calculated, and a data popularity distribution map is drawn based on the access popularity.

[0032] Specifically, for each data block in the data access sequence list, multiple time windows are divided along the time axis, and the access frequency of the data block within each time window is counted. The process of obtaining access frequency information first requires determining the length and number of time windows. This length can be set according to the typical cycle of the task processed by the HBF chip; for example, in an AI training scenario, one training epoch or several iteration steps can be set as one time window. Then, based on the access timestamps recorded in the data access sequence list, the entire access sequence is divided into continuous and non-overlapping time windows along the time axis. Next, for each time window, all access records contained within it are traversed, the data block address is extracted, and its occurrence frequency is accumulated, thereby generating corresponding access frequency information for each data block within each time window. This information is stored in the form of a triple of "(data block address, time window number, access frequency)". Based on this, the access popularity of each data block in different time windows is calculated based on the access frequency information. Specifically, a popularity calculation model is introduced, for example, using an exponential decay weighted method to assign higher weight to recent time windows. The formula can be expressed as: Popularity = Σ(access frequency i × α^(T)) / (2 * α^(T)) The process involves using the time window number (i), T (the latest window), and α (a decay factor, 0 < α ≤ 1), where i represents the time window number, T represents the latest window, α represents the decay factor, and ^ represents exponentiation. This process yields the overall heat value of each data block at the current moment. Finally, based on the access heat of all data blocks in each time window, a two-dimensional data heat distribution map is plotted with the data block address as the x-axis, the time window as the y-axis, and the heat value encoded by color depth or grayscale levels. For example, when the HBF chip performs deep neural network training, the model weight parameters are frequently accessed in each time window, and their access count is displayed as a consistently high value. After heat calculation, this appears as a bright band spanning multiple time windows in the distribution map. Conversely, some temporary intermediate variables used only in specific stages may only have access peaks in the 3rd or 5th time window, with zero access counts in other windows, thus appearing as isolated hotspots in the distribution map. Through these executable steps, not only is a quantitative characterization of temporal locality achieved, but a structured, visualized, and traceable data foundation is also provided for subsequent cache priority sorting.

[0033] In a specific embodiment, the cache space of the HBF chip is partitioned based on the cache priority list to obtain a cache partition mapping table, including: The data blocks in the cache priority list are divided into groups based on their number of groups, resulting in the number of groups for each partition. Based on the quantity information, the cache space of the HBF chip is divided proportionally to obtain initial cache partitions. Then, based on the priority sorted data blocks, the data blocks in each initial cache partition are matched and mapped to obtain a cache partition mapping table.

[0034] Specifically, the cache space of the HBF chip is partitioned and managed based on the cache priority list. First, the data blocks in the cache priority list need to be grouped. This step requires determining the number of data blocks at different priority levels based on their access frequency or importance. For example, in an AI training scenario, data blocks are sorted according to their access frequency and most recent access time during the entire training process, and then divided into high, medium, and low priority groups based on a pre-set priority threshold. Next, the cache space of the HBF chip is proportionally divided based on the number of data blocks in each partition. This means that if the high-priority group contains 30% of the total number of data blocks, then the cache space allocated to high-priority data blocks should also be 30% of the total cache space, and so on, ensuring that data blocks at each priority level receive storage resources corresponding to their quantity. After the initial cache partitioning is completed, the data blocks within each initial cache partition can be matched and mapped based on the priority-sorted data blocks. That is, according to the specific priority position of each data block, it is placed in the cache area of ​​the corresponding priority level to achieve efficient data management and fast access. For example, during deep neural network training, model weights, due to frequent updates and usage, reside in a high-priority group. Therefore, they are mapped to the core cache region near the processor to accelerate computation. Meanwhile, occasionally used intermediate variables or auxiliary data may be relegated to a low-priority group and placed in a larger external cache or main memory located further from the core. This approach not only optimizes the utilization efficiency of the HBF chip's internal resources but also effectively improves the overall system performance, demonstrating significant advantages, especially when handling large datasets or complex calculations. Finally, the cache partition mapping table generated based on the above steps records the detailed mapping relationship between each data block and the cache region, providing a reliable basis for subsequent data scheduling and management.

[0035] In a specific embodiment, the cache space of the HBF chip is divided proportionally based on the quantity information to obtain an initial cache partition, including: The quantity information is parsed to obtain the number of partitions, and the total cache space size is obtained through the cache space management unit of the HBF chip. The total cache space is proportionally divided based on the number of partitions to obtain the size of each partition. The cache space of the HBF chip is then divided according to the size of each partition to obtain the initial cache partitions.

[0036] Specifically, the process of dividing the cache space of the HBF chip proportionally based on the quantity information to obtain the initial cache partition first requires parsing the quantity information to extract the specific partition number value, which indicates how many independent regions the cache space will be divided into. Subsequently, the total available cache space size is read through the cache space management unit of the HBF chip. This value is usually measured in bytes or cache lines and serves as the basis for subsequent calculations. After obtaining the number of partitions and the total cache size, the system performs a proportional partitioning calculation, which divides the total cache size by the number of partitions to obtain the size of each partition. If there is a remainder in the division, the remainder is appended to the first few partitions in sequence to ensure that all cache space is fully utilized and the size difference between the partitions does not exceed one minimum allocation unit. Then, based on the size of each partition, starting from the beginning address of the cache space, a continuous memory region is divided in sequence. The first partition occupies the range from address 0 to the size of the first partition, the second partition follows immediately, and so on, until the last partition covers the end address of the total cache space, thus forming multiple physically continuous and logically isolated initial cache partitions. For example, when the HBF chip performs AI training tasks, if the cache priority list determines that it needs to be divided into three partitions to hold high, medium, and low-hot data blocks respectively, and the total cache space is 3 MB, then the space size of each partition is 1 MB. The system then defines the three address spaces of 0–1 MB, 1–2 MB, and 2–3 MB as high-hot, medium-hot, and low-hot zones respectively. Even if the total cache space cannot be divided evenly in some cases (such as a total space of 10 MB and 3 partitions), the remaining 1 MB can be divided equally or preferentially allocated to high-priority partitions, ensuring that resource allocation is both fair and takes performance requirements into account. Through the above series of executable operation steps, not only is the structured organization of the cache space realized, but a clear physical basis is also provided for subsequent data mapping and replacement strategies based on popularity.

[0037] In a specific embodiment, the replacement location of newly entered data blocks is selected according to the cache partition mapping table to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks, including: The cache partition mapping table is parsed to obtain the cache priority and space usage status of each partition; Based on the cache priority and space usage status of each partition, priority matching and space adaptation analysis are performed on newly entered data blocks to obtain a list of adapted partitions. The partitions in the adaptation partition list are sorted by priority and remaining space, and the optimal partition in the initial cache partition is selected as the replacement position to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks.

[0038] Specifically, the process of selecting a replacement location for newly entered data blocks in the cache according to the cache partition mapping table first requires parsing the cache partition mapping table to extract the cache priority and current space usage status of each partition. The space usage status specifically includes the used space size and remaining available space size of the partition. Then, based on this information, priority matching and space adaptation analysis are performed on the newly entered data blocks. That is, first, the priority level to which the data block belongs based on its popularity is determined, and then all partitions in the cache partition mapping table that match its cache priority and whose remaining space size is not less than the storage capacity required by the data block are selected, thereby generating a cache partition mapping table. A list of suitable partitions is generated. Next, each partition in this list is sorted based on two dimensions: first, the partition's cache priority (higher priority partitions appear earlier); second, the remaining space size (partitions with larger remaining space are ranked higher when priorities are the same, to improve subsequent write efficiency and reduce fragmentation). After sorting, the first partition from the top of the suitable partition list is selected as the target replacement location. If there is free space in this partition, the new data block is written directly. If there is no free space but it belongs to a low-priority subset (e.g., the partition itself is a low-hot area), the lowest-priority data block within that partition is further located and replaced according to the cache priority list. For example, when the HBF chip performs AI training tasks, if a new intermediate activation value data block is determined to be of medium popularity and needs to be loaded into the cache, the system first parses the cache partition mapping table. It finds that the medium-hot zone has zero remaining space, while the high-hot zone has space but a priority mismatch. The low-hot zone, however, has both matching priority and sufficient remaining space, so it is included in the suitable partition list. If multiple low-hot sub-partitions exist simultaneously, the one with the largest remaining space is selected as the final replacement location. Within this partition, the least frequently accessed temporary gradient data is replaced, ensuring that the high-hot model weights always reside in the high-hot zone without interference. Through these executable steps, fine-grained control of the cache replacement process is achieved. This ensures the persistent residence of high-value data while accurately cleaning up low-value data, effectively improving the overall efficiency and stability of the HBF chip caching system.

[0039] In a specific embodiment, based on the cache priority and space usage status corresponding to each partition, priority matching and space adaptation analysis are performed on newly entered data blocks to obtain an adapted partition list, including: The cache priority corresponding to each partition is parsed to obtain the priority level of each partition, and the priority attribute of the newly entered data block is obtained through the data block attribute reading unit of the HBF chip. The priority attribute of newly entered data blocks is compared with the priority level of each partition one by one to obtain priority-matching partitions; The space usage status corresponding to the priority matching partition is extracted to obtain the used space size and remaining space size of each matching partition, and the space size required for the newly entered data block is calculated by the space calculation unit of the HBF chip. The space required for the new data block entering the cache is compared with the remaining space of each matching partition to filter out partitions with enough remaining space to accommodate the new data block, thus obtaining a list of suitable partitions.

[0040] Specifically, based on the cache priority and space usage status corresponding to each partition, priority matching and space adaptation analysis are performed on newly entered data blocks to obtain the adapted partition list. First, the cache priority recorded in the cache partition mapping table is parsed to extract the priority level corresponding to each partition. These levels are usually represented numerically, such as high, medium, low, or 1, 2, 3. Simultaneously, the data block attribute reading unit of the HBF chip reads the metadata of the new data block before it enters the cache to obtain its priority attribute. This attribute is assigned by the aforementioned cache priority list and transmitted along with the data block. Then, the priority attribute of the newly entered data block is compared one by one with the priority level of each partition. If the two are different... If a partition matches or meets the preset mapping rules (such as "medium-priority data blocks can be placed in medium or low-priority partitions"), then the partition is marked as a priority matching partition. Next, the space usage status of all priority matching partitions is extracted, specifically including reading the current used space size and remaining space size of each matching partition from the cache partition mapping table. At the same time, the space calculation unit of the HBF chip accurately calculates the required space size of the new data block according to the length of the new data block or the cache line alignment requirements. Based on this, the required space size of the new data block is compared with the remaining space size of each priority matching partition, and only those partitions with remaining space greater than or equal to the required space size are retained, thereby filtering out the candidate partitions that truly have the capacity to accommodate the data block, and finally forming a list of suitable partitions. For example, when the HBF chip performs AI training tasks, if a gradient data block determined to be of "medium priority" needs to be loaded into the cache, the system first identifies all partitions in the cache with a priority level of "medium" or that allow backward compatibility (such as medium-hot and low-hot zones). Then, it checks the remaining space of each of these two partitions—assuming the medium-hot zone has 64 bytes of remaining space and the low-hot zone has 128 bytes of remaining space, and the gradient data block is calculated to require 96 bytes, only the low-hot zone meets the space requirement, so the adaptation partition list only includes the low-hot zone; if both partitions meet the requirement, both are included in the adaptation partition list for subsequent comprehensive sorting. Through the above series of strict and executable operation steps, it is ensured that the cache placement of new data blocks conforms to both the heat strategy and physical space constraints, laying the foundation for prioritizing the residence of high-hot data blocks and targeted replacement of low-hot data blocks.

[0041] The above describes the HBF chip intelligent cache prefetching and replacement strategy method in the embodiments of the present invention. The following describes the HBF chip intelligent cache prefetching and replacement strategy system in the embodiments of the present invention. Please refer to [link / reference]. Figure 2 One embodiment of the HBF chip intelligent cache prefetching and replacement strategy system of the present invention includes: The statistics module 21 is used to perform access frequency statistics on cached prefetched data, obtain a data access sequence list, and perform time access analysis on cached prefetched data based on the data access sequence list to obtain a data heat distribution map. Analysis module 22 is used to perform priority sorting analysis on the cache prefetched data based on the data heat distribution map to obtain a cache priority list; Management module 23 is used to partition the cache space of the HBF chip based on the cache priority list to obtain a cache partition mapping table; Selection module 24 is used to select the replacement location of newly entered data blocks according to the cache partition mapping table, so as to realize the priority of high-frequency data blocks and the targeted replacement of low-frequency data blocks.

[0042] In this embodiment, the specific implementation of each unit in the above system embodiment is the same as that in the above method embodiment, and will not be repeated here.

[0043] like Figure 3 As shown in the diagram, this embodiment of the invention provides a structural schematic block diagram of a computer device, including: At least one processor; At least one memory for storing at least one program; When at least one program is executed by at least one processor, the at least one processor implements the above-described HBF chip intelligent cache prefetch and replacement strategy method.

[0044] It is evident that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented in this device embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0045] Furthermore, this application also discloses a computer program product or computer program stored in a computer-readable storage medium. The processor of a computer device can read the computer program from the computer-readable storage medium, and the processor executes the computer program, causing the computer device to perform the aforementioned HBF chip intelligent cache prefetch and replacement strategy method. Similarly, the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0046] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A method for intelligent cache prefetching and replacement strategy in HBF chips, characterized in that, Includes the following steps: Access frequency statistics are performed on cached prefetched data to obtain a data access sequence list, and time access analysis is performed on cached prefetched data based on the data access sequence list to obtain a data heat distribution map. Based on the data heat distribution map, the cache prefetched data is prioritized and analyzed to obtain a cache priority list; The cache space of the HBF chip is partitioned and managed based on the cache priority list to obtain a cache partition mapping table; The replacement location of newly entered data blocks is selected according to the cache partition mapping table, so as to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks.

2. The HBF chip intelligent cache prefetching and replacement strategy method according to claim 1, characterized in that, By analyzing the access frequency of cached prefetched data, a data access sequence list is obtained, including: The cache prefetch data is extracted by the cache prefetch data reading unit of the HBF chip to obtain the cache prefetch data fields; The cached prefetch data fields are sorted according to access time, and the number of accesses to the same data block address is accumulated to obtain a data access sequence table.

3. The HBF chip intelligent cache prefetching and replacement strategy method according to claim 1, characterized in that, Based on the data access sequence list, time access analysis is performed on the cached prefetched data to obtain a data heat distribution map, including: For each data block in the data access sequence list, multiple time windows are divided according to the time axis, and the number of accesses to the data block in each time window is counted to obtain access count information; Based on the access frequency information, the access popularity of each data block in different time windows is calculated, and a data popularity distribution map is drawn based on the access popularity.

4. The HBF chip intelligent cache prefetching and replacement strategy method according to claim 1, characterized in that, Based on the cache priority list, the cache space of the HBF chip is partitioned for management, resulting in a cache partition mapping table, including: The data blocks in the cache priority list are divided into groups based on their number of groups, resulting in the number of groups for each partition. Based on the quantity information, the cache space of the HBF chip is divided proportionally to obtain initial cache partitions. Then, based on the priority sorted data blocks, the data blocks in each initial cache partition are matched and mapped to obtain a cache partition mapping table.

5. The HBF chip intelligent cache prefetching and replacement strategy method according to claim 4, characterized in that, Based on the aforementioned quantity information, the cache space of the HBF chip is divided proportionally to obtain an initial cache partition, including: The quantity information is parsed to obtain the number of partitions, and the total cache space size is obtained through the cache space management unit of the HBF chip. The total cache space is proportionally divided based on the number of partitions to obtain the space size of each partition. The cache space of the HBF chip is then divided according to the space size to obtain the initial cache partitions.

6. The HBF chip intelligent cache prefetching and replacement strategy method according to claim 5, characterized in that, The replacement location for newly entered data blocks is selected based on the cache partition mapping table to prioritize the retention of high-frequency data blocks and selectively replace low-frequency data blocks, including: The cache partition mapping table is parsed to obtain the cache priority and space usage status of each partition; Based on the cache priority and space usage status of each partition, priority matching and space adaptation analysis are performed on newly entered data blocks to obtain a list of adapted partitions. The partitions in the adaptation partition list are sorted by priority and remaining space, and the optimal partition in the initial cache partition is selected as the replacement position to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks.

7. The HBF chip intelligent cache prefetching and replacement strategy method according to claim 6, characterized in that, Based on the cache priority and space usage status of each partition, priority matching and space adaptation analysis are performed on newly entered data blocks to obtain a list of adapted partitions, including: The cache priority corresponding to each partition is parsed to obtain the priority level of each partition, and the priority attribute of the newly entered data block is obtained through the data block attribute reading unit of the HBF chip. The priority attribute of newly entered data blocks is compared with the priority level of each partition one by one to obtain priority-matching partitions; The space usage status corresponding to the priority matching partition is extracted to obtain the used space size and remaining space size of each matching partition, and the space size required for the newly entered data block is calculated by the space calculation unit of the HBF chip. The space required for the new data block entering the cache is compared with the remaining space of each matching partition to filter out partitions with enough remaining space to accommodate the new data block, thus obtaining a list of suitable partitions.

8. A smart cache prefetching and replacement strategy system for HBF chips, characterized in that, include: The statistics module is used to count the access frequency of cached prefetched data, obtain a data access sequence list, and perform time access analysis on the cached prefetched data based on the data access sequence list to obtain a data heat distribution map. The analysis module is used to perform priority sorting analysis on the cached prefetched data based on the data heat distribution map to obtain a cache priority list; The management module is used to partition the cache space of the HBF chip based on the cache priority list to obtain a cache partition mapping table; The selection module is used to select the replacement location for newly entered data blocks according to the cache partition mapping table, so as to achieve priority retention of high-frequency data blocks and targeted replacement of low-frequency data blocks.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, The processor executes the steps of any one of claims 1 to 7 when executing a computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When a computer program is executed by a processor, it implements the steps of the method of any one of claims 1 to 7.

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