Data storage method, electronic equipment and storage medium
By combining the number of ECC error correction bits and historical erase time data, healthy blocks are dynamically selected for writing, solving the wear leveling problem of NAND Flash storage blocks, improving system reliability and memory lifespan, and achieving efficient wear leveling effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-03
AI Technical Summary
Existing wear leveling algorithms cannot promptly address the actual physical fatigue of NAND Flash memory blocks, leading to early failures and efficiency bottlenecks. In particular, in high-density and advanced processes, traditional methods struggle to push wear leveling efficiency above 95%.
By combining the number of ECC error correction bits and historical erase time data, the health of storage blocks is monitored in real time, and healthy storage blocks are dynamically selected for writing when writing data. The risk threshold is dynamically adjusted to avoid repeated erasure and writing of risky blocks and optimize wear leveling.
It achieves multi-dimensional and high-precision wear leveling control, improves system reliability and memory lifespan, can adapt to environmental changes, and achieves wear leveling efficiency of 95%~99%.
Smart Images
Figure CN121785544A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage management technology, and in particular to a data storage method, electronic device and storage medium. Background Technology
[0002] For non-volatile memories (such as NAND Flash), existing wear leveling algorithms mainly rely on recording the number of erases and writes to each memory block in the memory, and determine the memory block to be written to next based on the number of erases and writes.
[0003] The inventors discovered that existing wear leveling algorithms, which rely solely on the number of erases, cannot reflect the true physical fatigue of memory blocks. This is especially true in high-density and advanced NAND flash memory, where the aging rate varies greatly. Some memory blocks may have deteriorated rapidly despite having few erases, while others may have been erased less frequently but are in good health.
[0004] This results in existing wear leveling algorithms being unable to respond promptly to early failures: a small number of memory blocks may experience a sharp performance degradation due to manufacturing defects or environmental stress, even when the number of erase cycles is far below the nominal lifespan. This leads to data read errors and uncorrectable ECC cycles, a phenomenon known as the "bottleneck effect," which severely impacts system reliability. Simultaneously, it creates an efficiency bottleneck, especially in high-endurance NAND flash memory, where traditional methods struggle to achieve wear leveling efficiency above 95%, resulting in the waste of thousands of erase / write cycles.
[0005] Therefore, improvements to existing technologies are necessary.
[0006] The above information is provided as background information only to aid in understanding this application and does not constitute an assertion or admission that any of the above content can be used as prior art relative to this application. Summary of the Invention
[0007] This application provides a data storage method, an electronic device, and a storage medium to solve the problem of poor wear leveling effect in the prior art.
[0008] To achieve the above objectives, this application provides the following technical solution:
[0009] In a first aspect, embodiments of this application provide a data storage method applied to an electronic device, the electronic device including a memory, the memory including multiple storage blocks, the data storage method including:
[0010] Each time a read data operation is performed, the number of ECC error correction bits generated by the current read data operation is determined. If the number of ECC error correction bits is greater than the risk threshold, the storage block corresponding to the current read data operation is determined to be a risk block, and a preset risk response operation is performed on the risk block. The risk threshold is determined based on the historical number of erasures of the storage block and the maximum ECC error correction capability of the memory.
[0011] When data is to be written, a target storage block is selected from the currently idle storage blocks based on the historical erase count and historical erase time data, and the write data operation is performed on the target storage block.
[0012] Optionally, the preset risk response operation includes: lowering the usage priority of the risk block according to a preset method, and / or, moving the data of the risk block;
[0013] The usage priority is used to indicate the order in which the corresponding storage blocks are selected when writing data tasks are subsequently allocated;
[0014] The preset method includes: forcibly modifying the historical erase count of the risk block to the rated maximum erase count; and / or, adding a mark to the risk block, the mark being used to directly identify its lowest usage priority.
[0015] Optionally, the risk threshold does not exceed 75% of the maximum error correction capability of ECC, and the risk threshold is inversely proportional to the historical number of erases of the corresponding storage block.
[0016] Optionally, the method for determining the risk threshold includes:
[0017] ;
[0018] in, Risk threshold;
[0019] This represents the historical erase count for the current storage block.
[0020] This is the maximum number of erase cycles allowed.
[0021] This represents the maximum ECC error correction capability of the memory.
[0022] This is the slope coefficient, and its value range is... .
[0023] Optionally, the historical erase time data includes the latest erase time and / or the change in erase time; the change in erase time is the change in the latest erase time relative to the initial erase time.
[0024] Optionally, selecting a target storage block from currently idle storage blocks based on historical erase counts and historical erase time data includes:
[0025] From the currently idle storage blocks, first select the set of blocks whose historical erase count is lower than the preset erase count threshold, and then select the storage block with the shortest latest erase time or the smallest change in erase time as the target storage block.
[0026] Optionally, selecting a target storage block from currently idle storage blocks based on historical erase counts and historical erase time data includes:
[0027] Determine the lifetime attrition index of each currently idle storage block; the lifetime attrition index is calculated based on the historical write / erase count and historical erase time data of the corresponding storage block.
[0028] From the currently idle storage blocks, select the storage block with the smallest lifetime decay index as the target storage block.
[0029] Optionally, the life loss index is calculated according to the following formula:
[0030] ;
[0031] in, For the first The lifetime degradation index of a storage block;
[0032] These are the weighting coefficients, and ;
[0033] For the first The historical number of erase / write operations for each storage block;
[0034] For the first The maximum number of erase / write cycles per memory block;
[0035] For the first The latest erase time for each storage block;
[0036] For the first The initial erase time for each storage block;
[0037] The maximum acceptable erase time threshold.
[0038] Secondly, embodiments of this application provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement any of the above-described data storage methods.
[0039] Thirdly, embodiments of this application provide a computer-readable storage medium having computer-executable instructions stored thereon, which are executed by a computer processor to implement any of the data storage methods described above.
[0040] Compared with the prior art, this application has the following beneficial effects:
[0041] The invention achieves multi-dimensional, high-precision wear leveling control by combining the number of ECC error correction bits and historical erase time data. Compared with traditional solutions that rely solely on the number of erase cycles, it has the following significant advantages:
[0042] 1) Improved reliability: The health prediction mechanism based on ECC status can detect and isolate risk blocks caused by manufacturing defects or early aging in advance, avoiding sudden data reading errors and significantly improving the long-term operational reliability of the system.
[0043] 2) Maximize system lifespan: The dynamic allocation mechanism can optimize based on the actual physical state (fatigue) of the block rather than a simple historical count, which can push wear leveling efficiency to the limit (up to 95%~99%), thereby maximizing memory utilization.
[0044] 3) Enhanced adaptability: The erase time data reflects the true performance of the storage block under the current temperature and voltage environment, enabling the method to adapt to environmental changes and ensure that wear leveling is always based on the optimal physical indicators.
[0045] This application has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of this application. Attached Figure Description
[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0047] Figure 1This is a flowchart of the data storage method provided in the embodiments of this application. Detailed Implementation
[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0049] NAND Flash is a memory array composed of floating-gate transistors. Each memory cell represents the data state through the amount of charge in the floating gate. Data erasure and programming operations are controlled by the tunneling effect to manage the charge in the floating gate.
[0050] The inventors discovered that during the erasure and writing process, electrons pass through an extremely thin tunnel oxide layer. As the number of erasures and writes increases, the tunnel oxide layer will continue to age and become damaged. The damaged oxide layer makes it more difficult for electrons to be effectively and evenly extracted or injected during subsequent erasures. This manifests as increased erasure and writing time and a higher error rate, ultimately leading to bad blocks.
[0051] On the one hand, the time required to erase a block is positively correlated with the aging and damage degree of its tunnel oxide layer. The longer the erasure time, the more severe the physical aging of the block, the shorter its remaining lifespan, and the more likely it is to develop bad blocks.
[0052] On the other hand, physical aging of NAND Flash (damage to the tunnel oxide layer, charge leakage) directly leads to an increase in the bit error rate of data storage. The number of ECC error correction bits is a direct quantitative representation of the bit error rate. That is, the more ECC error correction bits there are, the more serious the current data error of the storage block is and the higher the degree of physical aging.
[0053] Based on this, please refer to Figure 1 This application proposes a data storage method applied to an electronic device, which includes a memory comprising multiple storage blocks. The method includes:
[0054] S1. When performing a read data operation, determine the number of ECC error correction bits generated by the current read data operation. If the number of ECC error correction bits is greater than the risk threshold, the storage block corresponding to the current read data operation is determined to be a risk block, and a preset risk response operation is performed on the risk block. The risk threshold is determined based on the historical number of erases of the storage block and the maximum ECC error correction capability of the memory.
[0055] S2. When data is to be written, select the target storage block from the currently idle storage blocks based on the historical erase count and historical erase time data, and perform the write operation on the target storage block.
[0056] Therefore, this application's embodiments introduce the number of ECC error correction bits as a health prediction indicator, and simultaneously introduce historical erasure time data as a dynamic allocation indicator to achieve the following mechanism:
[0057] The health prediction mechanism based on ECC status involves real-time monitoring of the number of ECC error correction bits during data reading. If the number of ECC error correction bits exceeds a risk threshold, the block is identified as a risky block, and measures are taken to accelerate its removal, such as setting the risky block's usage priority to the lowest level. Furthermore, the risk threshold is dynamically adjusted, not fixed. This is because the physical aging rate of the storage block changes dynamically during repeated erase and write operations. Therefore, this embodiment dynamically adjusts the risk threshold based on historical erase counts to adapt it to the current physical aging situation.
[0058] A dynamic allocation mechanism based on erasure time: When data needs to be written, the free block with better physical health is selected as the first choice of target storage block based on the historical number of erasures and the historical erasure time data, so as to ensure that the write is always allocated to the storage block with the best current state.
[0059] It is important to note that in this embodiment, the health prediction mechanism and the dynamic allocation mechanism work together: the health prediction mechanism provides risk blocks so that the dynamic allocation mechanism can accurately avoid them. Specifically, risk blocks identified by the health prediction mechanism can be included in the low-priority write list or directly prohibited from writing by the dynamic allocation mechanism. When writing data, healthy blocks with a low number of ECC error correction bits and short erase time are prioritized. This avoids the risk blocks from aging prematurely due to repeated writes and erases, and also prevents the risk of losing critical data due to high write error rates, thus optimizing wear leveling.
[0060] In summary, this invention achieves multi-dimensional and high-precision wear leveling control by combining the number of ECC error correction bits and historical erase time data. Compared with traditional solutions that rely solely on the number of erase cycles, it has the following significant advantages:
[0061] 1) Improved reliability: The health prediction mechanism based on ECC status can detect and isolate risk blocks caused by manufacturing defects or early aging in advance, avoiding sudden data reading errors and significantly improving the long-term operational reliability of the system.
[0062] 2) Maximize system lifespan: The dynamic allocation mechanism can optimize based on the actual physical state (fatigue) of the block rather than a simple historical count, which can push wear leveling efficiency to the limit (up to 95%~99%), thereby maximizing memory utilization.
[0063] 3) Enhanced adaptability: The erase time data reflects the true performance of the storage block under the current temperature and voltage environment, enabling the method to adapt to environmental changes and ensure that wear leveling is always based on the optimal physical indicators.
[0064] Furthermore, in some embodiments, the risk threshold does not exceed 75% of the maximum error correction capability of the ECC, and the risk threshold is inversely proportional to the number of historical erases. In other words, the more historical erases, the smaller the risk threshold; the fewer historical erases, the larger the risk threshold, and the risk threshold never exceeds 75% of the maximum error correction capability of the ECC.
[0065] This is because, on the one hand, the maximum error correction capability of ECC is the theoretical upper limit of the number of bit errors that the memory can correct. If the number of error-correcting bits reaches or approaches this upper limit, it means that the error rate of the memory block is on the verge of getting out of control. Once a sudden disturbance occurs (such as voltage fluctuations or temperature changes), ECC will be unable to complete error correction, directly leading to data loss or read / write failures. Therefore, this embodiment limits the risk threshold to a safe range of 75% to avoid the extreme situation of the error correction capability being exhausted. When a risk is identified, the system has a buffer time to execute preset risk response operations to eliminate or reduce the risk.
[0066] On the other hand, new storage blocks are theoretically in good health with a low error rate. In this case, the risk threshold is set more leniently (allowing a higher number of ECC correction bits), which avoids misjudging new healthy blocks as risky blocks and can quickly filter out inherently weak blocks (few historical erases but a high error rate). Conversely, older storage blocks have been erased more frequently, leading to accumulated damage to the tunnel oxide layer and an increased error rate due to repeated writes and erases. In this case, the risk threshold is set more strictly (allowing only a lower number of ECC correction bits), allowing for more accurate and early identification of risks caused by aging. Therefore, this embodiment, through a design where the risk threshold is inversely proportional to the number of historical erases, can dynamically adapt the risk threshold to the entire lifecycle of the storage block.
[0067] In some embodiments, the risk threshold can be determined by calculating it according to the following formula:
[0068] ;
[0069] in, Risk threshold;
[0070] This represents the historical erase count for the current storage block.
[0071] This is the maximum number of erase cycles allowed.
[0072] This represents the maximum ECC error correction capability of the memory.
[0073] This is the slope coefficient, and its value range is... The default value is 0.5, which can be fine-tuned based on different product models to ensure performance at the end of the product's lifespan. It will not drop to 0.
[0074] In step S1 above, the preset risk response operation may include:
[0075] One approach is to lower the usage priority of risky blocks according to a preset method. Usage priority indicates the order in which corresponding storage blocks are selected when subsequent write tasks are allocated. Based on this, in subsequent applications, the number of erases on risky blocks can be reduced, while the number of erases on healthy blocks can be increased, thereby achieving the effect of balancing the wear and tear on each storage block.
[0076] For example, the preset method may be: forcibly modifying the historical erase count of the risk block to the rated maximum erase count; and / or, adding a mark to the risk block, the mark being used to directly identify its lowest usage priority.
[0077] Another approach is to relocate the data in the risky block to reduce potential and urgent read errors and other risks associated with that block.
[0078] For example, the relocation process includes: requesting a new free block; copying the valid data of the risk block to the free block; updating the mapping table from logical address to physical address so that the original mapping pointing to the risk block points to the free block; performing an erase operation on the risk block to clear its data; and adding the erased risk block to the free block linked list with the maximum number of erases.
[0079] It should be noted that this relocation operation can be performed either immediately upon identification of the risky block, or after a certain delay following identification. During delayed execution, the data remains within the risky block, and the relocation request is sent to a low-priority garbage collection (GC) thread, where it will be processed when the system becomes idle.
[0080] In step S2 above, the historical erasure time data includes the latest erasure time and / or the change in erasure time; the change in erasure time is the change in the latest erasure time relative to the initial erasure time.
[0081] The latest erasure time refers to the time taken for the most recent erasure operation. It directly reflects the current degree of damage to the tunnel oxide layer and is an instant snapshot of the physical aging state.
[0082] The change in erase time measures the aging of a storage block from its new state to its current state. It directly reflects the aging rate. The larger the change, the more accumulated damage to the tunnel oxide layer and the faster the aging rate.
[0083] This embodiment combines the latest erase time and erase time change as two-dimensional indicators, which can more accurately filter out healthy storage blocks from free blocks, so as to allocate more write data tasks to them.
[0084] Based on this, in some embodiments, the method for selecting a target storage block from currently idle storage blocks in step S2 according to historical erase counts and historical erase time data may include:
[0085] From the currently idle storage blocks, first select the set of blocks whose historical erase count is lower than the preset erase count threshold (for example, the storage block with the fewest historical erase counts can be selected), and then select the storage block with the shortest latest erase time or the smallest change in erase time as the target storage block.
[0086] In some other embodiments, the method for selecting a target storage block from currently idle storage blocks in step S2 based on historical erase counts and historical erase time data may include:
[0087] Determine the lifetime attrition index of each currently idle storage block; the lifetime attrition index is calculated based on the historical write / erase count and historical erase time data of the corresponding storage block.
[0088] From all currently idle storage blocks, select the storage block with the smallest lifetime decay index as the target storage block.
[0089] This application embodiment prioritizes writing data to free blocks with higher health by using a lifespan wear index. This can increase the write operations on healthy blocks that have been erased many times but are actually in good health, while reducing the write operations on weak blocks that have been erased few times but are actually in poor performance. This dynamic allocation strategy makes the wear of all storage blocks more even, thereby improving the overall lifespan of the memory.
[0090] Weak blocks refer to memory blocks that have inherent defects during manufacturing (such as a thin oxide layer) or exhibit rapid aging characteristics in the early stages of use (such as a rapid increase in erasure time), and their actual lifespan is lower than the average level of the same batch.
[0091] In some embodiments, during the calculation of the lifetime attrition index, the weight of historical erasure time data can be given higher weight than the weight of historical write / erase count.
[0092] This is because the inventors discovered that the core of NAND Flash aging is the irreversible defects generated in the tunnel oxide layer during repeated erase and write operations. The outward manifestation of this physical damage is prolonged erase time: the more defects in the oxide layer, the greater the resistance to electron passage, and the longer the erase operation takes. In contrast, historical erase / write counts are merely statistical values of "usage frequency," failing to reflect the dispersion in aging rates caused by manufacturing process variations (for example, within the same batch of memory blocks, weaker blocks age much faster than ordinary blocks; they may have the same number of erase / write operations, but their erase times differ significantly). Therefore, assigning higher weight to historical erase time data allows the calculation of the lifespan degradation index to more closely reflect the actual physical state of the memory blocks, rather than relying solely on idealized assumptions about "number of erases."
[0093] Furthermore, in traditional solutions, a block is considered near failure only after reaching a specified write / erase count threshold. However, in real-world scenarios, many weak blocks exhibit high error rates and erase timeouts due to severe oxide layer damage even when the number of write / erase cycles is far below the specified threshold. Changes in erase timeout duration can show signs of failure earlier than the write / erase count threshold. Giving greater weight to erase timeout allows the lifetime decay index to detect this risk signal earlier, avoiding over-allocating write / erase tasks to weak blocks with low write / erase cycles but poor actual physical condition, thus improving the foresight and accuracy of the assessment.
[0094] Furthermore, in some embodiments, the lifetime loss index can be specifically calculated according to the following formula:
[0095] ;
[0096] in, For the first The lifetime degradation index of a storage block;
[0097] These are the weighting coefficients, and ;
[0098] For the first The historical number of erase / write operations for each storage block;
[0099] For the first The maximum number of erase / write cycles per memory block;
[0100] For the first The latest erase time for each storage block;
[0101] For the first The initial erase time for each storage block;
[0102] The maximum acceptable erase time threshold.
[0103] Secondly, embodiments of this application provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the data storage method described in any embodiment of this application.
[0104] The above-described device can execute the methods provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects for executing the methods, which will not be described in detail here.
[0105] It should be noted that the electronic device can be a mobile phone, tablet computer, desktop computer, laptop computer, handheld computer, notebook computer, super mobile personal computer, netbook, as well as cellular phone, personal digital assistant, augmented reality device, virtual reality device, artificial intelligence device, wearable device, in-vehicle device, smart home device and / or smart city device. The embodiments of this application do not impose any special restrictions on the specific type of the electronic device.
[0106] Thirdly, embodiments of this application provide a computer-readable storage medium having computer-executable instructions stored thereon, which, when executed by a processor, implement the data storage method provided in all embodiments of this application.
[0107] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.
[0108] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.
[0109] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.
[0110] Computer program code for performing the operations of this application can be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, and C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0111] Finally, it should be noted that although the above embodiments have been described in the text and drawings of this application, this should not limit the scope of patent protection of this application. Any technical solutions that are based on the essential concept of this application and utilize the content described in the text and drawings of this application, resulting in equivalent structural or procedural substitutions or modifications, as well as the direct or indirect application of the technical solutions of the above embodiments to other related technical fields, are all included within the scope of patent protection of this application.
Claims
1. A data storage method, characterized in that, Applied to an electronic device, the electronic device including a memory, the memory including multiple storage blocks, the data storage method includes: Each time a read data operation is performed, the number of ECC error correction bits generated by the current read data operation is determined. If the number of ECC error correction bits is greater than the risk threshold, the storage block corresponding to the current read data operation is determined to be a risk block, and a preset risk response operation is performed on the risk block. The risk threshold is determined based on the historical number of erasures of the storage block and the maximum ECC error correction capability of the memory. When data is to be written, a target storage block is selected from the currently idle storage blocks based on the historical erase count and historical erase time data, and the write data operation is performed on the target storage block.
2. The data storage method according to claim 1, characterized in that, The preset risk response operation includes: lowering the usage priority of the risk block according to a preset method, and / or, moving the data of the risk block; The usage priority is used to indicate the order in which the corresponding storage blocks are selected when writing data tasks are subsequently allocated; The preset method includes: forcibly modifying the historical erase count of the risk block to the rated maximum erase count; and / or, adding a mark to the risk block, the mark being used to directly identify its lowest usage priority.
3. The data storage method according to claim 1, characterized in that, The risk threshold does not exceed 75% of the maximum error correction capability of ECC, and the risk threshold is inversely proportional to the historical number of erases of the corresponding storage block.
4. The data storage method according to claim 3, characterized in that, The method for determining the risk threshold includes: ； in, Risk threshold; This represents the historical erase count for the current storage block. This is the maximum number of erase cycles allowed. This represents the maximum ECC error correction capability of the memory. This is the slope coefficient, and its value range is... .
5. The data storage method according to claim 1, characterized in that, The historical erase time data includes the latest erase time and / or the change in erase time; the change in erase time is the change in the latest erase time relative to the initial erase time.
6. The data storage method according to claim 5, characterized in that, The step of selecting a target storage block from currently idle storage blocks based on historical erase counts and historical erase time data includes: From the currently idle storage blocks, first select the set of blocks whose historical erase count is lower than the preset erase count threshold, and then select the storage block with the shortest latest erase time or the smallest change in erase time as the target storage block.
7. The data storage method according to claim 5, characterized in that, The step of selecting a target storage block from currently idle storage blocks based on historical erase counts and historical erase time data includes: Determine the lifetime attrition index of each currently idle storage block; the lifetime attrition index is calculated based on the historical write / erase count and historical erase time data of the corresponding storage block. From the currently idle storage blocks, select the storage block with the smallest lifetime decay index as the target storage block.
8. The data storage method according to claim 7, characterized in that, The life loss index is calculated using the following formula: ； in, For the first The lifetime degradation index of a storage block; These are the weighting coefficients, and ; For the first The historical number of erase / write operations for each storage block; For the first The maximum number of erase / write cycles per memory block; For the first The latest erase time for each storage block; For the first The initial erase time for each storage block; The maximum acceptable erase time threshold.
9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the data storage method as described in any one of claims 1 to 8.
10. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that, The computer-executable instructions are executed by a computer processor to implement the data storage method as described in any one of claims 1 to 8.