Semiconductor device, operating method and system thereof, and computer readable storage medium

Abstract

The invention provides a semiconductor device and an operation method and system thereof, and a computer readable storage medium. The semiconductor device comprises a storage array; the storage array comprises a first storage string and a second storage string; the first storage string comprises at least one first dummy storage unit; a peripheral circuit coupled to the memory array and configured to perform a programming operation on the at least one first dummy memory cell such that a threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold; wherein under the condition that the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, the difference between the current of the first memory string and the current of the second memory string is smaller than or equal to a preset threshold.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor device, a method of operating the same, a system thereof, and a computer-readable storage medium. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] This disclosure provides a semiconductor device, its operating method, system, and computer-readable storage medium.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, including:

[0005] A storage array; the storage array includes a first storage string and a second storage string; the first storage string includes at least one first dummy storage unit;

[0006] The peripheral circuitry, coupled to the memory array, is configured to: perform a programming operation on the at least one first dummy memory cell, such that the threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold; wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, the difference between the current of the first memory string and the current of the second memory string is less than or equal to a preset threshold.

[0007] In one optional implementation, the second storage string includes at least one second dummy storage cell; the threshold voltage of the at least one second dummy storage cell remains at the initial threshold; wherein, before performing a programming operation on the at least one first dummy storage cell, the current of the first storage string is greater than the current of the second storage string, and the difference between the current of the first storage string and the current of the second storage string is greater than the preset threshold.

[0008] In one optional implementation, the second storage string includes at least one second dummy storage cell; the peripheral circuitry is configured to:

[0009] A programming operation is performed on the at least one second dummy memory cell, such that the threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold to a second target threshold; wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold, the difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold.

[0010] In one alternative implementation, the first target threshold is equal to the second target threshold.

[0011] In one optional implementation, the first target threshold is greater than the second target threshold; wherein, before performing programming operations on the at least one first dummy memory cell and the at least one second dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

[0012] In an alternative implementation, the peripheral circuitry is further configured as follows:

[0013] Apply a read voltage to the target word line in the target memory block;

[0014] A first on-state voltage is applied to the non-target word lines in the target memory block;

[0015] A corresponding input voltage is applied to each of the multiple first selection lines in the target memory block;

[0016] A second on-state voltage is applied to each of the multiple second selection lines in the target memory block;

[0017] The current on the bit line coupled to the target memory block is sensed to obtain the current of the memory string in the target memory block;

[0018] The target storage block includes the first storage string and the second storage string.

[0019] In one alternative implementation, the peripheral circuit is specifically configured as follows:

[0020] A corresponding input voltage is applied to a first selection line coupled to a memory string in the target memory block to turn on the memory string;

[0021] A corresponding input voltage is applied to the first selection line of other memory strings coupled to the memory string on the same bit line to turn off all other memory strings.

[0022] In one optional implementation, the target storage block includes a plurality of storage units; the storage units are configured to store N-bit weight data, and the plurality of storage units in the target storage block are configured to have 2 N There are several memory states, and the read voltage is located between the threshold voltage distributions corresponding to two adjacent memory states; N is an integer greater than or equal to 1.

[0023] In one alternative implementation, the first selection line is one of the top selection line and the bottom selection line, and the second selection line is the other of the top selection line and the bottom selection line.

[0024] In one optional implementation, the peripheral circuitry includes: an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a voltage generator, a column decoder, and control logic; the ADC is coupled to the column decoder and the control logic; and the DAC is coupled to the voltage generator and the control logic.

[0025] In one alternative implementation, the semiconductor device includes a three-dimensional NAND-type memory.

[0026] In one optional embodiment, the semiconductor device includes a first semiconductor structure, a hybrid bonding layer, and a second semiconductor structure stacked along the thickness direction of the semiconductor device, the hybrid bonding layer being located between the first semiconductor structure and the second semiconductor structure; the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the memory array and the peripheral circuit are coupled through a bonding structure in the hybrid bonding layer.

[0027] In a second aspect, embodiments of this disclosure provide a system comprising: at least one semiconductor device as described in any of the above embodiments;

[0028] A controller, coupled to at least one of the semiconductor devices and configured to send input data to the semiconductor devices and receive computation results from the semiconductor devices.

[0029] Thirdly, embodiments of this disclosure provide a method for operating a semiconductor device, including:

[0030] A programming operation is performed on at least one first dummy memory cell included in the first memory string of the semiconductor device, such that the threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold.

[0031] Wherein, when the threshold voltage of at least one first dummy memory cell reaches the first target threshold, the difference between the current of the first memory string and the current of the second memory string contained in the semiconductor device is less than or equal to a preset threshold.

[0032] In one optional implementation, the operation method further includes:

[0033] The threshold voltage of at least one second dummy memory cell in the second memory string included in the semiconductor device remains at the initial threshold; wherein, before performing a programming operation on the at least one first dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

[0034] In one optional implementation, the operation method further includes:

[0035] A programming operation is performed on at least one second dummy memory cell included in the second memory string, such that the threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold to a second target threshold; wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold, the difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold.

[0036] In one alternative implementation, the first target threshold is equal to the second target threshold.

[0037] In one optional implementation, the first target threshold is greater than the second target threshold; wherein, before performing programming operations on the at least one first dummy memory cell and the at least one second dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

[0038] In one optional implementation, the operation method further includes:

[0039] A read voltage is applied to the target word line in the target memory block contained in the semiconductor device;

[0040] A first on-state voltage is applied to the non-target word lines in the target memory block;

[0041] A corresponding input voltage is applied to each of the multiple first selection lines in the target memory block;

[0042] A second on-state voltage is applied to each of the multiple second selection lines in the target memory block;

[0043] The current on the bit line coupled to the target memory block is sensed to obtain the current of the memory string in the target memory block;

[0044] The target storage block includes the first storage string and the second storage string.

[0045] In one optional implementation, applying corresponding input voltages to the plurality of first select lines in the target memory block includes:

[0046] A corresponding input voltage is applied to a first selection line coupled to a memory string in the target memory block to turn on the memory string;

[0047] A corresponding input voltage is applied to the first selection line of other memory strings coupled to the memory string on the same bit line to turn off all other memory strings.

[0048] In one optional implementation, the target storage block includes a plurality of storage units; the storage units are configured to store N-bit weight data, and the plurality of storage units are configured to have 2 N There are several memory states, and the read voltage is located between the threshold voltage distributions corresponding to two adjacent memory states; N is an integer greater than or equal to 1.

[0049] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the operation method described in any of the above embodiments.

[0050] In the technical solution provided in this disclosure, the peripheral circuit is configured to adjust the resistance of the memory string by adjusting the threshold voltage of the dummy memory cell in the memory string, so that the difference between the currents of different memory strings is less than a preset threshold. Thus, during the operation stage using semiconductor devices, the output current of different memory strings in the conducting state can be basically equal, thereby improving the reliability of the operation result of the multiplication and accumulation operation based on the multiple of the current on the bit line relative to the output current of a single memory string. Attached Figure Description

[0051] Figure 1 Illustration of a system provided in the embodiments of this disclosure Figure 1 ;

[0052] Figure 2 Illustration of a system provided in the embodiments of this disclosure Figure 2 ;

[0053] Figure 3 A schematic diagram of a memory card provided in an embodiment of this disclosure;

[0054] Figure 4 A schematic diagram of a solid-state drive provided in an embodiment of this disclosure;

[0055] Figure 5 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 1 ;

[0056] Figure 6 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 2 ;

[0057] Figure 7 This is a schematic diagram illustrating the input voltage to the memory block via word lines, provided as an embodiment of this disclosure.

[0058] Figure 8 A schematic diagram illustrating the input voltage to the memory block via a top selection line, provided for an embodiment of this disclosure;

[0059] Figure 9 A schematic diagram of the threshold voltage distribution of a memory cell coupled to a target word line, provided in an embodiment of this disclosure;

[0060] Figure 10 A schematic diagram of a string of multiple memory cells coupled to a bit line, provided in an embodiment of this disclosure;

[0061] Figure 11 A schematic diagram for measuring the current of a storage string according to an embodiment of this disclosure;

[0062] Figure 12 A current-voltage curve provided in an embodiment of this disclosure;

[0063] Figure 13 This is a schematic diagram showing the result of performing a programming operation on the first virtual storage unit according to an embodiment of this disclosure;

[0064] Figure 14 This is a schematic diagram illustrating the programming operation performed on the first and second virtual memory units according to embodiments of this disclosure. Figure 1 ;

[0065] Figure 15 The second current-voltage curve provided in this embodiment of the disclosure;

[0066] Figure 16 This is a schematic diagram illustrating the programming operation performed on the first and second virtual memory units according to embodiments of this disclosure. Figure 2 ;

[0067] Figure 17This is a schematic diagram of a computer-readable storage medium provided in an embodiment of this disclosure. Detailed Implementation

[0068] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0069] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0070] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0071] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0072] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0074] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0075] In the classic von Neumann computing architecture, the memory for storing data and the processor for data processing are separate, with data transfer between them via a data bus. When executing data processing commands, the processor first needs to read data from memory, process it, and then write the updated data back to memory. This requires frequent data transfer between memory and the processor, resulting in significant power consumption and time overhead. Furthermore, due to the limited bandwidth of memory, the processor's processing speed is limited by the memory access speed, thus restricting the improvement of computing performance. With the rise of applications such as big data and artificial intelligence, the demand for processing massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent.

[0076] To address the bottlenecks of the classic von Neumann computing architecture, in-memory computing chip architecture emerged. Its basic idea is to directly utilize memory for logical computation, thereby reducing the overhead caused by frequent data transfers between memory and processor, and improving computing performance while reducing power consumption.

[0077] In-memory computing chips possess both storage and computing capabilities due to their inherent physical characteristics. Storage capability refers to the ability to store numerical values ​​by changing the conductance of storage cells according to the physical characteristics of different types of memory cells. Computing capability refers to the ability to perform multiply-accumulate (MAC) operations by constructing an array of storage cells and applying Ohm's law and Kirchhoff's laws.

[0078] In specific examples, for in-memory computing chips, by changing the conductance of the storage cells, the weight matrix can be stored in the storage array according to a certain mapping rule. Specifically, the conductance of each storage cell can represent a weight in the weight matrix. After writing the weight matrix into the storage array, the elements in the input vector can be mapped to the voltage values ​​at the input terminals of the storage array. Taking mapping multiple elements in the input vector to multiple rows of input voltages as an example, based on Ohm's law, the current output by each storage cell in the storage array represents the result of multiplying an element in the input vector with a weight. Based on Kirchhoff's laws, summing the currents output by a column of storage cells yields the sum of multiple product results. The calculation result output by a column of storage cells corresponds to an element in the output vector. Thus, the calculation result of the weight matrix and the input vector can be output through a storage array containing multiple columns of storage cells. Therefore, the storage array in the in-memory computing chip not only stores the weight matrix, realizing both storage and computation functions.

[0079] In some embodiments, an in-memory computing chip may include one of the following types of memory: Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Phase-Change Memory (PCM), and NAND Flash Memory. NAND Flash Memory is a non-volatile memory with a large storage capacity. In particular, three-dimensional NAND flash memory, with its three-dimensional structure, has a high storage density and the potential to be developed into an in-memory computing chip. The following section will introduce the relevant content of three-dimensional NAND flash memory.

[0080] In some embodiments, a system including a three-dimensional NAND-type memory includes a semiconductor device and a controller coupled to the semiconductor device. The controller is configured to send input vectors or input matrices to the semiconductor device and to receive computation results from the semiconductor device.

[0081] In some embodiments, the system described above may be as follows: Figure 1 The system 102 shown includes a controller 103 and a semiconductor device 104 coupled to the controller 103.

[0082] According to some implementation methods, such as Figure 1 As shown, the controller 103 is coupled to the semiconductor device 104 and the host 101, and is configured to control the operation of the semiconductor device 104, such as read, erase, program, and compute operations.

[0083] In other embodiments, the system described in the above embodiments can be as follows: Figure 2 The system 100 shown includes a host 101 and a semiconductor device 104 that can communicate directly with the host 101. The controller in the above embodiment may be a central processing unit (CPU) in the host 101.

[0084] In such Figure 3 In one example shown, the system can be integrated into a memory card 200. The semiconductor device in the system can be the memory device 203 in the memory card 200, and the controller in the system can be the memory controller 202 in the memory card 200. The memory card 200 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 200 may also include a memory card connector 201 that couples the memory card 200 to a host computer. Figure 4 In another example shown, the system can be integrated into a solid-state disk (SSD) 210. The semiconductor device in the system can be a memory device 213 within the SSD 210, and the controller in the system can be a memory controller 212 within the SSD 210. The SSD 210 may also include a solid-state disk connector 211 that couples the SSD 210 to a host device. In some embodiments, the storage capacity and / or operating speed of the SSD 210 is greater than the storage capacity and / or operating speed of the memory card 200.

[0085] In other embodiments, the system can be integrated into a terminal device, and the controller can be the CPU of the terminal device. Here, the terminal device can be, but is not limited to, any terminal device or portable terminal device such as a mobile phone, smart TV, smart speaker, wearable device, tablet computer, desktop computer, all-in-one computer, handheld computer, laptop computer, server, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), laptop computer, mobile computer, augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, etc.

[0086] Figure 5 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 1 Semiconductor device 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. The memory array 301 is a three-dimensional NAND-type memory array, wherein memory cells 306 are NAND memory cells provided in the form of an array of memory strings 308, each memory string 308 extending vertically. In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons captured by the memory cell 306. Each memory cell 306 may be a charge-capture type memory cell including charge-capture transistors.

[0087] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0088] like Figure 5As shown, each memory string 308 may include a bottom select transistor 310 at its source terminal and a top select transistor 312 at its drain terminal. The bottom select transistor 310 and the top select transistor 312 can be configured to activate the selected memory string 308 during read and program operations. For example, during a program operation, the top select transistor 312 in the selected memory string 308 can be turned on, and the top select transistor 310 in the unselected memory string 308 can be turned off, so that only the selected memory string 308 can be coupled to the bit line (BL) 316, i.e., the selected memory string 308 is activated.

[0089] In some implementations, the sources of memory strings 308 within the same memory block 304 can be coupled via a Common Source Line (CSL) 314. In other words, all memory strings 308 within the same memory block 304 share a common source (ACS). According to some implementations, the top select transistor 312 of each memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 312) or a deselect voltage (e.g., 0V) to the corresponding top select transistor 312 via one or more top select lines (TSL) 313 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 310) or a deselect voltage (e.g., 0V) to the corresponding bottom select transistor 310 via one or more bottom select lines (BSL) 315.

[0090] like Figure 5 As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314. In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 in the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage bias can be used to couple the common source line 314 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read or program operations.

[0091] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, common-source line 314, bottom select line 315, and top select line 313, and for sensing voltage and / or current signals from each target memory cell 306 to operate the memory array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0092] Figure 6 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 2 .like Figure 6 As shown, the peripheral circuitry may include a page buffer / sensor amplifier 321, a column decoder / bit line driver 322, a row decoder / word line driver 323, a voltage generator 324, control logic 325, a register 326, a flash memory interface 327, and a data bus 328.

[0093] Page buffer / sensor amplifier 321 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 325. In one example, page buffer / sensor amplifier 321 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 321 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 321 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 322 can be configured to be controlled by control logic 325 and select one or more memory strings by applying a bit line voltage generated from voltage generator 324.

[0094] The row decoder / word line driver 323 can be configured to be controlled by control logic 325 and to select / deselect memory blocks of memory array 301 and select / deselect word lines of memory blocks. The row decoder / word line driver 323 can also be configured to drive word lines using word line voltages generated from voltage generator 324. In some embodiments, the row decoder / word line driver 323 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 323 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 324 can be configured to be controlled by control logic 325 and to generate word line voltages (e.g., read voltage, programming voltage, on-state voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0095] Control logic 325 can be coupled to each circuit described above and is configured to control the operation of each circuit. Register 326 can be coupled to control logic 325 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 327 can be coupled to control logic 325 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic 325, as well as to buffer status information received from control logic 325 and relay it to the memory controller. Flash interface 327 can also be coupled to column decoder / bitline driver 322 via data bus 328 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0096] In some embodiments, continue to refer to Figure 6 When a semiconductor device including a three-dimensional NAND flash memory is used as a memory computing chip, in addition to the circuits mentioned above, the peripheral circuits may also include a digital-to-analog converter (DAC) circuit 331 and an analog-to-digital converter (ADC) circuit 332. The DAC circuit 331 is connected to the control logic 325 and the voltage generator 324, while the ADC circuit 332 is connected to the control logic 325 and the column decoder / BL driver 322. During the computation phase using the three-dimensional NAND flash memory, the control logic 325 can receive input data sent by the controller, the DAC circuit 331 can convert the input data into a voltage signal, and the voltage generator 324 can generate a corresponding input voltage based on the voltage signal. The analog computation result obtained after the computation can be transmitted to the ADC circuit 332, which can convert the analog computation result into a digital computation result.

[0097] In some embodiments, for in-memory computing chips, it is necessary to perform operations on input data and weight matrices. The input data can be an input vector or an input matrix composed of multiple elements, and the weight matrix is ​​composed of multiple weights. Each element in the input data needs to be multiplied and added with the multiple weights in the weight matrix to obtain the corresponding element in the output data.

[0098] To achieve the aforementioned computational functions, the memory array in the semiconductor device can be configured to store a weight matrix. Specifically, the weights in the weight matrix can be written into the memory array according to a certain mapping rule, and each memory cell in the memory array can be configured to store one weight. During the inference operation phase, the semiconductor device can receive input data from the controller. The input data can be an input vector or an input matrix composed of multiple elements. Each element in the input data can be converted into an input voltage by a digital-to-analog converter circuit and input to the memory array via bit lines or word lines.

[0099] In some specific examples, Figure 7 This is a schematic diagram showing the input voltage being input to the memory block via the word line. (Example) Figure 7 As shown, the memory cell coupled to the target word line WLn can be configured to store weight data in the weight matrix. Specifically, the memory state corresponding to the threshold voltage of the memory cell can correspond to a weight data. An input voltage V can be applied to the target word line WLn. in And apply a turn-on voltage V to the non-target word line coupled to the same memory block. pass This ensures that all memory cells coupled to the non-target word line are in a conducting state. In this case, whether each memory string generates a significant current depends solely on whether the threshold voltage of the memory cell coupled to the target word line WLn is greater than the input voltage V. in Related to, when the input voltage V in When the voltage exceeds the threshold voltage of the memory cell, the memory string to which that memory cell belongs will conduct and generate a significant current. When the input voltage V... in When the voltage is less than the threshold voltage of the memory cell, the memory string to which that memory cell belongs is turned off, and no significant current is generated. In this case, the current on each bit line can be detected at the end coupled to the sensing circuit. Taking bit line BL0 as an example, the current I0 on it corresponds to the input voltage V. in Corresponding input data and weights w 00 w 10 w 20 Multiply and then sum the results.

[0100] In the example above, only one element of the input data can be processed at a time along with the weight matrix, resulting in low computational flexibility. Furthermore, when the input data is an input vector or matrix containing multiple elements, the input voltages corresponding to these elements must be sequentially input via the target word line WLn, leading to a longer computation cycle and lower efficiency. Therefore, further optimization of the computational scheme for semiconductor devices, including three-dimensional NAND flash memory, is required.

[0101] In this embodiment of the disclosure, the input voltage corresponding to the element in the input data can be input via a first selection line, which can be either a top selection line or a bottom selection line. Figure 8 This is a schematic diagram illustrating the input voltage to the memory block via the top selection line, as provided in an embodiment of this disclosure. Figure 9 This is a schematic diagram of the threshold voltage distribution of a memory cell coupled to a target word line, provided in an embodiment of this disclosure. Figure 10 This is a schematic diagram of multiple memory strings coupled to a bit line, provided in an embodiment of this disclosure.

[0102] In some specific examples, such as Figure 8 As shown, the input voltage corresponding to an element in the input data can be input via multiple top select lines. During the computation phase using semiconductor devices, a read voltage V can be applied to the target word line WLn coupled to the target memory block. rd Appropriate input voltages are applied to the multiple top select lines coupled to the target memory block. For example, input voltages V can be applied to the top select lines TSL0, TSL1, and TSL2 coupled to the target memory block. in0 V in1 V in2 A first on-state voltage is applied to a non-target word line coupled to the target memory block. For example, a first on-state voltage V can be applied to word line WLn+1. pass1 A second on-state voltage is applied to the bottom select line coupled to the target memory block; for example, a second on-state voltage V can be applied to the bottom select line BSL. pass2 The computation result can be obtained by sensing the current on the bit line coupled to the target memory block and converting the current on the bit line. For example, by sensing the current I0 on the bit line BL0 and converting the current I0, the result can be obtained by converting the current I0 relative to the input voltage V. in0 Corresponding elements and weights w 00 The product of the input voltage V in1 Corresponding elements and weights w 10 The product of the input voltage V in2 Corresponding elements and weights w 20 The sum of the product of these three.

[0103] In some embodiments, the target storage block includes a plurality of storage units, which can be configured to store N-bit weight data, and the plurality of storage units in the target storage block are configured to have 2 N Each memory state, and the read voltage V in the example above. rd It lies between the threshold voltage distributions corresponding to two adjacent memory states. Here, N is an integer greater than or equal to 1.

[0104] In some specific examples, such as Figure 9 As shown, taking a storage cell configured to store 1 bit of weighted data as an example, multiple storage cells in the target storage block have a first memory state and a second memory state. The threshold voltage of the storage cell with the first memory state is less than the threshold voltage of the storage cell with the second memory state. The read voltage V rd The threshold voltage is greater than that of the memory cell with the first memory state and less than that of the memory cell with the second memory state. Here, the memory cell in the target memory block can be a single-level cell (SLC) storing one bit of data, the first memory state can be an erase state (E), and the second memory state can be a programmable state (P). The peripheral circuit can be configured to perform a programming operation on the memory cell coupled to the target word line before performing the operation, writing weights to the memory cell according to a certain mapping rule. For a single-level cell, the weight writing process includes applying a corresponding programming voltage to adjust the threshold voltage of a portion of the memory cells coupled to the target word line to the range of the threshold voltage distribution corresponding to the second memory state.

[0105] In some embodiments, refer to Figure 10Taking a target memory block comprising eight memory strings coupled to bit line BL0 as an example, four memory cells coupled to the target word line WLn are in the first memory state (erase state E), and the other four memory cells are in the second memory state (programming state P). Input data can be input from the eight top select lines TSL0 to TSL7. Specifically, the input data can be an input vector comprising eight elements, which can include five "1"s and three "0"s. The digital-to-analog converter circuit can convert each element of the input vector into a corresponding voltage signal, and conduct a voltage generator to convert the voltage signal into an input voltage to be applied to the top select line. The input voltage is then transmitted to the top select line through a driver coupled to the top select line. Specifically, the eight input voltages can be applied to the eight top select lines simultaneously. Specifically, the input voltage corresponding to "1" turns on the top select transistors TSG0, TSG1, TSG4, TSG5, and TSG6, which are coupled to the top select lines TSL0, TSL1, TSL4, TSL5, and TSL6, respectively, while the input voltage corresponding to "0" turns off the top select transistors TSG2, TSG3, and TSG7, which are coupled to the top select lines TSL2, TSL3, and TSL7, respectively. Furthermore, a first on-state voltage V can be applied to the non-target word lines coupled to the target memory block. pass1 This ensures that all memory cells coupled to non-target word lines are turned on; a second on-state voltage V is applied to the bottom select line BSL coupled to the target memory block. pass2 This ensures that all bottom select transistors coupled to the bottom select line BSL are turned on. In this case, the current I0 on the bit line BL0 is the sum of the output currents of the eight memory strings coupled to the bit line BL0. The input voltage on the top select line coupled to memory strings Str0, Str4, and Str5 causes the top select transistors TSG0, TSG4, and TSG5 to be turned on. The memory cells in memory strings Str0, Str4, and Str5 coupled to the target word line WLn have a first memory state (erase state E). Therefore, memory strings Str0, Str4, and Str5 are turned on, which can generate a current greater than or equal to a preset current. The current I0 on the bit line BL0 is approximately equal to the sum of the output currents of memory strings Str0, Str4, and Str5, and the multiple of the current I0 relative to the current generated by any one of the memory strings Str0, Str4, and Str5 is approximately 3. If the weight value stored in the memory cell in the first memory state is equivalent to "1", and the weight value stored in the memory cell in the second memory state is equivalent to "0", then the operation performed by the eight memory strings coupled to the bit line BL0 can be equivalent to: 1*1+1*0+0*1+0*0+1*1+1*1+1*0+0*0=3.

[0106] In the computational scheme provided in the above embodiments, when there are Y+1 memory strings coupled to bit lines BLx in the target memory block, the Y+1 elements corresponding to the input voltage input by the top selection lines of the Y+1 strings are α0, α1...α... Y The Y+1 memory cells coupled to the target word line WLn store weights w0, w1, ..., w1, respectively. Y The equivalent calculation result of the current on bit line BLx being a multiple of the output current greater than or equal to the preset current can be α. 0* w0+α 1* w1+……+α Y* w Y This multiplication and accumulation operation includes Y+1 multiplication operations, and the multipliers in the multiple multiplication operations are α0, α1, ..., α... Y They are not the same, and for the entire target memory block, the multipliers of the multiplication operations performed with memory strings coupled to different top selection lines can be different, thereby improving the flexibility of the operation and facilitating the implementation of more complex operations through semiconductor devices.

[0107] In the above-described embodiment, the calculation result is obtained based on the multiple of the current on the bit line relative to the output current of a single memory string. When the threshold voltage of the memory cell coupled to the target word line is less than the read voltage (e.g., all memory cells coupled to the target word line are in the erase state, and the input voltage applied to the top select line causes the top select transistor to be in the on state), the difference between the output currents of different memory strings should be less than a preset threshold to ensure that the result of the multiplication and accumulation operation based on the current on the bit line is reliable. However, due to manufacturing process errors, the performance of different memory strings may vary. For example, the resistance values ​​of different memory strings may vary significantly, which may lead to significant differences in the output current when different memory strings are turned on. This may reduce the reliability of the calculation result.

[0108] To further improve the reliability of semiconductor devices as in-memory computing chips, the present disclosure proposes the following implementation methods.

[0109] This disclosure provides a semiconductor device, including: a memory array; the memory array including a first memory string and a second memory string; the first memory string including at least one first dummy memory cell; and peripheral circuitry coupled to the memory array and configured to: perform a programming operation on the at least one first dummy memory cell, such that the threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold; wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, the difference between the current of the first memory string and the current of the second memory string is less than or equal to a preset threshold.

[0110] In this embodiment of the disclosure, in order to improve the reliability of the semiconductor device as a memory computing chip, the difference in current between different memory strings can be reduced by adjusting the threshold voltage of the dummy memory cells in the memory string before the semiconductor device is used for computation. Here, the current of the memory string can be the current on the bit line sensed when only one of the multiple memory strings connected to a bit line is turned on.

[0111] In some specific examples, such as Figure 11 As shown, the storage array includes a first storage string STR1 and a second storage string STR2. The first storage string STR1 is coupled to a bit line BL1, and the second storage string STR2 is coupled to a bit line BL2. The first storage string STR1 includes at least one first dummy storage cell coupled to a dummy word line WLd, and the second storage string STR2 includes at least one second dummy storage cell coupled to a dummy word line WLd.

[0112] It should be noted that in the embodiments of this disclosure, the first storage string and the second storage string can represent two types of storage strings in the target storage block. The first storage string can represent a storage string with lower resistance and corresponding higher current, while the second storage string can represent a storage string with higher resistance and corresponding lower current. For ease of explanation, this is illustrated by an example of a first storage string STR1 and a second storage string STR2, with the first and second storage strings STR1 and STR2 respectively coupled to different bit lines. It is understood that the operation performed by the external circuit on the first storage string STR1 can be the same operation performed on all storage strings with lower resistance in the target storage block, and the operation performed on the second storage string STR2 can be the same operation performed on all storage strings with higher resistance in the target storage block. Furthermore, the first and second storage strings STR1 and STR2 can also be storage strings coupled to the same bit line.

[0113] Furthermore, in this embodiment of the disclosure, a dummy storage unit refers to a storage unit in the storage string that is not used for storing weights. Figure 11 Taking the example that both the first memory string STR1 and the second memory string STR2 include a dummy memory cell coupled to a dummy word line WLd, and that the dummy memory cell is coupled between the bit line and other memory cells in the memory string, this disclosure is not limited to this. In other embodiments, the dummy memory cell may be coupled between a common source and other memory cells in the memory string, or the dummy memory cell may be coupled between memory cells in the memory string. This disclosure does not impose specific limitations on the location or number of dummy memory cells in the memory string.

[0114] In some embodiments, the current in the memory string can be measured before performing programming operations on the first dummy memory cell. Specifically, such as Figure 11 As shown, the peripheral circuit can be configured to apply a read voltage V to the target word line WLn in the target memory block. rd Apply a first on-state voltage V to the non-target word lines in the target memory block. pass1 Apply corresponding input voltages to the multiple first selection lines in the target memory block; apply a second on-state voltage V to the multiple second selection lines in the target memory block. pass2 The current on the bit line coupled to the target memory block is sensed to obtain the current of the memory string in the target memory block. Here, the first selection line can be one of the top selection line and the bottom selection line, and the second selection line can be the other of the top selection line and the bottom selection line. In this embodiment of the disclosure, the first selection line is the top selection line and the second selection line is the bottom selection line as an example.

[0115] In this embodiment, the current of the memory string can be measured using a scheme similar to that used in the computation phase. In this case, the memory cells coupled to the target word line WLn can all be in a first memory state (erase state). Specifically, the peripheral circuitry is configured to: apply a corresponding input voltage to the first select line coupled to one memory string in the target memory block to turn on that memory string; and apply corresponding input voltages to the first select lines coupled to other memory strings on the same bit line to turn off the other memory strings. For example, when measuring the current of the first memory string STR1, the input voltage applied to the first select line coupled to the first memory string STR1 can turn on the top select transistor in the first memory string STR1. Then, when the read voltage V is applied to the target word line WLn... rd Apply a first on-state voltage V to the non-target word line. pass1 And apply a second on-state voltage V to the second selection line. pass2 In this case, the first memory string STR1 can be turned on, and only the first memory string STR1 among the multiple memory strings coupled to the bit line BL1 can be turned on. In this case, the current of the first memory string STR1 can be obtained by sensing the current on the bit line BL1.

[0116] In some embodiments, the current of each memory string in the target memory block can be measured using the above method. Taking the first memory string STR1 as having a smaller resistance and the second memory string STR2 as having a larger resistance as an example, Figure 12 As shown, before performing a programming operation on at least one first dummy memory cell, the current of the first memory string STR1 is Ia, and the current of the second memory string STR is Ib. Ia is greater than Ib, and the difference between Ia and Ib is greater than a preset threshold It. That is, the difference between the current Ia of the first memory string STR1 and the current Ib of the second memory string STR2 is large, which may affect the reliability of the operation.

[0117] In this embodiment of the disclosure, the peripheral circuit can be configured to perform a programming operation on at least one dummy memory cell in the first memory string STR1, such that the threshold voltage of at least one dummy memory cell is adjusted from an initial threshold to a first target threshold Vt1, and when the threshold voltage of at least one first dummy memory cell reaches the first target threshold Vt1, the difference between the current of the first memory string STR1 and the current of the second memory string STR2 is less than or equal to a preset threshold It.

[0118] In a specific example, the preset threshold It should be less than Ib / 2.

[0119] In some specific examples, programming at least one first dummy memory cell involves programming the first dummy memory cell using an Increment Step Pulse Program (ISPP) method. During ISPP, a bit line voltage (e.g., ground voltage Vss) is applied to the bit line BL1 coupled to the first memory string STR1, and an increasing programming voltage is applied to the dummy word line WLd coupled to at least one first dummy memory cell to program the at least one first dummy memory cell. The difference between two adjacent programming voltages is the step size of the step pulse. Between two adjacent programming pulses, a programming verification operation is performed, applying a verification voltage to the dummy word line WLd to confirm whether the threshold voltage of the first dummy memory cell has reached a first target threshold Vt1. If the first dummy memory cell fails the programming verification operation, the programming-verification operation continues until the threshold voltage of the first dummy memory cell reaches the first target threshold Vt1.

[0120] In some embodiments, refer to Figure 13 When the threshold voltage of at least one first dummy memory cell in the first memory string STR1 is adjusted to the first target threshold Vt1, the threshold voltage of at least one second dummy memory cell in the second memory string STR2 remains at the initial threshold Vt0. Here, the initial threshold Vt0 is less than the first target threshold Vt1.

[0121] In this embodiment of the disclosure, by performing a programming operation on at least one first dummy memory cell in the first memory string, the threshold voltage of the first dummy memory cell can be increased. While the magnitude of the conduction voltage applied to the dummy word line remains unchanged, the resistance of the first memory string in the conduction state can be increased, the current of the first memory string can be decreased, and the difference between the current of the first memory string and the current of the second memory string can be decreased, thereby improving the reliability of the calculation result.

[0122] In some embodiments, the peripheral circuit is configured to: perform a programming operation on at least one second dummy memory cell, such that the threshold voltage of at least one second dummy memory cell is adjusted from an initial threshold to a second target threshold Vt2; wherein, when the threshold voltage of at least one first dummy memory cell reaches the first target threshold Vt1 and the threshold voltage of at least one second dummy memory cell reaches the second target threshold Vt2, the difference between the current of the first memory string STR1 and the current of the second memory string STR2 is less than or equal to a preset threshold It.

[0123] In some embodiments, refer to Figure 14 The first target threshold Vt1 is equal to the second target threshold Vt2. The peripheral circuit is configured to perform programming operations on the first dummy memory cell in the first memory string STR1 and the second dummy memory cell in the second memory string STR2, so as to adjust the threshold voltage of the first dummy memory cell and the threshold voltage of the second dummy memory cell to the first target threshold Vt1. This allows for simultaneous increase in the resistance values ​​of the first memory string STR1 and the second memory string STR2. Here, the first dummy memory cell in the first memory string STR1 and the second dummy memory cell in the second memory string STR2 can be coupled to the same dummy word line WLd, allowing for simultaneous programming operations on both the first and second dummy memory cells.

[0124] In some specific examples, in conjunction with reference Figure 12 and Figure 15 By increasing the threshold voltage of all dummy memory cells in the memory string to the first target threshold Vt1, the resistance of the memory string can be increased, thus reducing the resistance when the read voltage Vt1 is applied to the target word line. rd The current of the storage string is reduced. For example, the current of the first storage string STR1 is reduced from Ia to Ia', and the current of the second storage string STR2 is reduced from Ib to Ib'. At the same time, the difference between the current of the first storage string and the current of the second storage string can be compressed, thereby improving the reliability of the calculation results.

[0125] In some embodiments, refer to Figure 16 The peripheral circuit is also configured to perform a programming operation on at least one second dummy memory cell, such that the threshold voltage of at least one second dummy memory cell reaches a second target threshold Vt2, and the first target threshold Vt1 is greater than the second target threshold Vt2.

[0126] In some specific examples, both the first target threshold Vt1 and the second target threshold Vt2 are higher than the target threshold Vt0, and the first target threshold Vt1 is within the range of the threshold voltage distribution corresponding to the programming state, while the second target threshold Vt2 may still be within the range of the threshold voltage distribution corresponding to the erasure state.

[0127] In this embodiment, programming operations can be performed on the first dummy storage cell in the first storage string and the second dummy storage cell in the second storage string to adjust the threshold voltage of the first dummy storage cell to a first target threshold and the threshold voltage of the second dummy storage cell to a second target threshold. The first target threshold is greater than the second target threshold. This allows for an increase in the resistance of the first storage string (which had a lower resistance before the programming operation) to be greater than the increase in the resistance of the second storage string (which had a higher resistance). This further reduces the difference between the current in the first storage string and the current in the second storage string, improving the reliability of the calculation results.

[0128] In this embodiment of the disclosure, before performing calculations using semiconductor devices, the resistance of the memory strings in the target memory block can be adjusted by the method provided in any of the above embodiments, so that the difference between the currents of different memory strings is less than a preset threshold. Thus, during the calculation stage using semiconductor devices, the output currents of different memory strings in the conducting state can be basically equal, thereby improving the reliability of the calculation results of the multiplication and accumulation operation based on the multiple of the current on the bit line relative to the output current of a single memory string.

[0129] In some embodiments, the semiconductor device in the above embodiments includes a three-dimensional NAND type memory.

[0130] In the embodiments disclosed herein, the semiconductor device in any of the above embodiments can be obtained without making significant modifications to the three-dimensional NAND-type memory, which is an integrated memory chip. That is, the effect of improving computing accuracy can be achieved without increasing the area of ​​the circuit and the chip.

[0131] In some embodiments, the semiconductor device in the above embodiments includes a first semiconductor structure and a second semiconductor structure, the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device.

[0132] In some embodiments, the semiconductor device includes a first semiconductor structure, a hybrid bonding layer, and a second semiconductor structure stacked along the thickness direction of the semiconductor device; the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the peripheral circuit and the memory array are coupled through a bonding structure in the hybrid bonding layer.

[0133] In this embodiment, the first and second semiconductor structures of the semiconductor device can be formed by bonding two wafers. For example, the first semiconductor structure can be formed on one wafer, and the second semiconductor structure can be formed on another wafer. The two wafers are then bonded to form a hybrid bonding layer between the first and second semiconductor structures. In other embodiments, the first and second semiconductor structures of the semiconductor device can also be formed on the same wafer, but the first and second semiconductor structures are stacked along the thickness direction of the semiconductor device. This stacked architecture saves more area of ​​the semiconductor device.

[0134] Based on a concept similar to the aforementioned semiconductor devices, this disclosure also provides a system comprising: at least one semiconductor device as described in any of the foregoing embodiments; and a controller coupled to at least one of the semiconductor devices and configured to send input data to the semiconductor device and receive computation results from the semiconductor device.

[0135] In some embodiments, the computational result of the semiconductor device can be the computational result obtained based on the current on the bit line in the above embodiments.

[0136] In other embodiments, the peripheral circuitry in the semiconductor device may also be configured to perform logical operations on the calculation results obtained based on the current on the bit line, so that the calculation result of the semiconductor device may be the result obtained by performing logical operations again on the calculation results obtained based on the current on the bit line in the above embodiments.

[0137] In some embodiments, the specific composition and functional implementation of the system can be referred to the preceding text. Figures 1 to 6 For the sake of brevity, the description will not be repeated here.

[0138] Based on a concept similar to the aforementioned semiconductor device, this disclosure also provides a method for operating a semiconductor device, comprising: performing a programming operation on at least one first dummy memory cell included in a first memory string included in the semiconductor device, such that the threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold; wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, the difference between the current of the first memory string and the current of the second memory string included in the semiconductor device is less than or equal to a preset threshold.

[0139] In some embodiments, the operation method further includes: maintaining the threshold voltage of at least one second dummy memory cell included in the second memory string of the semiconductor device at the initial threshold; wherein, before performing a programming operation on the at least one first dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

[0140] In some embodiments, the operation method further includes: performing a programming operation on at least one second dummy memory cell included in the second memory string, such that the threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold to a second target threshold; wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold, the difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold.

[0141] In some embodiments, the first target threshold is equal to the second target threshold.

[0142] In some embodiments, the first target threshold is greater than the second target threshold; wherein, before performing programming operations on the at least one first dummy memory cell and the at least one second dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

[0143] In some embodiments, the operation method further includes: applying a read voltage to a target word line in a target memory block included in the semiconductor device; applying a first on-state voltage to a non-target word line in the target memory block; applying corresponding input voltages to a plurality of first select lines in the target memory block; applying second on-state voltages to a plurality of second select lines in the target memory block; and sensing currents on bit lines coupled to the target memory block to obtain currents in memory strings in the target memory block; wherein the target memory block includes the first memory string and the second memory string.

[0144] In some embodiments, applying corresponding input voltages to the plurality of first select lines in the target memory block includes: applying a corresponding input voltage to a first select line coupled to one memory string in the target memory block to turn on the memory string; and applying corresponding input voltages to the first select lines coupled to other memory strings on the same bit line to turn off the other memory strings.

[0145] In some embodiments, the target storage block includes a plurality of storage units; each storage unit is configured to store N-bit weight data, and the plurality of storage units are configured to have 2 N There are several memory states, and the read voltage is located between the threshold voltage distributions corresponding to two adjacent memory states; N is an integer greater than or equal to 1.

[0146] Based on a concept similar to the operation method of the aforementioned semiconductor devices, this disclosure also provides a computer-readable storage medium. Figure 17 This is a schematic diagram of a computer-readable storage medium provided in an embodiment of this disclosure. The computer-readable storage medium 501 stores a computer program, which, when executed by the processor 502, can implement the operation method of the semiconductor device in any of the above embodiments.

[0147] In some specific embodiments, the computer-readable storage medium 501 may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0148] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0149] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0150] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0151] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Storage array; The storage array includes a first storage string and a second storage string; the first storage string includes at least one first dummy storage unit. The peripheral circuitry, coupled to the memory array, is configured to: perform a programming operation on the at least one first dummy memory cell, such that the threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold; wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, the difference between the current of the first memory string and the current of the second memory string is less than or equal to a preset threshold.

2. The semiconductor device according to claim 1, characterized in that, The second storage string includes at least one second dummy storage cell; the threshold voltage of the at least one second dummy storage cell remains at the initial threshold; wherein, before performing a programming operation on the at least one first dummy storage cell, the current of the first storage string is greater than the current of the second storage string, and the difference between the current of the first storage string and the current of the second storage string is greater than the preset threshold.

3. The semiconductor device according to claim 1, characterized in that, The second storage string includes at least one second dummy storage cell; the peripheral circuitry is configured as follows: A programming operation is performed on the at least one second dummy memory cell, such that the threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold to a second target threshold; wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold, the difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold.

4. The semiconductor device according to claim 3, characterized in that, The first target threshold is equal to the second target threshold.

5. The semiconductor device according to claim 3, characterized in that, The first target threshold is greater than the second target threshold; wherein, before performing programming operations on the at least one first dummy storage unit and the at least one second dummy storage unit, the current of the first storage string is greater than the current of the second storage string, and the difference between the current of the first storage string and the current of the second storage string is greater than the preset threshold.

6. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is also configured to: Apply a read voltage to the target word line in the target memory block; A first on-state voltage is applied to the non-target word lines in the target memory block; A corresponding input voltage is applied to each of the multiple first selection lines in the target memory block; A second on-state voltage is applied to each of the multiple second selection lines in the target memory block; The current on the bit line coupled to the target memory block is sensed to obtain the current of the memory string in the target memory block; The target storage block includes the first storage string and the second storage string.

7. The semiconductor device according to claim 6, characterized in that, The peripheral circuit is specifically configured as follows: A corresponding input voltage is applied to a first selection line coupled to a memory string in the target memory block to turn on the memory string; A corresponding input voltage is applied to the first selection line of other memory strings coupled to the memory string on the same bit line to turn off all other memory strings.

8. The semiconductor device according to claim 6, characterized in that, The target storage block comprises multiple storage units; each storage unit is configured to store N-bit weight data, and the multiple storage units in the target storage block are configured to have 2 N There are several memory states, and the read voltage is located between the threshold voltage distributions corresponding to two adjacent memory states; N is an integer greater than or equal to 1.

9. The semiconductor device according to claim 6, characterized in that, The first selection line is one of the top selection line and the bottom selection line, and the second selection line is the other of the top selection line and the bottom selection line.

10. The semiconductor device according to claim 1, characterized in that, The peripheral circuitry includes: an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a voltage generator, a column decoder, and control logic; the ADC is coupled to the column decoder and the control logic; the DAC is coupled to the voltage generator and the control logic.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a three-dimensional NAND flash memory.

12. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a first semiconductor structure, a hybrid bonding layer, and a second semiconductor structure stacked along the thickness direction of the semiconductor device, wherein the hybrid bonding layer is located between the first semiconductor structure and the second semiconductor structure; the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the memory array and the peripheral circuit are coupled through a bonding structure in the hybrid bonding layer.

13. A system, characterized in that, include: At least one semiconductor device as described in any one of claims 1 to 12; A controller, coupled to at least one of the semiconductor devices and configured to send input data to the semiconductor devices and receive computation results from the semiconductor devices.

14. A method of operating a semiconductor device, characterized in that, include: A programming operation is performed on at least one first dummy memory cell included in the first memory string of the semiconductor device, such that the threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold. Wherein, when the threshold voltage of at least one first dummy memory cell reaches the first target threshold, the difference between the current of the first memory string and the current of the second memory string contained in the semiconductor device is less than or equal to a preset threshold.

15. The operating method according to claim 14, characterized in that, The operation method further includes: The threshold voltage of at least one second dummy memory cell in the second memory string included in the semiconductor device remains at the initial threshold; wherein, before performing a programming operation on the at least one first dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

16. The operating method according to claim 14, characterized in that, The operation method further includes: A programming operation is performed on at least one second dummy memory cell included in the second memory string, such that the threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold to a second target threshold; wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold, the difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold.

17. The operating method according to claim 16, characterized in that, The first target threshold is equal to the second target threshold.

18. The operating method according to claim 16, characterized in that, The first target threshold is greater than the second target threshold; wherein, before performing programming operations on the at least one first dummy storage unit and the at least one second dummy storage unit, the current of the first storage string is greater than the current of the second storage string, and the difference between the current of the first storage string and the current of the second storage string is greater than the preset threshold.

19. The operating method according to claim 14, characterized in that, The operation method further includes: A read voltage is applied to the target word line in the target memory block contained in the semiconductor device; A first on-state voltage is applied to the non-target word lines in the target memory block; A corresponding input voltage is applied to each of the multiple first selection lines in the target memory block; A second on-state voltage is applied to each of the multiple second selection lines in the target memory block; The current on the bit line coupled to the target memory block is sensed to obtain the current of the memory string in the target memory block; The target storage block includes the first storage string and the second storage string.

20. The operating method according to claim 19, characterized in that, Applying corresponding input voltages to the plurality of first select lines in the target memory block includes: A corresponding input voltage is applied to a first selection line coupled to a memory string in the target memory block to turn on the memory string; A corresponding input voltage is applied to the first selection line of other memory strings coupled to the memory string on the same bit line to turn off all other memory strings.

21. The operating method according to claim 19, characterized in that, The target storage block comprises multiple storage units; each storage unit is configured to store N-bit weight data, and the multiple storage units are configured to have 2 N There are several memory states, and the read voltage is located between the threshold voltage distributions corresponding to two adjacent memory states; N is an integer greater than or equal to 1.

22. A computer-readable storage medium having a computer program stored thereon, the computer program performing the operating method as described in any one of claims 14 to 21 when executed by a processor.

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