Semiconductor device, preparation method thereof and electronic equipment
By constructing a gradient epitaxial pillar structure on a semiconductor structure and using laser-induced processing, the lattice mismatch problem in heterogeneous Si-Ge substrate combination was solved, achieving high-quality integration under monolithic process conditions and efficient integration of Si-Ge devices. This solved the lattice mismatch and stress concentration problems existing in the prior art, and improved the stability and reliability of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-03
Smart Images
Figure CN121793431A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method for fabricating the same, and an electronic device. Background Technology
[0002] As semiconductor processes advance to 3nm and below, CFET (Complementary FET) has become a key architecture for improving integration density and performance due to its ability to stack nMOS and pMOS in the vertical direction. However, if a heterogeneous combination of Si substrate nMOS and Ge substrate pMOS is used, lattice mismatch (e.g., 4.2% lattice mismatch) will lead to interface mismatch dislocations, stress concentration, and differences in thermal expansion coefficients, which will seriously affect device reliability.
[0003] In related technologies, heterogeneous integration methods such as wafer bonding and layer transfer (TLT / Smart-Cut) can achieve heterogeneous stacking, but they suffer from problems such as low yield, high interface defects, and difficulty in controlling flatness. Summary of the Invention
[0004] The purpose of this disclosure is to provide a conductor device and its fabrication method and electronic device. By constructing an epitaxial pillar structure with a compositional gradient between a first semiconductor structure and a second semiconductor structure, it can play the roles of lattice matching buffer, stress adjustment and thermal conductivity channel, thereby achieving high-quality integration of the second semiconductor structure and the first semiconductor structure under monolithic process conditions, and obtaining a stable semiconductor device structure without bonding or layer transfer processes.
[0005] To achieve the above objectives, according to a first aspect of this disclosure, a method for fabricating a semiconductor device is provided, the method comprising: A first hole structure is formed on a first semiconductor structure; the first semiconductor structure includes a first substrate formed of a first semiconductor material, a first active region located on the first substrate, and a first dielectric layer located above the first active region; wherein the first hole structure extends from the first dielectric layer to the first substrate; An epitaxial pillar structure is formed within the first hole structure, wherein, along the direction away from the first substrate, the material composition of the epitaxial pillar structure gradually changes from the first semiconductor material to the second semiconductor material; A second semiconductor structure is fabricated over the first dielectric layer, the second semiconductor structure including a second substrate formed of a second semiconductor material.
[0006] Optionally, fabricating the second semiconductor structure over the first dielectric layer includes: A second semiconductor material is deposited over the first dielectric layer to form an amorphous material layer; The amorphous material layer is transformed into a single crystal material layer by a laser-induced process. A second semiconductor structure is prepared using the single-crystal material layer as a second substrate.
[0007] Optionally, one of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.
[0008] Optionally, there are multiple first active regions, and two adjacent first active regions are separated by a first shallow trench isolation structure; The process of forming a first hole structure on the first semiconductor structure includes: The first dielectric layer and the first shallow trench isolation structure are etched sequentially to expose the first substrate and form a first hole, which forms the first hole structure.
[0009] Optionally, forming the first hole structure on the first semiconductor structure further includes: A first isolation layer is formed on the inner wall of the first hole.
[0010] Optionally, the diameter of the first hole structure is 100-200 nm.
[0011] Optionally, after fabricating the second semiconductor structure using the single-crystal material layer as the second substrate, the method includes: Contact holes are formed in the first semiconductor structure and / or the second semiconductor structure; The second semiconductor structure is electrically connected to the first semiconductor structure through the contact hole.
[0012] Optionally, the method further includes: Fabrication of the first semiconductor structure: Provide a first substrate; A first epitaxial layer and a first sacrificial layer are alternately formed on the first substrate; wherein the first epitaxial layer is made of a first semiconductor material; The first epitaxial layer and the first sacrificial layer are etched to form a first fin structure, and a first shallow trench isolation structure is formed between the first fin structures; Selectively etch the first sacrificial layer in the first fin structure, retaining the first epitaxial layer, to form the first channel; A first fully encircling gate structure is formed in the circumference of the first channel; A first source structure and a first drain structure are formed at both ends of the first all-around gate structure by selective epitaxial growth; A first dielectric layer is deposited over the first source structure, the first drain structure, and the first all-around gate structure, and a first metal wiring layer is fabricated; and / or The fabrication of the second semiconductor structure includes: A second epitaxial layer and a second sacrificial layer are alternately formed on the second substrate; wherein the second epitaxial layer is made of a second semiconductor material; The second epitaxial layer and the second sacrificial layer are etched to form a second fin structure, and a second shallow trench isolation structure is formed between the second fin structures; Selectively etch the second sacrificial layer in the second fin structure, retaining the second epitaxial layer, to form the second channel; A second fully encircling gate structure is formed circumferentially in the second channel; A second source structure and a second drain structure are formed at both ends of the second fully encircling gate structure by selective epitaxial growth; A second dielectric layer is deposited above the second source structure, the second drain structure, and the second all-around gate structure, and a second metal wiring layer is fabricated.
[0013] According to a second aspect of this disclosure, a semiconductor device is also provided, comprising: A first semiconductor structure includes a first substrate formed of a first semiconductor material, a first active region located on the first substrate, and a first dielectric layer located above the first active region. The first semiconductor structure further includes a first hole structure extending from the first dielectric layer to the first substrate; A second semiconductor structure, located above the first dielectric layer, includes a second substrate formed of a second semiconductor material; and An epitaxial pillar structure is disposed inside the first hole structure, wherein, along the direction away from the first substrate, the material composition of the epitaxial pillar structure gradually changes from the first semiconductor material to the second semiconductor material.
[0014] Optionally, one of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.
[0015] Optionally, there are multiple first active regions, and two adjacent first active regions are separated by a first shallow trench isolation structure; The first hole structure includes a first hole that passes sequentially through the first dielectric layer and the first shallow trench isolation structure and exposes the first substrate; The extension column structure is located inside the first hole.
[0016] Optionally, the first hole structure further includes a first isolation layer disposed on the inner sidewall of the first hole; The first isolation layer surrounds the circumference of the extended column structure.
[0017] Optionally, the diameter of the first hole structure is 100-200 nm.
[0018] Optionally, the second semiconductor structure and the first semiconductor structure are electrically connected through contact holes disposed in the first semiconductor structure and / or the second semiconductor structure.
[0019] Optionally, at least one of the first semiconductor structure and the second semiconductor structure is a fully all-around gate field-effect transistor.
[0020] According to a third aspect of this disclosure, an electronic device is also provided, the electronic device including a semiconductor device, the semiconductor device including the semiconductor device described above, or prepared by the method for preparing the semiconductor device described above.
[0021] The above-described technical solution, namely the semiconductor device fabrication method disclosed herein, firstly forms a first hole structure on a first semiconductor structure, wherein the first semiconductor structure (e.g., a Si-channel nMOS transistor) comprises a first substrate, a first active region, and a first dielectric layer stacked sequentially. Subsequently, an epitaxial pillar structure (Si...) is constructed within this first hole structure, with a continuous gradient from a first semiconductor material (e.g., Si, silicon) to a second semiconductor material (e.g., Ge, germanium). 1-x Ge x A gradient structure is used, and a second semiconductor structure (e.g., a pMOS transistor with a Ge or high-Ge content SiGe channel) is fabricated on top of the epitaxial pillar structure and the first dielectric layer. The material composition of the epitaxial pillar structure gradually changes from the first semiconductor material to the second semiconductor material (i.e., the material composition transitions gradually from the first substrate to the second substrate). This can serve as a lattice matching buffer, stress regulation, and thermal conductivity channel, thereby achieving high-quality integration of the second semiconductor structure (upper Ge substrate pMOS) and the first semiconductor structure (lower Si substrate nMOS) under monolithic process conditions, and obtaining a stable semiconductor device structure (e.g., CFET structure) without bonding or layer transfer processes.
[0022] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description
[0023] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1This is a flowchart of a method for fabricating a semiconductor device according to some embodiments of this disclosure; Figures 2 to 9 This is a schematic diagram of the process for fabricating a semiconductor device according to some embodiments of this disclosure.
[0024] Explanation of reference numerals in the attached figures 100 - First semiconductor structure; 101 - First epitaxial layer; 102 - First sacrificial layer; 103 - First via structure; 110 - First substrate; 120 - First all-around gate structure; 130 - First source structure; 140 - First drain structure; 150 - First shallow trench isolation structure; 160 - First dielectric layer; 170 - First contact hole; 180 - First metal wiring layer; 200-Extensional column structure; 300 - Second semiconductor structure; 301 - Amorphous material layer; 310 - Single crystal material layer; 320 - Second all-around gate structure; 330 - Second source structure; 340 - Second drain structure; 350 - Second shallow trench isolation structure; 360 - Second dielectric layer; 370 - Second contact hole; 380 - Second metal wiring layer; 400 - Interconnection contact hole. Detailed Implementation
[0025] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.
[0026] As semiconductor process nodes advance to 3nm and below, CFET (Complementary Field-Effect Transistor) is considered a key architecture in the post-FinFET era because it can stack nMOS and pMOS devices in the same vertical channel, significantly improving integration density and shortening interconnect paths. However, if a heterogeneous channel material combination is used—with a Si substrate nMOS and a Ge substrate pMOS on top—multiple challenges arise from differences in lattice constants (up to 4.2%) and mismatches in thermal expansion coefficients, including interface mismatches, stress concentration, and thermal budget conflicts, which seriously affect device performance and reliability.
[0027] Currently, mainstream technologies for achieving such heterogeneous stacks include wafer bonding and layer transfer (such as TLT / Smart-Cut), but these processes are complex, costly, and suffer from numerous interface defects and difficulties in flatness control, hindering their large-scale application. While monolithic epitaxial growth of Ge-on-Si structures is structurally simple, it is prone to stress cracking due to lattice mismatch, making it difficult to balance thermal stability and process compatibility. Therefore, there is an urgent need to develop a technical approach that can achieve high-quality vertical integration of Si and Ge devices on a monolithic substrate, ensuring lattice integrity and thermal management capabilities while being compatible with standard CMOS process flows.
[0028] The purpose of this disclosure is to provide a conductor device and its fabrication method and electronic device. By constructing an epitaxial pillar structure 200 with a compositional gradient between a first semiconductor structure 100 and a second semiconductor structure 300, it can play the roles of lattice matching buffer, stress adjustment and thermal conductivity channel, thereby achieving high-quality integration of the second semiconductor structure 300 and the first semiconductor structure 100 under monolithic process conditions, and obtaining a stable semiconductor device structure without bonding or layer transfer processes.
[0029] To achieve the above objectives, according to a first aspect of this disclosure, a method for fabricating a semiconductor device is provided, as shown in FIG1, the method comprising steps S100 to S300.
[0030] In step S100, a first hole structure 103 is formed on the first semiconductor structure 100. The first semiconductor structure 100 includes a first substrate 110 formed of a first semiconductor material, a first active region located on the first substrate 110, and a first dielectric layer 160 located above the first active region. The first hole structure 103 extends from the first dielectric layer 160 to the first substrate 110. It should be noted that the first dielectric layer 160 includes, but is not limited to, silicon dioxide, silicon nitride, etc.
[0031] In step S200, an epitaxial pillar structure 200 is formed in the first hole structure 103, wherein, along the direction away from the first substrate 110, the material composition of the epitaxial pillar structure 200 gradually changes from a first semiconductor material to a second semiconductor material, and the second semiconductor material is different from the first semiconductor material.
[0032] In step S300, a second semiconductor structure 300 is prepared over the first dielectric layer 160. The second semiconductor structure 300 includes a second substrate formed of a second semiconductor material.
[0033] Through the above-described technical solution, namely the semiconductor device fabrication method disclosed herein, a first hole structure is first formed on a first semiconductor structure 100, wherein the first semiconductor structure 100 (e.g., a Si-channel nMOS transistor) includes a first substrate 110, a first active region, and a first dielectric layer 160 stacked sequentially. Subsequently, an epitaxial pillar structure 200 (Si) is constructed within the first hole structure 103, which is a continuous gradient from a first semiconductor material (e.g., Si, silicon) to a second semiconductor material (e.g., Ge, germanium). 1-x Ge x A gradient structure is used, and a second semiconductor structure 300 (e.g., a pMOS transistor with a Ge or high-Ge content SiGe channel) is fabricated on top of the epitaxial pillar structure 200 and the first dielectric layer 160, including a second substrate. The material composition of the epitaxial pillar structure 200 gradually changes from the first semiconductor material to the second semiconductor material (i.e., the material composition transitions continuously in a gradient from the first substrate 110 towards the second substrate), which can serve as a lattice matching buffer, stress regulation, and thermal conductivity channel. This allows for the high-quality integration of the second semiconductor structure 300 (upper Ge substrate pMOS) and the first semiconductor structure 100 (lower Si substrate nMOS) under monolithic process conditions, obtaining a stable semiconductor device structure (e.g., a CFET structure) without bonding or layer transfer processes.
[0034] In some embodiments, the fabrication of the second semiconductor structure 300 over the first dielectric layer 160 includes: depositing a second semiconductor material over the first dielectric layer 160 to form an amorphous material layer 301.
[0035] The amorphous material layer 301 is transformed into a single crystal material layer 310 by laser-induced process.
[0036] A second semiconductor structure 300 is prepared using a single crystal material layer 310 as a second substrate.
[0037] The specific process may include the following steps.
[0038] Depositing an amorphous material layer: First, an amorphous material layer 301 (e.g., amorphous germanium) is deposited on the first dielectric layer 160 by chemical vapor deposition.
[0039] Laser treatment: The sample was irradiated with a green nanosecond laser with specific parameters. The laser parameters were: wavelength 532 nm, pulse width 13 ns, and frequency 50,000 Hz.
[0040] Liquid phase crystallization: The energy of the laser melts the amorphous material layer 301 of the second semiconductor material to form a liquid phase.
[0041] Guided crystallization: During the cooling and solidification process, the pre-prepared epitaxial pillar structure 200 below acts as a "seed" or guiding template, guiding the molten second semiconductor material to rearrange itself based on its orderly crystal lattice structure. Ultimately, the original amorphous material layer 301 is transformed into a high-quality single-crystal material layer 310, forming the second substrate. For example, amorphous germanium is transformed into single-crystal germanium to form a germanium substrate for fabricating pMOS.
[0042] The above-described technical solution, namely the semiconductor device fabrication method disclosed herein, firstly provides a first semiconductor structure 100 (e.g., a Si-channel nMOS transistor), comprising a first substrate 110, a first active region, and a first dielectric layer 160 stacked sequentially. Subsequently, a first hole structure 103 is formed thereon, and within this first hole structure 103, an epitaxial pillar structure 200 (Si) is constructed, which continuously gradients from a first semiconductor material (e.g., Si, silicon) to a second semiconductor material (e.g., Ge, germanium). 1-x Ge x A gradient structure is constructed, and an amorphous material layer 301 of the second semiconductor material is deposited on top of the epitaxial pillar structure 200. Then, a laser-induced process is used to transform the amorphous material layer 301 into a single-crystal material layer 310 to form a second substrate. Based on this second substrate, a second semiconductor structure 300 (e.g., a pMOS transistor with a Ge or high-Ge content SiGe channel) is fabricated. The material composition of the epitaxial pillar structure 200 gradually changes from the first semiconductor material to the second semiconductor material (i.e., the material composition transitions gradually from the first substrate 110 towards the second substrate). This can serve as a lattice matching buffer, stress regulation, and thermal conductivity channel, thereby achieving high-quality integration of the second semiconductor structure 300 (upper Ge substrate pMOS) and the first semiconductor structure 100 (lower Si substrate nMOS) under monolithic process conditions. A stable semiconductor device structure (e.g., CFET structure) can be obtained without bonding or layer transfer processes.
[0043] For example, when the first semiconductor material is Si and the second semiconductor material is Ge, Si can be epitaxially generated in the first hole structure 103 using low-temperature RPCVD. 1-x Ge x Epitaxial pillars, where x gradually changes from 0 to 1, thus forming silicon-germanium continuous gradient pillars.
[0044] The first semiconductor structure 100 and the second semiconductor structure 300 are not specifically limited. In some embodiments, both the first semiconductor structure 100 and the second semiconductor structure 300 can be all-around gate field-effect transistors. Of course, the first semiconductor structure 100 and the second semiconductor structure 300 can also be conventional planar MOSFETs or FinFETs (fin field-effect transistors).
[0045] The core of all-gate field-effect transistor (GAA FET) fabrication is to construct a gate structure that surrounds the channel. The mainstream fabrication method is based on "nanowire / nanosheet channel + gate surrounding deposition". The key is to first form a suspended channel and then achieve full encapsulation of the channel by thin film deposition.
[0046] The method also includes the step of preparing a first semiconductor structure 100, which may include the following steps.
[0047] A first substrate 110 is provided; the first substrate 110 may be made of a first semiconductor material, such as silicon.
[0048] A first epitaxial layer 101 and a first sacrificial layer 102 are alternately formed on a first substrate 110 by epitaxial growth. The first epitaxial layer 101 is made of a first semiconductor material. The first epitaxial layer 101 can be made of the same first semiconductor material as the first substrate 110, such as silicon, for subsequent communication. The first sacrificial layer 102 can be made of any suitable material, including but not limited to silicon-germanium, such as Si. 0.7 Ge 0.3 For example, Si layers (first epitaxial layer 101) and Si can be alternately epitaxially grown on a silicon substrate using an RPCVD (plasma-enhanced vapor deposition) process. 0.7 Ge 0.3 The first sacrificial layer (102) forms a superlattice structure.
[0049] The first epitaxial layer 101 and the first sacrificial layer 102 are etched to form the first fin structure, and a first shallow trench isolation structure 150 is formed between the first fin structures. A photolithography + etching process can be used to etch the stacked layers (alternating stacked first epitaxial layer 101 and first sacrificial layer 102) into elongated fin structures to form the first fin structure, and then a shallow trench isolation (STI) process is used to form the first shallow trench isolation structure 150 to achieve electrical isolation between devices.
[0050] The first sacrificial layer 102 in the first fin structure is etched while the first epitaxial layer 101 is retained to form the first channel. The etching selectivity of silicon and silicon-germanium (e.g., using hydrofluoric acid-based etching solution) can be utilized to etch away the first sacrificial layer 102 of silicon-germanium material on both sides of the first fin structure, leaving the first epitaxial layer 101 of silicon material in the middle suspended, forming an independent nanosheet channel array, i.e., the first channel.
[0051] A first fully encircling gate structure 120 is formed circumferentially around the first channel. A high-k gate dielectric layer (such as HfO2) and a metal gate electrode (such as TiN, W) are sequentially deposited around the suspended nanosheet channel. The uniformity of the dielectric layer and the electrode layer is ensured by atomic layer deposition (ALD) process, so as to achieve 360° encirclement of the nanosheet channel.
[0052] By selective epitaxial growth, a first source structure 130 and a first drain structure 140 are formed at both ends of the first fully surrounding gate structure 120. The first source structure 130 at one end can connect to one end of a plurality of first channels, and the first drain structure 140 at the other end can connect to the other end of a plurality of first channels, thereby leading out source and drain electrodes. That is, heavily doped source and drain regions are epitaxially grown at both ends of the first fully surrounding gate structure 120 (to improve conductivity), and subsequent connection between the device and external circuitry can be achieved through contact holes and metal interconnect layers.
[0053] A first dielectric layer 160 is deposited over the first source structure 130, the first drain structure 140, and the first all-around gate structure 120, and a first contact hole 170 and a first metal wiring layer 180 are formed. The first metal wiring layer 180 is electrically connected to the first source structure 130 and the first drain structure 140 through the first contact hole 170, respectively. The first metal wiring layer 180 facilitates interconnection with external circuits.
[0054] It should be noted that the first semiconductor structure 100 and the second semiconductor structure 300 can both be any suitable structural form, such as nMOS or pMOS. In some embodiments, the first semiconductor structure 100 can be nMOS and the second semiconductor structure 300 can be pMOS, and the two are stacked vertically in the vertical direction.
[0055] In some embodiments, one of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium. For example, the first semiconductor material can be silicon, and the second semiconductor material can be germanium. In step S300, the material composition of the epitaxial pillar structure 200 gradually changes from silicon to germanium in the direction from the first substrate 110 toward the second substrate (the single crystal material layer 310 to be formed subsequently). This allows the epitaxial pillar structure 200 to function as a lattice matching buffer, stress regulation, and thermal conductivity channel.
[0056] In other embodiments, the first semiconductor material can be germanium, and the second semiconductor material can be silicon. In step S300, the material composition of the epitaxial pillar structure 200 gradually changes from germanium to silicon in the direction from the first substrate 110 toward the second substrate (the single crystal material layer 310 to be formed subsequently). This also enables the epitaxial pillar structure 200 to function as a lattice matching buffer, stress regulation, and thermal conductivity channel.
[0057] Optionally, there are multiple first active regions, and adjacent first active regions are separated by a first shallow trench isolation structure 150. Forming a first hole structure 103 on the first semiconductor structure 100 includes: sequentially etching a first dielectric layer 160 and a first shallow trench isolation structure 150 to expose a first substrate 110 to form a first hole, and the first hole forms the first hole structure 103.
[0058] The first active region is the first source structure 130, the first drain structure 140 and the first all-around gate structure 120 between them. Considering that the first hole structure 103 needs to avoid the active region in physical space, the first dielectric layer 160, the first shallow trench isolation structure 150 between the first active regions and the upper surface of the first substrate 110 can be etched from top to bottom through an etching process to form the first hole, which forms the first hole structure 103.
[0059] To further reduce electrical isolation and stress between the epitaxial pillar structure 200 and the surrounding structure, in some embodiments, a first hole structure 103 is formed on the first semiconductor structure 100, further comprising forming a first isolation layer on the inner sidewall of the first hole. This first isolation layer can be an oxide or a nitride, which, on the one hand, improves the electrical isolation between the epitaxial pillar structure 200 and other metal layers or electrode structures; on the other hand, it improves stress buffering between the epitaxial pillar structure 200 and the layers.
[0060] The size and shape of the first hole structure 103 can be adjusted according to actual needs. In some embodiments, the diameter of the first hole structure 103 is 100-200 nm, and the height can be 200-400 nm. Within this size range, it can both meet the requirements of laser-induced process to transform the amorphous material layer 301 into a single crystal material layer 310, and meet the stress buffering requirements between the first substrate 110 and the second substrate.
[0061] After the second semiconductor is formed, the two can be electrically connected using interconnect contact holes 400. Any suitable method can be used. In some embodiments, after fabricating the second semiconductor structure 300 using a single-crystal material layer 310 as the second substrate, the method further includes: forming interconnect contact holes 400 in the first semiconductor structure 100 and / or the second semiconductor structure 300; electrically connecting the second semiconductor structure 300 to the first semiconductor structure 100 through the interconnect contact holes 400, ultimately connecting to the output terminal of an inverter, as detailed in an inverter circuit.
[0062] Interconnection contact holes 400 are selectively formed in preset regions of the first semiconductor structure 100 and / or the second semiconductor structure 300. The aperture, depth and position of the interconnection contact holes 400 are adapted to the electrical connection requirements of the first semiconductor structure 100 and the second semiconductor structure 300. Based on the interconnection contact holes 400 as electrical conduction channels, a stable electrical connection between the second semiconductor structure 300 and the first semiconductor structure 100 is achieved through processes such as metallization filling and conductive dielectric deposition.
[0063] It should be noted that the interconnect contact hole 400 can be an opening arranged in the first semiconductor structure 100 or an opening in the second semiconductor structure 300, and both are simultaneously arranged in the first semiconductor structure 100 and the second semiconductor structure 300. In addition, the electrical connection method guided by the interconnect contact hole 400 can shorten the conduction path, reduce contact resistance, and ensure the stability and timeliness of signal transmission between the two semiconductor structures.
[0064] Both the first semiconductor structure 100 and the second semiconductor structure 300 can adopt any suitable structure. In some embodiments, both the first semiconductor structure 100 and the second semiconductor structure 300 can be all-around gate field-effect transistors. Therefore, the fabrication of the first semiconductor structure 100 includes the following steps.
[0065] A first substrate 110 is provided, such as a Si substrate.
[0066] A first epitaxial layer 101 and a first sacrificial layer 102 are alternately formed on a first substrate 110. The first epitaxial layer 101 is made of a first semiconductor material, i.e., the same material as the first substrate 110; for example, Si can also be used. The first sacrificial layer 102 can be made of any suitable material, such as Si. 0.7 Ge 0.3 .
[0067] The first epitaxial layer 101 and the first sacrificial layer 102 are etched to form the first fin structure, and a first shallow trench isolation structure 150 is formed between the first fin structures.
[0068] Select the first sacrificial layer 102 in the first fin structure to be etched, and retain the first epitaxial layer 101 to form the first channel.
[0069] A first fully encircling gate structure 120 is formed in the circumference of the first channel.
[0070] A first source structure 130 and a first drain structure 140 are formed at both ends of the first fully encircling gate structure 120 by selective epitaxial growth.
[0071] A first dielectric layer 160 is deposited over the first source structure 130, the first drain structure 140 and the first all-around gate structure 120, and a first metal wiring layer 180 is fabricated.
[0072] Through the above steps, a fully all-around gate field-effect transistor can be fabricated, for example, an nMOS transistor with a Si substrate.
[0073] In some embodiments, the fabrication of the second semiconductor structure 300 includes the following steps.
[0074] A second epitaxial layer and a second sacrificial layer are alternately formed on a second substrate; wherein the second epitaxial layer is made of a second semiconductor material.
[0075] The second epitaxial layer and the second sacrificial layer are etched to form the second fin structure, and a second shallow trench isolation structure 350 is formed between the second fin structures.
[0076] The second sacrificial layer in the second fin structure is etched to preserve the second epitaxial layer in order to form the second channel.
[0077] A second fully encircling gate structure 320 is formed circumferentially in the second channel.
[0078] A second source structure 330 and a second drain structure 340 are formed at both ends of the second fully encircling gate structure 320 by selective epitaxial growth.
[0079] A second dielectric layer 360 is deposited over the second source structure 330, the second drain structure 340, and the second all-around gate structure 320, and a second metal wiring layer 380 is fabricated.
[0080] A second dielectric layer 360 is deposited above the second source structure 330, the second drain structure 340, and the second all-around gate structure 320, and a second contact hole 370 and a second metal wiring layer 380 are formed. The second metal wiring layer 380 is electrically connected to the second source structure 330 and the second drain structure 340 through the second contact hole 370, respectively. The second metal wiring layer 380 facilitates interconnection with external circuits.
[0081] It should be noted that the above steps also include doping the first channel and the second channel, and photolithography before etching, etc., all of which can be found in publicly available related technologies and will not be repeated here. The single-crystal material layer 310 is a single-crystal Ge layer formed by a laser-induced process. Through the above steps, a fully surround gate field-effect transistor can be fabricated, for example, a pMOS transistor on a Si substrate.
[0082] The first semiconductor structure 100 and the second semiconductor structure 300 can be stacked in the vertical direction, with one being an nMOS and the other a pMOS, thereby forming a CFET (complementary field-effect transistor) under monolithic process conditions, without the need for wafer bonding, layer transfer and other conductive integration methods, thus improving the overall stability of the device.
[0083] This fabrication method involves selectively epitaxially forming epitaxial pillar structures 200 in the first dielectric layer 160 or the first dielectric layer 160 and the shallow trench isolation structure, for example, Si. 1-x Ge x Gradient pillars, epitaxial temperature 450–650℃, Ge content continuously varying from 0 to ≥0.9%. An upper pMOS layer is formed by epitaxially growing a Ge film on top. This can be achieved using ELLPE or other low-temperature epitaxial methods.
[0084] Applications include advanced node CFET, GAA devices, or 3DIC vertical CMOS integration. It can be used in conjunction with Backside Power Supply Network (BSPDN), Hybrid Bonding (HB), or TSV (Through-Silicon Via) technologies.
[0085] In one specific embodiment, referring to Figures 2 to 9, the method for fabricating a semiconductor device is as follows.
[0086] like Figure 2 As shown, Si was epitaxially grown using alternating RPCVD (Remote Plasma Chemical Vapor Deposition). 0.7 Ge 0.3 Superlattice structure.
[0087] like Figure 3 As shown, selective etching of Si is used. 0.7 Ge 0.3 Leave the Si channel. First, fabricate the GAA NMOS on the lower Si substrate using the GAA process, and stop after completing M0.
[0088] like Figure 4 As shown, the ILD (Inter-Layer Dielectric) and the first shallow trench isolation structure 150 (STI) are etched to form a first hole structure 103. The diameter of the first hole structure 103 can be 100-200nm and the height can be 200-400nm.
[0089] like Figure 5 As shown, Si is epitaxially grown in the first porous structure 103 using a low-temperature RPCVD process. 1-x Ge x, where x gradually changes from 0 to 1, forming an extensional column structure 200.
[0090] like Figure 6 As shown, amorphous Ge is deposited over the first dielectric layer 160 and the epitaxial pillar structure 200 using a CVD (Chemical Vapor Deposition) process.
[0091] like Figure 7 As shown, amorphous germanium is transformed into single-crystal germanium through laser-induced liquid phase under the guidance of the epitaxial pillar structure 200. The laser-induced process is performed under the following conditions: irradiation with a green nanosecond laser with specific parameters: wavelength 532 nm, pulse width 13 ns, and frequency 50,000 Hz.
[0092] like Figure 8 As shown, all subsequent processes are low-temperature processes. Ge / SiGe fabrication is performed on the upper c-Ge substrate. 0.7 Epitaxial structure, selective release of SiGe 0.7 Leave the Ge channel for subsequent low-temperature GAA process.
[0093] like Figure 9 As shown, the upper second semiconductor structure 300 and the lower first semiconductor structure 100 are interconnected using interconnect contact holes 400. Figure 9 The diagram below only illustrates the connection between the upper-layer pMOS (p-type MOSFET) and the lower-layer nMOS (n-type MOSFET). The final circuit will connect to the Vout of the inverter; please refer to the inverter circuit diagram for details, which will not be elaborated here. Finally, semiconductor devices can be processed using laser annealing technology.
[0094] like Figure 9 As shown, according to a second aspect of this disclosure, a semiconductor device is also provided, including a first semiconductor structure 100, a second semiconductor structure 300, and an epitaxial pillar structure 200. The first semiconductor structure 100 includes a first substrate 110 formed of a first semiconductor material, a first active region located on the first substrate 110, and a first dielectric layer 160 located above the first active region; the first semiconductor structure 100 also includes a first via structure 103 extending from the first dielectric layer 160 to the first substrate 110; the second semiconductor structure 300 is located above the first dielectric layer 160 and includes a second substrate formed of a second semiconductor material. The epitaxial pillar structure 200 is disposed inside the first via structure 103, wherein, along a direction away from the first substrate 110, the material composition of the epitaxial pillar structure 200 gradually changes from the first semiconductor material to the second semiconductor material.
[0095] The semiconductor device disclosed herein comprises a first semiconductor structure 100 formed on a first substrate 110, and a second substrate formed above a first dielectric layer 160 thereon, and a second semiconductor structure 300 formed on the second substrate. The first substrate 110 is made of a first semiconductor material, and the second substrate is made of a second semiconductor material. A first hole structure 103 is constructed in the first semiconductor structure 100 (e.g., the first dielectric layer 160), and an epitaxial pillar structure 200 connecting the first substrate 110 and the second substrate is formed in the first hole structure 103. The composition of the epitaxial pillar structure 200 gradually changes from the first semiconductor material to the first semiconductor material in the direction from the first substrate 110 toward the second substrate, that is, the epitaxial pillar structure 200 with a gradient of material composition. The epitaxial pillar structure 200 also serves as a lattice matching buffer, stress adjustment and thermal conductivity channel, thereby achieving high-quality integration of the first semiconductor structure 100 and the second semiconductor structure 300 under monolithic process conditions.
[0096] For example, this disclosure can be used for complementary vertical field-effect transistor (CFET) structures in three-dimensional integrated circuits. A lower-layer nMOS transistor (first semiconductor structure 100) is first formed on a silicon substrate; subsequently, an epitaxial pillar structure 200 (Si-Ge continuously graded from Si) is constructed in the dielectric layer above it. 1-x Ge x A gradient structure is used, and a pMOS transistor with a Ge or high-Ge content SiGe channel is epitaxially formed on the top of the epitaxial pillar structure 200. High-quality integration of the upper Ge substrate pMOS and the lower Si substrate nMOS is achieved under monolithic process conditions, and a stable CFET structure can be obtained without bonding or layer transfer processes.
[0097] At the structural level, an epitaxial pillar structure 200 (Si) with a continuously gradient composition is provided between the second semiconductor structure 300 and the first semiconductor structure 100 (upper and lower CMOS layers). 1-x Ge x Gradient pillars (SiGe), whose composition changes continuously from a first semiconductor material to a second semiconductor material along the vertical direction. For example, the upper end is Ge or high-Ge SiGe, and the lower end is Si or low-Ge SiGe. Epitaxial pillar structure 200 (Si 1-x Ge x The gradient pillars serve simultaneously as a lattice-matching layer and a thermal / stress buffer layer. An electrical isolation or stress-suppressing layer may be arranged around the epitaxial pillar structure 200 within the first void structure 103.
[0098] Optionally, one of the first semiconductor material and the second semiconductor material is silicon (Si), and the other is germanium (Ge). For example, the first semiconductor material can be silicon, and the first semiconductor structure 100 can be an nMOS (n-type MOS transistor) on a silicon substrate. The second semiconductor material can be germanium (Ge), and the second semiconductor structure 300 can be a pMOS (p-type MOS transistor) on a germanium substrate. From the first substrate 110 toward the second substrate (e.g., a single crystal material layer 310), the material composition of the epitaxial pillar structure 200 gradually changes from silicon to germanium. The bottom of the epitaxial pillar structure 200 is Si or Si-rich SiGe, and the top is Ge or Ge-rich SiGe, forming a continuous lattice-matching bridge, thereby enabling the epitaxial pillar structure 200 to function as a lattice-matching buffer, stress regulation, and thermal conductivity channel.
[0099] In other embodiments, the first semiconductor material can be germanium and the second semiconductor material can be silicon. In step S300, the material composition of the epitaxial pillar structure 200 gradually changes from germanium to silicon in the direction from the first substrate 110 toward the second substrate (the single crystal material layer 310 to be formed later). This also enables the epitaxial pillar structure 200 to play the role of lattice matching buffer, stress adjustment and thermal conductivity channel.
[0100] Optionally, there are multiple first active regions, and adjacent first active regions are separated by a first shallow trench isolation structure 150. The first active region can be a region jointly formed by the first source structure 130, the first drain structure 140, and the gate structure. The first shallow trench isolation structure 150 is used to isolate two adjacent first active regions. The first hole structure 103 includes a first hole that sequentially passes through the first dielectric layer 160 and the first shallow trench isolation structure 150 and exposes the first substrate 110; an epitaxial pillar structure 200 is disposed inside the first hole. The first hole can be formed by forming a patterned mask above the first dielectric layer 160 and then sequentially etching the first dielectric layer 160 and the first shallow trench isolation structure 150 downwards.
[0101] Optionally, the first hole structure 103 further includes a first isolation layer disposed on the inner sidewall of the first hole; the first isolation layer surrounds the circumference of the extension column structure 200. The first isolation layer can be formed on the circumferential sidewall of the first hole using any suitable process, forming an inner cavity in its center. The extension column structure 200 can be formed within this inner cavity. Because the first isolation layer is disposed on the inner sidewall of the first hole, it serves to electrically isolate the extension column structure 200 from the external structure and also provides stress buffering between the extension column structure 200 and the other layers.
[0102] The first hole structure 103 can be constructed using any suitable structure, including size and shape, and can be adjusted according to actual needs. In some embodiments, the diameter of the first hole structure 103 is 100-200 nm, and the height can be 200-400 nm. Within this size range, it can satisfy both the laser-induced process for converting the amorphous material layer 301 into a single-crystal material layer 310, and the stress buffering requirement between the first substrate 110 and the second substrate.
[0103] After the second semiconductor structure 300 is formed, it can be electrically connected to the first semiconductor structure 100 using interconnect contact holes 400. For example, an inverter circuit connection can be specifically referenced. In some embodiments, the second semiconductor structure 300 and the first semiconductor structure 100 are electrically connected through interconnect contact holes 400 disposed in the first semiconductor structure 100 and / or the second semiconductor structure 300. By selectively forming interconnect contact holes 400 in predetermined regions of the first semiconductor structure 100 and the second semiconductor structure 300, the aperture, depth, and position of the interconnect contact holes 400 are adapted to the electrical connection requirements of the first semiconductor structure 100 and the second semiconductor structure 300; based on the interconnect contact holes 400 as electrical conduction channels, a stable electrical connection between the second semiconductor structure 300 and the first semiconductor structure 100 is achieved through processes such as metallization filling and conductive dielectric deposition.
[0104] Both the first semiconductor structure 100 and the second semiconductor structure 300 can adopt any suitable structure. Optionally, at least one of the first semiconductor structure 100 and the second semiconductor structure 300 is a full-around-gate field-effect transistor. In some embodiments, both the first semiconductor structure 100 and the second semiconductor structure 300 can be full-around-gate field-effect transistors.
[0105] Understandably, one of the first semiconductor structure 100 and the second semiconductor structure 300 may be a gate-all-around field-effect transistor, and the other may be a fin field-effect transistor (FinFET) or an enhancement-mode metal-oxide field-effect transistor.
[0106] Using the above-described technical solution, namely the semiconductor device and its fabrication method disclosed herein, a first semiconductor structure 100 (e.g., a Si-channel nMOS transistor) is first fabricated, comprising a first substrate 110, a first active region, and a first dielectric layer 160 stacked sequentially. Subsequently, a first via structure 103 is formed thereon, and an epitaxial pillar structure 200 (Si) is constructed within this first via junction, transitioning from a first semiconductor material (e.g., Si, silicon) to a second semiconductor material (e.g., Ge, germanium). 1-x Ge xA gradient structure is constructed, and an amorphous material layer 301 of the second semiconductor material is deposited on top of the epitaxial pillar structure 200. Then, a laser-induced process is used to transform the amorphous material layer 301 into a single-crystal material layer 310 to form a second substrate. Based on this second substrate, a second semiconductor structure 300 (e.g., a pMOS transistor with a Ge or high-Ge content SiGe channel) is fabricated. The material composition of the epitaxial pillar structure 200 gradually changes from the first semiconductor material to the second semiconductor material (i.e., the material composition transitions gradually from the first substrate 110 towards the second substrate). This can serve as a lattice matching buffer, stress regulation, and thermal conductivity channel, thereby achieving high-quality integration of the second semiconductor structure 300 (upper Ge substrate pMOS) and the first semiconductor structure 100 (lower Si substrate nMOS) under monolithic process conditions. A stable semiconductor device structure (e.g., CFET structure) can be obtained without bonding or layer transfer processes.
[0107] In other embodiments of this disclosure, an electronic device is also provided, which includes a semiconductor device. The semiconductor device may be the semiconductor device described in the above embodiments, or it may be a semiconductor device prepared by the above-described semiconductor device preparation method. Therefore, the electronic device also has the advantages described in the above-described semiconductor device and its preparation method, which will not be repeated here.
[0108] The method for fabricating semiconductor devices and the semiconductor devices and electronic devices disclosed herein have the following advantages.
[0109] I. Structural Innovation: An epitaxial pillar with a continuous Si→Ge composition gradient is set between the first semiconductor structure 100 and the second semiconductor structure 300. The bottom of the epitaxial pillar structure 200 is Si or Si-rich SiGe, and the top is Ge or Ge-rich SiGe, forming a continuous lattice matching bridge.
[0110] II. Functional Integration: This epitaxial pillar structure 200 (Si→Ge gradient pillar) simultaneously functions as a lattice transition layer, a thermal conductivity channel, and a stress buffer layer, allowing for the direct formation of high-quality Ge substrate pMOS on a completed Si substrate nMOS.
[0111] III. Process Compatibility: This epitaxial pillar structure 200 (Si→Ge graded pillar) can be realized through selective epitaxy, ELLPE or other SEG processes, with a thermal budget of less than 600°C, and is compatible with advanced CMOS BEOL.
[0112] IV. Performance Improvement: This epitaxial pillar structure 200 (Si→Ge graded pillar) eliminates mismatched dislocations, reduces interface defect density, and improves mobility and thermal reliability.
[0113] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.
[0114] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.
[0115] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The method includes: A first hole structure is formed on a first semiconductor structure; the first semiconductor structure includes a first substrate formed of a first semiconductor material, a first active region located on the first substrate, and a first dielectric layer located above the first active region; wherein the first hole structure extends from the first dielectric layer to the first substrate; An epitaxial pillar structure is formed within the first hole structure, wherein, along the direction away from the first substrate, the material composition of the epitaxial pillar structure gradually changes from the first semiconductor material to the second semiconductor material; A second semiconductor structure is fabricated over the first dielectric layer, the second semiconductor structure including a second substrate formed of a second semiconductor material.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The fabrication of the second semiconductor structure above the first dielectric layer includes: A second semiconductor material is deposited over the first dielectric layer to form an amorphous material layer; The amorphous material layer is transformed into a single crystal material layer by a laser-induced process. A second semiconductor structure is prepared using the single-crystal material layer as a second substrate.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, One of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, There are multiple first active regions, and two adjacent first active regions are separated by a first shallow trench isolation structure; The process of forming a first hole structure on the first semiconductor structure includes: The first dielectric layer and the first shallow trench isolation structure are etched sequentially to expose the first substrate and form a first hole, which forms the first hole structure.
5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The step of forming the first hole structure on the first semiconductor structure further includes: A first isolation layer is formed on the inner wall of the first hole.
6. The method for fabricating a semiconductor device according to claim 4 or 5, characterized in that, The diameter of the first hole structure is 100-200 nm.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method includes: Contact holes are formed in the first semiconductor structure and / or the second semiconductor structure; The second semiconductor structure is electrically connected to the first semiconductor structure through the contact hole.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method further includes: Fabrication of the first semiconductor structure: Provide a first substrate; A first epitaxial layer and a first sacrificial layer are alternately formed on the first substrate; wherein the first epitaxial layer is made of a first semiconductor material; The first epitaxial layer and the first sacrificial layer are etched to form a first fin structure, and a first shallow trench isolation structure is formed between the first fin structures; Selectively etch the first sacrificial layer in the first fin structure, retaining the first epitaxial layer, to form the first channel; A first fully encircling gate structure is formed in the circumference of the first channel; A first source structure and a first drain structure are formed at both ends of the first all-around gate structure by selective epitaxial growth; A first dielectric layer is deposited over the first source structure, the first drain structure, and the first all-around gate structure, and a first metal wiring layer is fabricated; and / or The fabrication of the second semiconductor structure includes: A second epitaxial layer and a second sacrificial layer are alternately formed on the second substrate; wherein the second epitaxial layer is made of a second semiconductor material; The second epitaxial layer and the second sacrificial layer are etched to form a second fin structure, and a second shallow trench isolation structure is formed between the second fin structures; Selectively etch the second sacrificial layer in the second fin structure, retaining the second epitaxial layer, to form the second channel; A second fully encircling gate structure is formed circumferentially in the second channel; A second source structure and a second drain structure are formed at both ends of the second fully encircling gate structure by selective epitaxial growth; A second dielectric layer is deposited above the second source structure, the second drain structure, and the second all-around gate structure, and a second metal wiring layer is fabricated.
9. A semiconductor device, characterized in that, include: A first semiconductor structure includes a first substrate formed of a first semiconductor material, a first active region located on the first substrate, and a first dielectric layer located above the first active region. The first semiconductor structure further includes a first hole structure extending from the first dielectric layer to the first substrate; A second semiconductor structure, located above the first dielectric layer, includes a second substrate formed of a second semiconductor material; as well as An epitaxial pillar structure is disposed inside the first hole structure, wherein, along the direction away from the first substrate, the material composition of the epitaxial pillar structure gradually changes from the first semiconductor material to the second semiconductor material.
10. The semiconductor device according to claim 9, characterized in that, One of the first semiconductor material and the second semiconductor material is silicon, and the other is germanium.
11. The semiconductor device according to claim 9, characterized in that, There are multiple first active regions, and two adjacent first active regions are separated by a first shallow trench isolation structure; The first hole structure includes a first hole that passes sequentially through the first dielectric layer and the first shallow trench isolation structure and exposes the first substrate; The extension column structure is located inside the first hole.
12. The semiconductor device according to claim 11, characterized in that, The first hole structure also includes a first isolation layer disposed on the inner sidewall of the first hole; The first isolation layer surrounds the circumference of the extended column structure.
13. The semiconductor device according to claim 11 or 12, characterized in that, The diameter of the first hole structure is 100-200 nm.
14. The semiconductor device according to claim 9, characterized in that, The second semiconductor structure and the first semiconductor structure are electrically connected through contact holes disposed in the first semiconductor structure and / or the second semiconductor structure.
15. The semiconductor device according to claim 9, characterized in that, At least one of the first semiconductor structure and the second semiconductor structure is a fully all-around gate field-effect transistor.
16. An electronic device, characterized in that, Includes a semiconductor device, which includes the semiconductor device according to any one of claims 9-15, or is prepared by the method of preparing the semiconductor device according to any one of claims 1-8.