Frequency adjustment method and device, electronic equipment and storage medium

Abstract

The invention discloses a frequency adjustment method and device, electronic equipment and a storage medium, and belongs to the technical field of electronics. The method comprises the following steps: determining a cycle count threshold value based on a difference value between a period total number parameter and a turn-off period number parameter; and under the condition that the first clock signal output by the main clock source is received, the transmission of the first clock signal to a downstream logic module of the main clock source is controlled based on the cycle counting threshold.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronics, and particularly relates to a frequency adjustment method and device, an electronic device, and a storage medium. BACKGROUND

[0002] With the development of electronic technology, the demand for low power consumption of electronic devices is increasingly high. The current strategy for reducing power consumption is to reduce performance and power consumption by reducing the frequency of chips in scenarios with low performance requirements. Currently, the frequency of chips is mainly adjusted by the way of re-dividing and locking based on a phase-locked loop (PLL). Specifically, the target frequency is calculated first, and then the register is configured to make the PLL re-generate a frequency division ratio to obtain a new output frequency, and the phase and frequency are re-locked according to the configuration. After the locking is completed, the system clock source is switched to the new output frequency.

[0003] However, the current frequency adjustment method based on re-dividing and locking of the PLL mainly relies on the re-dividing and locking mechanism of the PLL. The delay of the PLL when re-locking is high, which leads to slow system response and is difficult to meet the demand for sudden high-performance computing. In the process of re-locking of the PLL, the clock signal may have glitches, jitter or short interruptions, which can easily cause instantaneous freezing or performance degradation. Therefore, the stability of the adjustment frequency of the existing frequency adjustment method is poor. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a frequency adjustment method, device, electronic device and storage medium, which can improve the stability of frequency adjustment.

[0005] In a first aspect, the embodiments of the present application provide a frequency adjustment method, which comprises: determining a cycle count threshold based on the difference between a total cycle number parameter and an off cycle number parameter; and in the case of receiving a first clock signal output by a main clock source, controlling the transmission of the first clock signal to a downstream logic module of the main clock source based on the cycle count threshold.

[0006] In a second aspect, the embodiments of the present application provide a frequency adjustment device, which comprises a determination module and an execution module. The determination module is configured to determine a cycle count threshold based on the difference between a total cycle number parameter and an off cycle number parameter. The execution module is configured to, in the case of receiving a first clock signal output by a main clock source, control the transmission of the first clock signal to a downstream logic module of the main clock source based on the cycle count threshold determined by the determination module.

[0007] In a third aspect, an electronic device is provided, which includes a processor and a memory. The memory stores programs or instructions executable on the processor. When the programs or instructions are executed by the processor, the steps of the method according to the first aspect are implemented.

[0008] In a fourth aspect, a readable storage medium is provided, which stores programs or instructions. When the programs or instructions are executed by a processor, the steps of the method according to the first aspect are implemented.

[0009] In a fifth aspect, a chip is provided, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is configured to execute programs or instructions to implement the method according to the first aspect.

[0010] In a sixth aspect, a computer program product is provided, which is stored in a storage medium. The program product is executed by at least one processor to implement the method according to the first aspect.

[0011] In the embodiments of the present application, the cycle count threshold can be determined based on the difference between the total cycle number parameter and the off cycle number parameter. Then, based on the cycle count threshold, the transmission of the first clock signal output by the master clock source to the downstream logic module of the master clock source is controlled when the first clock signal is received. In this scheme, the cycle count threshold is determined by using the difference between the total cycle number parameter and the off cycle number parameter, so that the cycle count threshold can represent the demand for frequency adjustment. In this way, when the electronic device receives the clock signal output by the master clock source, whether to transmit the clock signal to the downstream logic module of the master clock source can be controlled by the cycle count threshold, so that how many clock pulses can be accurately controlled in a specific clock cycle, thereby achieving accurate adjustment of the output frequency without relocking the phase and frequency by the PLL, effectively reducing the frequency adjustment delay, glitches, jitter or short interruptions caused by the relocking of the PLL, thereby avoiding instantaneous freezing or performance degradation, and improving stability and reliability. In this way, the stability of frequency adjustment is improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is an architecture schematic diagram of the frequency adjustment method provided by the embodiments of the present application;

[0013] Figure 2 is one of the flowcharts of the frequency adjustment method provided by the embodiments of the present application;

[0014] Figure 3 is one of the flowcharts of the frequency adjustment method provided by the embodiments of the present application;

[0015] Figure 4 This is a schematic diagram illustrating the change in the value of the counter provided in an embodiment of this application;

[0016] Figure 5 This is a schematic diagram of the digital frequency synthesis architecture provided in the embodiments of this application;

[0017] Figure 6 This is a schematic diagram of the frequency adjustment device provided in the embodiments of this application;

[0018] Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0019] Figure 8 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0022] The terms "at least one," "at least one," etc., in this application refer to any one, any two, or a combination of two or more of the included objects. For example, at least one of a, b, and c can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple. Similarly, "at least two" refers to two or more, and its meaning is similar to that of "at least one."

[0023] The following explains some concepts and terms involved in the frequency adjustment method, apparatus, and electronic device provided in the embodiments of this application.

[0024] The system framework of the frequency adjustment method provided in the embodiments of this application will be described exemplarily below with reference to the accompanying drawings.

[0025] Figure 1 A schematic diagram illustrating the architecture of the frequency adjustment method provided in this application embodiment is shown. Figure 1 As shown, the architecture includes a clock source, a Digital Frequency Synthesis (DFS) architecture, subsequent functional modules, and a configuration bus. The DFS architecture can function as an independent Intellectual Property Core (IP), directly placed at the root node or critical path of the chip's internal clock network. Specifically, it is located between the clock source and the clock input of the subsequent functional modules. The clock source can be a PLL output, and the subsequent functional modules can be a Central Processing Unit (CPU) core, a Neural Processing Unit (NPU), a bus, peripherals, etc. The core function of the DFS architecture is to act as a programmable, highly agile clock gating and frequency regulator.

[0026] The frequency adjustment method, apparatus, electronic device, and storage medium provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0027] The embodiments of this application can be applied to scenarios that require dynamic frequency adjustment. For example, when a user is using a mobile phone to run small software or in standby mode, it is necessary to reduce the processor frequency to save battery power; when a user is using a mobile phone to run large software, it is necessary to increase the processor frequency to improve mobile phone performance.

[0028] It should be noted that the above scenarios are merely illustrative examples of some possible applications of the embodiments of this application. In actual implementation, the embodiments of this application can also be applied to more possible scenarios of frequency adjustment, and the embodiments of this application are not limited here.

[0029] Currently, there are various low-power design methods for conventional chips, mainly including clock gating: automatically / passively shutting down the clock through hardware handshake or software configuration; power gating: shutting down the power supply of some IPs in special scenarios; adaptive voltage scaling (AVS): adaptive frequency scaling (AFS); and state machine management built into the IP subsystem. For complementary metal-oxide-semiconductor (CMOS) circuits, power consumption can be expressed by formula (1), which is:

[0030] Formula (1)

[0031] Where C represents the capacitance of the load capacitor, V is the operating voltage, α is the switching rate at the current frequency, and f is the operating frequency. This represents quiescent current. It is related to load capacitance, device manufacturing process, toggle ratio, and specific application scenarios and designs. Voltage and current regulation is the most common low-power method in chip design; however, voltage regulation can significantly impact system stability. In some scenarios where performance requirements are not high, performance and power consumption are often reduced by lowering the frequency. Therefore, Direct Current Scaling (DFS) technology is widely used in scenarios where system stability is not affected and extreme performance is not required. Furthermore, when encountering scenarios requiring high performance and rapid mode switching, DFS is also used to simply increase the frequency and linearly improve performance. The general method of DFS is as follows:

[0032] 1. Target frequency calculation: The target frequency is obtained by monitoring the performance and load of the monitoring unit and by comparing thresholds or using a prediction model.

[0033] 2. PLL Reconfiguration: By writing to the configuration register via software, the ratio of the PLL's feedback divider (M), input divider (N), or post divider (P) can be changed to generate a new output frequency.

[0034] 3. Waiting to lock: The PLL starts working according to the new configuration and needs some time to relock the phase and frequency. During this period, the clock output may be unstable or interrupted.

[0035] 4. Clock switching: After the PLL is locked, switch the system clock source to the new output frequency of the PLL.

[0036] 5. The system has entered a stable operating state. Continue monitoring for the next round of adjustments.

[0037] Although PLL reconfiguration schemes are widely used, their implementation mechanism leads to several core defects that are difficult to overcome, especially in scenarios requiring high-frequency, fast, and fine-grained frequency modulation:

[0038] 1. Large frequency modulation delay and slow response speed: PLL relocking is an analog circuit process that typically requires tens or even hundreds of microseconds of locking time. During this time, the system must wait and cannot immediately respond to load changes, resulting in a huge frequency modulation delay. This makes it difficult to cope with sudden high-performance computing demands, easily causing momentary performance lag, or performance degradation due to untimely low-power switching.

[0039] 2. Coarse frequency modulation granularity and imprecise energy efficiency optimization: Frequency changes rely on integer multiples of the PLL division ratio, meaning that frequency changes occur in large steps. For example, a jump from 1 gigahertz (GHz) to 800 megahertz (MHz) or 1.2 GHz is possible, without the ability to achieve finer, linear frequency adjustments. This forces the trade-off between power consumption and performance to be made over large ranges, failing to find the optimal frequency and resulting in unnecessary energy efficiency losses.

[0040] 3. The switching process carries stability and reliability risks: During PLL unlocking and relocking, the clock signal may experience glitches, jitter, or brief interruptions. This poses a risk to synchronous digital circuits with extremely high clock quality requirements, potentially leading to timing violations or system instability. Therefore, the switching process often requires complex clock switching circuits and protection mechanisms, increasing design complexity and cost.

[0041] 4. Hardware Overhead and Power Consumption: To achieve frequency switching, a high-performance, reconfigurable PLL circuit must be integrated, which is itself a large analog IP in terms of power consumption and area. In addition, supporting stable control logic is required, increasing the overall hardware overhead and static power consumption of the chip.

[0042] 5. Difficulty in achieving extremely high-frequency dynamic adjustment: Due to the aforementioned latency, stability, and power consumption issues, traditional PLL reconfiguration schemes are not suitable for frequent switching and frequency adjustments within extremely short time intervals, such as tens of thousands of times per second. This limits their application in power management scenarios where power consumption is extremely sensitive.

[0043] In summary, existing PLL-based dynamic frequency modulation (DFS) technologies are inherently limited by the nature of their analog circuits, resulting in large response delays, coarse frequency modulation granularity, stability risks, high hardware costs, and difficulty in achieving instantaneous high-frequency adjustments. Therefore, a new digital dynamic frequency modulation technology is needed that can achieve zero delay, ultra-fine granularity, high stability, and low hardware overhead to overcome the fundamental limitations of traditional analog frequency modulation schemes.

[0044] This application provides a frequency adjustment method, apparatus, electronic device, and storage medium. A cycle count threshold is determined by using the difference between a total number of cycles parameter and a shutdown cycle number parameter. This cycle count threshold characterizes the frequency adjustment requirement. Thus, when the electronic device receives a clock signal from the master clock source, it can control whether to transmit the clock signal to the downstream logic module of the master clock source using the cycle count threshold. This allows for precise control over how many clock pulses are retained within a specific clock cycle, achieving precise output frequency adjustment without needing to relock the phase and frequency through a PLL. This effectively reduces frequency modulation delay, glitches, jitter, or brief interruptions caused by PLL relocking, thereby avoiding momentary stuttering or performance degradation and improving stability and reliability. This enhances the stability of frequency adjustment.

[0045] The frequency adjustment method provided in this application can be executed by a frequency adjustment device, which can be an electronic device, or a functional module or functional entity within an electronic device. The following description uses an electronic device as an example to illustrate the technical solution provided in this application.

[0046] Figure 2 A flowchart of a frequency adjustment method provided in an embodiment of this application is shown, as follows: Figure 3 As shown, the frequency adjustment method provided in this application embodiment may include the following steps 201 and 202.

[0047] Step 201: The electronic device determines the cycle count threshold based on the difference between the total number of cycles parameter and the number of shutdown cycles parameter.

[0048] In some embodiments of this application, the total number of cycles parameter mentioned above is a configured calculated value, a dimensionless parameter, which can be represented by P_pll. It refers to the total number of cycles required for the counter to complete one full counting cycle during frequency adjustment. Together with the cycle counting threshold, it determines the clock signal transmission control logic and output frequency. Here, completing one full counting cycle means the counter starts counting from 0 and continues counting until it returns to 0.

[0049] In some embodiments of this application, the above-mentioned shutdown cycle number parameter is also a configured calculated value, which is a dimensionless parameter and can be represented by Q_pll. It refers to the number of clock signals that need to be shut down in the total number of cycles in which the counter completes one full counting cycle during the frequency adjustment process, which is dynamically calculated by the electronic device according to the current task load or power consumption strategy.

[0050] In some embodiments of this application, the aforementioned cycle count threshold is a control parameter obtained based on the difference between the total number of cycles parameter and the number of shutdown cycles parameter, used to control the transmission of the first clock signal.

[0051] In some embodiments of this application, combined with Figure 2 ,like Figure 3 As shown, step 201 can be implemented through steps 201a and 201b below.

[0052] Step 201a: The electronic device determines the denominator of the ratio of the target turn-off frequency to the first output frequency as the total number of cycles parameter, and determines the numerator of the ratio as the number of turn-off cycles parameter.

[0053] In some embodiments of this application, the total number of cycles and the number of turn-off cycles can be obtained by simplifying the division between the target turn-off frequency and the first output frequency. The total number of cycles can be the denominator of the ratio of the target turn-off frequency to the first output frequency, and the number of turn-off cycles can be the numerator of that ratio. This ratio can be in its simplest form or it may not be in its simplest form.

[0054] In some embodiments of this application, the first output frequency is the frequency at which the master clock source is currently operating, which can be directly read from a hardware register or obtained through system configuration parameters.

[0055] In some embodiments of this application, reading the first output frequency from the hardware register can be achieved through memory mapping. Specifically, the hardware register is mapped to a specific memory address, and the electronic device can obtain the frequency information by reading the value at that address.

[0056] For example, in an embedded system, by defining a pointer to that address and then directly reading the value pointed to by the pointer, the real-time status of the hardware can be obtained directly, providing accurate initial frequency data for subsequent frequency adjustments.

[0057] In some embodiments of this application, the target shutdown frequency is a frequency that the electronic device needs to shut down dynamically based on the current task load or power consumption strategy. For example, this frequency value can be calculated in real time by a monitoring unit, such as a performance monitor or load detector, or it can be determined by a preset performance curve or prediction model. For instance, if the current frequency of the electronic device is 1.5 GHz, and the current load dictates that the frequency should be reduced by 1.1 GHz to save power, then the target shutdown frequency is 1.1 GHz.

[0058] Step 201b: The electronic device determines the difference between the total number of cycles parameter and the number of shutdown cycles parameter as the cycle counting threshold.

[0059] In some embodiments of this application, the electronic device may determine the difference between the total number of cycles parameter and the number of off cycles parameter as a cycle counting threshold, which is used to control the transmission of the first clock signal via a counter in the subsequent process.

[0060] In some embodiments of this application, when the first clock signal sent by the master clock source is received, the electronic device can calculate the target shutdown frequency fq based on information such as the current system load and power consumption strategy, and calculate the ratio with the current first output frequency f1, i.e., fq / f1. Then, the ratio is converted into the simplest fractional form, and the denominator of the ratio in the simplest fractional form is determined as the total number of cycles parameter P_pll, and the numerator of the ratio is determined as the shutdown cycle number parameter. Then, the difference between the total number of cycles parameter and the shutdown cycle number parameter is calculated, i.e. (P_pll-Q_pll), to obtain the cycle count threshold.

[0061] For example, assuming the current first output frequency f1 of the electronic device is 1.5GHz and needs to be reduced by 1.1GHz, the ratio fq / f1 can be obtained as 1100 / 1500, which is converted to the simplest fraction 11 / 15. Then 15-11=4 is the cycle count threshold.

[0062] In some embodiments of this application, the aforementioned master clock source is the core clock signal provider in the chip system, used to provide basic time reference signals for modules in the chip. For example, the master clock source can be a PLL.

[0063] In some embodiments of this application, the first clock signal is a clock signal generated by the master clock source according to the first output frequency. It is a periodic signal and can be in the form of a square wave. Each cycle includes a rising edge and a falling edge. A complete cycle of the clock signal can be called a clock cycle.

[0064] In some embodiments of this application, the aforementioned first clock signal refers to the signal of the first clock cycle output by the master clock source, which can trigger subsequent operations. In embodiments of this application, the first clock signal sent by the master clock source can trigger a subsequent frequency adjustment process.

[0065] In this way, the electronic device can immediately obtain the total number of cycles and the number of off cycles based on the ratio of the target off frequency to the current frequency, and use the difference between the total number of cycles and the number of off cycles as the cycle count threshold. Through the precise calculation of the cycle count threshold, the electronic device can control the transmission of the clock signal in a fine-grained manner, avoiding the frequency jumps caused by the frequency division ratio limitation in traditional methods, thereby achieving precise adjustment of the output frequency and improving the accuracy of frequency adjustment.

[0066] Step 202: Upon receiving a first clock signal output from the master clock source, the electronic device controls the transmission of the first clock signal to the downstream logic module of the master clock source based on the cycle counting threshold.

[0067] In some embodiments of this application, the downstream logic modules mentioned above refer to subsequent functional modules to which the clock signal from the master clock source needs to be transmitted, such as processor cores, buses, peripherals, etc. These modules rely on clock signals to synchronize their operations.

[0068] In some embodiments of this application, the electronic device triggers a frequency adjustment operation whenever the master clock source outputs a new first clock signal. This operation is periodic and is performed each time a new first clock signal is received.

[0069] In some embodiments of this application, frequency adjustment is triggered by accurately detecting changes in the clock signal. Electronic devices can use edge triggers to capture the rising or falling edge of the clock signal to achieve accurate detection of changes in the clock signal.

[0070] It should be noted that an edge-triggered trigger is a sequential logic circuit that can be triggered when a specific change occurs in the clock signal, such as a rising edge or a falling edge. In the embodiments of this application, when a new first clock signal is detected, the edge-triggered trigger will respond immediately, start a counter or other logic unit, and begin a frequency adjustment cycle, enabling the electronic device to dynamically adjust the transmission of the clock signal in each clock cycle.

[0071] In some embodiments of this application, upon receiving a first clock signal output from the master clock source, the electronic device controls the transmission of the first clock signal to the downstream logic module of the master clock source based on a cycle count threshold. Thus, the electronic device can dynamically determine whether to allow the clock signal to pass through in each clock cycle based on the cycle count threshold, thereby achieving adjustment of the target frequency.

[0072] This application provides a frequency adjustment method, apparatus, electronic device, and storage medium. A cycle count threshold is determined by using the difference between a total number of cycles parameter and a shutdown cycle number parameter. This cycle count threshold characterizes the frequency adjustment requirement. Thus, when the electronic device receives a clock signal from the master clock source, it can control whether to transmit the clock signal to the downstream logic module of the master clock source using the cycle count threshold. This allows for precise control over how many clock pulses are retained within a specific clock cycle, achieving precise output frequency adjustment without needing to relock the phase and frequency through a PLL. This effectively reduces frequency modulation delay, glitches, jitter, or brief interruptions caused by PLL relocking, thereby avoiding momentary stuttering or performance degradation and improving stability and reliability. This enhances the stability of frequency adjustment.

[0073] In some embodiments of this application, the frequency adjustment method provided in this application further includes the following step 301, and the above step 202 can be specifically implemented by the following step 202a.

[0074] Step 301: The electronic device starts the counter.

[0075] In some embodiments of this application, the counter described above can perform non-linear cyclic counting according to a specific jump algorithm to track the count value within the current clock cycle and help the electronic device determine whether the current clock signal should be transmitted.

[0076] In some embodiments of this application, during frequency adjustment, the electronic device can use a counter to count and determine whether to transmit the current clock signal.

[0077] In some embodiments of this application, at the start of the frequency adjustment process, i.e. after receiving the first first clock signal sent by the master clock source, the electronic device may initialize a counter.

[0078] Specifically, the electronic device can set the initial value of the counter to 0, indicating that counting starts from the current moment. Then, the electronic device can configure the bit width of the counter to ensure it can represent the required range of count values. For example, if the total number of cycles parameter P_pll is 15, the counter's bit width should be 4 bits, because 2 to the power of 4 = 16, which is sufficient to represent values ​​from 0 to 15, and is the smallest possible value. After the timer initialization is complete, the electronic device can start the counter.

[0079] Step 202a: Upon receiving the first clock signal output from the master clock source, the electronic device controls the transmission of the first clock signal to the downstream logic module of the master clock source based on the counter's counting and cycle counting thresholds.

[0080] In some embodiments of this application, each time a first clock signal is received, the electronic device can compare the current count value with a cycle count threshold to control the transmission of the first clock signal to the downstream logic module of the master clock source.

[0081] In this way, electronic devices can control clock signal transmission based on counter counts and cycle count thresholds, enabling fast and accurate frequency adjustment.

[0082] In some embodiments of this application, step 202a can be specifically implemented by the following steps 202a1 and 202a2.

[0083] Step 202a1: When the counter count is greater than or equal to the cycle count threshold, the electronic device shuts off a first clock signal and reduces the counter count by the cycle count threshold.

[0084] In some embodiments of this application, the aforementioned clock signal shutdown refers to the process in an electronic device of preventing the clock signal from being transmitted to a specific downstream logic module through hardware logic control. This operation is typically used for dynamic frequency adjustment to reduce power consumption or adapt to different performance requirements.

[0085] In some embodiments of this application, the clock signal can be shut down using clock gating, a hardware technique used to prevent the clock signal from being transmitted to a specific logic module when it is not needed. Clock gating can be implemented by controlling a switch with a gating signal, such as an AND gate or an OR gate. When the gating signal is low, the output of the AND gate is low, thus preventing the clock signal from passing through; when the gating signal is high, the clock signal passes through normally, controlling the transmission path of the clock signal.

[0086] In some embodiments of this application, when the counter count reaches or exceeds a cycle counting threshold, the electronic device can set a clock gating signal to a low level, pulling the clock signal low and thus preventing the clock signal from passing. Simultaneously, the electronic device can reduce the counter value by a cycle counting threshold, ensuring the counter value accurately reflects the current counting state so that frequency adjustment can continue in subsequent cycles.

[0087] Step 202a2: When the counter count is less than the cycle count threshold, the electronic device sends a first clock signal to the downstream logic module and increments the counter count by the shutdown cycle number parameter.

[0088] In some embodiments of this application, when the counter count has not reached the cycle counting threshold, the electronic device can set a clock gating signal to a high level to pull the clock signal high, thereby ensuring that the clock signal passes through. Simultaneously, the electronic device can add a shutdown cycle number parameter to the counter value so that the counter value can accurately reflect the current counting state, allowing for continued frequency adjustment in subsequent cycles.

[0089] The frequency adjustment method provided in the embodiments of this application is described below with a complete example.

[0090] For example, assuming the target shutdown frequency is 1.1 GHz and the first output frequency is 1.5 GHz, the electronic device can calculate the total number of cycles parameter P_pll as 15, the number of shutdown cycles parameter P_pll as 11, and the cycle count threshold T as 4. The electronic device can, within every 15 clock cycles, shut down the current clock signal and decrement the counter value by 4 when the counter value reaches or exceeds 4; when the counter value is less than 4, transmit the current clock signal to the downstream logic module and increment the counter value by 11. Specifically:

[0091] Upon receiving the first clock signal, the counter value is initially 0, which is less than the cycle counting threshold T=4. The electronic device transmits the clock signal and increments the counter value by P_pll=11.

[0092] When the second clock signal is received, the value of the counter is 11, which is greater than the loop counting threshold of 4. The electronic device turns off the clock signal and reduces the value of the counter by 4, making it 7.

[0093] When the third clock signal is received, the counter value is 7, which is greater than the loop counting threshold of 4. The electronic device turns off the clock signal and reduces the counter value by 4, making it 3.

[0094] When the fourth clock signal is received, the value of the counter is 3, which is less than the cycle counting threshold of 4. The electronic device transmits the clock signal and increases the value of the counter by 11, making it 14.

[0095] When the 5th clock signal is received, the value of the counter is 14, which is greater than the cycle counting threshold of 4. The electronic device turns off the clock signal and reduces the value of the counter by 4, making it 10.

[0096] When the 6th clock signal is received, the value of the counter is 10, which is greater than the cycle counting threshold of 4. The electronic device turns off the clock signal and reduces the value of the counter by 4, making it 6.

[0097] When the 7th clock signal is received, the value of the counter is 6, which is greater than the cycle counting threshold of 4. The electronic device turns off the clock signal and reduces the value of the counter by 4, making it 2.

[0098] When the 8th clock signal is received, the value of the counter is 2, which is less than the cycle counting threshold of 4. The electronic device transmits the clock signal and increases the value of the counter by 11, making it 13.

[0099] When the 9th clock signal is received, the value of the counter is 13, which is greater than the cycle counting threshold of 4. The electronic device turns off the clock signal and reduces the value of the counter by 4, making it 9.

[0100] When the 10th clock signal is received, the counter value is 9, which is greater than the cycle count threshold of 4. The electronic device turns off the clock signal and reduces the counter value by 4, making it 5.

[0101] When the 11th clock signal is received, the value of the counter is 5, which is greater than the cycle counting threshold of 4. The electronic device turns off the clock signal and reduces the value of the counter by 4, making it 1.

[0102] When the 12th clock signal is received, the value of the counter is 1, which is less than the cycle counting threshold of 4. The electronic device transmits the clock signal and increases the value of the counter by 11, making it 12.

[0103] When the 13th clock signal is received, the value of the counter is 12, which is greater than the cycle counting threshold of 4. The electronic device turns off the clock signal and reduces the value of the counter by 4, making it 8.

[0104] When the 14th clock signal is received, the value of the counter is 8, which is greater than the cycle counting threshold of 4. The electronic device turns off the clock signal and reduces the value of the counter by 4, making it 4.

[0105] Upon receiving the 15th clock signal, the counter value is 4, which equals the cycle counting threshold of 4. The electronic device then turns off the clock signal and decrements the counter value by 4, bringing it back to 0. At this point, a complete cycle ends, the counter value returns to its initial state, and it is ready to begin the next cycle.

[0106] like Figure 4 The diagram illustrates the changes in the counter's value. The numbers in the squares represent the counter's value. The first row of squares represents the change in the counter's value from the 1st to the 3rd clock cycle, the second row represents the change from the 4th to the 7th clock cycle, the third row represents the change from the 8th to the 11th clock cycle, and the fourth row represents the change from the 12th to the 15th clock cycle. The arrows indicate jumps in the counter's value; the top arrow indicates adding 11, and the bottom arrow indicates subtracting 4.

[0107] In summary, starting from the first clock cycle, the value of the counter changes sequentially as follows: 0→11→7→3→14→10→6→2→13→9→5→1→12→8→4→0… That is to say, the value of the counter is 0 in the first clock cycle, 11 in the second clock cycle, …, 4 in the 15th clock cycle, and returns to 0 in the 16th clock cycle. Then, a new cycle begins from the 16th clock cycle, and returns to 0 in the 31st clock cycle.

[0108] This cycle repeats continuously, maintaining the sequence 0→11→7→3→14→10→6→2→13→9→5→1→12→8→4 every 15 clock cycles. Since only numbers 0, 1, 2, and 3 in the sequence 0→11→7→3→14→10→6→2→13→9→5→1→12→8→4 trigger the electronic device to send the current clock signal to the downstream logic module, while numbers 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 trigger the electronic device to turn off the clock signal, only 4 clock signals are sent to the downstream logic module every 15 clock cycles. This reduces the frequency to 4 / 15 of the current output frequency, i.e., from 1.5GHz to 1.5GHz * 4 / 15 = 0.4GHz = 400MHz.

[0109] In this way, the electronic device can turn off the clock signal and reduce the counter count when the counter count reaches or exceeds the cycle count threshold, and transmit the clock signal and increase the counter count when the counter count is below the cycle count threshold. The digital circuit achieves precise control of the clock signal transmission, avoids the delay and instability caused by PLL relocking, improves the system response speed, and achieves fine-grained frequency adjustment through a precise clock signal selection mechanism.

[0110] In some embodiments of this application, the step 202a1 above, "reducing the counter count by the cycle count threshold", can be specifically implemented by the following steps 401 and 402, and the step 202a2 above, "increasing the counter count by the shutdown cycle number parameter", can be specifically implemented by the following steps 403 and 404.

[0111] Step 401: The electronic device determines the difference between the counter's count and the cycle count threshold as the first value.

[0112] Step 402: The electronic device updates the counter value to the first value.

[0113] In some embodiments of this application, after a clock signal is turned off, the electronic device can determine the difference between the counter's count and the loop count threshold as the new value of the counter, i.e., the first value, and then update the value of the counter to the calculated first value to realize the update of the counter value.

[0114] For example, suppose the loop count threshold T is 4 and the current value of the counter is 7. The electronic device can calculate the difference between the current value of the counter and the loop count threshold, i.e., the first value = 7 - 4 = 3.

[0115] Step 403: The electronic device determines the second value as the sum of the counter count and the number of shutdown cycles.

[0116] Step 404: The electronic device updates the counter value to the second value.

[0117] In some embodiments of this application, after transmitting a clock signal, the electronic device can determine the sum of the counter count and the number of off cycles as the new value of the counter, i.e., the second value, and then update the value of the counter to the calculated second value to realize the update of the counter value.

[0118] For example, suppose the shutdown cycle count parameter is 11 and the current value of the counter is 3. The electronic device can calculate the sum of the current value of the counter and the shutdown cycle count parameter, i.e., the second value = 3 + 11 = 14.

[0119] In this way, the electronic device can reduce the counter count by calculating the difference and updating the counter value when the counter count reaches or exceeds the cycle count threshold, and increase the counter count by calculating the sum and updating the counter value when the counter count is less than the cycle count threshold. This achieves precise adjustment of the counter value and ensures the accuracy and stability of frequency adjustment.

[0120] The frequency adjustment method provided in this application is based on the need for a new digital dynamic frequency modulation technology that is delay-free, ultra-fine-grained, highly stable, and has low hardware overhead. It abandons the complex PLL reconfiguration and locking process, and instead employs a precise clock cycle gating technology based on chip hardware digitalization. By introducing an algorithm logic based on loop counting and conditional transitions, Q_pll cycles are uniformly masked within each basic unit consisting of P_pll clock cycles, thereby precisely adjusting the output frequency to (P_pll - Q_pll) / P_pll times the original frequency. This method eliminates the microsecond-level delay caused by PLL locking time, achieving nanosecond-level instantaneous frequency switching. Simultaneously, by configuring the integer values ​​of P_pll and Q_pll, extremely fine frequency adjustment steps can be provided. Furthermore, since the entire process is a purely digital logic operation, it significantly reduces chip area and power consumption. Moreover, the digital gating frequency conversion method does not change the phase of the original clock, making the system relatively stable and reliable.

[0121] In some embodiments of this application, different computing cores, such as NPUs, Graphics Processing Units (GPUs), Digital Signal Processors (DSPs), CPUs, or other common IPs, have different workloads. Each core or computing unit can be equipped with an independent DFS controller. The software can dynamically and independently configure the P_pll and Q_pll parameters for each unit based on its real-time workload.

[0122] In some embodiments of this application, within a System on a Chip (SoC), a high-performance DSP or GPU may simultaneously process multiple task threads with different priorities and performance requirements. The operating system scheduler can assign different performance levels (P_pll, Q_pll) to different task threads, enabling the SoC to achieve a better balance between performance and power consumption in a multitasking environment.

[0123] In some embodiments of the present application, when the computing core is in a task-free state, the hardware can automatically trigger a frequency boost mechanism without software intervention. Specifically, the hardware can quickly detect the task-free state of the computing core, for example, by monitoring that the task queue is empty or the execution unit is in an idle state. Once this state is detected, the hardware immediately initiates a frequency boost operation, rapidly increasing the frequency of the computing core from near zero to the maximum within the first clock cycle. This process is achieved by setting the Q_pll parameter to 0. When Q_pll = 0, the clock gating mechanism is fully opened, allowing the clock signal to pass through at full speed, thereby enabling the computing core to reach its maximum frequency. This design not only ensures that the computing core can quickly provide maximum performance when needed but also maintains extremely low power consumption when there is no task, effectively optimizing the energy efficiency ratio of the system. In addition, the effect of this automatic clock gating can also reduce the overhead of software intervention, improving the response speed and overall performance of the system.

[0124] The data transmission method provided by the embodiments of the present application can also be extended to the fast and smooth switching of the display refresh rate. For example, in a mobile device, the current refresh rate can be quickly and smoothly adjusted to the target refresh rate according to the dynamic changes of the display content, such as scrolling and animations, while maintaining the smoothness of the display and reducing power consumption. It can also be combined with other display technologies, such as adaptive synchronization technology, to provide a better user experience.

[0125] Figure 5 shows Figure 1 a schematic diagram of the architecture of DFS in Figure 5 As shown, the DFS architecture includes a configuration register group, a clock cycle counter (clk_cnt), an update counter, a comparator, and an integrated clock gating unit (ICG). Among them:

[0126] 1. Configuration register group: A parameter register configured through the Advanced Peripheral Bus (APB) or other buses, that is, a hardware unit for storing control parameters. It includes the total cycle parameter P_pll and the off-cycle parameter Q_pll, where Q_pll < P_pll. These parameters can be configured by software through the APB or other buses. By configuring these parameters, the electronic device can dynamically adjust the clock frequency according to the current performance requirements and power consumption strategy. The configuration register group is connected to the update counter to provide P_pll and Q_pll to the update counter for calculation. The configuration register group is also connected to the comparator to provide P_pll and Q_pll to the comparator to compare the relationship between the counted value and the loop count threshold (P_pll - Q_pll).

[0127] 2. Clock Cycle Counter: Often simply called a counter, this is a register with a bit width of P_pll-1 that performs non-linear cyclic counting according to a specific jump algorithm. The clock cycle counter tracks the count value within the current clock cycle, helping electronic devices determine whether the current clock signal should be transmitted. The counter's bit width is designed to represent the value of P_pll-1 to ensure coverage of all possible count values. The counter updates its count value according to specific rules each clock cycle. It is connected to an update counter, providing the update counter with the count value for calculations. The counter is also connected to a comparator, receiving updates to the count value from the comparator and providing the comparator with the count value to compare with the cycle count threshold (P_pll - Q_pll).

[0128] 3. Jump Logic Unit: Also known as the update counter, this is a combinational logic circuit used to calculate the count value for the next cycle based on the current count value clk_cnt, the total number of cycles parameter P_pll, and the number of off cycles parameter Q_pll. The inputs are the current clk_cnt, P_pll, and Q_pll, and the output is the next cycle count value clk_cnt, implementing the core jump algorithm.

[0129] 4. Comparator: Used to compare the current value of the clock cycle counter with the loop count threshold to determine whether to transmit the current clock signal. The comparator can compare the current count value clk_cnt with the loop count threshold (P_pll - Q_pll) in real time. When the count value reaches or exceeds the loop count threshold, the comparator will trigger the clock gating unit to turn off the clock signal; when the count value is lower than the loop count threshold, the comparator will trigger the clock gating unit to transmit the clock signal. In addition to the above connections, the comparator is also connected to the clock gating unit to control the clock gating unit to turn off or transmit the clock signal based on the comparison result after comparing the relationship between the count value and the loop count threshold (P_pll - Q_pll).

[0130] 5. Clock Gating Unit: The standard clock gating unit is a hardware logic unit used to control the transmission of clock signals. Based on the comparator's output signal, the clock gating unit determines whether to transmit the clock signal output from the master clock source to the downstream logic module. If the comparator indicates that the clock signal should be turned off, the clock gating unit will prevent the clock signal from passing through; if the comparator indicates that the clock signal should be transmitted, the clock gating unit will transmit the clock signal to the downstream logic module. Its enable signal is driven by the comparison result: when clk_cnt < (P_pll - Q_pll), a valid clock is output; otherwise, the clock output is turned off.

[0131] The following is combined with Figure 5This describes the execution process of the data transmission method provided in the embodiments of this application and its execution location in the architecture. For example... Figure 5 As shown, the data transmission method provided in this application embodiment may include the following steps 10 to 15.

[0132] Step 10: Trigger the execution of steps 11 to 15 at each rising edge of clk_in clock cycle to achieve real-time, continuous frequency adjustment within each input clock cycle.

[0133] Step 11: The software calculates parameters P_pll and Q_pll based on the target frequency, and resets the counter to 0 through the APB configuration register group, providing an accurate initial state for dynamic frequency adjustment.

[0134] Step 12: Update the counter. Based on parameters P_pll, Q_pll, and the current clk_cnt value, calculate the next value according to the conditions:

[0135] When clk_cnt < (P_pll - Q_pll): clk_cnt_next = clk_cnt + Q_pll

[0136] When clk_cnt >= (P_pll - Q_pll): clk_cnt_next = clk_cnt - (P_pll - Q_pll)

[0137] Here, clk_cnt_next represents the next value of the counter. The electronic device controls the counting period by incrementing / decrementing, providing a basis for the frequency and duty cycle of the output clock.

[0138] Step 13: Update the counter by loading clk_cnt_next into the counter.

[0139] Step 14: The comparator receives the counter value clk_cnt from the counter and the loop count threshold (P_pll - Q_pll) from the register, and controls the clock gating in real time based on the comparison result of these two values. When clk_cnt < (P_pll - Q_pll), the clock is enabled, and clk_out = clk_in; otherwise, it is disabled, and clk_out is turned off. The target frequency and duty cycle are output by periodically blocking the clock pulses.

[0140] Step 15: Clock gating controls the switching off or transmission of the clock signal based on the output signal of the comparator.

[0141] Step 16: The clock-gated output frequency reaches (P_pll - Q_pll) / P_pll times the input frequency.

[0142] The frequency adjustment method provided in this application, through a purely digital logic-gated frequency conversion approach, eliminates the analog locking process required for traditional PLL reconfiguration, achieving nanosecond-level frequency switching, improving response speed and reducing latency. Based on the precise integer configuration of parameters P_pll and Q_pll, extremely fine-grained adjustment of the output frequency can be achieved, solving the problem of coarse frequency stepping in traditional solutions. The combination of this synchronous digital circuit design and a dedicated clock gating unit avoids output clock glitches and interruptions, ensuring the reliability and security of the frequency switching process. This architecture is implemented entirely by standard digital units, eliminating the need to integrate high-power, large-area analog PLL circuits, thus reducing the overall hardware overhead, power consumption, and design complexity of the system.

[0143] Each of the above-described method embodiments, or various possible implementations of each method embodiment, can be executed individually or in combination of any two or more. The specific implementation can be determined according to actual usage requirements, and this application does not impose any restrictions on this.

[0144] The frequency adjustment method provided in this application can be executed by a frequency adjustment device. This application uses an example of a frequency adjustment device executing the frequency adjustment method to illustrate the frequency adjustment device provided in this application.

[0145] Figure 6 A schematic diagram of a possible structure of the frequency adjustment device involved in some embodiments of this application is shown. For example... Figure 6 As shown, the frequency adjustment device 70 may include a determination module 71 and an execution module 72.

[0146] The aforementioned determining module 71 is used to determine the cycle count threshold based on the difference between the total number of cycles parameter and the number of shutdown cycles parameter.

[0147] The execution module 72 is used to control the transmission of the first clock signal to the downstream logic module of the main clock source based on the cycle count threshold determined by the determination module 71, whenever the first clock signal output by the main clock source is received.

[0148] Optionally, the aforementioned determining module 71 is specifically used to determine the numerator of the simplest fractional form of the ratio of the difference between the first output frequency and the target turn-off frequency to the first output frequency when the first clock signal sent by the master clock source is received, as the loop counting threshold.

[0149] Optionally, the execution module 72 is further configured to start a counter. Specifically, upon receiving a first clock signal output from the master clock source, the execution module 72 controls the transmission of the first clock signal to the downstream logic module of the master clock source based on the cycle count threshold determined by the counter counting and determination module 71.

[0150] Optionally, the execution module 72 is specifically used to: turn off a first clock signal and reduce the counter count to the cycle count threshold determined by the determining module 71 when the counter count is greater than or equal to the cycle count threshold determined by the determining module 71; and send a first clock signal to the downstream logic module and increase the counter count to the turn-off cycle number parameter when the counter count is less than the cycle count threshold determined by the determining module 71.

[0151] Optionally, the execution module 72 is specifically used to: determine the difference between the counter count and the loop count threshold as a first value; and update the counter value to the first value. The execution module 72 is also specifically used to: determine the sum of the counter count and the shutdown cycle number parameter as a second value; and update the counter value to the second value.

[0152] This application provides a frequency adjustment device that determines a cycle count threshold by using the difference between a total number of cycles parameter and a shutdown cycle number parameter. This cycle count threshold characterizes the frequency adjustment requirement. Thus, when the frequency adjustment device receives a clock signal from the master clock source, it can control whether to transmit the clock signal to the downstream logic module of the master clock source using the cycle count threshold. This allows for precise control over how many clock pulses are retained within a specific clock cycle, achieving precise output frequency adjustment without needing to relock the phase and frequency through a PLL. This effectively reduces frequency modulation delay, glitches, jitter, or brief interruptions caused by PLL relocking, thereby avoiding momentary stuttering or performance degradation and improving stability and reliability. This enhances the stability of frequency adjustment.

[0153] The frequency adjustment device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0154] The frequency adjustment device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0155] The frequency adjustment device provided in this application embodiment can realize the various processes implemented in the above method embodiment, and will not be described again here to avoid repetition.

[0156] Optionally, such as Figure 7 As shown, this application embodiment also provides an electronic device 1000, including a processor 1001 and a memory 1002. The memory 1002 stores a program or instructions that can run on the processor 1001. When the program or instructions are executed by the processor 1001, they implement the various steps of the frequency adjustment method embodiment described above and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0157] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0158] Figure 8 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0159] The electronic device 100 includes, but is not limited to, components such as: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, and processor 110.

[0160] Those skilled in the art will understand that the electronic device 100 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 110 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 8 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0161] The processor 110 is used to determine the cycle count threshold based on the difference between the total number of cycles parameter and the number of shutdown cycles parameter.

[0162] The processor 110 described above is used to control the transmission of the first clock signal to the downstream logic module of the main clock source based on a cycle count threshold when it receives the first clock signal output by the main clock source.

[0163] Optionally, the processor 110 is specifically configured to, upon receiving the first clock signal sent by the master clock source, determine the numerator of the simplest fractional form of the ratio of the difference between the first output frequency and the target shutdown frequency to the first output frequency as the loop counting threshold.

[0164] Optionally, the processor 110 is also used to start a counter. Specifically, upon receiving a first clock signal output from the master clock source, the processor 110 controls the transmission of the first clock signal to the downstream logic module of the master clock source based on the counter's counting and cycle counting thresholds.

[0165] Optionally, the processor 110 is specifically configured to: shut down a first clock signal and reduce the counter count to the cycle count threshold when the counter count is greater than or equal to the cycle count threshold; and send a first clock signal to the downstream logic module and increase the counter count to the shutdown cycle number parameter when the counter count is less than the cycle count threshold.

[0166] Optionally, the processor 110 is specifically configured to: determine the difference between the counter count and the cycle count threshold as a first value; and update the counter value to the first value. The processor 110 is also specifically configured to: determine the sum of the counter count and the shutdown cycle number parameter as a second value; and update the counter value to the second value.

[0167] This application provides an electronic device that determines a cycle count threshold by using the difference between a total cycle count parameter and a shutdown cycle count parameter. This cycle count threshold characterizes the frequency adjustment requirements. Thus, when the electronic device receives a clock signal from a master clock source, it can control whether to transmit the clock signal to the downstream logic module of the master clock source using this cycle count threshold. This allows for precise control over how many clock pulses are retained within a specific clock cycle, achieving precise output frequency adjustment without needing to relock the phase and frequency through a PLL. This effectively reduces frequency modulation delay, glitches, jitter, or brief interruptions caused by PLL relocking, thereby avoiding momentary stuttering or performance degradation and improving stability and reliability. This enhances the stability of frequency adjustment.

[0168] The electronic device provided in this application embodiment can implement all the processes implemented in the above method embodiments and achieve the same technical effects. To avoid repetition, it will not be described again here. The beneficial effects of the various implementation methods in this embodiment can be found in the beneficial effects of the corresponding implementation methods in the above method embodiments. To avoid repetition, it will not be described again here.

[0169] It should be understood that, in this embodiment, the input unit 104 may include a graphics processor 1041 and a microphone 1042. The graphics processor 1041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 106 may include a display panel 1061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0170] The memory 109 can be used to store software programs and various data. The memory 109 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 109 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 109 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0171] Processor 110 may include one or more processing units; optionally, processor 110 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 110.

[0172] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the frequency adjustment method embodiments described above and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0173] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0174] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the frequency adjustment method embodiments described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0175] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0176] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the frequency adjustment method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0177] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0178] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0179] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A frequency adjustment method, characterized in that, include: The cycle count threshold is determined based on the difference between the total number of cycles parameter and the number of shutdown cycles parameter. Upon receiving the first clock signal output by the master clock source, the transmission of the first clock signal to the downstream logic module of the master clock source is controlled based on the cycle count threshold.

2. The method according to claim 1, characterized in that, The determination of the cycle count threshold based on the difference between the total number of cycles parameter and the number of shutdown cycles parameter includes: The denominator of the ratio of the target turn-off frequency to the first output frequency is determined as the total number of cycles parameter, and the numerator of the ratio is determined as the number of turn-off cycles parameter; The difference between the total number of cycles parameter and the number of shutdown cycles parameter is determined as the cycle count threshold.

3. The method according to claim 1 or 2, characterized in that, The method further includes: Start the counter; The step of controlling the transmission of the first clock signal to the downstream logic module of the master clock source based on the cycle count threshold includes: Upon receiving the first clock signal output by the master clock source, the transmission of the first clock signal to the downstream logic module of the master clock source is controlled based on the counter's count and the cycle count threshold.

4. The method according to claim 3, characterized in that, The step of controlling the transmission of the first clock signal to the downstream logic module of the main clock source based on the counter's count and the cycle count threshold includes: If the counter count is greater than or equal to the cycle count threshold, the first clock signal is turned off, and the counter count is reduced by the cycle count threshold. If the counter count is less than the cycle count threshold, the first clock signal is sent to the downstream logic module, and the counter count is incremented by the shutdown cycle number parameter.

5. The method according to claim 4, characterized in that, The step of reducing the count of the first counter by the cycle count threshold includes: The difference between the counter count and the loop count threshold is determined as the first value; Update the value of the counter to the first value; or, The step of incrementing the counter count by the shutdown cycle number parameter includes: The sum of the counter count and the shutdown cycle number parameter is determined as the second value; Update the value of the counter to the second value.

6. A frequency adjustment device, characterized in that, include: Determine the module and execute the module; The determining module is used to determine the cycle count threshold based on the difference between the total number of cycles parameter and the number of shutdown cycles parameter; The execution module is configured to, upon receiving a first clock signal output from the master clock source, control the transmission of the first clock signal to the downstream logic module of the master clock source based on the cycle count threshold determined by the determining module.

7. The apparatus according to claim 6, characterized in that, The determining module is specifically used for: The numerator of the ratio of the target turn-off frequency to the first output frequency is determined as the number of turn-off cycles parameter, and the denominator of the ratio is determined as the total number of cycles parameter; and, The difference between the total number of cycles parameter and the number of shutdown cycles parameter is determined as the cycle count threshold.

8. The apparatus according to claim 6 or 7, characterized in that, The execution module is also used to start the counter; The execution module is specifically used to control the transmission of the first clock signal to the downstream logic module of the main clock source based on the counter's count and the cycle count threshold determined by the determining module when it receives the first clock signal output by the main clock source.

9. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the frequency adjustment method as described in any one of claims 1 to 5.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the frequency adjustment method as described in any one of claims 1 to 5.

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