SPI operation sequence execution system and chip

Abstract

The invention discloses an SPI (Serial Peripheral Interface) operation sequence execution system and a chip. The SPI operation sequence execution system is based on a processor, a DMA controller, an SPI physical layer interface and a system memory, and is characterized by comprising a TCB module and a TCB processing device, wherein the TCB module comprises a TCB linked list, the TCB linked list comprises a plurality of TCB tables which are connected in sequence, and each TCB table is TCB data composed of SPI operation sequences; the TCB processing device obtains a TCB linked list, analyzes TCB data obtained from a system memory, determines and executes preset SPI operations in the TCB data, and informs a processor through single interruption when all the SPI operations are executed or a specific event occurs. According to the embodiment of the invention, the SPI operation sequence can be autonomously acquired, analyzed and executed in sequence from the memory, so that the whole SPI operation sequence execution process asynchronously runs on the processor.

Description

Technical Field

[0001] This invention relates to the field of communication interface technology, and in particular to an SPI operation sequence execution system and chip. Background Technology

[0002] The Serial Peripheral Interface (SPI), as a synchronous serial bus, is widely used for data exchange between microcontroller units (MCUs) and peripherals. SPI communication executes an ordered sequence of operations, including chip select (CS) control, command transmission and reception, data transmission and reception, mode changes, and delays.

[0003] In related technologies, techniques for executing operation sequences via SPI communication include the MCU processor directly manipulating the SPI controller registers through software to execute operation sequences, utilizing a Direct Memory Access (DMA) controller to assist in batch data transfer between memory and SPI peripherals, and buffering the data stream through a built-in First-In-First-Out (FIFO) queue in the SPI controller. Directly manipulating the SPI controller registers through software leads to high processor utilization, poor real-time performance, high interrupt overhead, and difficulty in maintaining the software driver for the operation sequences. The built-in FIFO allows the processor or DMA controller to read and write small amounts of data in batches, reducing direct access to data registers. However, the FIFO is only used for data buffering, has limited capacity, and cannot store or execute operation sequences containing control logic; long transactions still require frequent processor intervention. The DMA controller batches data between the SPI peripheral and memory, reducing the processor load. The CPU starts the DMA controller after configuring its parameters and notifies the processor upon completion via an interrupt. Some DMA controllers support chained transfers, configuring multiple data blocks at once. However, the DMA controller primarily addresses data transfer and lacks SPI control semantics, making it unable to independently handle operation sequences involving multiple CS switching, mode changes, command interaction, short packet transmission and reception, and delays. The processor still needs to frequently intervene in reconfiguring SPI, CS management and triggering subsequent operations, and descriptor preparation and linking also increase overhead.

[0004] In related technologies, the processor remains the core of operation sequence organization and scheduling during the execution of operation sequences via SPI communication. While DMA controllers share data transmission, they lack a general, efficient, and low-power hardware execution solution for complete operation sequences involving control, configuration, data, and timing management. These technologies have significant shortcomings in reducing the overhead of processor execution of operation sequences, improving real-time determinism, and simplifying software drivers, necessitating a mechanism that can liberate the processor from the micro-management of SPI operation sequences. Summary of the Invention

[0005] This invention provides an SPI operation sequence execution system and chip to solve the problems of high processor load, limited real-time performance, large system overhead and complex software drivers caused by the deep involvement of processor software in operation sequence control in related technologies.

[0006] According to one aspect of the present invention, an SPI operation sequence execution system is provided, based on a processor, a DMA controller, an SPI physical layer interface, and system memory, including: a TCB module and a TCB processing device;

[0007] The TCB module includes a TCB linked list, which consists of several sequentially linked TCB tables. Each TCB table contains TCB data composed of SPI operation sequences.

[0008] The TCB processing device acquires the TCB linked list, parses the TCB data obtained from the system memory, determines and executes the preset SPI operations in the TCB data, and notifies the processor through a single interrupt when all SPI operations are completed or a specific event occurs.

[0009] The TCB processing unit includes a CPU interface and control unit, a TCB acquisition unit, a TCB parsing and execution unit, and an interrupt and status management unit connected in sequence; wherein...

[0010] The CPU interface and control unit include a series of registers;

[0011] The CPU interface and control unit obtain the starting address, start / stop information, and interrupt enable information of the TCB linked list sent by the processor, and read the working status and error information of the TCB processing device, and send the starting address of the TCB linked list to the TCB acquisition unit.

[0012] The TCB acquisition unit has built-in prefetch buffer / caching and data reading logic. It retrieves the TCB linked list from system memory via the system bus and reads the TCB data.

[0013] The TCB acquisition unit retrieves the TCB list from system memory based on the starting address or the next TCB list address of the received TCB list, reads the TCB data in the TCB list, and sends the read TCB data to the TCB parsing and execution unit.

[0014] The TCB parsing and execution unit includes TCB control information analysis logic and master control state machine and execution logic; among which...

[0015] The TCB control information analysis logic parses the preset control information in the received TCB data and generates an enable signal; the master control state machine and execution logic drive the TCB table operation and send the TCB table operation status information to the interrupt and status management unit.

[0016] The TCB table received by the master control state machine and the execution logic includes the DMA enable flag being set. The master control state machine and the execution logic drive the SPI operation, configure and trigger the DMA controller, so that the DMA controller can transfer data between the system memory and the SPI physical layer. After the data transfer is completed, the working status information of the DMA controller is fed back to the TCB parsing and execution unit.

[0017] If the TCB table received by the master control state machine and the execution logic does not include the DMA enable flag being set and the TCB table defines embedded short data, the master control state machine and the execution logic extract the short data from the TCB table and send it to the SPI physical layer interface for transmission.

[0018] The master state machine and execution logic control the transmission, reception, start / stop, and status monitoring of the SPI physical layer interface, and promote the internal operation of the SPI physical layer interface.

[0019] The interrupt and status management unit includes an event collection module, a status register, and an interrupt generator; among which,

[0020] The event collection module collects operational status information for the TCB table;

[0021] The status register operates on the collected TCB table information, triggers the interrupt generator to send an interrupt signal to the external interrupt controller, and updates the status register.

[0022] According to another aspect of the present invention, a chip is provided, including the SPI operation sequence execution system provided by the present invention.

[0023] In the technical solution of this invention, the SPI operation sequence execution system, based on a processor, a DMA controller, an SPI physical layer interface, and system memory, includes: a TCB module and a TCB processing device; wherein, the TCB module includes a TCB linked list, the TCB linked list includes several sequentially connected TCB tables, each TCB table being TCB data composed of SPI operation sequences; the TCB processing device acquires the TCB linked list, parses the TCB data acquired from system memory, determines and executes the preset SPI operations in the TCB data, and notifies the processor through a single interrupt when all SPI operations are completed or a specific event occurs, thus solving the problems of high processor load, limited real-time performance, large system overhead, and complex software drivers caused by deep involvement of processor software in operation sequence control in related technologies. After the processor submits the complete SPI communication task in the form of a TCB linked list at once, it can autonomously acquire, parse, and execute the SPI operation sequence from memory in sequence, completing operations such as CS control, command transmission and reception, data transmission and reception, mode change, and delay in the SPI operation sequence, so that the entire SPI operation sequence execution process runs asynchronously to the processor, triggering a single interrupt only when the sequence is completed or an error event occurs, significantly reducing real-time intervention by the processor.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of an SPI operation sequence execution system provided in an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram of a TCB linked list for an SPI operation sequence provided in an embodiment of the present invention.

[0028] Figure 3 This is a schematic diagram of the structure of an SPI operation sequence execution system provided in an embodiment of the present invention.

[0029] Figure 4 This is a schematic diagram of a CPU interface and control unit provided in an embodiment of the present invention.

[0030] Figure 5This is a schematic diagram of the structure of a TCB acquisition unit provided in an embodiment of the present invention.

[0031] Figure 6 This is a schematic diagram of the structure of a TCB parsing and execution unit provided in an embodiment of the present invention.

[0032] Figure 7 This is a schematic diagram of the structure of an interrupt and status management unit provided in an embodiment of the present invention.

[0033] Figure 8 This is a schematic diagram of the structure of a chip provided in an embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "target," "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising," "including," and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] Figure 1 This is a schematic diagram of an SPI operation sequence execution system provided in an embodiment of the present invention. This embodiment is applicable to situations where an ordered sequence of operations, including CS control, command transmission and reception, data transmission and reception, mode changing, and / or delay, is executed between an MCU and its SPI peripheral via SPI communication. The SPI operation sequence execution system is located on the MCU. The SPI peripheral is an external device connected to the MCU via SPI. For example... Figure 1As shown, the SPI operation sequence execution system 100, based on processor 101, DMA controller 102, SPI physical layer interface 103 and system memory 104, includes: Transmission Control Block (TCB) module 105 and TCB processing device 106. Its structure and function are described below.

[0037] The TCB module 105 includes a TCB linked list, which consists of several sequentially connected TCB tables. Each TCB table contains TCB data composed of SPI operation sequences.

[0038] TCB processing device 106 acquires the TCB linked list, parses the TCB data acquired from system memory 104, determines and executes the preset SPI operations in the TCB data, and notifies processor 101 through a single interrupt when all SPI operations are completed or a specific event occurs.

[0039] Optionally, processor 101 is a processor in an MCU. System memory 104 is system memory in an MCU. DMA controller 102 can be a DMA controller in an MCU used for data transfer between system memory 104 and SPI physical layer interface 103. During data transfer, DMA controller 102 reads data from system memory 104 and writes the data to SPI physical layer interface 103. SPI physical layer interface 103 is a hardware module in an MCU used for SPI communication with SPI peripherals. Data can be sent to and received from SPI peripherals through SPI physical layer interface 103. TCB linked list can be a linked list used to store control information for each operation in the SPI operation sequence. TCB linked list is stored in system memory 104. TCB processing device 106 can be a hardware module used to retrieve, parse, and execute the SPI operation sequence sequentially from memory, so that the entire SPI operation sequence execution process runs asynchronously to processor 101.

[0040] Optionally, the SPI operation sequence can refer to an ordered sequence of operations that need to be performed between the MCU and its SPI peripheral via SPI communication, including CS control, command transmission and reception, data transmission and reception, mode changing, and / or delay. The SPI operation sequence can consist of M operations concatenated, where M is an integer greater than or equal to 2. Operations must be executed sequentially, starting with the first operation in the SPI operation sequence. Each operation in the SPI operation sequence is either CS control, command transmission and reception, data transmission and reception, mode changing, or delay or short packet transmission and reception.

[0041] Optionally, CS control can refer to controlling the operation of the SPI peripheral via a chip select signal output by the MCU. CS control includes CS switching. CS switching can be the operation of controlling the SPI peripheral to switch communication modes according to the chip select signal. Performing a CS switch can mean sending data to the SPI peripheral to instruct it to switch communication modes according to the chip select signal.

[0042] Optionally, command transmission and reception can include command sending and command receiving. Command sending can be an operation of sending a specified control command to an SPI peripheral. Command receiving can be an operation of receiving a specified control command sent by an SPI peripheral. Executing command sending can refer to sending a specified control command to an SPI peripheral. Executing command receiving can refer to receiving a specified control command sent by an SPI peripheral.

[0043] Optionally, data transmission and reception can include data sending and data receiving. Data sending can be an operation of sending specified data to an SPI peripheral. Data receiving can be an operation of receiving specified data sent by an SPI peripheral. Performing data sending can refer to sending specified data to an SPI peripheral. Performing data receiving can refer to receiving specified data sent by an SPI peripheral.

[0044] Optionally, a mode change can be an operation that controls the SPI peripheral to change its operating mode. Performing a mode change can refer to sending data to the SPI peripheral to instruct it to change its operating mode.

[0045] Optionally, the delay can be an operation that controls the SPI peripheral to perform a delay. Performing a delay can refer to sending data to the SPI peripheral to instruct it to perform a delay.

[0046] Optionally, short packet transmission and reception can include short packet sending and short packet receiving. Short packet sending can be an operation of sending specified short packet data to an SPI peripheral. Short packet receiving can be an operation of receiving specified short packet data sent by an SPI peripheral. Performing short packet sending can refer to sending specified short packet data to an SPI peripheral. Performing short packet receiving can refer to receiving specified short packet data sent by an SPI peripheral.

[0047] Optional, such as Figure 2As shown, the TCB linked list comprises several sequentially linked TCB tables. Each TCB table can be a list storing control information for an operation in the SPI operation sequence. Each TCB table is a different list in system memory 104. The first TCB table (TCB0) in the TCB linked list stores the control information for the first operation in the SPI operation sequence. The second TCB table (TCB1) in the TCB linked list stores the control information for the second operation in the SPI operation sequence. The third TCB table (TCB2) in the TCB linked list stores the control information for the third operation in the SPI operation sequence. And so on, with the Mth TCB table in the TCB linked list storing the control information for the Mth operation in the SPI operation sequence. The control information for an operation can be information used to define the operation content. The operation content can refer to the specific steps involved in executing the operation. The operation control information consists of eight fields: Operation Type, DMA Control, Interrupt Control, CS Control, Data Transmission Information, Inline Data Field, SPI Communication Parameter, and Next TCB Pointer.

[0048] Optionally, the operation type can be information used to define the type of operation. The operation type is transmit, receive, or full-duplex. An operation type of transmit indicates that the operation is performed by sending data to the SPI peripheral. For example, CS switching, command transmission, data transmission, mode change, delay, and short packet transmission are operations performed by sending data to the SPI peripheral. An operation type of receive indicates that the operation is implemented by receiving data sent by the SPI peripheral. For example, command reception, data reception, and short packet reception are operations performed by sending data to the SPI peripheral. An operation type of full-duplex indicates that the operation is performed by both sending data to and receiving data sent by the SPI peripheral.

[0049] Optionally, DMA control can be used to define whether data transfer between system memory 104 and SPI physical layer interface 103 is required during the execution of an operation via DMA controller 102. DMA control can be used for DMA transfers via "data buffer pointers" or for programmed input / output (PIO) transfers via "embedded data fields".

[0050] Optionally, DMA control uses a "data buffer pointer" for DMA transfer, indicating that data needs to be moved between system memory 104 and SPI physical layer interface 103 via DMA controller 102 during the operation. When the operation is performed by sending data to the SPI peripheral, the data buffer pointer in the "data transfer information" field is the identifier of the memory area in system memory 104 that stores the data to be sent to the SPI peripheral, and the data length in the "data transfer information" field is the number of bytes of data to be sent to the SPI peripheral. DMA controller 102 needs to move the data to be sent to the SPI peripheral from the memory area to the FIFO of SPI physical layer interface 103 for transmission based on the data buffer pointer and the data length. When the operation is performed by receiving data sent by the SPI peripheral, the data buffer pointer in the "Data Transfer Information" field is the identification information of the memory area in system memory 104 used to store the data sent by the SPI peripheral. The data length in the "Data Transfer Information" field is the number of bytes of data sent by the SPI peripheral. After the SPI physical layer interface 103 receives the data sent by the SPI peripheral, the DMA controller 102 needs to move the data sent by the SPI peripheral from the SPI physical layer interface 103 to the memory area according to the data buffer pointer and the data length. The identification information of the memory area can be information used to uniquely identify the memory area.

[0051] Optionally, DMA control uses "embedded data fields" for programmable input / output (PIO) transfers, indicating that data transfer between memory and SPI physical layer interface 103 is not required during operation via DMA controller 102. When the operation is performed by sending data to the SPI peripheral, the "embedded data field" contains the data to be sent to the SPI peripheral. This data needs to be directly sent to the SPI physical layer interface 103 so that it can send the data to the SPI peripheral. When the operation is performed by receiving data from the SPI peripheral, the data buffer pointer in the "data transfer information" field identifies the memory area in system memory 104 used to store the data sent by the SPI peripheral, and the data length in the "data transfer information" field is the number of bytes of data sent by the SPI peripheral. After receiving the data sent by the SPI peripheral, the SPI physical layer interface 103 needs to transfer the data to the memory area based on the data buffer pointer and the data length.

[0052] Optionally, interrupt control can be information used to indicate whether a corresponding interrupt signal needs to be generated to the CPU after the operation is completed. Chip select control can be information used to define the behavior of the chip select signal before and after the operation.

[0053] Optionally, the data transmission information includes a data buffer pointer and a data length. When the operation is performed by sending data to the SPI peripheral, the data buffer pointer in the "Data Transmission Information" field identifies the memory area in memory that stores the data to be sent to the SPI peripheral, and the data length in the "Data Transmission Information" field is the number of bytes of data to be sent to the SPI peripheral. When the operation is performed by receiving data sent by the SPI peripheral, the data buffer pointer in the "Data Transmission Information" field identifies the memory area in memory used to store the data sent by the SPI peripheral, and the data length in the "Data Transmission Information" field is the number of bytes of data sent by the SPI peripheral.

[0054] Optionally, when the operation is performed by sending data to the SPI peripheral and the DMA control is set to use the "Embedded Data Field" for programmable input / output PIO transfers, the "Embedded Data Field" is the data to be sent to the SPI peripheral. When the operation is performed by receiving data from the SPI peripheral, or when the DMA control is set to use the "Data Buffer Pointer" for DMA transfers, the "Embedded Data Field" can be empty.

[0055] Optionally, the SPI communication parameters can be the communication parameters used when the SPI physical layer interface 103 communicates with the SPI peripheral. The SPI communication parameters can include the mode, rate, bit width, and delay when the SPI physical layer interface 103 communicates with the SPI peripheral.

[0056] Optionally, the next TCB pointer can refer to the identifier of the TCB table storing the control information for the next operation. The next operation is the operation following the previous operation in the SPI operation sequence. The next TCB pointer in the control information of the first operation is the identifier of the TCB table storing the control information for the second operation. The next TCB pointer in the control information of the second operation is the identifier of the TCB table storing the control information for the third operation. The next TCB pointer in the control information of the third operation is the identifier of the TCB table storing the control information for the fourth operation. And so on, the next TCB pointer in the control information of the (M-1)th operation is the identifier of the TCB table storing the control information for the Mth operation. The Mth operation is the last operation in the sequence, with no following operation, and the next TCB pointer in the control information of the (M-1)th operation is empty. The TCB tables are linked together through their stored next TCB pointers to form a TCB linked list.

[0057] like Figure 3As shown, the SPI operation sequence execution system 300, based on a processor 301, a DMA controller 302, an SPI physical layer interface 303, and system memory 304, includes a TCB module 305 and a TCB processing device 306. The TCB processing device 306 includes a CPU interface and control unit 3061, a TCB acquisition unit 3062, a TCB parsing and execution unit 3063, and an interrupt and status management unit 3064 connected in sequence. The CPU interface and control unit 3063 includes a series of registers. The CPU interface and control unit 3063 acquires the starting address, start / stop information, and interrupt enable information of the TCB linked list sent by the processor, and reads the working status and error information of the TCB processing device, sending the starting address of the TCB linked list to the TCB acquisition unit 3062.

[0058] Optionally, the starting address of the TCB linked list can refer to the identifier information of the TCB table that stores the control information of the first operation in the sequence of SPI operations to be executed. Start / stop information can be information used to control the start or stop of the TCB processing device 306. Interrupt enable information can be information used to control the interrupt enable / disable of the TCB processing device 306.

[0059] Optionally, the processor 301 can send the starting address of the TCB linked list of the SPI operation sequence to be executed to the CPU interface and control unit 3063 in the TCB processing device 306 via the system bus, thereby calling the TCB module 305 via the system bus. In terms of workflow, the processor 301 first sends the starting address of the TCB linked list of the SPI operation sequence to be executed to the CPU interface and control unit 3063, instructing the TCB processing device 306 to start executing the SPI operation sequence. Based on the control information, it executes each operation in the SPI operation sequence. Then, the processor 301 can continue to execute other programs without synchronously waiting for the completion of the SPI operation sequence. The TCB processing device 306 then autonomously and asynchronously reads the control information sequentially from the system memory 304 through the TCB acquisition unit 3062. The core TCB parsing and execution unit 3063 is responsible for understanding and executing the operation content defined in each control information. Through coordination with the SPI physical layer interface 303 and the DMA controller 302, it precisely executes the complete SPI operation and parameter configuration defined by the TCB linked list in hardware. The entire SPI operation sequence is executed asynchronously to the processor 301, and the interrupt and status management unit 3064 notifies the processor 301 when the entire task chain is completed or an error event occurs.

[0060] Optionally, the TCB parsing and execution unit 3063 can send DMA requests to the DMA controller 302 or configure the DMA controller 302 through a connection with the DMA controller 302. The DMA controller 302 can send DMA data transfer task completion information or DMA data transfer task error information to the DMA controller 302 through a connection with the TCB parsing and execution unit 3063. A DMA request can be information used to instruct the DMA controller 302 to perform data transfer. DMA data transfer task completion information can be information indicating that the data transfer operation has been completed. DMA data transfer task error information can be information indicating that the data transfer operation cannot be completed. The TCB parsing and execution unit 3063 can perform SPI operations or configure the SPI physical layer interface 303 through a connection with the SPI physical layer interface 303. The SPI physical layer interface 303 can input SPI underlying status or received data to the TCB parsing and execution unit 3063 through a connection with the TCB parsing and execution unit 3063. The TCB parsing and execution unit 3063 can send sequence completion information or error information to the interrupt and status management unit 3064. The interrupt and status management unit 3064 can generate interrupt signals to the external interrupt controller 307.

[0061] Optionally, the core functions of the TCB processing device 306 are implemented by a closely cooperating CPU interface and control unit 3063, TCB acquisition unit 3062, TCB parsing and execution unit 3063, and interrupt and status management unit 3064.

[0062] Optional, such as Figure 4 As shown, the CPU interface and control unit 41 of the TCB processing device 400 includes a series of registers, including a control register 411, a status register 412, an error information register 413, and a channel-independent register group 414. The processor 401 is connected to the control register 411, the status register 412, the error information register 413, and the channel-independent register group 414.

[0063] Optionally, the CPU interface and control unit 41 can be a hardware module for information transfer between the processor 401 and the TCB processing device 400. The CPU interface and control unit 41 acts as a bridge between the TCB processing device 400 and the processor 401. The control register 411 is used to obtain the starting address, start / stop information, and interrupt enable information of the TCB linked list of the SPI operation sequence sent by the processor 401, and send the starting address of the obtained TCB linked list of the SPI operation sequence to the register of the TCB acquisition unit. The status register 412 is a register for managing the working status information in the TCB processing device 400. The working status information can refer to information used to characterize the working status of the TCB processing device 400. The working status information can include operation completion information corresponding to the operation generated when it is determined that the operation has been completed. The error information register 413 is a register for managing error information. Error information can refer to information used to characterize the error that has occurred in the TCB processing device 400. Error information can include error information corresponding to the operation generated when an error occurs during the execution of the operation content. The channel-independent register group 414 can be used to manage the tasks of the SPI channel. An SPI channel can refer to a channel formed by the SPI physical layer interface used for data transmission with SPI peripherals. The task of an SPI channel can refer to the data transmission process performed through it.

[0064] Optionally, the processor 401 can submit the starting address of the TCB linked list of the SPI operation sequence to be executed, start / stop information for controlling the start or stop of the TCB processing device 400, and enable / interrupt information for controlling the TCB processing device 400 through the control register 411. The processor 401 can send the starting address, start / stop information, or enable / interrupt information to the control register 411. The processor 401 can read the operating status information from the status register 412. The processor 401 can read error information from the error information register 413. The processor 401 can manage the tasks of the SPI channels through the channel-independent register group 414. When multiple SPI channels exist, an independent channel-independent register group 414 can be provided for each SPI channel to manage the tasks of each SPI channel separately. The TCB processing device 400 obtains the starting address, start / stop information, or enable / interrupt information sent by the processor 401 through the control register 411. The TCB processing device 400 can provide status feedback through the status register 412. The TCB processing device 400 can provide error feedback through the error information register 413. The TCB processing device 400 can configure the SPI channel through the channel-independent register group 414.

[0065] Optionally, after receiving the starting address of the TCB linked list of the SPI operation sequence sent by the processor 401, the CPU interface and control unit 41 will send the starting address of the TCB linked list of the SPI operation sequence sent by the processor 401 to the TCB acquisition unit 3062. The CPU interface and control unit 41 can receive the starting address of the TCB linked list of the SPI operation sequence sent by the processor 401 through the control register 411 and send the starting address of the TCB linked list of the SPI operation sequence sent by the processor 401 to the TCB acquisition unit.

[0066] Optional, such as Figure 5 As shown, the TCB acquisition unit 500 has a built-in prefetch buffer / cache 51 and data reading logic 52. It retrieves the TCB linked list from the system memory 501 via the system bus and reads the TCB data. Based on the starting address or the next TCB linked list address of the received TCB linked list, the TCB acquisition unit 500 retrieves the TCB linked list from the system memory 501, reads the TCB data in the TCB linked list, and sends the read TCB data to the TCB parsing and execution unit 502.

[0067] Optionally, the process of executing the SPI operation sequence based on the TCB linked list begins with the TCB acquisition unit 500. The TCB acquisition unit 500 reads TCB data from system memory via the system bus, based on the starting address of the TCB linked list of the SPI operation sequence provided by the CPU interface and control unit 503, or the next TCB linked list address generated based on the operation completion information sent by the TCB parsing and execution unit 502. The TCB data refers to the control information in the TCB table identified by the starting address or the next TCB linked list address. The read TCB data is then sent to the TCB parsing and execution unit 502. The next TCB linked list address can refer to the identification information of the TCB table storing the next control information to be read. Current TCB feedback can refer to the TCB parsing and execution unit 502 sending the operation completion information corresponding to each operation in the SPI operation sequence to the TCB acquisition unit 500 after the operation is completed. The operation completion information corresponding to the operation can be information indicating that the operation has been completed. The operation completion information corresponding to each operation in the SPI operation sequence, except for the last operation, includes the next TCB pointer from the operation's control information. The operation completion information corresponding to the last operation in the SPI operation sequence does not include the next TCB pointer in the operation's control information. When operation completion information containing the next TCB pointer is received, the next TCB pointer in the operation completion information is the identifier information of the TCB table storing the next control information to be read. The next TCB pointer can be extracted from the operation completion information to generate the address of the next TCB linked list. When operation completion information without the next TCB pointer is received, it is determined that there is no address for the next TCB linked list.

[0068] Optionally, the prefetch buffer / cache 51 can be a prefetch buffer or a cache of preset capacity used to send the received start address or the generated next TCB list address to the data read logic 52. The data read logic 52 can be a hardware module used to read the control information of the TCB table to which the address belongs from the TCB list of the SPI operation sequence stored in memory via the system bus according to the received start address or the generated next TCB list address, and then send the read control information to the TCB parsing and execution unit 502.

[0069] Optionally, after receiving the starting address of the TCB linked list of the SPI operation sequence sent by the CPU interface and control unit 503, the TCB acquisition unit 500 reads the control information in the TCB table to which the receiving starting address belongs, thereby reading the control information of the first operation in the SPI operation sequence from the TCB linked list of the SPI operation sequence stored in memory. Then, it sends the read control information to the TCB parsing and execution unit 502, instructing the TCB parsing and execution unit 502 to execute the first operation based on the control information of the first operation. The TCB acquisition unit 500 can send the received starting address provided by the CPU interface and control unit 503 to the data reading logic 52 through the prefetch buffer / cache 51. The TCB acquisition unit 500 can read the control information in the TCB table to which the received start address belongs through the data reading logic 52. In this way, it can read the control information of the first operation in the SPI operation sequence from the TCB linked list of the SPI operation sequence stored in memory. Then, it sends the read control information to the TCB parsing and execution unit 502, thereby instructing the TCB parsing and execution unit 502 to execute the first operation based on the control information of the first operation.

[0070] Optionally, after receiving the operation completion information containing the next TCB pointer sent by the TCB parsing and execution unit 502, the TCB acquisition unit 500 extracts the next TCB pointer from the operation completion information to generate the next TCB linked list address. Based on the generated next TCB linked list address, it reads the control information in the next TCB linked list address, thereby reading the control information of the operation to be executed next in the SPI operation sequence from the TCB linked list of the SPI operation sequence stored in memory. Then, it sends the read control information to the TCB parsing and execution unit 502, thereby instructing the TCB parsing and execution unit 502 to execute the operation to be executed next based on the control information of the operation to be executed next. The TCB acquisition unit 500 can also extract the next TCB pointer from the operation completion information containing the next TCB pointer sent by the TCB parsing and execution unit 502 to generate the next TCB linked list address, and send the generated next TCB linked list address to the prefetch buffer / cache 51. The TCB acquisition unit 500 can send the generated next TCB linked list address to the data reading logic 52 through the prefetch buffer / cache 51. The TCB acquisition unit 500 can read the control information in the next TCB linked list address generated by the data reading logic 52, thereby reading the control information of the next operation to be executed in the SPI operation sequence from the TCB linked list of the SPI operation sequence stored in memory, and then sending the read control information to the TCB parsing and execution unit 502, thereby instructing the TCB parsing and execution unit 502 to execute the next operation based on the control information of the next operation to be executed.

[0071] Optionally, after receiving the operation completion information sent by the TCB parsing and execution unit 502 that does not contain the next TCB pointer, the TCB acquisition unit 500 will determine that there is no next TCB linked list address.

[0072] Optional, such as Figure 6 As shown, the TCB parsing and execution unit 600 includes TCB control information analysis logic 61 and master control state machine and execution logic 62; wherein, the TCB control information analysis logic 61 parses the preset control information in the received TCB data and generates an enable signal; the master control state machine and execution logic 62 drives the TCB table operation and sends the TCB table operation working status information to the interrupt and status management unit 601.

[0073] Optionally, the TCB parsing and execution unit 600 is a hardware module used to understand the control information of an operation and execute the operation content defined by the control information, thereby performing the operation. The workflow of the TCB parsing and execution unit 600 begins with a detailed analysis of the TCB data sent by the TCB acquisition unit 604. The TCB control information analysis logic 61 is a hardware module within the TCB parsing and execution unit 600 used to determine the operation content defined by the TCB data sent by the TCB acquisition unit 604 and generate enable signals to drive the master control state machine and execution logic 62 to execute the operation content. The TCB parsing and execution unit 600 can identify the specific parameters in the preset control information used to define the operation content in the TCB data sent by the TCB acquisition unit 604 through its internal TCB control information analysis logic 61, determine the operation content defined by the control information, and generate enable signals to drive the master control state machine and execution logic 62 to execute the operation content. The enable signal can be a control signal used to drive the master control state machine and execution logic 62 to execute the specified operation content. The master state machine and execution logic 62 is a hardware module within the TCB parsing and execution unit 600 used to execute operations. The master state machine and execution logic 62 can perform DMA control or configuration output on the DMA controller 602 through a connection with it. The DMA controller 602 can send DMA data transfer task completion information or DMA data transfer task error information to the master state machine and execution logic 62 through a connection with it. The master state machine and execution logic 62 can perform SPI control or data output on the SPI physical layer interface 603 through a connection with it. The SPI physical layer interface 603 can input the SPI underlying state or received data to the master state machine and execution logic 62 through a connection with it. The master state machine and execution logic 62 can send calculation results to the TCB acquisition unit 604. The calculation results can be operation completion information corresponding to the operation used to generate the next TCB linked list address. The master control state machine and execution logic 62 can send the TCB table operation status information to the interrupt and status management unit 601. The TCB table operation status information can be sequence completion information or error information corresponding to the operation. The sequence completion information can be used to indicate that the SPI operation sequence has been completed.

[0074] Optionally, the TCB data received by the master control state machine and execution logic 62 includes a DMA enable flag being set. The master control state machine and execution logic 62 drive SPI operation, configure and trigger the DMA controller 602, so that the DMA controller 602 performs data transfer between system memory and SPI physical layer interface 603. After the data transfer is completed, the DMA controller's working status information is fed back to the TCB parsing and execution unit 600. The DMA enable flag being set can be used to indicate that the DMA control is using a "data buffer pointer" for DMA transfer.

[0075] Optionally, when the TCB data received by the master state machine and execution logic 62 includes a DMA enable flag being set and the operation is determined to be that the DMA controller 602 moves the data to be sent to the SPI peripheral from the memory area to the FIFO of the SPI physical layer interface 603 for transmission according to the data buffer pointer and data length, the TCB control information analysis logic 61 can generate an enable signal to drive the master state machine and execution logic 62 to perform the above operation, and send the enable signal to the master state machine and execution logic 62. The master state machine and execution logic 62 can then control the DMA controller 602 to move the data to be sent to the SPI peripheral from the memory area to the FIFO of the SPI physical layer interface 603 according to the data buffer pointer and data length, and then control the SPI physical layer interface 603 to send the data to the SPI peripheral. After completing the data transfer operation—moving the data to be sent to the SPI peripheral from the memory area to the FIFO of the SPI physical layer interface 603 according to the data buffer pointer and data length—the DMA controller 602 sends DMA data transfer task completion information to the master control state machine and execution logic 62. If the DMA controller 602 cannot complete the data transfer operation, it sends DMA data transfer task error information to the master control state machine and execution logic 62. After controlling the SPI physical layer interface 603 to send data to the SPI peripheral, the master control state machine and execution logic 62 can determine the completed operation content, identify the operation to which the completed operation belongs, generate operation completion information corresponding to the operation, and send the operation completion information to the TCB acquisition unit 604.

[0076] Optionally, when the TCB data received by the master state machine and execution logic 62 includes a DMA enable flag being set and the operation content is determined to be that after the SPI physical layer interface 603 receives data sent by the SPI peripheral, the DMA controller 602 moves the data sent by the SPI peripheral from the SPI physical layer interface 603 to the memory area according to the data buffer pointer and data length, the TCB control information analysis logic 61 can generate an enable signal to drive the master state machine and execution logic 62 to execute the above operation content, and send the enable signal to the master state machine and execution logic 62. The master state machine and execution logic 62 can then control the SPI physical layer interface 603 to receive data sent by the SPI peripheral, and control the DMA controller 602 to move the data sent by the SPI peripheral from the SPI physical layer interface 603 to the memory area according to the data buffer pointer and data length, based on the enable signal. After completing the data transfer operation—moving data sent by the SPI peripheral from the SPI physical layer interface 603 to the memory area according to the data buffer pointer and data length—the DMA controller 602 sends DMA data transfer task completion information to the master control state machine and execution logic 62. If the DMA controller 602 cannot complete the data transfer operation, it sends DMA data transfer task error information to the master control state machine and execution logic 62. Upon receiving information indicating that the data transfer operation is complete, the master control state machine and execution logic 62 can determine the completed operation content, identify the operation to which the completed operation belongs, generate operation completion information corresponding to the operation, and send the operation completion information to the TCB acquisition unit 604.

[0077] Optionally, if the TCB data received by the master state machine and execution logic 62 does not include a DMA enable flag and the TCB data defines embedded short data, the master state machine and execution logic 62 extracts the short data from the TCB data and sends it to the SPI physical layer interface 603 for transmission. Defining embedded short data in the TCB data can mean that the "embedded data field" in the TCB data is not empty. The data in the "embedded data field" is the data to be sent to the SPI peripheral. Not defining embedded short data in the TCB data can mean that the "embedded data field" in the TCB data is empty.

[0078] Optionally, when the TCB data received by the master state machine and execution logic 62 does not include a DMA enable flag being set, and the TCB data defines embedded short data, and the operation is determined to be sending the data in the "embedded data field" that needs to be sent to the SPI peripheral to the SPI physical layer interface 603, so that the SPI physical layer interface 603 sends the data to the SPI peripheral, the TCB control information analysis logic 61 can generate an enable signal to drive the master state machine and execution logic 62 to perform the above operation, and send the enable signal to the master state machine and execution logic 62. The master state machine and execution logic 62 can then, based on the enable signal, send the data in the "embedded data field" that needs to be sent to the SPI peripheral to the SPI physical layer interface 603, and then control the SPI physical layer interface 603 to send the data to the SPI peripheral. After the master control state machine and execution logic 62 send data to the SPI peripheral via the control SPI physical layer interface 603, it determines the completed operation content, determines the operation to which the completed operation content belongs, generates operation completion information corresponding to the operation, and sends the operation completion information corresponding to the operation to the TCB acquisition unit 604.

[0079] Optionally, when the TCB data received by the master state machine and execution logic 62 does not include a DMA enable flag being set and no embedded short data is defined in the TCB data, and the operation content is determined to be that after the SPI physical layer interface 603 receives data sent by the SPI peripheral, it moves the data sent by the SPI peripheral to the memory area according to the data buffer pointer and data length, the TCB control information analysis logic 61 can generate an enable signal to drive the master state machine and execution logic 62 to execute the above operation content, and send the enable signal to the master state machine and execution logic 62. The master state machine and execution logic 62 can control the SPI physical layer interface 603 to move the data sent by the SPI peripheral to the memory area according to the data buffer pointer and data length after receiving the data sent by the SPI peripheral, based on the enable signal. After the master control state machine and execution logic 62 move the data sent by the SPI peripheral to the memory area through the control SPI physical layer interface 603, it determines the content of the completed operation, determines the operation to which the completed operation belongs, generates operation completion information corresponding to the operation, and sends the operation completion information corresponding to the operation to the TCB acquisition unit 604.

[0080] Optionally, the master control state machine and execution logic 62 can generate error information corresponding to the operation when an error occurs during the execution of the operation, and send the error information to the interrupt and status management unit 601. The error information corresponding to the operation can be information used to characterize the error that occurred during the execution of the operation.

[0081] Optionally, when the TCB control information analysis logic 61 detects that the control information sent by the TCB acquisition unit 604 does not include the next TCB pointer, it determines that the operation to which the control information belongs is the last operation in the sequence, and sends the last operation prompt information and the enable signal used to drive the master control state machine and execution logic 62 to execute the operation content together. The last operation prompt information can be information used to indicate that the operation is the last operation in the sequence. After the master control state machine and execution logic 62 completes the operation content, it can send the operation completion information corresponding to the operation to the TCB acquisition unit 604 and the sequence completion information to the interrupt and status management unit 601.

[0082] Optionally, the master state machine and execution logic 62 control the transmission, reception, start / stop, and status monitoring of the SPI physical layer interface 603, and advance the internal operations of the SPI physical layer interface 603. The master state machine and execution logic 62 can monitor whether the SPI physical layer interface 603 has completed the data transmission process, whether the SPI physical layer interface 603 has completed the data reception process, monitor the start and stop of the SPI physical layer interface 603, and monitor the status of the FIFO of the SPI physical layer interface 603. Throughout the entire execution of the SPI operation sequence, the master state machine and execution logic 62 continuously monitors the operational status of each relevant unit. The master state machine and execution logic 62 can generate operation completion information corresponding to the operation when it determines that the operation has been completed, and can generate error information corresponding to the operation when an error occurs during the execution of the operation. Both sequence completion information and error information are collected by the interrupt and status management unit 601. The interrupt and status management unit 601 is responsible for generating interrupt signals corresponding to the collected sequence completion information or error information to the processor and updating the status register in the interrupt and status management unit 601.

[0083] Optional, such as Figure 7 As shown, the interrupt and status management unit 700 includes an event collection module 71, a status register 72, and an interrupt generator 73; wherein, the event collection module 71 collects TCB table operation status information; the status register 72 triggers the interrupt generator 73 to generate an interrupt signal to the external interrupt controller 701 based on the collected TCB table operation status information, and updates the status register 72.

[0084] Optionally, the interrupt and status management unit 700 is a hardware module used to generate corresponding interrupt signals to the processor based on the collected TCB table operation status information. The collected TCB table operation status information is either sequence completion information or error information. The interrupt signal corresponding to the sequence completion information can be an interrupt signal used to characterize the sequence execution completion event described by the sequence completion information. The interrupt signal corresponding to the error information can be an interrupt signal used to characterize the error event described by the error information. The event collection module 71 is a hardware module inside the interrupt and status management unit 700 used to collect sequence completion information or error information. The status register 72 is a register inside the interrupt and status management unit 700 used to trigger the interrupt generator 73 to generate an interrupt signal to the external interrupt controller based on the collected TCB table operation status information, and to update the status register. The interrupt generator 73 is a hardware module used to generate an interrupt signal to the interrupt controller 701 in the processor, thereby sending an interrupt request.

[0085] Optionally, the interrupt and status management unit 700 can collect sequence completion information or error information sent by the TCB parsing and execution unit 702 through the event collection module 71. After collecting the sequence completion information through the event collection module 71, the interrupt and status management unit 700 can trigger the interrupt generator 73 through the status register 72 to generate an interrupt signal corresponding to the sequence completion information, and send the interrupt signal corresponding to the sequence completion information to the interrupt controller 701 in the processor, thereby generating an interrupt signal corresponding to the sequence completion information for the processor, and notifying the processor through the interrupt signal when a sequence completion event occurs.

[0086] Optionally, after the interrupt and status management unit 700 collects error information through the event collection module 71, it can trigger the interrupt generator 73 through the status register 72 to generate an interrupt signal corresponding to the error information and send the interrupt signal corresponding to the error information to the interrupt controller 701 in the processor, thereby generating an interrupt signal corresponding to the error information for the processor and notifying the processor through the interrupt signal when an error event occurs.

[0087] Optionally, the status register 72 can store the sequence completion information collected by the event collection module 71, thereby updating the status register 72. The status register 72 can provide status feedback to the CPU interface and control unit 703, sending the newly stored sequence completion information to the CPU interface and control unit 703.

[0088] In the technical solution of this invention, the SPI operation sequence execution system, based on a processor, a DMA controller, an SPI physical layer interface, and system memory, includes: a TCB module and a TCB processing device; wherein, the TCB module includes a TCB linked list, the TCB linked list includes several sequentially connected TCB tables, each TCB table being TCB data composed of SPI operation sequences; the TCB processing device acquires the TCB linked list, parses the TCB data acquired from system memory, determines and executes the preset SPI operations in the TCB data, and notifies the processor through a single interrupt when all SPI operations are completed or a specific event occurs, thus solving the problems of high processor load, limited real-time performance, large system overhead, and complex software drivers caused by deep involvement of processor software in operation sequence control in related technologies. After the processor submits the complete SPI communication task in the form of a TCB linked list at once, it can autonomously acquire, parse, and execute the SPI operation sequence from memory in sequence, completing operations such as CS control, command transmission and reception, data transmission and reception, mode change, and delay in the SPI operation sequence, so that the entire SPI operation sequence execution process runs asynchronously to the processor, triggering a single interrupt only when the sequence is completed or an error event occurs, significantly reducing real-time intervention by the processor.

[0089] The SPI operation sequence execution system provided in this embodiment of the invention achieves automated and asynchronous execution of complex SPI operation sequences submitted by the processor through the coordinated work of the CPU interface and control unit, TCB acquisition unit, TCB parsing and execution unit, interrupt and status management unit, DMA controller and SPI physical layer interface, thereby significantly reducing the processor load and improving the performance and flexibility of SPI communication.

[0090] The technical solution of this invention can eliminate software scheduling latency, improve SPI communication efficiency and real-time determinism, and simplify upper-layer software drivers by performing TCB switching and SPI operations in hardware. Developers only need to build the TCB linked list and process the results. The technical solution of this invention can free up the processor, improve system performance, and reduce software development and maintenance costs. Although it requires additional hardware resources and TCB definition debugging, its innovative hardware offloading mechanism provides an efficient solution to the SPI communication bottleneck.

[0091] This invention proposes a TCB data structure and its dedicated SPI operation sequence execution device, realizing the hardware-based, automated, and asynchronous execution of SPI operation sequences. By decomposing complex SPI transactions into hardware-parseable command sequences, it eliminates the burden of frequent SPI controller configuration and control flow management for the processor, laying the foundation for autonomous hardware execution. The SPI operation sequence execution device can integrate a TCB acquisition unit, a parsing and execution unit, an SPI physical layer interface, and a CS management unit, and can cooperate with DMA. The SPI operation sequence execution device can automatically retrieve the TCB linked list from memory, parse and execute each operation in the SPI operation sequence (such as CS switching, mode adjustment, and data transmission and reception) sequentially, and only notify the processor through a single interrupt when the SPI operation sequence is completed or a specific event (such as an error event) is triggered. Compared to direct processor control, the SPI operation sequence execution device hardwareizes the control logic, reducing interrupt or polling overhead. Compared to traditional DMA, which only handles data transfer, the SPI operation sequence execution device can autonomously schedule complete SPI operation sequences (such as multiple command-data-delay segments). The processor only needs to initially configure and start the device, and then run asynchronously, significantly improving SPI communication efficiency and real-time determinism.

[0092] The technical solution of this invention combines the TCB data structure with a dedicated hardware device to transform the SPI operation sequence from processor-driven to hardware-autonomous execution, surpassing related technologies in terms of control granularity, autonomy, and transaction processing capabilities, and effectively solving the problems of high processor load, insufficient real-time performance, and software complexity.

[0093] In the technical solution of this invention, the TCB linked list encapsulates the complete SPI operation definition. The hardware autonomously executes complex SPI operation sequences according to the TCB linked list, and the processor runs asynchronously after submitting the task. The technical solution of this invention can significantly reduce the load and improve the real-time performance and efficiency of SPI. It is fundamentally different from the prior art in terms of hardware-based control logic, autonomous sequence execution, and asynchronous decoupling.

[0094] Figure 8 This is a schematic diagram of a chip structure provided in an embodiment of the present invention. Figure 8 As shown, chip 80 includes an SPI operation sequence execution system 800. The SPI operation sequence execution system 800 is disposed in chip 80.

[0095] The SPI operation sequence execution system 800, based on processor 801, DMA controller 802, SPI physical layer interface 803 and system memory 804, includes: TCB module 805 and TCB processing device 806. Its structure and function are described below.

[0096] The TCB module 805 includes a TCB linked list, which consists of several sequentially connected TCB tables. Each TCB table contains TCB data composed of SPI operation sequences.

[0097] TCB processing device 806 obtains the TCB linked list, parses the TCB data obtained from system memory 804, determines and executes the preset SPI operations in the TCB data, and notifies processor 801 through a single interrupt when all SPI operations are completed or a specific event occurs.

[0098] For example, the chip 80 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), an interface chip, or other integrated chip. The chip 80 may be coupled to the processor 801.

[0099] In the technical solution of this invention, the SPI operation sequence execution system, based on a processor, a DMA controller, an SPI physical layer interface, and system memory, includes: a TCB module and a TCB processing device; wherein, the TCB module includes a TCB linked list, the TCB linked list includes several sequentially connected TCB tables, each TCB table being TCB data composed of SPI operation sequences; the TCB processing device acquires the TCB linked list, parses the TCB data acquired from system memory, determines and executes the preset SPI operations in the TCB data, and notifies the processor through a single interrupt when all SPI operations are completed or a specific event occurs, thus solving the problems of high processor load, limited real-time performance, large system overhead, and complex software drivers caused by deep involvement of processor software in operation sequence control in related technologies. After the processor submits the complete SPI communication task in the form of a TCB linked list at once, it can autonomously acquire, parse, and execute the SPI operation sequence from memory in sequence, completing operations such as CS control, command transmission and reception, data transmission and reception, mode change, and delay in the SPI operation sequence, so that the entire SPI operation sequence execution process runs asynchronously to the processor, triggering a single interrupt only when the sequence is completed or an error event occurs, significantly reducing real-time intervention by the processor.

[0100] DMA data transfer task error information. It should be understood that the various processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0101] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An SPI operation sequence execution system, based on a processor, a DMA controller, an SPI physical layer interface, and system memory, characterized in that, include: TCB module and TCB processing unit; The TCB module includes a TCB linked list, which consists of several sequentially linked TCB tables. Each TCB table contains TCB data composed of SPI operation sequences. The TCB processing device acquires the TCB linked list, parses the TCB data obtained from the system memory, determines and executes the preset SPI operations in the TCB data, and notifies the processor through a single interrupt when all SPI operations are completed or a specific event occurs.

2. The SPI operation sequence execution system according to claim 1, characterized in that, The TCB processing unit includes a CPU interface and control unit, a TCB acquisition unit, a TCB parsing and execution unit, and an interrupt and status management unit connected in sequence; wherein... The CPU interface and control unit include a series of registers; The CPU interface and control unit obtain the starting address, start / stop information, and interrupt enable information of the TCB linked list sent by the processor, and read the working status and error information of the TCB processing device, and send the starting address of the TCB linked list to the TCB acquisition unit.

3. The SPI operation sequence execution system according to claim 2, characterized in that, The TCB acquisition unit has built-in prefetch buffer / caching and data reading logic. It retrieves the TCB linked list from system memory via the system bus and reads the TCB data.

4. The SPI operation sequence execution system according to claim 3, characterized in that, The TCB acquisition unit retrieves the TCB list from system memory based on the starting address or the next TCB list address of the received TCB list, reads the TCB data in the TCB list, and sends the read TCB data to the TCB parsing and execution unit.

5. The SPI operation sequence execution system according to claim 2, characterized in that, The TCB parsing and execution unit includes TCB control information analysis logic and master control state machine and execution logic; among which... The TCB control information analysis logic parses the preset control information in the received TCB data and generates an enable signal; the master control state machine and execution logic drive the TCB table operation and send the TCB table operation status information to the interrupt and status management unit.

6. The SPI operation sequence execution system according to claim 5, characterized in that, The TCB data received by the master control state machine and execution logic includes the DMA enable flag being set. The master control state machine and execution logic drive SPI operation, configure and trigger the DMA controller, so that the DMA controller can transfer data between the system memory and the SPI physical layer interface. After the data transfer is completed, the working status information of the DMA controller is fed back to the TCB parsing and execution unit.

7. The SPI operation sequence execution system according to claim 5, characterized in that, The TCB data received by the master control state machine and the execution logic does not include the DMA enable flag being set, and the TCB data defines embedded short data. The master control state machine and the execution logic extract the short data from the TCB data and send it to the SPI physical layer interface for transmission.

8. The SPI operation sequence execution system according to claim 5, characterized in that, The master state machine and execution logic control the transmission, reception, start / stop, and status monitoring of the SPI physical layer interface, and promote the internal operation of the SPI physical layer interface.

9. The SPI operation sequence execution system according to claim 2, characterized in that, The interrupt and status management unit includes an event collection module, a status register, and an interrupt generator; among which, The event collection module collects operational status information for the TCB table; The status register operates on the working status information based on the collected TCB table, triggers the interrupt generator to generate an interrupt signal to the external interrupt controller, and updates the status register.

10. A chip, characterized in that, Includes the SPI operation sequence execution system as described in any one of claims 1-9.

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