SPI operation sequence execution system and chip

Abstract

The invention discloses an SPI (Serial Peripheral Interface) operation sequence execution system and a chip. The SPI operation sequence execution system is based on a processor and a system memory, and comprises a TCB module and a TCB processing device, the TCB module comprises a plurality of TCB linked lists, each TCB linked list comprises a plurality of TCB lists connected in sequence, and each TCB list is TCB data composed of SPI operation sequences; the TCB processing device obtains each TCB linked list according to a preset strategy, analyzes TCB data obtained from a system memory, determines and executes preset SPI operations in the TCB data, and informs a processor through a single interrupt when all the SPI operations are executed or a specific event occurs. According to the embodiment of the invention, the concurrent automatic execution of the multiple SPI operation sequences can be realized, the task scheduling executed by the multiple SPI operation sequences is subjected to hardware processing thoroughly, and a processor is liberated from complex coordination work.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to an SPI operation sequence execution system and chip. Background Technology

[0002] The Serial Peripheral Interface (SPI), as a synchronous serial bus, is widely used for data exchange between microcontroller units (MCUs) and peripherals. SPI communication executes an ordered sequence of operations, including chip select (CS) control, command transmission and reception, data transmission and reception, mode changes, and delays.

[0003] In related technologies, techniques for executing operation sequences via SPI communication include the MCU processor directly manipulating the SPI controller registers through software to execute operation sequences, utilizing a Direct Memory Access (DMA) controller to assist in batch data transfer between memory and SPI peripherals, and buffering the data stream through a built-in First-In-First-Out (FIFO) queue in the SPI controller. Directly manipulating the SPI controller registers through software leads to high processor utilization, poor real-time performance, high interrupt overhead, and difficulty in maintaining the software driver for the operation sequences. The built-in FIFO allows the processor or DMA controller to read and write small amounts of data in batches, reducing direct access to data registers. However, the FIFO is only used for data buffering, has limited capacity, and cannot store or execute operation sequences containing control logic; long transactions still require frequent processor intervention. The DMA controller batches data between the SPI peripheral and memory, reducing the processor load. The processor starts the DMA controller after configuring its parameters and notifies the processor of interrupts upon completion. Some DMA controllers support chained transfers, configuring multiple data blocks at once. However, the DMA controller primarily addresses data transfer and lacks SPI control semantics, making it unable to independently handle operation sequences involving multiple CS switching, mode changes, command interaction, short packet transmission and reception, and delays. The processor still needs to frequently intervene in reconfiguring SPI, CS management and triggering subsequent operations, and descriptor preparation and linking also increase overhead.

[0004] In related technologies, the processor remains the core of operation sequence organization and scheduling during the execution of operation sequences via SPI communication. While DMA controllers share data transmission, they lack a general, efficient, and low-power hardware execution solution for complete operation sequences involving control, configuration, data, and timing management. These technologies have significant shortcomings in reducing the overhead of processor execution of operation sequences, improving real-time determinism, and simplifying software drivers, necessitating a mechanism that can liberate the processor from the micro-management of SPI operation sequences. Summary of the Invention

[0005] This invention provides an SPI operation sequence execution system and chip to solve the problems of high processor load, limited real-time performance, large system overhead and complex software drivers caused by the deep involvement of processor software in operation sequence control in related technologies.

[0006] According to one aspect of the present invention, an SPI operation sequence execution system is provided, based on a processor and system memory, comprising: a TCB module and a TCB processing device;

[0007] The TCB module includes multiple TCB linked lists, each TCB linked list includes several TCB tables connected in sequence, and each TCB table is TCB data composed of SPI operation sequences.

[0008] The TCB processing device obtains each TCB linked list according to a preset strategy, parses the TCB data obtained from the system memory, determines and executes the preset SPI operations in the TCB data, and notifies the processor through a single interrupt when all SPI operations are completed or a specific event occurs.

[0009] The TCB processing unit includes a CPU interface, a channel arbitration and scheduling unit, a shared TCB acquisition unit, a shared TCB parsing and execution unit, and a shared interrupt and status management unit connected in sequence; wherein, the CPU interface includes various CPU interface units, and the CPU interface unit includes a control register, a status register, and a channel register group;

[0010] The control register sends the TCB linked list base address and task start / stop information sent by the processor to the channel arbitration scheduling unit;

[0011] The status register feeds back the channel's operating status to the channel arbitration and scheduling unit;

[0012] The channel register group configures each SPI physical layer interface.

[0013] The channel arbitration scheduling unit has a built-in arbitrator, task queue and channel selector. The channel arbitration scheduling unit selects the active channel corresponding to the TCB linked list base address sent by each CPU interface unit according to the preset strategy, and sends the active channel identifier and TCB linked list base address to the shared TCB acquisition unit.

[0014] The arbitrator generates a task scheduling plan corresponding to the base address of the TCB linked list sent by each CPU interface unit according to a preset strategy, and sends the task scheduling plan to the task queue. The preset strategy is fixed priority or round-robin.

[0015] The task queue stores the base address of the TCB linked list sent by each CPU interface unit.

[0016] The channel selector sends the active channel identifier and the TCB linked list base address to the shared TCB acquisition unit to perform multi-channel task scheduling.

[0017] The shared TCB acquisition unit has a built-in prefetch cache, data reading logic, and next TCB address resolution unit;

[0018] The prefetch buffer sends the received active channel identifier and the current TCB list base address to the data reading logic, and obtains the next TCB list base address from the next TCB address parsing unit;

[0019] The next TCB address resolution unit generates the next TCB list base address based on the received current TCB list base address and sends it to the prefetch cache;

[0020] The data reading logic reads TCB data from system memory based on the received current TCB list base address and the next TCB list base address, and sends the read TCB data and the corresponding active channel identifier to the shared TCB parsing and execution unit.

[0021] The shared TCB parsing and execution unit includes a TCB parser, a main control state machine, and channel selection logic;

[0022] The TCB parser parses the TCB data passed in by the shared TCB acquisition unit, extracts control information and parameters, and generates parsing results;

[0023] Based on the parsing results, the main control state machine traverses the TCB linked list, generates a request for the base address of the next TCB linked list and sends it to the shared TCB acquisition unit, generates control instructions and sends them to the channel selection logic, and generates an interrupt request and sends it to the shared interrupt and status management unit.

[0024] The channel selection logic routes the extracted control information to the SPI physical layer interface and the DMA controller based on the received control commands. The control information includes SPI configuration, CS control, DMA request, and delay configuration in the operation sequence.

[0025] It also includes a DMA controller and an SPI physical layer interface;

[0026] Delay configuration in SPI configuration, CS control, and operation sequences is routed to the SPI physical layer interface; DMA requests are routed to the data stream in the DMA controller.

[0027] The shared interrupt and status management unit includes an event collection module, a status register, and an interrupt generator;

[0028] The event collection module collects events and errors reported by the shared TCB parsing and execution unit;

[0029] The interrupt generator generates interrupt requests corresponding to events and errors and passes them to the interrupt controller.

[0030] The status register feeds back events and errors to the CPU interface unit.

[0031] According to another aspect of the present invention, a chip is provided, including the SPI operation sequence execution system provided by the present invention.

[0032] In the technical solution of this invention, the SPI operation sequence execution system, based on a processor and system memory, includes: a TCB module and a TCB processing device; the TCB module includes multiple TCB linked lists, each TCB linked list includes several sequentially connected TCB tables, and each TCB table is TCB data composed of SPI operation sequences; the TCB processing device obtains each TCB linked list according to a preset strategy, parses the TCB data obtained from system memory, determines and executes the preset SPI operations in the TCB data, and notifies the processor through a single interrupt when all SPI operations are completed or a specific event occurs. This solves the problems of high processor load, limited real-time performance, large system overhead, and complex software drivers caused by deep involvement of processor software in operation sequence control in related technologies. After the processor submits the TCB linked list base address and task start information of multiple SPI operation sequences at once, it can realize the concurrent automated execution of multiple SPI operation sequences through hardware arbitration and shared core logic, completely hardware-based task scheduling for the execution of multiple SPI operation sequences, freeing the processor from complex coordination work, thereby significantly improving concurrency performance and real-time determinism at the system level, and simplifying software development.

[0033] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of an SPI operation sequence execution system provided in an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of a TCB linked list for an SPI operation sequence provided in an embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of the structure of an SPI operation sequence execution system provided in an embodiment of the present invention.

[0038] Figure 4 This is a schematic diagram of the structure of a CPU interface unit provided in an embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram of the structure of a channel arbitration scheduling unit provided in an embodiment of the present invention.

[0040] Figure 6 This is a schematic diagram of a shared TCB acquisition unit provided in an embodiment of the present invention.

[0041] Figure 7 This is a schematic diagram of a shared TCB parsing and execution unit provided in an embodiment of the present invention.

[0042] Figure 8 This is a schematic diagram of a shared interrupt and status management unit provided in an embodiment of the present invention.

[0043] Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of the present invention. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "target," "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising," "including," and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] Figure 1This is a schematic diagram of an SPI operation sequence execution system provided in an embodiment of the present invention. This embodiment is applicable to situations where an ordered sequence of operations, including CS control, command transmission and reception, data transmission and reception, mode changing, and / or delay, is executed between an MCU and its SPI peripheral via SPI communication. The SPI operation sequence execution system is located on the MCU. The SPI peripheral is an external device connected to the MCU via SPI. For example... Figure 1 As shown, the SPI operation sequence execution system 100, based on processor 101 and system memory 102, includes: a Transmission Control Block (TCB) module 103 and a TCB processing device 104. Its structure and function are described below.

[0047] The TCB module 103 includes multiple TCB linked lists, each TCB linked list includes several sequentially connected TCB tables, and each TCB table is TCB data composed of SPI operation sequences. The TCB processing device 104 obtains each TCB linked list according to a preset strategy, parses the TCB data obtained from the system memory 102, determines and executes the preset SPI operations in the TCB data, and notifies the processor 101 through a single interrupt when all SPI operations are completed or a specific event occurs.

[0048] Optionally, processor 101 is the processor in the MCU. System memory 102 is the system memory in the MCU. Each TCB linked list is stored in system memory 102. TCB processing device 104 can be a hardware module for acquiring, parsing, and sequentially executing multiple SPI operation sequences from system memory 102, so that the execution process of each SPI operation sequence runs asynchronously to processor 101. Each TCB linked list can be a linked list for storing control information of each operation in a specified SPI operation sequence. The number of TCB linked lists is greater than or equal to 2. An SPI operation sequence can refer to an ordered sequence of operations including CS control, command transmission and reception, data transmission and reception, mode change, and / or delay that needs to be performed between the MCU and its SPI peripheral via SPI communication. An SPI operation sequence can be composed of M operations concatenated. M is an integer greater than or equal to 2. Each operation needs to be executed sequentially, starting from the first operation in the SPI operation sequence. Each operation in the SPI operation sequence is CS control, command transmission and reception, data transmission and reception, mode change, delay, or short packet transmission and reception.

[0049] Optionally, CS control can refer to controlling the operation of the SPI peripheral via a chip select signal output by the MCU. CS control includes CS switching. CS switching can be the operation of controlling the SPI peripheral to switch communication modes according to the chip select signal. Performing a CS switch can mean sending data to the SPI peripheral to instruct it to switch communication modes according to the chip select signal.

[0050] Optionally, command transmission and reception can include command sending and command receiving. Command sending can be an operation of sending a specified control command to an SPI peripheral. Command receiving can be an operation of receiving a specified control command sent by an SPI peripheral. Executing command sending can refer to sending a specified control command to an SPI peripheral. Executing command receiving can refer to receiving a specified control command sent by an SPI peripheral.

[0051] Optionally, data transmission and reception can include data sending and data receiving. Data sending can be an operation of sending specified data to an SPI peripheral. Data receiving can be an operation of receiving specified data sent by an SPI peripheral. Performing data sending can refer to sending specified data to an SPI peripheral. Performing data receiving can refer to receiving specified data sent by an SPI peripheral.

[0052] Optionally, a mode change can be an operation that controls the SPI peripheral to change its operating mode. Performing a mode change can refer to sending data to the SPI peripheral to instruct it to change its operating mode.

[0053] Optionally, the delay can be an operation that controls the SPI peripheral to perform a delay. Performing a delay can refer to sending data to the SPI peripheral to instruct it to perform a delay.

[0054] Optionally, short packet transmission and reception can include short packet sending and short packet receiving. Short packet sending can be an operation of sending specified short packet data to an SPI peripheral. Short packet receiving can be an operation of receiving specified short packet data sent by an SPI peripheral. Performing short packet sending can refer to sending specified short packet data to an SPI peripheral. Performing short packet receiving can refer to receiving specified short packet data sent by an SPI peripheral.

[0055] Optional, such as Figure 2As shown, the TCB linked list consists of several sequentially linked TCB tables. Each TCB table can be a list storing control information for an operation in a specified SPI operation sequence. Each TCB table is a different list in system memory. The first TCB table (TCB0) in the TCB linked list stores the control information for the first operation in the specified SPI operation sequence. The second TCB table (TCB1) in the TCB linked list stores the control information for the second operation in the specified SPI operation sequence. The third TCB table (TCB2) in the TCB linked list stores the control information for the third operation in the specified SPI operation sequence. And so on, with the Mth TCB table in the TCB linked list storing the control information for the Mth operation in the specified SPI operation sequence. The control information of an operation can be information used to define the operation content. The operation content can refer to the specific steps involved in executing the operation. The operation control information consists of eight fields: Operation Type, DMA Control, Interrupt Control, CS Control, Data Transmission Information, Inline Data Field, SPI Communication Parameter, and Next TCB Pointer.

[0056] Optionally, the operation type can be information used to define the type of operation. The operation type is transmit, receive, or full-duplex. An operation type of transmit indicates that the operation is performed by sending data to the SPI peripheral. For example, CS switching, command transmission, data transmission, mode change, delay, and short packet transmission are operations performed by sending data to the SPI peripheral. An operation type of receive indicates that the operation is implemented by receiving data sent by the SPI peripheral. For example, command reception, data reception, and short packet reception are operations performed by sending data to the SPI peripheral. An operation type of full-duplex indicates that the operation is performed by both sending data to and receiving data sent by the SPI peripheral.

[0057] Optionally, DMA control can define whether data transfer between system memory and the SPI physical layer interface is required during the execution of an operation. DMA control can be used for DMA transfers via a "data buffer pointer" or for Programmed Input / Output (PIO) transfers via "embedded data fields".

[0058] Optionally, DMA control uses a "data buffer pointer" for DMA transfer, indicating that data needs to be moved between system memory and the SPI physical layer interface during operation. When the operation is performed by sending data to the SPI peripheral, the data buffer pointer in the "Data Transfer Information" field identifies the memory region in system memory that stores the data to be sent to the SPI peripheral, and the data length in the "Data Transfer Information" field is the number of bytes of data to be sent to the SPI peripheral. The DMA controller needs to move the data to be sent to the SPI peripheral from the memory region to the FIFO of the SPI physical layer interface for transmission based on the data buffer pointer and the data length. When the operation is performed by receiving data from the SPI peripheral, the data buffer pointer in the "Data Transfer Information" field identifies the memory region in system memory used to store the data sent by the SPI peripheral, and the data length in the "Data Transfer Information" field is the number of bytes of data sent by the SPI peripheral. After receiving the data sent by the SPI peripheral at the SPI physical layer interface, the DMA controller needs to move the data sent by the SPI peripheral from the SPI physical layer interface to the memory region based on the data buffer pointer and the data length. The memory region identifier can be information used to uniquely identify the memory region.

[0059] Optionally, DMA control uses the "Embedded Data Field" for programmable input / output (PIO) transfers, indicating that data movement between system memory and the SPI physical layer interface does not require the DMA controller during operation. When the operation is performed by sending data to the SPI peripheral, the "Embedded Data Field" contains the data to be sent to the SPI peripheral. This data needs to be directly sent to the SPI physical layer interface so that the SPI physical layer interface can then send the data to the SPI peripheral. When the operation is performed by receiving data from the SPI peripheral, the data buffer pointer in the "Data Transfer Information" field identifies the memory area in system memory used to store the data sent by the SPI peripheral, and the data length in the "Data Transfer Information" field is the number of bytes of data sent by the SPI peripheral. After receiving the data sent by the SPI peripheral, the SPI physical layer interface needs to move the data sent by the SPI peripheral to the memory area based on the data buffer pointer and the data length.

[0060] Optionally, interrupt control can be information used to indicate whether a corresponding interrupt signal needs to be generated to the processor after the operation is completed. Chip select control can be information used to define the behavior of the chip select signal before and after the operation.

[0061] Optionally, the data transmission information includes a data buffer pointer and a data length. When the operation is performed by sending data to the SPI peripheral, the data buffer pointer in the "Data Transmission Information" field identifies the memory area in system memory that stores the data to be sent to the SPI peripheral, and the data length in the "Data Transmission Information" field is the number of bytes of data to be sent to the SPI peripheral. When the operation is performed by receiving data sent by the SPI peripheral, the data buffer pointer in the "Data Transmission Information" field identifies the memory area in system memory used to store the data sent by the SPI peripheral, and the data length in the "Data Transmission Information" field is the number of bytes of data sent by the SPI peripheral.

[0062] Optionally, when the operation is performed by sending data to the SPI peripheral and the DMA control is set to use the "Embedded Data Field" for programmable input / output PIO transfers, the "Embedded Data Field" is the data to be sent to the SPI peripheral. When the operation is performed by receiving data from the SPI peripheral, or when the DMA control is set to use the "Data Buffer Pointer" for DMA transfers, the "Embedded Data Field" can be empty.

[0063] Optionally, the SPI communication parameters can be the communication parameters used when the SPI physical layer interface communicates with the SPI peripheral. The SPI communication parameters can include the mode, rate, bit width, and delay when the SPI physical layer interface communicates with the SPI peripheral.

[0064] Optionally, the next TCB pointer can refer to the identifier of the TCB table storing the control information for the next operation. The next operation is the operation following the previous operation in the SPI operation sequence. The next TCB pointer in the control information of the first operation is the identifier of the TCB table storing the control information for the second operation. The next TCB pointer in the control information of the second operation is the identifier of the TCB table storing the control information for the third operation. The next TCB pointer in the control information of the third operation is the identifier of the TCB table storing the control information for the fourth operation. And so on, the next TCB pointer in the control information of the (M-1)th operation is the identifier of the TCB table storing the control information for the Mth operation. The Mth operation is the last operation in the sequence, with no following operation, and the next TCB pointer in the control information of the (M-1)th operation is empty. The TCB tables are linked together through their stored next TCB pointers to form a TCB linked list.

[0065] Optionally, the base address of the TCB linked list can refer to the identification information of the TCB table that stores the control information of the first operation in the SPI operation sequence. The task start / stop information of the TCB linked list includes task start information. The task start information of the TCB linked list can be information used to indicate the start of the SPI operation sequence to which the TCB linked list belongs. The TCB linked list is the core link connecting the upper-layer software and the execution hardware. The processor statically defines a complete and complex SPI communication task by creating a TCB linked list linked by pointers in system memory. Each TCB linked list is an independent, self-contained task unit. The TCB processing device 104 locates these tasks through the list head pointer (the starting address of the TCB linked list) submitted by the processor, and autonomously and dynamically traverses the entire task chain at the hardware level using the "next TCB pointer" within the TCB linked list. This mechanism, which separates the "definition" and "execution" of tasks and allows multiple task chains to be traversed concurrently by the hardware, is key to achieving efficient multi-tasking automation.

[0066] Optional, such as Figure 3As shown, the SPI operation sequence execution system 300, based on processor 301 and system memory 302, includes a TCB module 303 and a TCB processing device 304. The SPI operation sequence execution system 300 is located on an MCU. Processor 301 is the processor in the MCU. System memory 302 is the system memory in the MCU. TCB module 303 includes multiple TCB linked lists. Each TCB linked list is stored in system memory 302. Processor 301 statically defines a complete and complex SPI communication task by creating TCB linked lists linked by pointers in system memory 302. Each TCB linked list is an independent, self-contained task unit. TCB processing device 304 is used to acquire, parse, and execute multiple SPI operation sequences sequentially from system memory 302, so that the execution process of each SPI operation sequence runs asynchronously to processor 301. TCB processing device 304 includes a CPU interface 31, a channel arbitration scheduling unit 32, a shared TCB acquisition unit 33, a shared TCB parsing and execution unit 34, and a shared interrupt and status management unit 35, connected in sequence. The CPU interface 31 includes various CPU interface units 311. The CPU interface units 311 in the SPI operation sequence execution system 300 are used for information transfer between the processor 301 and the TCB processing device 304. The SPI operation sequence execution system 300 also includes a DMA controller 305 in the MCU and multiple SPI physical layer interfaces 306. The DMA controller 305 in the SPI operation sequence execution system 300 can be a DMA controller in the MCU used for data transfer between system memory 302 and SPI physical layer interfaces 306. During data transfer, the DMA controller 305 reads data from system memory 302 and writes the data to the SPI physical layer interface 306. The SPI physical layer interface 306 in the SPI operation sequence execution system 300 is a hardware module in the MCU used for SPI communication with SPI peripherals. Data can be sent to and received from SPI peripherals through the SPI physical layer interface 306.

[0067] When processor 301 needs to execute multiple SPI operation sequences, it can simultaneously send the TCB (Tracking Block) base address and task startup information of each required SPI operation sequence to different CPU interface units 311, instructing the TCB processing device 304 to start executing each required SPI operation sequence. Then, processor 301 can continue executing other programs without synchronously waiting for the completion of each SPI operation sequence. The TCB data can refer to the TCB base address and task startup information of the TCB linked list. After receiving the TCB base address and task startup information sent by processor 301, each CPU interface unit 311 in the SPI operation sequence execution system 300 sends these information to the channel arbitration and scheduling unit 32. The channel arbitration and scheduling unit 32 selects the active channel corresponding to the TCB base address sent by each CPU interface unit 311 according to a preset strategy and sends the active channel identifier and TCB base address to the shared TCB acquisition unit 33. The shared TCB acquisition unit 33 reads TCB data sequentially from the system memory 302 based on the active channel identifier and TCB list base address provided by the channel arbitration scheduling unit 32, and sends the read TCB data and the corresponding active channel identifier to the shared TCB parsing and execution unit 34. The shared TCB parsing and execution unit 34 parses the TCB data passed from the shared TCB acquisition unit 33 and routes the extracted control information to the SPI physical layer interface 306 and the DMA controller 305. The shared interrupt and status management unit 35 collects events and errors reported by the shared TCB parsing and execution unit 34, generates interrupt requests corresponding to the events and errors, and passes them to the interrupt controller 307. The shared TCB parsing and execution unit 34 can send DMA requests to the DMA controller 305. The DMA controller 305 can send the DMA status to the shared TCB parsing and execution unit 34. The shared TCB parsing and execution unit 34 can perform SPI operations on the SPI physical layer interface 306. The SPI physical layer interface 306 can send SPI status or data to the shared TCB parsing and execution unit 34.

[0068] Optional, such as Figure 4As shown, the CPU interface unit 400 includes a control register 41, a status register 42, and a channel register group 43. The control register 41 sends the TCB linked list base address and task start / stop information sent by the processor 401 to the channel arbitration and scheduling unit 402; the status register 42 feeds back the channel operating status to the channel arbitration and scheduling unit 402; the channel register group 43 configures each SPI physical layer interface. The TCB linked list base address is the TCB linked list base address of the TCB linked list of the SPI operation sequence to be executed. The task start / stop information is either task start information or task stop information. The task stop information can be information used to indicate the cessation of SPI operation sequence execution. The channel status information can refer to information used to characterize the operating status of the SPI channel. The channel status information can include operation completion information and sequence completion information.

[0069] Optionally, when the processor 401 needs to execute multiple SPI operation sequences, the processor 401 can simultaneously send the TCB linked list base address and task start information of each required SPI operation sequence to different CPU interface units 411, instructing the TCB processing device to start executing each required SPI operation sequence. Then the processor 401 can continue to execute other programs without synchronously waiting for each SPI operation sequence to complete.

[0070] Optionally, the CPU interface unit 411 can be a hardware module for information transfer between the processor 401 and the TCB processing device. As a bridge between the processor 401 and the TCB processing device, the CPU interface unit 411 is responsible for receiving the TCB linked list base address and task start information submitted by the processor 401. The CPU interface unit 411 can provide an independent register set for each SPI channel, allowing the processor 401 to independently define multi-channel TCB linked list tasks. An SPI channel can refer to a channel for data transmission with SPI peripherals, constructed from SPI physical layer interfaces. Each SPI physical layer interface constitutes an SPI channel. The channel identifier of an SPI channel can be the identification information of the SPI physical layer interface constituting the SPI channel. The identification information of the SPI physical layer interface can be a numerical number used to uniquely identify the SPI physical layer interface. The task of an SPI channel can refer to the data transmission process performed through the SPI channel. The control register 41 can be a register used to obtain the TCB linked list base address and task start information sent by the processor 401 and send them to the channel arbitration and scheduling unit 402. Status register 42 is used to feed back the channel operating status to the channel arbitration and scheduling unit 402. Channel register group 43 is a register group used to configure each SPI physical layer interface. Processor 401 can send the TCB linked list base address and task start information to control register 41, thereby submitting the TCB linked list base address and task start information. Processor 401 can read channel status information from status register 42. After receiving the TCB linked list base address and task start information sent by processor 401 through control register 41, CPU interface unit 411 can send the TCB linked list base address and task start information sent by processor 401 to channel arbitration and scheduling unit 402. CPU interface unit 411 can provide status feedback through status register 42, feeding back the channel operating status to channel arbitration and scheduling unit 402. CPU interface unit 411 can configure the channel and configure each SPI physical layer interface through channel register group 43.

[0071] Optional, such as Figure 5As shown, the channel arbitration scheduling unit 500 incorporates an arbitrator 51, a task queue 52, and a channel selector 53. The channel arbitration scheduling unit 500 selects the active channel corresponding to the TCB linked list base address sent by each CPU interface unit 501 according to a preset strategy, and sends the active channel identifier and the TCB linked list base address to the shared TCB acquisition unit 502. For each TCB linked list base address, the SPI channel corresponding to the TCB linked list base address is the SPI channel used to execute the SPI operation sequence defined by the TCB linked list to which the TCB linked list base address belongs. The active channel identifier is the channel identifier of the SPI channel corresponding to the TCB linked list base address. The channel arbitration scheduling unit 500 is a hardware module used to select the active channel corresponding to the TCB linked list base address sent by each CPU interface unit 501 according to a preset strategy, and send the active channel identifier and the TCB linked list base address to the shared TCB acquisition unit 502.

[0072] Optionally, the arbitrator 51 generates a task scheduling plan corresponding to the TCB linked list base address sent by each CPU interface unit 501 according to a preset strategy, and sends the task scheduling plan to the task queue 52. The preset strategy is fixed priority or round-robin. The task scheduling plan corresponding to the TCB linked list base address sent by each CPU interface unit 501 can be selected based on the order of the active channels corresponding to the TCB linked list base addresses sent by each CPU interface unit 501. The arbitrator 51 is a hardware module used to generate a task scheduling plan corresponding to the TCB linked list base address sent by each CPU interface unit 501 according to fixed priority or round-robin, and send the task scheduling plan to the task queue 52.

[0073] Optionally, the arbitrator 51 generates a task scheduling plan corresponding to the TCB linked list base addresses sent by each CPU interface unit 501 according to a fixed priority, and sends the task scheduling plan to the task queue 52. This includes: the arbitrator 51 sorts the TCB linked list base addresses sent by each CPU interface unit 501 in descending order of priority value, obtaining a sorted sequence of the TCB linked list base addresses sent by each CPU interface unit 501; the sorted order of the TCB linked list base addresses sent by each CPU interface unit 501 in the sorted sequence is determined as the task scheduling plan corresponding to the TCB linked list base addresses sent by each CPU interface unit 501; the arbitrator 51 sends the sorted sequence of the TCB linked list base addresses sent by each CPU interface unit 501 to the task queue 52, thereby sending the task scheduling plan to the task queue 52. The priority value of each CPU interface unit 501 can be a pre-set value used to characterize the priority of each CPU interface unit 501. The larger the priority value of the CPU interface unit 501, the higher the priority of the CPU interface unit 501. The priority values ​​of each CPU interface unit 501 are different.

[0074] Optionally, the arbitrator 51 generates a task scheduling plan corresponding to the TCB linked list base addresses sent by each CPU interface unit 501 based on polling, and sends the task scheduling plan to the task queue 52. This includes: the arbitrator 51 sorts the TCB linked list base addresses sent by each CPU interface unit 501 in ascending order of their identification information, obtaining a sorted sequence of the TCB linked list base addresses sent by each CPU interface unit 501; determining the sorted order of the TCB linked list base addresses sent by each CPU interface unit 501 in the sorted sequence as the task scheduling plan corresponding to the TCB linked list base addresses sent by each CPU interface unit 501; and sending the sorted sequence of the TCB linked list base addresses sent by each CPU interface unit 501 to the task queue 52, thereby sending the task scheduling plan to the task queue 52. The identification information of each CPU interface unit 501 can be a pre-set numerical number used to identify each CPU interface unit 501. The identification information of each CPU interface unit 501 is different.

[0075] Optionally, task queue 52 stores the TCB linked list base addresses sent by each CPU interface unit 501. Task queue 52 can be a queue used to store the TCB linked list base addresses sent by each CPU interface unit 501.

[0076] Optionally, the channel selector 53 sends the active channel identifier and the TCB linked list base address to the shared TCB acquisition unit 502 to perform multi-channel task scheduling. The channel selector 53 may be a hardware module used to select the active channel corresponding to the TCB linked list base address sent by each CPU interface unit 501 according to the task scheduling plan after the arbitrator 51 sends the task scheduling plan to the task queue 52, and send the active channel identifier and the TCB linked list base address to the shared TCB acquisition unit 502. The channel selector 53 selects the active channel corresponding to the TCB list base address sent by each CPU interface unit 501 according to the task scheduling plan, and sends the active channel identifier and TCB list base address to the shared TCB acquisition unit 502. This may include: the channel selector 53 performs the following operation for each TCB list base address sent by each CPU interface unit 501 according to the sorting order of the TCB list base addresses in the sorting sequence: selects an idle SPI channel from among the idle SPI channels as the active channel corresponding to the TCB list base address sent by the CPU interface unit 501, and sends the active channel identifier and TCB list base address to the shared TCB acquisition unit 502. This ensures multi-channel task scheduling at the hardware level. An idle SPI channel may refer to an SPI channel without a corresponding TCB list.

[0077] Optional, such as Figure 6 As shown, the shared TCB acquisition unit 600 includes a prefetch cache 61, data reading logic 62, and a next TCB list base address parsing unit 63. The prefetch cache 61 sends the received active channel identifier and the current TCB list base address to the data reading logic 62, and obtains the next TCB list base address from the next TCB list base address parsing unit 63. The next TCB list base address parsing unit 63 generates the next TCB list base address based on the received current TCB list base address and sends it to the prefetch cache 61. The data reading logic 62 reads TCB data from the system memory 602 based on the received current TCB list base address and the next TCB list base address, and sends the read TCB data and the corresponding active channel identifier to the shared TCB parsing and execution unit 603. TCB data refers to the control information in the TCB table identified by the received current TCB list base address or the next TCB list base address.

[0078] Optionally, the shared TCB acquisition unit 600 is a hardware module used to sequentially read TCB data from system memory 602 based on the active channel identifier and TCB list base address provided by the channel arbitration scheduling unit 601. The next TCB list base address can refer to the identifier information of the TCB table storing the next TCB data to be read. The shared TCB acquisition unit 600 improves efficiency through a built-in prefetch cache 61 and dynamically traverses the TCB list through the "next TCB pointer" inside the TCB list, passing the active channel identifier and the read TCB data to the shared TCB parsing and execution unit 603. The prefetch cache 61 is a prefetch buffer or a cache with a preset capacity. The prefetch cache 61 is a hardware module used to send the active channel identifier and the current TCB list base address provided by the channel arbitration scheduling unit 601, and the next TCB list base address generated by the next TCB list base address parsing unit 63 to the data reading logic 62. The next TCB list base address parsing unit 63 is a hardware module used to generate the next TCB list base address and send it to the prefetch cache 61. The data reading logic 62 is a hardware module used to read TCB data from the system memory 602 via the system bus based on the current TCB list base address and the next TCB list base address, and send the read TCB data and the corresponding active channel identifier to the shared TCB parsing and execution unit 603.

[0079] Optionally, the prefetch buffer 61 can send the active channel identifier and TCB list base address provided by the channel arbitration scheduling unit 601, received by the shared TCB acquisition unit 600, to the data reading logic 62. The data reading logic 62 can read the TCB data in the TCB table to which the received TCB list base address belongs, thereby reading the control information of the first operation in the SPI operation sequence from the TCB list of the SPI operation sequence stored in the system memory 602. Then, it sends the read TCB data and the corresponding active channel identifier to the shared TCB parsing and execution unit 603, thereby instructing the shared TCB parsing and execution unit 603 to execute the first operation based on the control information of the first operation and the corresponding active channel identifier.

[0080] Optionally, data reading logic 62 can send the received TCB linked list base address to the next TCB linked list base address parsing unit 63. The next TCB linked list base address parsing unit 63 can read the next TCB pointer from the TCB data in the TCB table to which the received TCB linked list base address belongs, thereby generating the next TCB linked list base address. The next TCB linked list base address parsing unit 63 can then send the generated next TCB linked list base address to the prefetch cache 61. The prefetch cache 61 then sends the generated next TCB linked list base address to data reading logic 62. Data reading logic 62 can read TCB data from the base address of the next TCB linked list based on the generated base address of the next TCB linked list, thereby reading the control information of the next operation to be executed in the SPI operation sequence from the TCB linked list of the SPI operation sequence stored in system memory 602, and then sending the read TCB data and the corresponding active channel identifier to the shared TCB parsing and execution unit 603, thereby instructing the TCB parsing and execution unit 602 to execute the next operation to be executed based on the control information of the next operation to be executed and the corresponding active channel identifier.

[0081] Optionally, the next TCB list base address resolution unit 63 may determine that there is no next TCB list address after detecting that the control information in the TCB table to which the TCB list base address belongs does not contain the next TCB pointer, and the list traversal process for the active channel identifier and TCB list base address provided by the channel arbitration scheduling unit 601 this time ends.

[0082] Optional, such as Figure 7 As shown, the shared TCB parsing and execution unit 700 includes a TCB parser 71, a main control state machine 72, and channel selection logic 73. The TCB parser 71 parses the TCB data input from the shared TCB acquisition unit 701, extracts control information and parameters, and generates a parsing result. Based on the parsing result, the main control state machine 72 traverses the TCB linked list, generates a request for the next TCB linked list base address, sends it to the shared TCB acquisition unit 701, generates control instructions, sends them to the channel selection logic 73, and generates interrupt requests, sends them to the shared interrupt and status management unit 702. The channel selection logic 73, based on the received control instructions, routes the extracted control information to the SPI physical layer interface 703 and the DMA controller 704. The control information includes SPI configuration, CS control, DMA requests, and delay configurations in the operation sequence. The SPI configuration, CS control, and delay configurations in the operation sequence are routed to the SPI physical layer interface 703. The DMA request is routed to the data stream in the DMA controller 704.

[0083] Optionally, the shared TCB parsing and execution unit 700 is a shared execution core. The shared TCB parsing and execution unit 700 is a hardware module used to parse the TCB data input from the shared TCB acquisition unit 701, extract control information and parameters, and execute the operation content defined by the control information, thereby executing the operation. The TCB parser 71 is a hardware module used to extract control information and parameters from the TCB data. Parameters can refer to specific parameters in the control information used to define the operation content. After receiving the TCB data and active channel identifier input from the shared TCB acquisition unit 701, the TCB parser 71 parses the TCB data, extracts control information and parameters from the TCB data, and generates a parsing result. The parsing result is the control information and parameters extracted from the TCB data. The TCB parser 71 sends the parsing result and active channel identifier to the main control state machine 72. The main control state machine 72 can be a hardware module used to determine the operation content defined by the control information based on the control information and parameters, and generate control instructions for driving the channel selection logic 73 to execute the operation content through the DMA data stream and SPI physical layer interface 703 corresponding to the active channel identifier.

[0084] Optionally, after receiving the parsing result and the active channel identifier, the main control state machine 72 can determine the operation content defined by the control information based on the parsing result, determine the DMA data stream and SPI physical layer interface 703 corresponding to the active channel identifier, and generate control instructions for driving the channel selection logic 73 to execute the operation content through the DMA data stream and SPI physical layer interface 703 corresponding to the active channel identifier. The SPI physical layer interface 703 corresponding to the active channel identifier is the SPI physical layer interface 703 to which the active channel identifier belongs. The DMA data stream corresponding to the active channel identifier is the DMA data stream corresponding to the SPI physical layer interface 703 to which the active channel identifier belongs. The generated control instructions can be instructions generated based on the determined operation content and the DMA data stream and SPI physical layer interface 703 corresponding to the active channel identifier, used to drive the channel selection logic 73 to execute the operation content through the DMA data stream and SPI physical layer interface 703 corresponding to the active channel identifier. The DMA data stream in the DMA controller 704 can send the DMA task status to the main control state machine 72 through the connection with the main control state machine 72. The DMA task status is either DMA task completion information or DMA task error information.

[0085] Optionally, after the main control state machine 72 determines the operation to which the completed operation content belongs, generates operation completion information corresponding to the operation, and sends the operation completion information and the active channel identifier as the next TCB list base address request to the shared TCB acquisition unit 701.

[0086] Optionally, the main control state machine 72 can generate error information corresponding to the operation when an error occurs during the execution of the operation content by the channel selection logic 73, and send the error information and the active channel identifier to the shared interrupt and status management unit 702. The error information corresponding to the operation can be information used to characterize the error that occurred during the execution of the operation content.

[0087] Optionally, the master control state machine 72 can determine that the operation to which the operation control information belongs is the last operation in the sequence when it detects that the operation control information does not include the next TCB pointer. Then, after determining that the channel selection logic 73 has completed the operation content of the last operation, it sends the sequence completion information and the active channel identifier to the shared interrupt and status management unit 702. The sequence completion information can be used to indicate that the SPI operation sequence has been completed.

[0088] Optionally, the main control state machine 72 can send an interrupt request to the shared interrupt and status management unit 702 by sending sequence completion information and active channel identifier to the shared interrupt and status management unit 702, or by sending error information and active channel identifier to the shared interrupt and status management unit 702. The main control state machine 72 can dynamically track the execution progress of the TCB linked list to ensure parallel processing of multi-channel tasks.

[0089] Optionally, the channel selection logic 73 is a hardware module shared within the TCB parsing and execution unit 700, used to execute operations via the DMA data stream specified by control instructions and the SPI physical layer interface 703. The channel selection logic 73 can execute operations defined by control information, including SPI configuration, CS control, DMA requests, and delay configurations in the operation sequence, through the DMA data stream corresponding to the active channel identifier and the SPI physical layer interface 703, based on the received control instructions. SPI configuration can be information used to instruct the SPI physical layer interface 703 to perform configuration. CS control can be information used to instruct the SPI physical layer interface 703 to control the SPI peripheral via a chip select signal output to the SPI peripheral. DMA requests can be information used to instruct the DMA data stream in the DMA controller 704 to perform data transfer. Delay configuration can be information used to instruct the SPI physical layer interface 703 to control the SPI peripheral to perform a delay. The channel selection logic 73 can perform SPI configuration, CS control, and delay configuration definition operations through the SPI physical layer interface 703 corresponding to the active channel identifier, thereby routing the delay configuration in the SPI configuration, CS control, and operation sequence to the SPI physical layer interface 703. The channel selection logic 73 can perform DMA request definition operations through the DMA data stream corresponding to the active channel identifier, thereby routing the DMA request to the data stream in the DMA controller 704.

[0090] Optional, such as Figure 8 As shown, the shared interrupt and status management unit 800 includes an event collection module 81, a status register 82, and an interrupt generator 83; the event collection module 81 collects events and errors reported by the shared TCB parsing and execution unit 801; the interrupt generator 83 generates interrupt requests corresponding to the events and errors and passes them to the interrupt controller 802; the status register 82 feeds back the events and errors to the CPU interface unit 803.

[0091] Optionally, the events and errors reported by the shared TCB parsing and execution unit 801 can refer to sequence completion information and error information sent by the shared TCB parsing and execution unit 801. The shared interrupt and status management unit 800 is a hardware module used to generate interrupt requests corresponding to the active channel identifiers of the collected sequence completion information or error information and to feed back the events and errors to the CPU interface unit 803. The active channel identifier for sequence completion information is the active channel identifier received along with the sequence completion information. The active channel identifier for error information is the active channel identifier received along with the error information. The interrupt request corresponding to the active channel identifier can be an interrupt signal indicating that a sequence completion event or error event has occurred on the SPI channel to which the active channel identifier belongs. The event collection module 81 can be a hardware module used to collect the events and errors reported by the shared TCB parsing and execution unit 801. The interrupt generator 83 can be a hardware module used to generate interrupt requests corresponding to the events and errors, and the status register 82 can be a register used to feed back the events and errors to the CPU interface unit 803.

[0092] Optionally, the event collection module 81 can trigger an interrupt after collecting the sequence completion information and active channel identifier sent by the shared TCB parsing and execution unit 801. Specifically, it triggers the interrupt generator 83 to generate an interrupt request corresponding to the active channel identifier and sends this request to the interrupt controller 802 in the processor. This generates an interrupt request corresponding to the active channel identifier for the processor, notifying it of the sequence completion event and ensuring accurate notification of multi-channel TCB linked list task completion events. The event collection module 81 can store the collected sequence completion information and active channel identifier in the status register 82, thereby updating the status register 82. The status register 82 can provide status feedback to the CPU interface unit 803, sending the newly stored sequence completion information and active channel identifier to the CPU interface unit 803.

[0093] Optionally, the event collection module 81 can trigger an interrupt after collecting error information and active channel identifiers sent by the shared TCB parsing and execution unit 801. Specifically, it triggers the interrupt generator 83 to generate an interrupt request corresponding to the active channel identifier and sends this request to the interrupt controller 802 in the processor. This generates an interrupt request corresponding to the active channel identifier for the processor, notifying it via the interrupt request when an error information event occurs, ensuring accurate notification of abnormal events. The event collection module 81 can store the collected error information and active channel identifiers in the status register 82, thereby updating the status register 82. The status register 82 can provide status feedback to the CPU interface unit 803, sending the newly stored error information and active channel identifiers to the CPU interface unit 803.

[0094] In the technical solution of this invention, the SPI operation sequence execution system, based on a processor and system memory, includes: a TCB module and a TCB processing device; the TCB module includes multiple TCB linked lists, each TCB linked list includes several sequentially connected TCB tables, and each TCB table is TCB data composed of SPI operation sequences; the TCB processing device obtains each TCB linked list according to a preset strategy, parses the TCB data obtained from system memory, determines and executes the preset SPI operations in the TCB data, and notifies the processor through a single interrupt when all SPI operations are completed or a specific event occurs. This solves the problems of high processor load, limited real-time performance, large system overhead, and complex software drivers caused by deep involvement of processor software in operation sequence control in related technologies. After the processor submits the TCB linked list base address and task start information of multiple SPI operation sequences at once, it can realize the concurrent automated execution of multiple SPI operation sequences through hardware arbitration and shared core logic, completely hardware-based task scheduling for the execution of multiple SPI operation sequences, freeing the processor from complex coordination work, thereby significantly improving concurrency performance and real-time determinism at the system level, and simplifying software development.

[0095] In the technical solution of this invention embodiment, the SPI operation sequence execution system achieves concurrent execution of multiple SPI communication tasks on a macroscopic level by rapidly switching between channels and time-division multiplexing the core logic of the shared TCB acquisition unit, the shared TCB parsing and execution unit, and the shared interrupt and status management unit, effectively balancing hardware resource consumption and multi-task processing capabilities.

[0096] The technical solution of this invention allows the processor to submit all tasks at once and completely escape management. It can autonomously schedule and concurrently execute tasks on each channel through the hardware arbitrator built into the SPI operation sequence execution system, efficiently reuse core processing logic, and fundamentally hardwareize multi-task scheduling and sequence control. This upgrades the automation level from a single task to multi-task concurrency, achieving a fundamental leap in system efficiency and real-time performance.

[0097] The technical solution of this invention adopts a multi-channel architecture of "shared core, hardware scheduling". This architecture provides an independent CPU task interface for each SPI channel, and a central hardware arbitrator schedules tasks according to a preset strategy. The arbitrator directs a shared execution core, which is responsible for acquiring and parsing the TCB (Transaction Control Block), and precisely sending control commands to the target SPI physical interface through its internal channel routing logic. This method of fully hardware-based task scheduling and execution is a key technical means to solve the multi-channel concurrency bottleneck.

[0098] Figure 9 This is a schematic diagram of a chip structure provided in an embodiment of the present invention. Figure 9 As shown, chip 90 includes an SPI operation sequence execution system 900. The SPI operation sequence execution system 900 is disposed in chip 90.

[0099] The SPI operation sequence execution system 900, based on processor 901 and system memory 902, includes: TCB module 903 and TCB processing device 904;

[0100] The TCB module 903 includes multiple TCB linked lists, each TCB linked list includes several TCB tables connected in sequence, and each TCB table is TCB data composed of SPI operation sequences.

[0101] The TCB processing device 904 obtains each TCB linked list according to a preset strategy, parses the TCB data obtained from the system memory 902, determines and executes the preset SPI operation in the TCB data, and notifies the processor 901 through a single interrupt when all SPI operations are completed or a specific event occurs.

[0102] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0103] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An SPI operation sequence execution system, based on a processor and system memory, characterized in that, include: TCB module and TCB processing unit; The TCB module includes multiple TCB linked lists, each TCB linked list includes several TCB tables connected in sequence, and each TCB table is TCB data composed of SPI operation sequences. The TCB processing device obtains each TCB linked list according to a preset strategy, parses the TCB data obtained from the system memory, determines and executes the preset SPI operations in the TCB data, and notifies the processor through a single interrupt when all SPI operations are completed or a specific event occurs.

2. The SPI operation sequence execution system according to claim 1, characterized in that, The TCB processing unit includes a CPU interface, a channel arbitration and scheduling unit, a shared TCB acquisition unit, a shared TCB parsing and execution unit, and a shared interrupt and status management unit connected in sequence; wherein, the CPU interface includes various CPU interface units, and the CPU interface unit includes a control register, a status register, and a channel register group; The control register sends the TCB linked list base address and task start / stop information sent by the processor to the channel arbitration scheduling unit; The status register feeds back the channel's operating status to the channel arbitration and scheduling unit; The channel register group configures each SPI physical layer interface.

3. The SPI operation sequence execution system according to claim 2, characterized in that, The channel arbitration scheduling unit has a built-in arbitrator, task queue and channel selector. The channel arbitration scheduling unit selects the active channel corresponding to the TCB linked list base address sent by each CPU interface unit according to the preset strategy, and sends the active channel identifier and TCB linked list base address to the shared TCB acquisition unit.

4. The SPI operation sequence execution system according to claim 3, characterized in that, The arbitrator generates a task scheduling plan corresponding to the base address of the TCB linked list sent by each CPU interface unit according to a preset strategy, and sends the task scheduling plan to the task queue. The preset strategy is fixed priority or round-robin.

5. The SPI operation sequence execution system according to claim 4, characterized in that, The task queue stores the base address of the TCB linked list sent by each CPU interface unit.

6. The SPI operation sequence execution system according to claim 5, characterized in that, The channel selector sends the active channel identifier and the TCB linked list base address to the shared TCB acquisition unit to perform multi-channel task scheduling.

7. The SPI operation sequence execution system according to claim 6, characterized in that, The shared TCB acquisition unit has a built-in prefetch cache, data reading logic, and next TCB address resolution unit; The prefetch buffer sends the received active channel identifier and the current TCB list base address to the data reading logic, and obtains the next TCB list base address from the next TCB address parsing unit; The next TCB address resolution unit generates the next TCB list base address based on the received current TCB list base address and sends it to the prefetch cache; The data reading logic reads TCB data from system memory based on the received current TCB list base address and the next TCB list base address, and sends the read TCB data and the corresponding active channel identifier to the shared TCB parsing and execution unit.

8. The SPI operation sequence execution system according to claim 7, characterized in that, The shared TCB parsing and execution unit includes a TCB parser, a main control state machine, and channel selection logic; The TCB parser parses the TCB data passed in by the shared TCB acquisition unit, extracts control information and parameters, and generates parsing results; Based on the parsing results, the main control state machine traverses the TCB linked list, generates a request for the base address of the next TCB linked list and sends it to the shared TCB acquisition unit, generates control instructions and sends them to the channel selection logic, and generates an interrupt request and sends it to the shared interrupt and status management unit. The channel selection logic routes the extracted control information to the SPI physical layer interface and the DMA controller based on the received control commands. The control information includes SPI configuration, CS control, DMA request, and delay configuration in the operation sequence.

9. The SPI operation sequence execution system according to claim 8, characterized in that, It also includes a DMA controller and an SPI physical layer interface; Delay configuration in SPI configuration, CS control, and operation sequences is routed to the SPI physical layer interface; DMA requests are routed to the data stream in the DMA controller.

10. The SPI operation sequence execution system according to claim 9, characterized in that, The shared interrupt and status management unit includes an event collection module, a status register, and an interrupt generator; The event collection module collects events and errors reported by the shared TCB parsing and execution unit; The interrupt generator generates interrupt requests corresponding to events and errors and passes them to the interrupt controller. The status register feeds back events and errors to the CPU interface unit.

11. A chip, characterized in that, Including the SPI operation sequence execution system as described in any one of claims 1-10.

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