SOC (system on chip) multi-access cache subsystem based on TDM (time division multiplexing) technology
By implementing point-to-point connections and time-division multiplexing between access sources and cache points in the SOC caching system using TDM technology, the problems of access congestion and resource consumption in traditional SOC caching systems are solved, and access efficiency and system scalability are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-25
- Publication Date
- 2026-04-07
AI Technical Summary
Traditional SOC caching systems rely on bus interconnection, which leads to access congestion, high data link latency, and high resource consumption. Furthermore, the lack of clear priority definition between different access sources increases system complexity and resource consumption.
The SOC multi-access cache subsystem based on TDM technology connects the access source to the cache point-to-point, manages access using TDM time slot control rules, abandons bus interconnection, realizes point-to-point connection and time-division multiplexing of the access source, and rationally classifies the access source to optimize resource utilization.
Improve the access efficiency of the caching system, reduce access latency and resource consumption, optimize the bandwidth requirements and resource consumption of the access source, and enhance the system's flexibility and scalability.
Smart Images
Figure CN121807738A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data storage technology, and in particular to a SOC multi-access cache subsystem based on TDM technology. Background Technology
[0002] Currently, SOC systems are becoming increasingly large. Taking storage controller SOC chips as an example, they integrate various functional IPs, such as CPU, PCIe, NVMe, SATA, and NAND. As the data exchange center for these IPs, the pressure on the system's shared cache system is also increasing, requiring both high access bandwidth and lower access latency.
[0003] Current traditional SOC caching systems employ a relatively rigid bus interconnect architecture, requiring bus interconnect support, and the priority levels between different access sources are not clearly defined, exhibiting the following significant drawbacks: 1. Access congestion: When multiple access sources access the bus simultaneously, the bus becomes a bottleneck, leading to increased data transmission latency; 2. High resource consumption: The bus itself consumes a lot of chip resources; and the traditional cache subsystem + bus interconnect architecture will add redundant design that other access sources do not need in the interconnect due to the needs of a specific access source, which greatly increases the difficulty of system construction and consumes more resources and power. Summary of the Invention
[0004] This application provides a SOC multi-access cache subsystem based on TDM (Time Division Multiplex) technology, which solves the problems of access congestion, high data link latency, and high resource consumption caused by the reliance on bus interconnection in traditional SOC cache systems. By using TDM technology, it realizes point-to-point connection between the access source and the cache, gets rid of bus dependence, avoids congestion, reduces latency, and reduces resource consumption.
[0005] This application provides a SOC multiple access cache subsystem based on TDM technology, including: an access source module, an address decoding preprocessing module, a TDM control module, and an SRAM group module; The access source module contains multiple access sources, and the SRAM group module contains multiple SRAM banks. The access source initiates a read / write access request for the cache (SRAM). The address decoding preprocessing module converts the source access logical address into an address format that is easy for the TDM control module to manage. The TDM control module manages and schedules the cache access of each access source based on the predetermined TDM time slot control rules, further decomposes the cache access of each access source into access to each SRAM bank, and performs cyclic access within and between banks according to the time slot access order of each SRAM bank, thereby realizing point-to-point connection between each access source and the cache.
[0006] The beneficial effects of the above embodiments are as follows: In this SOC multi-access cache subsystem, when an access source initiates a read / write access to the cache (SRAM), the access passes through the address decoding preprocessing module, which converts the system logical address into an address format that is easy for the TDM control module to manage. The TDM control module stores data in the SRAM or reads it back from the SRAM in a specific time slot according to predetermined time slot control rules. This SOC multi-access cache subsystem eliminates the interconnection network in traditional SOC systems through time-division multiplexing (TDM) technology, allowing the access source and cache to connect point-to-point. Different access sources access each other at different times, which greatly improves the continuous high bandwidth capability of the cache subsystem, significantly reduces data link transmission latency, and significantly reduces the resource consumption of the cache subsystem. This achieves the effects of getting rid of dependence on traditional bus interconnection, avoiding congestion from multiple access sources, reducing data link latency, and reducing resource consumption.
[0007] Based on the above embodiments, this application can be further improved as follows: In one embodiment of this application, the access sources are at least divided into three categories: Category 1: Access sources with high and continuous bandwidth requirements occupy a TDM time slot on their own; Category 2: Access sources with high bandwidth but no continuous bandwidth requirements share a TDM time slot through a front-end arbitrator; The third category: Access sources without high bandwidth requirements are divided into high priority (low latency requirements) and low priority (high latency tolerance), and are inserted into TDM time slots. Technical effect: By rationally classifying access sources, balancing bandwidth requirements and resource consumption, the number of TDM time slots is reduced, thereby reducing the number of SRAM banks and thus reducing the complexity of TDM control logic.
[0008] In one embodiment of this application, in the second type of access source, the arbitrator allocates time slot usage rights according to the real-time demand of the access source; in the third type of access source, high-priority access sources preferentially fill in idle time slots, while low-priority access sources wait for idle time slots before accessing. Technical effects: Optimizes resource utilization, meets diverse access needs, and improves system flexibility.
[0009] In one embodiment of this application, the address decoding preprocessing module includes an address decoding unit and a data caching unit; the address decoding unit is used to convert the source access logical address into a bank number and a bank entry; the data caching unit is used to cache data that is not aligned with the target SRAM bank. Technical advantages: The address format, which is a combination of bank number and entry number, is easily managed by the TDM control module; the data caching unit implements address-adaptive TDM scheduling, solving the problem of mismatch between access timing and the target SRAM bank, and ensuring data continuity.
[0010] In one embodiment of this application, the decoding rule of the address decoding unit is as follows: The bank number accessed is: A[log2N + log2W - 1 : log2W]; The bank entry accessed: A[P - 1 : log2N + log2W]; Where A is the logical address, N is the number of SRAM banks, W is the data width of the SRAM, and P is the address width.
[0011] Technical benefits: Precisely locates SRAM banks and entries, supports continuous address access, and improves bandwidth utilization.
[0012] In one embodiment of this application, when the currently allowed SRAM bank is inconsistent with the target bank, the data caching unit caches the misaligned data to be written to the target bank in the next time slot. Technical effect: Ensures complete storage of misaligned data, avoids data loss or errors, and improves access reliability.
[0013] In one embodiment of this application, the number of SRAM banks in the SRAM group module is equal to the number of TDM time slots, and each SRAM bank has an independent access interface. Technical effect: This ensures that each access source participating in TDM time slot control can access the SRAM in every time slot, achieving high bandwidth and continuous bandwidth requirements, while reducing the number of SRAM banks and avoiding congestion in the chip's back-end layout and routing.
[0014] In one embodiment of this application, the number of time slots in the TDM control module is dynamically adjusted according to the number of access sources, and the number of SRAM banks in the SRAM group module is adjusted synchronously with the number of TDM time slots. Technical benefits: Adapts to different access source scales, improves system scalability, and reduces design complexity.
[0015] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: 1. In this SOC multi-access caching subsystem, the application of TDM (Transmission Management Module) eliminates the reliance on traditional interconnect buses for data interaction between the caching system and the access sources, thus avoiding the significant resource consumption associated with the bus itself. Point-to-point direct access to the cache by each access source avoids access congestion and reduces access latency, improving access efficiency in multi-access source caching systems and ensuring the requirements for continuous high bandwidth and low latency.
[0016] 2. In this SOC multi-access caching subsystem, by reasonably classifying access sources, balancing bandwidth demand and resource consumption, reducing the number of TDM time slots and thus the number of SRAM banks, the complexity of TDM control logic is reduced.
[0017] 3. In this SOC multi-access cache subsystem, the data cache unit implements address adaptation TDM scheduling to solve the problem of mismatch between access timing and target SRAM bank, ensuring data continuity and reliability.
[0018] 4. In this SOC multi-access cache subsystem, the number of SRAM banks and the number of TDM time slots in the SRAM group module can be dynamically adjusted synchronously to adapt to different access source scales, improve system scalability, and reduce design complexity. Attached Figure Description
[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.
[0020] Figure 1 This is a schematic diagram of the structure of a SOC multi-access cache subsystem based on TDM technology in an embodiment of this application; Figure 2 This is a schematic diagram of TDM slot access control in an embodiment of this application; Figure 3 This is a schematic diagram of SRAM address decoding in an embodiment of this application; Figure 4 This is a schematic diagram of the access node and data cache in the embodiments of this application; Figure 5 This is a schematic diagram of continuous address access to access source 1 in an embodiment of this application. Detailed Implementation
[0021] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.
[0022] Example: like Figure 1 As shown, a SOC multi-access cache subsystem based on TDM technology includes: an access source module, an address dispatch module, a TDM control module, and an SRAM bank group module. The access source module contains multiple access sources. The access sources interact with the address decoding preprocessing module through a general interface (acc inf) to initiate read / write access requests for the cache (SRAM). The specific interface form is set according to the actual situation, and different access sources are allowed to have different acc inf.
[0023] Access sources can be divided into three categories: The first category consists of access sources with high and continuous bandwidth requirements. These access sources participate in TDM time slot control and occupy a TDM time slot independently, such as... Figure 1 In the context of access source j+1 and access source N+j, the number of first-type access sources is N-1. The second type is access sources with high bandwidth but no continuous bandwidth requirements. These access sources participate in TDM time slot control, but considering that they have no continuous bandwidth requirements, they can share a TDM time slot with other similar or mutually exclusive access sources through a pre-arbiter, as shown in access source 1-j in the figure. The number of access sources in the second type is j. The third category consists of access sources with no high bandwidth or continuous bandwidth requirements. These access sources can be further divided into high-priority access sources and low-priority access sources. Those with low access latency requirements can be set as high-priority access sources, and those with no access latency requirements can be set as low-priority access sources. The third category of access sources participates in TDM slot control but does not occupy any TDM slots on its own. It is a type of interstitial access. High-priority access sources will use any TDM slot of any SRAM bank to complete the access based on the logical access address. Low-priority access sources will wait for the corresponding TDM slot to become idle before using the slot. The number of third-priority access sources is k.
[0024] The processing methods for the second and third types of access sources can reduce the number of TDM time slots, reduce the complexity of TDM control logic, reduce the number of SRAM banks, and reduce the pressure on back-end layout and routing.
[0025] The address decoding preprocessing module includes an address decoding unit. This unit decodes the source access logical address into an address format suitable for TDM management, namely a combination of bank number and entry number, and interacts with the TDM control module via the TDM interface (TDM INF) to complete logical and data exchange. Figure 1 The description of the TDM interface (tdm inf 1) is shown in Table 1 below:
[0026] The bank number that can be accessed in a given time slot is issued by the TDM module and controlled by TDM. However, each access request from the access source cannot be perfectly aligned with the target bank number. In an access request, the misaligned data needs to be cached and waited for the next round of TDM bank access. Therefore, the address decoding preprocessing module also includes a data caching unit, thus having a certain amount of caching capacity to cache the data of the misaligned target SRAM bank.
[0027] The TDM control module is used for TDM time slot access management, priority level management, and SRAM bank access bus switching. Based on predetermined TDM time slot control rules, the TDM control module manages and schedules cache access from each access source, further breaking down cache access into accesses to each SRAM bank. It then performs intra-bank and inter-bank cyclic accesses according to the time slot access order of each SRAM bank, achieving point-to-point connections between each access source and the cache. Each TDM time slot requires an address decoding preprocessing module to interact with the TDM control module.
[0028] Circular access involves two aspects: 1. A single access source circularly accesses multiple banks; 2. Multiple access sources circularly access a single bank. The first aspect is achieved through the association of TDM time slot access order between adjacent SRAM banks (address contiguity); the second aspect is achieved through the access order of TDM time slots within each SRAM bank. The combination of these two aspects ensures that each access source accesses the cache simultaneously (from different SRAM banks).
[0029] TDM slot access management applies to all SRAM banks. Each SRAM bank has the same number of TDM slots, but the TDM slot control is independent for each SRAM bank. For example... Figure 2 As shown, by setting the SRAM bank and its TDM timeslot number N=8, it can be seen that the timeslot control between different SRAM banks is correlated, which satisfies the requirement of continuous address access.
[0030] TDM slot access management also requires that the number of SRAM banks be greater than or equal to the number of TDM slots to ensure that each slot has at least one SRAM bank that can be accessed. Similarly, there is a certain correspondence between the number of TDM slots and the number of access sources. If there are no second or third type access sources, then the number of access sources is the same as the number of TDM slots, which ensures that each slot has at least one access source.
[0031] The SRAM group module consists of N SRAM banks, the number of which is determined by the number of TDM time slots. Access to each bank is directly controlled by the TDM control module. Each SRAM bank has an independent access interface (bank acc inf), and the description of the SRAM access interface is shown in Table 2 below:
[0032] The following example uses N=8, meaning the number of access sources is 8+j+k-1, and the number of SRAM banks and TDM slots is 8. The description further elaborates on this scheme: 1. Setting the number of TDM time slots in the caching subsystem: The number of TDM slots in each SRAM bank within the TMD control module is dynamically adjusted based on the number of access sources. The basic concept of TDM technology can be simply described as allowing only specific sequences to pass through a specific slot, requiring each slot to have exactly one access source. In this example, the number of TDM slots in each SRAM bank is set to 8, resulting in 7+j+k access sources. Seven first-type access sources each occupy one TDM slot, j second-type access sources share one TDM slot via an arbitrator, and k third-type access sources do not occupy any TDM slots. The number of TDM slots directly determines the logical complexity of the TMD control module. By rationally classifying different access sources according to actual needs and balancing access requirements with the number of TDM slots, the logical complexity of the TMD control module can be reduced.
[0033] 2. Setting the number of SRAM banks in the cache subsystem: The number of SRAM banks in the SRAM group module is dynamically adjusted based on the number of TDM time slots.
[0034] This subsystem is applied to memory control SoC chips with high bandwidth requirements. To ensure high and continuous bandwidth, each access source participating in TDM time slot control must be able to access the SRAM in every time slot. This requires the number of SRAM banks to be greater than or equal to the number of TDM time slots. However, more SRAM banks are not necessarily better. Each additional SRAM bank means an additional set of SRAM access interfaces, which poses a significant challenge to the IC back-end design and can easily lead to placement and routing congestion. The aforementioned classification of access sources is also aimed at reducing the number of TDM time slots and thus the number of SRAM banks. Therefore, in this cache subsystem, the number of SRAM banks is set to be the same as the number of TDM time slots. In this example, the number of TDM time slots is set to 8, so the number of SRAM banks is set to 8.
[0035] 3. Address decoding and data caching processing in the caching subsystem: The source logical address is A (bit width is P), the SRAM data bit width is W bytes, and the number of SRAM banks is N. Then, the decoding of address A is as follows: The bank number accessed is: A[log2N + log2W-1 : log2W]; The bank entry accessed is: A[P-1 : log2N + log2W]; In this example, such as Figure 3As shown, the SRAM data width is 32 bytes, and the number of SRAM banks is 8. Its address width is 12 bits. The specific decoding result is as follows: Bank number accessed: A[7:5]; Bank entry accessed: A[11:8].
[0036] In addition to the address decoding function mentioned above, the address decoding preprocessing module also has a data caching function. Since the accessible SRAM bank is controlled by the TDM control module, and access from the access source can occur at any time, this can lead to a discrepancy between the currently allowed SRAM bank and the SRAM bank where the first piece of data needs to be stored. The caching function solves this problem. The access node and data cache are as follows: Figure 4 As shown in the diagram, the nth and n+1th rounds of TDM control are being performed. The current round is n, and the access source's access point is T8*n+4. Assuming the access source accesses 8*32 bytes of data with a 256-byte aligned address, according to the decoding rules, the first piece of data from this access source should be stored in bank1. However, the only SRAM bank allowed at this time is bank4. Therefore, the data stored in bank1, bank2, and bank3 needs to be cached and written to bank1, bank2, and bank3 in the n+1th round of TDM control.
[0037] 4. TDM slot access control in the caching subsystem: In this example, the number of TDM time slots and the number of SRAM banks are both set to 8. Figure 2 As shown, the horizontal axis represents the bank number, and the vertical axis represents the time slot number (time axis). The text "acc 0-7" indicates the labels of the 8 access sources. Figure 2 The TDM order of each SRAM bank can be seen in the diagram.
[0038] Column 1, TDM order of bank 1: In time slot T1, bank1 only allows access source 1 to access it; In time slot T2, bank1 only allows access source 2 to access it; ... In time slot T8, bank1 only allows access source 8 to access the site; Column 2, TDM order in bank 2: In time slot T1, bank2 only allows access source 8 to access the site; In time slot T2, bank2 only allows access source 1 to access it; ... In time slot T8, bank2 only allows access source 7 to access it; ... Column 8, TDM order in bank 8: In time slot T1, bank2 only allows access source 2 to access it; In time slot T2, bank2 only allows access source 3 to access it; ... In time slot T8, bank2 is only allowed to access source 1.
[0039] The seemingly independent TDM sequence between SRAM banks must not only ensure that the access source can access the SRAM in each time slot, but also guarantee the continuity of the access addresses. This means that the TDM sequence of different SRAM banks is related. (Specific comparison follows.) Figure 2 Between two adjacent columns, it can be observed that the TDM sequence on the right has been cyclically shifted down by one time slot compared to the left. If we only look at access source 0, the effect of this cyclical shifting down by one time slot column by column becomes very intuitive.
[0040] like Figure 5 As shown, the order in which access source 1 accesses the bank is as follows: In time slot T1, access source 1 accesses bank 1; In time slot T2, access source 1 accesses bank 2; ... In time slot T8, access source 1 accesses bank 8; Access source 0 can access SRAM in every time slot, ensuring continuous bandwidth requirements; its addressing order also corresponds to the decoding method in point three, guaranteeing the continuity of access addresses. The approach of cyclically shifting down one time slot column by column allows all access sources to achieve the same effect as access source 0.
[0041] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages: 1. The TDM-based cache subsystem eliminates its reliance on bus interconnection, significantly reducing resource consumption. Point-to-point data transmission between the access source and the subsystem also greatly reduces data link latency.
[0042] 2. The TDM-based caching subsystem enables all access sources participating in TDM to achieve high-bandwidth and continuous bandwidth data transmission without causing access congestion. This is a feature that traditional caching subsystems + bus interconnect architectures do not possess.
[0043] 3. Traditional architectures require bus interconnection to implement priority-based access, and the priority levels between different access sources are not clearly defined. A caching subsystem based on TDM technology can make the implementation of different priority levels simpler and more efficient.
[0044] 4. Traditional cache subsystem + bus interconnect architecture, due to the needs of a specific access source, adds redundant design to the interconnect that other access sources do not need, greatly increasing the difficulty of system construction and consuming more resources and power. The construction of a cache subsystem based on TDM technology is simpler and easier to expand than the traditional bus interconnect architecture; according to the number of access sources and the access requirements of each access source, they are divided into three categories, and a dedicated access path is customized for them, which will not interfere with other access sources.
[0045] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A SOC multi-access cache subsystem based on TDM technology, characterized in that, include: Access source module, address decoding preprocessing module, TDM control module, SRAM group module; The access source module contains multiple access sources, and the SRAM group module contains multiple SRAM banks. The access source initiates a read / write access request for the cache. The address decoding preprocessing module converts the source access logical address into an address format that is easy for the TDM control module to manage. The TDM control module manages and schedules the cache access of each access source based on predetermined TDM time slot control rules, further decomposes the cache access of each access source into access to each SRAM bank, and performs cyclic access within and between banks according to the time slot access order of each SRAM bank, thereby realizing point-to-point connection between each access source and the cache.
2. The SOC multi-access cache subsystem according to claim 1, characterized in that: The access sources are divided into at least three categories: Category 1: Access sources with high and continuous bandwidth requirements occupy a TDM time slot on their own; Category 2: Access sources with high bandwidth but no continuous bandwidth requirements share a TDM time slot through a front-end arbitrator; The third category: access sources without high bandwidth requirements, divided into high priority and low priority, which are used to access TDM time slots when there is no time to spare.
3. The SOC multi-access cache subsystem according to claim 2, characterized in that: In the second type of access source, the arbitrator allocates time slot usage rights according to the real-time needs of the access source; in the third type of access source, high-priority access sources take the lead in using idle time slots, while low-priority access sources wait for idle time slots before accessing.
4. The SOC multi-access cache subsystem according to claim 1, characterized in that: The address decoding preprocessing module includes an address decoding unit and a data caching unit; the address decoding unit is used to convert the source access logical address into a bank number and a bank entry; the data caching unit is used to cache data from an unaligned target SRAM bank.
5. The SOC multiple access cache subsystem according to claim 4, characterized in that: The decoding rule of the address decoding unit is as follows: The bank number accessed is: A[log2N + log2W - 1 : log2W]; The bank entry accessed: A[P - 1 : log2N + log2W]; Where A is the logical address, N is the number of SRAM banks, W is the data width of the SRAM, and P is the address width.
6. The SOC multiple access cache subsystem according to claim 4, characterized in that: When the currently allowed SRAM bank is inconsistent with the target bank, the data caching unit caches the misaligned data and writes it to the target bank in the next time slot.
7. The SOC multi-access cache subsystem according to claim 1, characterized in that: The number of SRAM banks in the SRAM group module is equal to the number of TDM time slots, and each SRAM bank has an independent access interface.
8. The SOC multiple access cache subsystem according to claim 7, characterized in that: The number of time slots in the TDM control module is dynamically adjusted according to the number of access sources, and the number of SRAM banks in the SRAM group module is adjusted synchronously with the number of TDM time slots.