Signal control device
By introducing a signal processing module before the signal output module to detect and correct the initial differential signal, the problem of low accuracy in high-speed serial signal transmission is solved, and signal accuracy is improved under dynamic factors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, high-speed serial signal transmission has low accuracy, especially in miniaturized or high-density wiring scenarios where it is difficult to effectively prevent duty cycle distortion, leading to data reception errors and system crashes.
A signal processing module is introduced to detect the initial differential signal and generate a fourth signal that constitutes the differential signal with the first signal. By detecting the parameters of the first and second signals, the second signal is corrected to ensure that the output target differential signal has the correct differential characteristics.
It improves the accuracy of high-speed serial signal transmission, avoids passive crosstalk prevention, and can cope with the effects of dynamic factors such as voltage fluctuations and electrostatic interference.
Smart Images
Figure CN121807761A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computers, and more specifically, to a signal control device. Background Technology
[0002] In related technologies, physical measures are typically employed to suppress duty cycle distortion caused by crosstalk between high-speed serial signal lines. For example, during chip packaging or printed circuit board (PCB) routing design, the spacing between high-speed signal lines is artificially increased to attenuate the interference intensity. However, the above methods have significant limitations: on the one hand, increasing the line spacing is limited by semiconductor manufacturing processes and the actual physical space of the PCB board, making it difficult to implement in miniaturized or high-density routing scenarios; on the other hand, this method can only passively prevent routing crosstalk and is ineffective against duty cycle distortion caused by dynamic factors such as voltage fluctuations or electrostatic interference during transmission. Once duty cycle distortion occurs, the receiving end will be unable to accurately identify the logic level, leading to data reception errors, accumulated bit error rate, or even system crashes.
[0003] No effective solution has yet been proposed to address the technical problems of low accuracy in high-speed serial signal transmission in related technologies. Summary of the Invention
[0004] This application provides a signal control device to at least solve the technical problem of low accuracy in high-speed serial signal transmission in related technologies.
[0005] According to one embodiment of the present application, a signal control device is provided, comprising:
[0006] The system includes a signal input module, a signal processing module, and a signal output module. The signal input module is connected to the signal processing module and the signal output module, and the signal processing module is connected to the signal output module.
[0007] The signal input module is used to receive an initial differential signal, which includes a first signal and a second signal; transmit the first signal to the signal output module, and transmit the first signal and the second signal to the signal processing module.
[0008] The signal processing module is used to detect a first signal to obtain a first signal parameter, and to detect a second signal to obtain a second signal parameter. The first signal parameter indicates the duration of the first signal being in a high-level state per unit time, and the second signal parameter indicates the duration of the second signal being in a low-level state per unit time. Based on the first signal parameter and the second signal parameter, the module generates a fourth signal that forms a differential signal with the first signal using the second signal. The fourth signal is then transmitted to the signal output module.
[0009] The signal output module is used to output the target differential signal, which includes a first signal and a fourth signal.
[0010] This application describes a method where a signal input module receives an initial differential signal comprising a first signal and a second signal. A signal processing module detects the first signal to obtain a first signal parameter indicating the duration of the first signal's high-level state per unit time, and detects the second signal to obtain a second signal parameter indicating the duration of the second signal's low-level state per unit time. Based on the first and second signal parameters, a fourth signal is generated using the second signal to form a differential signal with the first signal. Finally, a target differential signal comprising the first and fourth signals is output by the signal output module. By introducing an independent signal processing module before the signal output module to detect the initial differential signal and correct the second signal based on the detected signal parameters, the output target differential signal is guaranteed to have correct differential characteristics. This avoids the shortcomings of related technologies that rely solely on physical-level avoidance measures to passively prevent crosstalk and cannot cope with dynamic factors such as voltage fluctuations or electrostatic interference. Therefore, this method solves the technical problem of low accuracy in high-speed serial signal transmission in related technologies, achieving the technical effect of improving the accuracy of high-speed serial signal transmission. Attached Figure Description
[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 This is a structural block diagram of a signal control device according to an embodiment of this application;
[0013] Figure 2 This is a structural block diagram of a signal processing module according to an embodiment of this application. Figure 1 ;
[0014] Figure 3 This is a structural block diagram of a signal processing module according to an embodiment of this application. Figure 2 ;
[0015] Figure 4 This is a structural block diagram of a signal processing module according to an embodiment of this application. Figure 3 ;
[0016] Figure 5 This is a schematic diagram of the circuit structure of the first integrating device according to the embodiments of this application;
[0017] Figure 6This is a schematic diagram of the circuit structure of the second integrating device according to the embodiments of this application;
[0018] Figure 7 This is a schematic diagram of the circuit structure of the detection device according to the embodiments of this application;
[0019] Figure 8 This is a schematic diagram of the circuit structure of the controller according to the embodiments of this application;
[0020] Figure 9 This is a schematic diagram of the circuit principle of a signal control device according to an embodiment of this application. Detailed Implementation
[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0022] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0023] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0024] This embodiment provides a signal control device. Figure 1 This is a structural block diagram of a signal control device according to an embodiment of this application, such as... Figure 1 As shown, the device includes: a signal input module 10, a signal processing module 20, and a signal output module 30. The signal input module 10 is connected to the signal processing module 20 and the signal output module 30, and the signal processing module 20 is connected to the signal output module 30.
[0025] The signal input module 10 is used to receive an initial differential signal, which includes a first signal and a second signal; transmit the first signal to the signal output module 30, and transmit the first signal and the second signal to the signal processing module 20.
[0026] The signal processing module 20 is used to detect the first signal to obtain first signal parameters and detect the second signal to obtain second signal parameters. The first signal parameters indicate the duration of the first signal being in a high-level state per unit time, and the second signal parameters indicate the duration of the second signal being in a low-level state per unit time. Based on the first signal parameters and the second signal parameters, the module generates a fourth signal that constitutes a differential signal with the first signal using the second signal. The module then transmits the fourth signal to the signal output module 30.
[0027] The signal output module 30 is used to output a target differential signal, which includes a first signal and a fourth signal.
[0028] By introducing an independent signal processing module before the signal output module, the initial differential signal is detected, and the second signal is corrected based on the detected signal parameters. This ensures that the output target differential signal has correct differential characteristics, avoiding the shortcomings of related technologies that rely solely on physical-level avoidance measures to passively prevent crosstalk and cannot cope with dynamic factors such as voltage fluctuations or electrostatic interference. Therefore, this solves the technical problem of low accuracy in high-speed serial signal transmission in related technologies, achieving the technical effect of improving the accuracy of high-speed serial signal transmission.
[0029] Optionally, in this embodiment, the signal control device may be, but is not limited to, a calibration circuit module integrated inside the high-speed serial interface physical layer chip, a discrete component correction network deployed on the PCB near the receiving end, or a separate signal conditioning chip.
[0030] Optionally, in this embodiment, the initial differential signal includes a positive-phase signal (P signal) and a negative-phase signal (N signal) to be detected and corrected for duty cycle. In this embodiment, it is assumed that the P signal experiences less interference during transmission or its duty cycle characteristics are considered as a reference standard; the first signal can be a P signal, and the second signal can be an N signal. It is understood that, in optional embodiments, if it is assumed that the N signal experiences less interference during transmission or its duty cycle characteristics are considered as a reference standard, the first signal can also be an N signal, and the second signal can be a P signal.
[0031] Optionally, in this embodiment, the signal input module may, but is not limited to, consist of a pair of differential trace input terminals and a series coupling capacitor (such as a 10nF DC blocking capacitor) to filter out the DC bias voltage in the initial differential input signal, ensuring that subsequent processing circuits are within the correct common-mode voltage range. The signal input module adopts a shunt design, on the one hand directly transmitting the first signal to the signal output module, and on the other hand simultaneously sending both signals to the signal processing module for processing.
[0032] Optionally, in this embodiment, the signal processing module may be, but is not limited to, an analog circuit system built from discrete electronic components such as operational amplifiers, transistors, resistors, and capacitors, or it may be an analog front-end circuit integrated inside a chip.
[0033] Optionally, in this embodiment, the first signal parameter may be, but is not limited to, an analog voltage value proportional to the duration of the high level of the first signal. For example, the first signal parameter is a DC level obtained by time integration of the first signal, the amplitude of which linearly corresponds to the cumulative duration of the first signal being in a high-level state within a unit period. The second signal parameter may be, but is not limited to, an analog voltage value proportional to the duration of the low level of the second signal. Since the high-level time of the P signal in a differential signal with a normal duty cycle should be equal to the low-level time of the N signal, the second signal parameter is designed to reflect the cumulative duration of the second signal being in a low-level state, so as to make an equivalent comparison with the first signal parameter.
[0034] Optionally, in this embodiment, detecting the first signal to obtain the first signal parameter may include, but is not limited to, performing preliminary filtering on the first signal to obtain a fifth signal reflecting the high-level amplitude of the first signal, and then performing time integration on the fifth signal to obtain a voltage signal representing the total duration of the first signal being at a high level during the integration time period as the first signal parameter. Alternatively, but not limited to, using a counter driven by a high-frequency clock signal, starting counting on the rising edge of the first signal and stopping counting on the falling edge, the number of clock cycles obtained is the first signal parameter.
[0035] Optionally, in this embodiment, detecting the second signal to obtain second signal parameters may include, but is not limited to: phase-flipping the second signal to obtain a third signal with the same amplitude but opposite phase (i.e., flipping the low level of the original signal to a high level, and flipping the high level of the original signal to a low level); then performing preliminary filtering on the third signal to obtain a sixth signal; subsequently, performing time integration on the sixth signal to obtain a voltage signal representing the total duration of the sixth signal being at a high level during the integration time period, which serves as the second signal parameter. Since the sixth signal corresponds to the phase-flipped third signal, time integration of the high-level amplitude of the sixth signal is essentially equivalent to integrating the duration of the low level of the original second signal. The output second signal parameter can indicate both the duration of the third signal being at a high level per unit time and the duration of the second signal being at a low level per unit time.
[0036] Optionally, in this embodiment, the voltage difference between the first signal parameter and the second signal parameter can be directly compared, but is not limited to: if the first signal parameter and the second signal parameter are equal, it indicates that the duty cycle is normal and the second signal has formed a differential signal with the first signal; if the first signal parameter and the second signal parameter are not equal (for example, the low level time of the N signal is too short or too long), it indicates that the duty cycle is distorted and the second signal has not formed a differential signal with the first signal.
[0037] Optionally, in this embodiment, if it is determined from the first signal parameter and the second signal parameter that the second signal has formed a differential signal with the first signal, the fourth signal may be, but is not limited to, the original second signal; if it is determined from the first signal parameter and the second signal parameter that the second signal has not formed a differential signal with the first signal, the fourth signal may be, but is not limited to, a new signal used to replace the original second signal, which forms a differential signal with the first signal.
[0038] Optionally, in this embodiment, "the fourth signal that constitutes a differential signal with the first signal" is used to indicate that the fourth signal and the first signal are differential signals with normal duty cycles. The signal output module is used to transmit the target differential signal, including the first signal and the fourth signal, to the downstream main control chip's receiving pin.
[0039] As an alternative solution, Figure 2 This is a structural block diagram of a signal processing module according to an embodiment of this application. Figure 1 ,like Figure 2 As shown, the signal processing module 20 includes:
[0040] The first detection unit 22, the second detection unit 24, and the control unit 26 are respectively connected to the first detection unit 22, the second detection unit 24, and the control unit 26. The control unit 26 is connected to the first detection unit 22 and the second detection unit 24 respectively. The control unit 26 is connected to the signal output module 30.
[0041] The first detection unit 22 is used to detect the first signal to obtain the first signal parameters and transmit the first signal parameters to the control unit 26.
[0042] The second detection unit 24 is used to detect the second signal to obtain the second signal parameters and transmit the second signal parameters to the control unit 26.
[0043] The control unit 26 is used to generate a fourth signal that constitutes a differential signal with the first signal using the second signal according to the first signal parameter and the second signal parameter; and to transmit the fourth signal to the signal output module 30.
[0044] Optionally, in this embodiment, the first detection unit is used to convert the high-level duration of the input first signal into a DC voltage amplitude that is proportional to it, thereby quantifying the duty cycle characteristics of the first signal per unit time.
[0045] Optionally, in this embodiment, the second detection unit is used to convert the low-level duration of the input second signal into a DC voltage amplitude that is proportional to it. For example, in a differential signal with a normal duty cycle, the low-level time of the N signal should theoretically be equal to the high-level time of the P signal. Therefore, the second detection unit may, but is not limited to, first perform a phase flip on the N signal, and then perform time integration measurement on the high-level amplitude of the obtained signal after the flip, thereby obtaining a second signal parameter that can be directly compared with the amplitude of the first signal parameter.
[0046] Optionally, in this embodiment, the control unit may, but is not limited to, determine whether the current N signal is in a duty cycle distortion state by comparing the voltage difference between the received first signal parameter and the second signal parameter, and select to directly output the original N signal or output the corrected signal according to the determination result, thereby generating an N signal (i.e., the fourth signal) that constitutes a standard differential signal with the P signal.
[0047] In the above embodiments, the signal processing module's function is decoupled into two independent stages: detection and control. The first and second detection units can work in parallel, eliminating timing delays. The control unit centrally processes the comparison of the two parameters and signal generation, simplifying the circuit logic. This not only improves the detection response speed but also ensures compatibility with differential signals of different frequencies and amplitudes, enhancing the device's versatility and scalability.
[0048] As an alternative solution, Figure 3 This is a structural block diagram of a signal processing module according to an embodiment of this application. Figure 2 ,like Figure 3 As shown, the first detection unit 22 includes a first integrating device 222; the second detection unit 24 includes an inverting device 242 and a second integrating device 244. The signal input module 10 is connected to the control unit 26 through the first integrating device 222, the signal input module 10 is connected to the second integrating device 244 through the inverting device 242, and the second integrating device 244 is connected to the control unit 26.
[0049] The first integrator 222 is used to detect the first signal to obtain the first signal parameters and transmit the first signal parameters to the control unit 26.
[0050] The inverting device 242 is used to perform phase conversion on the second signal to obtain a third signal with the same amplitude but opposite phase as the second signal; the third signal is then transmitted to the second integrator 244.
[0051] The second integrator 244 is used to detect the third signal to obtain the second signal parameter, wherein the second signal parameter is used to indicate the duration of the second signal being in a low-level state per unit time; and the second signal parameter is transmitted to the control unit 26.
[0052] Optionally, in this embodiment, the first integrator can be, but is not limited to, an analog integrator circuit based on an operational amplifier, used to convert the high-level duration of the input signal into an analog voltage amplitude through integration. For example, the device includes an operational amplifier, an input resistor, and a feedback capacitor. When the first signal is in a high-level state, a constant or approximately constant current charges the feedback capacitor, causing the output voltage of the operational amplifier to increase linearly with time.
[0053] Optionally, in this embodiment, the inverting device can be, but is not limited to, an analog or digital circuit unit used to flip the signal phase by 180 degrees. For example, the inverting device can be composed of complementary transistor pairs (such as a push-pull circuit composed of PNP and NPN transistors). When the second signal is low, the inverting device outputs a high level; when the second signal is high, the inverting device outputs a low level. The inverting device is used to convert the "low-level characteristic" of the second signal into a "high-level characteristic" that can be processed by the subsequent integrator circuit, while keeping the signal's time width information unchanged, thereby enabling a device that can only integrate high levels to indirectly measure the duration of the low level.
[0054] Optionally, in this embodiment, the second integrator has the same function as the first integrator, which is used to accumulate the high-level energy of the input signal. The second integrator may have the same or different structure as the first integrator.
[0055] In the above embodiments, the comparison reference of the first signal and the second signal is unified by using an inverting device, and the duty cycle characteristics (high level and low level) of different polarities are uniformly converted into electrical signals of the same polarity (such as high-level integrated voltage). This allows the subsequent circuit to use a simple comparator for judgment, which improves the accuracy of high-speed serial signal transmission and also improves the detection efficiency of high-speed serial signals.
[0056] As an alternative solution, Figure 4 This is a structural block diagram of a signal processing module according to an embodiment of this application. Figure 3 ,like Figure 4 As shown, the control unit 26 includes:
[0057] The detection device 262 is connected to the first detection unit 22 and the second detection unit 24 respectively. The detection device 262 is connected to the control device 264, and the control device 264 is connected to the signal output module 30.
[0058] Among them, the detection device 262 is used to detect the parameter relationship between the first signal parameter and the second signal parameter to obtain the deviation parameter; generate a control signal based on the deviation parameter; and transmit the control signal to the control device 264;
[0059] Among them, the controller 264 is used to generate a fourth signal that constitutes a differential signal with the first signal using the second signal according to the control signal; and transmit the fourth signal to the signal output module 30.
[0060] Optionally, in this embodiment, the deviation parameter may be, but is not limited to, a polarized analog voltage value, the positive or negative polarity of which indicates the direction of duty cycle distortion (e.g., whether the duty cycle of the N signal is larger or smaller than that of the P signal), and its voltage amplitude indicates the severity of the distortion.
[0061] Optionally, in this embodiment, the detection device can calculate the difference between a first signal parameter (representing the high-level duration of the P signal) and a second signal parameter (representing the low-level duration of the N signal) to obtain a deviation parameter. This deviation parameter is then converted into a logic control signal capable of driving subsequent circuitry through threshold comparison or logical judgment. For example, the detection device may include an operational amplifier performing subtraction (for generating the deviation parameter) and a signal generator composed of diodes and logic gates (for generating a control signal based on the polarity of the deviation parameter).
[0062] Optionally, in this embodiment, the controller may be, but is not limited to, an analog switching network or a logic control circuit, configured to switch between two modes according to the indication of the control signal. For example, when the control signal indicates that there is no deviation between the first signal parameter and the second signal parameter, the controller directly outputs the second signal as the fourth signal; when the control signal indicates that there is a deviation between the first signal parameter and the second signal parameter, the controller activates an inverting or reconstructing path to perform phase flipping or delay adjustment on the second signal, thereby outputting a corrected fourth signal to ensure that the final output signal pair has standard differential characteristics.
[0063] In the above embodiments, the high sensitivity of the detection device can identify minute duty cycle deviations, and the control device can quickly switch or adjust the signal path according to the deviation results, ensuring that correction is only intervened when signal duty cycle distortion actually occurs, while maintaining direct flow when the signal duty cycle is normal, thereby preserving the integrity of the original signal to the greatest extent.
[0064] As an alternative solution, the detection device is used for:
[0065] When the deviation parameter is used to indicate that the first signal parameter is equal to the second signal parameter, a first control signal is generated, wherein the first control signal is used to indicate that the second signal has formed a differential signal with the first signal;
[0066] When the deviation parameter is used to indicate that the first signal parameter is not equal to the second signal parameter, a second control signal is generated. The second control signal is used to indicate that the second signal does not form a differential signal with the first signal. The control signal includes the first control signal and the second control signal.
[0067] Optionally, in this embodiment, "equal to" can be understood, but is not limited to, as equality within a preset error range (e.g., the absolute value of the deviation voltage is less than 10mV, depending on the circuit accuracy requirements). "Not equal to" means that the deviation voltage exceeds the preset threshold. The first control signal can be, but is not limited to, a low-level logic signal (or a high-level signal, depending on the logic design), used to indicate that the second signal has formed a differential signal with the first signal, i.e., the duty cycle of the N signal is normal; the second control signal can be, but is not limited to, a high-level logic signal (or a low-level signal, depending on the logic design), used to indicate that the second signal has not formed a differential signal with the first signal, i.e., the duty cycle of the N signal is distorted.
[0068] As an alternative solution, the controller is used for:
[0069] Upon receiving the first control signal, the second signal is determined to be the fourth signal;
[0070] Upon receiving the second control signal, the second signal is phase-converted to obtain a fourth signal with the same amplitude but opposite phase as the second signal.
[0071] Optionally, in this embodiment, when the controller receives the first control signal, it indicates that the duty cycle is normal and no correction is needed, and directly outputs the second signal as the fourth signal. When the controller receives the second control signal, it indicates that the duty cycle is distorted and needs correction, so it performs a phase conversion (e.g., inversion) on the second signal, that is, by flipping the signal polarity within a specific time period, it forcibly lengthens or shortens the duration of the level to achieve the purpose of correcting the duty cycle.
[0072] As an alternative solution, Figure 5 This is a circuit structure diagram of the first integrating device according to the embodiments of this application, such as... Figure 5 As shown, the first integrator 222 includes:
[0073] The first operational amplifier U1, the first input filter 2222, and the first feedback regulator 2224 are connected. The signal input module 10 is connected to the non-inverting input terminal of the first operational amplifier U1 through the first input filter 2222. The output terminal of the first operational amplifier U1 is connected to the inverting input terminal of the first operational amplifier U1 through the first feedback regulator. The output terminal of the first operational amplifier U1 is connected to the control unit 26.
[0074] The first input filter 2222 is used to filter the first signal to obtain the fifth signal, wherein the amplitude of the fifth signal is positively correlated with the duration of the first signal being in a high-level state per unit time; the fifth signal is transmitted to the non-inverting input terminal of the first operational amplifier U1;
[0075] The first feedback regulator 2224 is used to perform feedback sampling on the signal output by the first operational amplifier U1 to generate a first feedback adjustment signal; and to transmit the first feedback adjustment signal to the inverting input terminal of the first operational amplifier U1.
[0076] The first operational amplifier U1 is used to amplify the fifth signal in phase according to the first feedback adjustment signal, and output a voltage signal that is linearly related to the amplitude of the fifth signal as the first signal parameter; and transmit the first signal parameter to the control unit 26.
[0077] Optionally, in this embodiment, the first operational amplifier U1 may be, but is not limited to, a voltage amplifier device with high input impedance, low output impedance and high open-loop gain, such as the LM307 series integrated operational amplifier chip.
[0078] Optionally, in this embodiment, such as Figure 5 As shown, the first input filter 2222 can be, but is not limited to, a DC blocking circuit composed of a resistor (e.g., R2) and a capacitor (e.g., C2). The first input filter is used to remove the DC component from the first signal b, thereby obtaining a fifth signal, which is a pure pulse signal after DC removal, and its effective energy or average level is positively correlated with the duration of the first signal being in a high-level state per unit time.
[0079] Optionally, in this embodiment, such as Figure 5 As shown, the first feedback regulator 2224 can be, but is not limited to, a negative feedback network connected between the output terminal and the inverting input terminal of the first operational amplifier U1, for example, composed of an integrating capacitor (e.g., C1). The first feedback regulator utilizes the characteristic that the voltage across the capacitor cannot change abruptly, in conjunction with the virtual short and virtual open principles of the first operational amplifier U1, to control the closed-loop gain and integral time constant of the circuit.
[0080] Optionally, in this embodiment, the step of the first operational amplifier U1 outputting the first signal parameter can be, but is not limited to, the following: the first operational amplifier U1 receives the fifth signal at its non-inverting input terminal. When the first signal is at a high level (e.g., 3.3V), the fifth signal is also at a high level. Since the output of U1 is fed back to the negative input terminal, it is in the linear amplification region, satisfying the virtual short and virtual open principle. From the virtual short, we can obtain... , We can obtain: Then, the first input filter 2222 is analyzed. , We can obtain: If taken , From the above equations, we can obtain: ,So Since the amount of charge accumulated during charging is proportional to the charging time, the first signal parameter output by U1 is... It is strictly linearly proportional to the positive pulse width of the fifth signal (i.e., the high-level duration of the first signal).
[0081] In the above embodiments, the operational amplifier used to construct the integrating circuit features high input impedance and low output impedance, effectively isolating the signal source from subsequent processing circuits and preventing load effects from affecting signal quality. The feedback regulator allows for precise control of the amplification factor, maintaining a good linear relationship between the first signal parameter and the duty cycle, thus ensuring the accuracy of the detection results.
[0082] As an alternative solution, Figure 6 The circuit structure diagram of the second integrating device in the embodiments of this application is shown below. Figure 6 As shown, the second integrating device 244 includes:
[0083] The second operational amplifier U2, the second input filter 2442, and the second feedback regulator 2444 are connected. The inverting device 242 is connected to the non-inverting input terminal of the second operational amplifier U2 through the second input filter 2442. The output terminal of the second operational amplifier U2 is connected to the inverting input terminal of the second operational amplifier U2 through the second feedback regulator 2444. The output terminal of the second operational amplifier U2 is connected to the control unit 26.
[0084] The second input filter 2442 is used to filter the third signal to obtain the sixth signal, wherein the amplitude of the sixth signal is positively correlated with the duration of the second signal being in a low-level state per unit time; the sixth signal is transmitted to the non-inverting input of the second operational amplifier U2.
[0085] The second feedback regulator 2444 is used to sample the signal output by the second operational amplifier U2 to generate a second feedback regulation signal; and to transmit the second feedback regulation signal to the inverting input terminal of the second operational amplifier U2.
[0086] The second operational amplifier U2 is used to amplify the sixth signal in phase according to the second feedback adjustment signal, and output a voltage signal that is linearly related to the amplitude of the sixth signal as the second signal parameter; the second signal parameter is transmitted to the control unit 26.
[0087] Optionally, in this embodiment, such as Figure 6As shown, the second signal is first input to an inverter device comprising a PNP transistor Q1 and an NPN transistor Q2. When the second signal is low (0V), Q1 is turned on and Q2 is turned off, outputting the third signal. When the second signal is high (3.3V), Q1 is off and Q2 is on, outputting the third signal. The signal is low. (Third signal) It then enters the second integrator, which consists of the second input filter, the second feedback regulator, and the second operational amplifier U2.
[0088] Optionally, in this embodiment, the circuit structure of the second integrator can be, but is not limited to, symmetrical with the first integrator. The second input filter integrates the input third signal (i.e., the inverted second signal) to obtain the sixth signal. The second operational amplifier U2 receives the sixth signal at its non-inverting input terminal, similarly to the first integrator. , We can obtain: Since the amount of charge accumulated during charging is proportional to the charging time, the first signal parameter output by U2 is... It is strictly linearly proportional to the positive pulse width of the sixth signal (i.e., the duration of the low level of the second signal).
[0089] As an alternative solution, Figure 7 This is a schematic diagram of the circuit structure of the detection device according to the embodiments of this application, such as... Figure 7 As shown, the detection device 262 includes:
[0090] The system comprises a third operational amplifier U3, an impedance 2622, a voltage divider 2624, a third feedback regulator 2626, and a signal generator 2628. The first detection unit is connected to the inverting input of the third operational amplifier U3 through the impedance 2622. The second detection unit is connected to the non-inverting input of the third operational amplifier U3 through the voltage divider 2624. The output of the third operational amplifier U3 is connected to the inverting input of the third operational amplifier U3 through the third feedback regulator 2626. The output of the third operational amplifier U3 is connected to the control device 264 through the signal generator 2628.
[0091] Impedance 2622 is used to generate a seventh signal based on the first signal parameters, wherein the amplitude of the seventh signal is positively correlated with the first signal parameters; and transmits the seventh signal to the inverting input of the third operational amplifier U3.
[0092] The voltage divider 2624 is used to generate an eighth signal based on the second signal parameters, wherein the amplitude of the eighth signal is positively correlated with the second signal parameters; and transmits the eighth signal to the non-inverting input of the third operational amplifier U3.
[0093] The third feedback regulator 2626 is used to sample the signal output by the third operational amplifier U3 to generate a third feedback regulation signal; and to transmit the third feedback regulation signal to the inverting input terminal of the third operational amplifier U3.
[0094] The third operational amplifier U3 is used to perform differential operation on the seventh and eighth signals to obtain the deviation parameter; the deviation parameter is then transmitted to the signal generator 2628.
[0095] The signal generator 2628 is used to generate a control signal based on the deviation parameter and transmit the control signal to the controller 264.
[0096] Optionally, in this embodiment, impedance 2622 is used to convert the first signal parameter into a current or voltage form suitable for the operational amplifier input, i.e., to generate the seventh signal; voltage divider 2624 is used to perform voltage division processing on the second signal parameter to generate the eighth signal; and third feedback regulator 2626 is used to perform feedback sampling on the output signal to generate the third feedback regulation signal.
[0097] Optionally, in this embodiment, the detection device employs a differential subtraction circuit architecture. For example... Figure 7 As shown, the third operational amplifier U3 may be, but is not limited to, an LM307 chip configured in differential mode. Impedance 2622 may be, but is not limited to, an input resistor (e.g., R8), voltage divider 2624 may be, but is not limited to, a voltage divider circuit consisting of resistors (e.g., R6, R7), and third feedback regulator 2626 may be, but is not limited to, a feedback resistor (e.g., R8).
[0098] Optionally, in this embodiment, the operation process of the third operational amplifier U3 performing differential operation on the seventh and eighth signals to obtain the deviation parameter is as follows: based on the virtual short and virtual open characteristics of the operational amplifier, it is assumed that the resistance values of the impedance device, voltage divider, and third feedback regulator satisfy a matching relationship, for example... Then the output voltage (i.e., the deviation parameter) of the third operational amplifier U3 is equal to the voltage at the non-inverting input (corresponding to the second signal parameter). The voltage at the inverting input terminal (corresponding to the first signal parameter) and the voltage at the inverting input terminal. The result of the proportional magnification of the difference between the two, or simply the difference between the two (i.e., or (This depends specifically on the polarity of the input connection). If ,but V indicates that the duration of the N signal being at a low level per unit time is equal to the duration of the P signal being at a high level per unit time, and the duty cycle of the N signal is normal; if ,but This means that the duration of the N signal being in a low-level state per unit time is less than the duration of the P signal being in a high-level state per unit time, and the duty cycle of the N signal is shortened; if ,but This means that the duration of the N signal being in a low-level state per unit time is greater than the duration of the P signal being in a high-level state per unit time, thus increasing the duty cycle of the N signal.
[0099] Optionally, in this embodiment, such as Figure 7 As shown, the signal generator may include, but is not limited to, a diode (e.g., D1), a fourth operational amplifier (e.g., U4), and its peripheral resistors (e.g., R9, R10) to generate the deviation parameter output by the third operational amplifier U3. Converted into control signals with defined logic levels .
[0100] Optionally, in this embodiment, the signal generator 2628 determines the signal based on the deviation parameter. Generate control signals The operation is as follows: Set the deviation parameter Connect diode D1. When the deviation parameter... At this time, the negative terminal of diode D1 is under high voltage, so the diode is open, and U4 does not work, thus the output control signal is not available. and Equal, both are greater than 0; when the deviation parameter At this time, the negative terminal of diode D1 is at a low voltage, therefore the diode conducts, and U4 operates. Similarly, the virtual short and virtual open characteristics are satisfied, resulting in: , ,Pick ,therefore When the deviation parameter At that time, .
[0101] Optionally, in this embodiment, in the first signal parameter With the second signal parameter If there is no deviation between them, that is, the duty cycle of the N signal is normal, no correction is needed, and the control signal... Low level (first control signal); in the first signal parameter With the second signal parameter When there is a deviation, i.e., the duty cycle of the N signal is distorted, the control signal... It is at a high level (second control signal).
[0102] As an alternative solution, Figure 8 This is a schematic diagram of the circuit structure of the controller according to the embodiments of this application, such as... Figure 8 As shown, the controller 264 includes:
[0103] Phase follower 2642 and phase inverter 2644 are included. Detection device 262 is connected to the enable terminal of phase follower 2642 and the enable terminal of phase inverter 2644, respectively. Signal input module 10 is connected to the input terminal of phase follower 2642 and the input terminal of phase inverter 2644, respectively. The output terminals of phase follower 2642 and phase inverter 2644 are both connected to signal output module 30.
[0104] The phase follower 2642 is used to transmit the second signal to the signal output module 30 when the enable terminal of the phase follower 2642 receives the first control signal.
[0105] The phase inverter 2644 is used to perform phase conversion on the second signal to obtain a fourth signal with the same amplitude but opposite phase as the second signal; when the enable terminal of the phase inverter 2644 receives the second control signal, the fourth signal is transmitted to the signal output module.
[0106] Optionally, in this embodiment, the phase follower may be, but is not limited to, an emitter follower composed of an NPN transistor, or an analog switch composed of a high-speed transmission gate. When the control terminal is active, it conducts with low impedance, directly connecting the input and output.
[0107] Optionally, in this embodiment, the phase inverter can be, but is not limited to, an inverter composed of a common-emitter amplifier circuit, which provides sufficient current gain while achieving a 180-degree phase flip; or a digital inverting unit composed of a high-speed XOR gate and enable logic. The phase inverter is used to output the inverted signal of the N signal when the duty cycle of the N signal is distorted.
[0108] Optionally, in this embodiment, the phase follower 2642 may include, but is not limited to, a high-speed buffer with an enable terminal. A control signal is connected to this enable terminal. When a normal duty cycle is detected, a valid first control signal (such as a high level) is issued, activating the output stage transistor bias circuit inside the buffer, driving the second signal at the input terminal to the signal output module with extremely low output impedance. At this time, the N signal in the output target differential signal is directly composed of the original N signal. In another embodiment, the phase follower 2642 may also include, but is not limited to, an NPN transistor. A control signal is connected to the base of the NPN transistor Q4. When the control signal is high, Q4 is saturated and conducts, transmitting the base signal to the emitter in an emitter-follower configuration, achieving the logical effect that the output level (fourth signal) follows the input level (second signal), ensuring that the signal is not subject to additional processing interference when the signal quality is good.
[0109] Optionally, in this embodiment, the phase inverter 2644 may include, but is not limited to, a set of complementary MOSFETs or BJTs (such as a CMOS inverter structure). When the second signal is input, if it is high, the N-type transistor is turned on to pull the output low; if it is low, the P-type transistor is turned on to pull the output high. This inverted signal node carries the fourth signal. This process is continuous, meaning that the fourth signal always changes with the second signal inside the phase inverter and is in a standby state. In another embodiment, the fourth signal may be obtained directly from the inverting output of a fully differential amplifier, ensuring that the fourth signal has a highly consistent common-mode voltage and swing with the second signal, only with opposite phase.
[0110] Optionally, in this embodiment, the input terminal of the phase inverter 2644 may also be connected to, but is not limited to, the output terminal of the inverter 242. When duty cycle distortion is detected (such as the N signal being too low for too short a time), the second control signal becomes active, activating the output enable of the phase inverter 2644. At this time, the aforementioned generated third signal is allowed to be transmitted to the signal output module as a fourth signal through the output stage, forcibly covering or driving the output bus. For example, an NPN transistor Q3 is used as the output switch of the phase inverter. When g is high, Q3 is turned on. Since Q3 is configured on the inverting path (or the conduction of Q3 itself causes the output node level to flip, such as being pulled low from high), the output presents a level opposite to the original second signal.
[0111] Optionally, in order to better understand the above-mentioned signal control device, the signal control device will be described in conjunction with optional embodiments below, but it is not intended to limit the technical solution of the embodiments of this application.
[0112] Assuming VCC is 3.3V, It is 100KΩ. The value is 10KΩ. , The value is 10nf. , The value is 1uf. U1, U2, U3, and U4 are LM307 operational amplifiers. NOT gate U5 is a 74LS04. Q2, Q3, and Q4 are NPN transistors (or bipolar junction transistors) BC846, and Q1 is a PNP transistor (or bipolar junction transistor) BC856. T0=0s, T1=0.1s, T2=0.2s, T3=1s, T4=1.2s, T5=1.3s. The above scenario describes a signal control device provided in this embodiment. Figure 9 This is a circuit diagram of a signal control device according to an embodiment of this application, such as... Figure 9As shown, the first signal is Vin_P and the second signal is Vin_N. During the time intervals T0-T2, the duty cycle of the N signal is shortened to 25%, and during the time intervals T3-T5, the duty cycle of the N signal is expanded to 75%.
[0113] At time T1, Vin_N is low. Since Q1 is a PNP MOS transistor and Q2 is an NPN MOS transistor, Q1 is turned on and Q2 is turned off. Therefore, the output a is high at VCC, which is logic "1". Now, we come to op-amp U2. Because the output of U2 is fed back to the negative input, it is in the linear amplification region, satisfying the virtual short and virtual open characteristics. From the virtual short, we can obtain... , We can obtain: Then, R4 and C4 were analyzed. , We can obtain: If we take R3=R4 and C3=C4, we can obtain the following from the above equations: ,So Similarly, taking values R1=R2 and C1=C2, at time T1, the output of U1 is... If we take the values C1=C3 and R2=R4, we can see that at this time... They are of equal size. Therefore Q3 is off and Q4 is on. At this time, the output Vout_N = Vin_N (low level) and Vout_P is high level. Vout_N and Vout_P form a differential signal with a normal duty cycle.
[0114] At time T2, Vin_N is high, so Q1 is off and Q2 is on, therefore the output... The level is low, which is logic "0". Similarly, the output of U2... Still The size did not change, while the output of U1 for: Since T2 > T1, therefore at this time Further obtained .because Therefore, the cathode of diode D1 is at a high voltage, so the diode is open, and U4 does not work, thus the output control signal is lost. At this time, Q3 is turned on and Q4 is turned off, and the output Vout_N = (Low level). Therefore, in the interval from T1 to T2, The voltage gradually increases from 3.3V to 6.6V, therefore The value was always greater than 0 during this period, therefore Since the value is always greater than 0, Q3 is on and Q4 is off. Therefore, the output Vout_N in this interval is of size [value missing]. Therefore, in the T1 to T2 interval, the duty cycle of the output Vout_N is lengthened, becoming a waveform with the same 50% duty cycle as the P signal, and the duty cycle is corrected to normal.
[0115] Similarly, in the T3-T5 interval, the duty cycle of the N signal increases. The situation is similar to that in the T0-T1 time interval, except that... , Similarly, Q3 is off, Q4 is on, and the output Vout_N = Vin_N (low level). At this time, Vout_P is high, and Vout_N and Vout_P form a differential signal with a normal duty cycle. During the T4-T5 time period, since Vin_P is 0, therefore... It has remained at 6.6V. ,therefore During the time period T4-T5, the voltage gradually increases from 6.6V to 9.9V. The output voltage during this time period... It is high level, therefore the entire time period ,because Therefore, the entire time period from T4 to T5 Therefore, the output Vout_N is a (high level) at this time. Thus, in the T4-T5 interval, the duty cycle of the output Vout_N is reduced and becomes a waveform with the same 50% duty cycle as the P signal. The duty cycle is corrected to normal.
[0116] In summary, after detection and correction by the signal control equipment, whether the duty cycle is reduced or increased, the final output N signal can be corrected to a normal duty cycle waveform.
[0117] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0118] The signal control device provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A signal control device, characterized in that, include: The system includes a signal input module, a signal processing module, and a signal output module. The signal input module is connected to the signal processing module and the signal output module, and the signal processing module is connected to the signal output module. The signal input module is configured to receive an initial differential signal, wherein the initial differential signal includes a first signal and a second signal; transmit the first signal to the signal output module, and transmit the first signal and the second signal to the signal processing module; The signal processing module is configured to detect the first signal to obtain a first signal parameter, and detect the second signal to obtain a second signal parameter, wherein the first signal parameter indicates the duration of the first signal being in a high-level state per unit time, and the second signal parameter indicates the duration of the second signal being in a low-level state per unit time; generate a fourth signal that constitutes a differential signal with the first signal using the second signal based on the first signal parameter and the second signal parameter; and transmit the fourth signal to the signal output module. The signal output module is used to output a target differential signal, wherein the target differential signal includes the first signal and the fourth signal.
2. The device according to claim 1, characterized in that, The signal processing module includes: The system comprises a first detection unit, a second detection unit, and a control unit. The signal input module is connected to the first detection unit, the second detection unit, and the control unit, respectively. The control unit is connected to the first detection unit and the second detection unit, respectively. The control unit is also connected to the signal output module. The first detection unit is used to detect the first signal to obtain a first signal parameter and transmit the first signal parameter to the control unit. The second detection unit is used to detect the second signal to obtain a second signal parameter; and to transmit the second signal parameter to the control unit. The control unit is configured to generate a fourth signal that constitutes a differential signal with the first signal using the second signal based on the first signal parameter and the second signal parameter; and transmit the fourth signal to the signal output module.
3. The device according to claim 2, characterized in that, The first detection unit includes a first integrating device; the second detection unit includes an inverting device and a second integrating device, wherein the signal input module is connected to the control unit through the first integrating device, the signal input module is connected to the second integrating device through the inverting device, and the second integrating device is connected to the control unit. The first integrator is used to detect the first signal to obtain a first signal parameter and transmit the first signal parameter to the control unit. The inverting device is used to perform phase conversion on the second signal to obtain a third signal with the same amplitude but opposite phase as the second signal; and to transmit the third signal to the second integrator. The second integrator is used to detect the third signal to obtain a second signal parameter, wherein the second signal parameter is used to indicate the duration of the second signal being in a low-level state per unit time; and the second signal parameter is transmitted to the control unit.
4. The device according to claim 2, characterized in that, The control unit includes: The system includes a detection device and a control device. The detection device is connected to the first detection unit and the second detection unit, respectively. The detection device is connected to the control device, and the control device is connected to the signal output module. The detection device is used to detect the parameter relationship between the first signal parameter and the second signal parameter to obtain a deviation parameter; generate a control signal based on the deviation parameter; and transmit the control signal to the control device. The controller is configured to generate a fourth signal that constitutes a differential signal with the first signal using the second signal according to the control signal; and to transmit the fourth signal to the signal output module.
5. The device according to claim 4, characterized in that, The detection device is used for: When the deviation parameter indicates that the first signal parameter is equal to the second signal parameter, a first control signal is generated, wherein the first control signal indicates that the second signal has formed a differential signal with the first signal; When the deviation parameter indicates that the first signal parameter is not equal to the second signal parameter, a second control signal is generated, wherein the second control signal indicates that the second signal does not constitute a differential signal with the first signal, and the control signal includes the first control signal and the second control signal.
6. The device according to claim 5, characterized in that, The control device is used for: Upon receiving the first control signal, the second signal is determined to be the fourth signal; Upon receiving the second control signal, the second signal is phase-converted to obtain the fourth signal, which has the same amplitude but opposite phase as the second signal.
7. The device according to claim 3, characterized in that, The first integrating device includes: The system comprises a first operational amplifier, a first input filter, and a first feedback regulator. The signal input module is connected to the non-inverting input of the first operational amplifier via the first input filter. The output of the first operational amplifier is connected to the inverting input of the first operational amplifier via the first feedback regulator. The output of the first operational amplifier is connected to the control unit. The first input filter is used to filter the first signal to obtain a fifth signal, wherein the amplitude of the fifth signal is positively correlated with the duration of the first signal being in a high-level state per unit time; the fifth signal is then transmitted to the non-inverting input of the first operational amplifier. The first feedback regulator is used to perform feedback sampling on the signal output by the first operational amplifier to generate a first feedback adjustment signal; and to transmit the first feedback adjustment signal to the inverting input terminal of the first operational amplifier. The first operational amplifier is used to amplify the fifth signal in phase according to the first feedback adjustment signal, and output a voltage signal that is linearly related to the amplitude of the fifth signal as the first signal parameter; and transmit the first signal parameter to the control unit.
8. The device according to claim 3, characterized in that, The second integrating device includes: The system comprises a second operational amplifier, a second input filter, and a second feedback regulator. The inverting device is connected to the non-inverting input of the second operational amplifier via the second input filter. The output of the second operational amplifier is connected to the inverting input of the second operational amplifier via the second feedback regulator. The output of the second operational amplifier is connected to the control unit. The second input filter is used to filter the third signal to obtain a sixth signal, wherein the amplitude of the sixth signal is positively correlated with the duration of the second signal being in a low-level state per unit time; the sixth signal is then transmitted to the non-inverting input of the second operational amplifier. The second feedback regulator is used to perform feedback sampling on the signal output by the second operational amplifier to generate a second feedback adjustment signal; and to transmit the second feedback adjustment signal to the inverting input terminal of the second operational amplifier. The second operational amplifier is used to amplify the sixth signal in phase according to the second feedback adjustment signal, and output a voltage signal that is linearly related to the amplitude of the sixth signal as the second signal parameter; and transmit the second signal parameter to the control unit.
9. The device according to claim 4, characterized in that, The detection device includes: The system comprises a third operational amplifier, an impedance transformer, a voltage divider, a third feedback regulator, and a signal generator. The first detection unit is connected to the inverting input of the third operational amplifier through the impedance transformer. The second detection unit is connected to the non-inverting input of the third operational amplifier through the voltage divider. The output of the third operational amplifier is connected to the inverting input of the third operational amplifier through the third feedback regulator. The output of the third operational amplifier is connected to the control device through the signal generator. The impedance is used to generate a seventh signal based on the first signal parameters, wherein the amplitude of the seventh signal is positively correlated with the first signal parameters; and to transmit the seventh signal to the inverting input of the third operational amplifier. The voltage divider is used to generate an eighth signal based on the second signal parameters, wherein the amplitude of the eighth signal is positively correlated with the second signal parameters; and to transmit the eighth signal to the non-inverting input of the third operational amplifier. The third feedback regulator is used to perform feedback sampling on the signal output by the third operational amplifier to generate a third feedback adjustment signal; and to transmit the third feedback adjustment signal to the inverting input terminal of the third operational amplifier. The third operational amplifier is used to perform differential operation on the seventh signal and the eighth signal to obtain the deviation parameter; and to transmit the deviation parameter to the signal generator. The signal generator is used to generate the control signal based on the deviation parameter and transmit the control signal to the control device.
10. The device according to claim 5, characterized in that, The control device includes: The system includes a phase follower and a phase inverter. The detection device is connected to the enable terminal of the phase follower and the enable terminal of the phase inverter, respectively. The signal input module is connected to the input terminal of the phase follower and the input terminal of the phase inverter, respectively. The output terminals of the phase follower and the phase inverter are both connected to the signal output module. The phase follower is configured to transmit the second signal to the signal output module when the enable terminal of the phase follower receives the first control signal. The phase inverter is used to perform phase conversion on the second signal to obtain the fourth signal with the same amplitude but opposite phase as the second signal; when the enable terminal of the phase inverter receives the second control signal, the fourth signal is transmitted to the signal output module.