Data interaction detection method and device

Abstract

The embodiment of the invention provides a data interaction detection method and device, and relates to the technical field of chips, and the method comprises the steps: obtaining first data which is transmitted by a first read-write interface and is interacted between a source circuit module and a target circuit module, obtaining second data interacted between the source circuit module and the target circuit module and transmitted by a second read-write interface; detecting whether the first data meets preset time sequence constraints and attribute constraints or not, and detecting whether the second data meets the time sequence constraints and the attribute constraints or not; and if both the first data and the second data meet the time sequence constraint and the attribute constraint, determining that the data interaction between the source circuit module and the target circuit module is correct. By applying the data interaction detection scheme provided by the embodiment of the invention, whether the circuit module integrated by the network processor chip can perform correct data interaction through the crossbar can be detected.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a data interaction detection method and apparatus. Background Technology

[0002] Network processor chips can integrate hundreds or even thousands of circuit modules. To enable data exchange between these modules, a crossbar (cross-connect bus) can be integrated into the chip. The circuit modules on the chip then communicate via the crossbar. To ensure the chip functions correctly, it is necessary to guarantee the correctness of data exchange between different circuit modules via the crossbar.

[0003] Therefore, a data interaction detection scheme is needed to detect whether different circuit modules can correctly interact with each other through cross_bar. Summary of the Invention

[0004] The purpose of this invention is to provide a data interaction detection method and apparatus to detect whether the circuit module integrated in a network processor chip can perform correct data interaction via cross_bar. The specific technical solution is as follows:

[0005] In a first aspect, embodiments of this application provide a data interaction detection method, the method comprising:

[0006] The system obtains first data exchanged between the source circuit module and the destination circuit module transmitted through the first read / write interface, and obtains second data exchanged between the source circuit module and the destination circuit module transmitted through the second read / write interface. Both the first and second read / write interfaces are read / write interfaces on the cross-connect bus included in the network processor chip. The source circuit module is a circuit module on the network processor chip that is equipped with the first read / write interface, and the destination circuit module is a circuit module on the network processor chip that is equipped with the second read / write interface.

[0007] The system detects whether the first data satisfies preset timing constraints and attribute constraints, and detects whether the second data satisfies the timing constraints and attribute constraints, wherein the timing constraints specify the timing of the data exchanged between the source circuit module and the destination circuit module, and the attribute constraints specify the attributes of the data exchanged between the source circuit module and the destination circuit module.

[0008] If both the first data and the second data satisfy the timing constraints and attribute constraints, then the data interaction between the source circuit module and the destination circuit module is determined to be correct.

[0009] In one embodiment of this application, the first read / write interface includes a first write channel and a first read channel, the second read / write interface includes a second write channel and a second read channel, the timing constraints include write data timing constraints and read data timing constraints, and the attribute constraints include write data attribute constraints and read data attribute constraints.

[0010] The step of detecting whether the first data satisfies the preset time constraints and attribute constraints, and detecting whether the second data satisfies the time constraints and attribute constraints, includes:

[0011] Detect whether the data transmitted through the first write channel in the first data satisfies the write data timing constraints and write data attribute constraints, and detect whether the data transmitted through the second write channel in the second data satisfies the write data timing constraints and write data attribute constraints;

[0012] The system detects whether the data transmitted through the first read channel in the first data satisfies the read data timing constraints and read data attribute constraints, and detects whether the data transmitted through the second read channel in the second data satisfies the read data timing constraints and read data attribute constraints.

[0013] In one embodiment of this application, the step of determining that the data interaction between the source circuit module and the destination circuit module is correct if both the first data and the second data satisfy the timing constraints and attribute constraints includes:

[0014] If the free space in the data buffer corresponding to the second read / write interface is not less than the preset space size, then it is detected whether an acknowledgment signal is transmitted in the second write channel, wherein the acknowledgment signal is used to notify the source circuit module that the data buffer is free;

[0015] If both the first data and the second data satisfy the timing constraints and attribute constraints, and the second write channel transmits the response signal, then it is determined that the data interaction between the source circuit module and the destination circuit module is correct.

[0016] In one embodiment of this application, determining that the data interaction between the source circuit module and the destination circuit module is correct if both the first data and the second data satisfy the timing constraints and attribute constraints, and the second write channel transmits the response signal, includes:

[0017] Detect whether the first read channel transmits a control response signal within a target time period, wherein the target time period is a time period with a signal feedback time as the start time and a duration of a preset number of clock cycles, the signal feedback time is the time when the second write channel transmits the response signal, and the control response signal indicates that the source circuit module has received the response signal;

[0018] If both the first data and the second data satisfy the timing constraints and attribute constraints, the second write channel transmits the response signal, and the first read channel transmits the control response signal within the target time period, then it is determined that the data interaction between the source circuit module and the destination circuit module is correct.

[0019] In one embodiment of this application, the timing constraint includes the timing of at least one of the following data:

[0020] Packet start flag, packet end flag, packet validity flag, and data to be transmitted in the data packet.

[0021] In one embodiment of this application, the attributes of the data include at least one of the following:

[0022] Read / write operation type, address accessed by the read / write operation, and data identification information.

[0023] Secondly, embodiments of this application provide a data interaction detection device, the device comprising:

[0024] A data acquisition unit is used to acquire first data exchanged between a source circuit module and a destination circuit module transmitted via a first read / write interface, and to acquire second data exchanged between the source circuit module and the destination circuit module transmitted via a second read / write interface. The first read / write interface and the second read / write interface are both read / write interfaces on a cross-connect bus included in the network processor chip. The source circuit module is a circuit module on the network processor chip that is equipped with the first read / write interface, and the destination circuit module is a circuit module on the network processor chip that is equipped with the second read / write interface.

[0025] A constraint detection unit is used to detect whether the first data satisfies preset timing constraints and attribute constraints, and to detect whether the second data satisfies the timing constraints and attribute constraints. If both the first data and the second data satisfy the timing constraints and attribute constraints, an interaction determination unit is triggered. The timing constraints specify the timing of the data exchanged between the source circuit module and the destination circuit module, and the attribute constraints specify the attributes of the data exchanged between the source circuit module and the destination circuit module.

[0026] The interaction determination unit is used to determine that the data interaction between the source circuit module and the destination circuit module is correct.

[0027] In one embodiment of this application, the first read / write interface includes a first write channel and a first read channel, the second read / write interface includes a second write channel and a second read channel, the timing constraints include write data timing constraints and read data timing constraints, and the attribute constraints include write data attribute constraints and read data attribute constraints.

[0028] The constraint detection unit is specifically used for:

[0029] Detect whether the data transmitted through the first write channel in the first data satisfies the write data timing constraints and write data attribute constraints, and detect whether the data transmitted through the second write channel in the second data satisfies the write data timing constraints and write data attribute constraints;

[0030] The system detects whether the data transmitted through the first read channel in the first data satisfies the read data timing constraints and read data attribute constraints, and detects whether the data transmitted through the second read channel in the second data satisfies the read data timing constraints and read data attribute constraints.

[0031] In one embodiment of this application, the interaction determination unit includes:

[0032] The first detection subunit is used to detect whether an acknowledgment signal is transmitted in the second write channel if the free space in the data buffer corresponding to the second read / write interface is not less than a preset space size. If the first data and the second data both satisfy the timing constraints and attribute constraints, and the second write channel transmits the acknowledgment signal, then the interaction determination subunit is triggered. The acknowledgment signal is used to notify the source circuit module that the data buffer is free.

[0033] The interaction determination subunit is used to determine that the data interaction between the source circuit module and the destination circuit module is correct.

[0034] In one embodiment of this application, the interactive determination subunit is specifically used for:

[0035] Detect whether the first read channel transmits a control response signal within a target time period, wherein the target time period is a time period with a signal feedback time as the start time and a duration of a preset number of clock cycles, the signal feedback time is the time when the second write channel transmits the response signal, and the control response signal indicates that the source circuit module has received the response signal;

[0036] If both the first data and the second data satisfy the timing constraints and attribute constraints, the second write channel transmits the response signal, and the first read channel transmits the control response signal within the target time period, then it is determined that the data interaction between the source circuit module and the destination circuit module is correct.

[0037] In one embodiment of this application, the timing constraint includes the timing of at least one of the following data:

[0038] Packet start flag, packet end flag, packet validity flag, and data to be transmitted in the data packet.

[0039] In one embodiment of this application, the attributes of the data include at least one of the following:

[0040] Read / write operation type, address accessed by the read / write operation, and data identification information.

[0041] Thirdly, embodiments of this application also provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0042] Memory, used to store computer programs;

[0043] When a processor executes a program stored in memory, it implements any of the steps described in the first aspect above.

[0044] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the steps described in the first aspect above.

[0045] Beneficial effects of the embodiments of the present invention:

[0046] As can be seen from the above, when performing data interaction detection using the solution provided in the embodiments of this application, if both the first data and the second data satisfy the timing constraints and attribute constraints, it indicates that the first data and the second data are the same data. This further indicates that the cross-connect bus can accurately perform data routing between the first read / write interface and the second read / write interface, and the source circuit module and the destination circuit module can achieve correct data interaction through the first read / write interface and the second read / write interface. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0048] Figure 1 This is a schematic diagram of the connection between the circuit module and the cross_bar in the first type of chip provided in the embodiments of this application;

[0049] Figure 2 A flowchart illustrating a data interaction detection method provided in an embodiment of this application;

[0050] Figure 3a A schematic diagram illustrating the first type of timing constraint provided in an embodiment of this application;

[0051] Figure 3b A schematic diagram illustrating the second type of timing constraint provided in an embodiment of this application;

[0052] Figure 4 This is a schematic diagram of the connection between the circuit module and the cross_bar in the second type of chip provided in the embodiments of this application;

[0053] Figure 5a A timing diagram of the first type of control response signal provided in an embodiment of this application;

[0054] Figure 5b A timing diagram illustrating the second type of control response signal provided in an embodiment of this application;

[0055] Figure 6 This is a schematic diagram of the structure of a data interaction detection device provided in an embodiment of this application;

[0056] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of the present invention.

[0058] With the rise of artificial intelligence technology, the demand for computing power in more and more fields is constantly increasing, making network processor chips in computers increasingly complex. A single chip can integrate hundreds or even thousands of circuit modules. In order to achieve efficient, high-throughput, and low-power communication between these circuit modules, the inter-module interconnection technology within the chip has become very important.

[0059] Currently popular module interconnect technologies utilize crossbars, where circuit modules on the chip connect to the crossbar's read / write interface for data exchange. To ensure proper chip operation, it's crucial to guarantee the correctness of data exchange between different circuit modules via the crossbar.

[0060] Below, firstly, in combination with Figure 1This section introduces the process of data interaction between circuit modules in the chip via cross_bar.

[0061] Figure 1 The diagram shows the connection between the circuit modules in the chip and the cross_bar. As can be seen from the diagram, each circuit module to be interacted with is connected to a read / write interface in the cross_bar. The read / write interface connected to the client (source circuit module, i.e., the circuit module that initiates the request) can be called the client-side read / write interface, and the read / write interface connected to the target (destination circuit module, i.e., the circuit module that responds to the request) can be called the target-side read / write interface.

[0062] When a client writes data to a target, the client can transmit a write request and the data to be written to the cross_bar through the read / write interface connected to it. The cross_bar then routes the write request and the data to be written to the read / write interface on the target side, thereby transmitting the write request and the data to be written to the target through the read / write interface on the target side, completing the data writing process.

[0063] When a client reads data from a target, it can send a read request to the cross-bar via its connected read / write interface. The cross-bar then routes the read request to the target's read / write interface, which in turn transmits the request to the target. After the target reads the data, it sends the read data back to the cross-bar via its connected read / write interface. The cross-bar then routes the read data to the client's read / write interface, which in turn transmits the data to the client, completing the data reading process.

[0064] Figure 1 The diagram illustrates source circuit module 0 (Client_0), source circuit module 1 (Client_1), source circuit module 2 (Client_2), destination circuit module 0 (Target_0), destination circuit module 1 (Target_1), destination circuit module 2 (Target_2), and destination circuit module 3 (Target_3). Client_0 is connected to read / write interface 0, Client_1 to read / write interface 1, Client_2 to read / write interface 2, Target_0 to read / write interface 3, Target_1 to read / write interface 4, Target_2 to read / write interface 5, and Target_3 to read / write interface 6.

[0065] Figure 1The three clients and four targets shown are merely examples, and the number of clients and targets is not limited in this embodiment.

[0066] In addition, the cross-connect bus involved in the embodiments of this application can be a cross-connect bus with flow control or a cross-connect bus without flow control.

[0067] The following describes the entity responsible for implementing the data interaction detection scheme provided in the embodiments of this application.

[0068] The entity executing this solution can be called a detection device, which can obtain data transmitted through the cross_bar read / write interface and perform detection on the data.

[0069] Next, the data interaction detection method and apparatus provided in this application will be described in detail through specific embodiments.

[0070] See Figure 2 , Figure 2 This is a flowchart illustrating a data interaction detection method provided in an embodiment of this application. In this embodiment, the method includes the following steps S201-S203.

[0071] Step S201: Obtain the first data exchanged between the source circuit module and the destination circuit module transmitted through the first read / write interface, and obtain the second data exchanged between the source circuit module and the destination circuit module transmitted through the second read / write interface.

[0072] The first read / write interface and the second read / write interface are both read / write interfaces on the cross-connect bus included in the network processor chip.

[0073] The source circuit module is a circuit module on the network processor chip that has a first read / write interface.

[0074] The target circuit module is a circuit module on the network processor chip that has a second read / write interface.

[0075] Specifically, `cross_bar` enables data interaction between multiple source circuit modules and multiple destination circuit modules. During data interaction detection, each group of circuit modules (one source and one destination) can be used as a group for data interaction detection. When performing data interaction detection on each group of circuit modules, the read / write interface assigned to the source circuit module in that group is the first read / write interface, and the read / write interface assigned to the destination circuit module in that group is the second read / write interface.

[0076] For example, in the above Figure 1If it is necessary to detect the data interaction between Client_0 and Target_2, then Client_0 and Target_2 are a set of circuit modules. Client_0 is the source circuit module, and the read / write interface assigned to Client_0 is read / write interface 0, which is the first read / write interface. Target_2 is the destination circuit module, and the read / write interface assigned to Target_2 is read / write interface 5, which is the second read / write interface.

[0077] Since the source circuit module and destination circuit module to be tested for data interaction are preset, the first read / write interface and the second read / write interface can also be determined. This allows us to filter out the data that interacts with the second read / write interface from the data transmitted through the first read / write interface, which is then used as the first data. The first data includes data transmitted from the first read / write interface to the second read / write interface and data transmitted from the second read / write interface. Furthermore, we can filter out the data that interacts with the first read / write interface from the data transmitted through the second read / write interface, which is then used as the second data. The second data includes data transmitted from the second read / write interface to the first read / write interface and data transmitted from the first read / write interface.

[0078] When detecting data transmitted in the read / write interface, on the one hand, an interface component can be defined according to the nature of the data transmitted by the cross_bar interface, and a clocking block for the interface signal can be defined in the interface component; on the other hand, the data transmitted in the read / write interface can be collected, and then the defined interface component and the collected data can be bound and instantiated to connect the interface component with the collected data, thereby obtaining the data transmitted in the read / write interface.

[0079] Step S202: Detect whether the first data satisfies the preset time constraints and attribute constraints, and detect whether the second data satisfies the time constraints and attribute constraints. If both the first data and the second data satisfy the time constraints and attribute constraints, then execute step S203.

[0080] For an introduction to timing constraints and attribute constraints, please refer to the subsequent embodiments; they will not be detailed here.

[0081] In this step, the timing sequence of the first data can be compared with the timing sequence specified in the timing constraints. If the timing sequence of the first data matches the timing sequence specified in the timing constraints, then the first data satisfies the timing constraints. Furthermore, the attributes of the first data can be compared with the attributes specified in the attribute constraints. If the attributes of the first data match the attributes specified in the attribute constraints, then the first data satisfies the attribute constraints. Similarly, for the second data, the timing constraints and attribute constraints can also be compared to determine whether the second data satisfies both the timing constraints and attribute constraints.

[0082] If the detection determines that both the first data and the second data satisfy the timing constraints and attribute constraints, it indicates that the first data and the second data are the same data. This means that the cross-connect bus can accurately perform data routing between the first read / write interface and the second read / write interface. The source circuit module and the destination circuit module can achieve correct data interaction through the first read / write interface and the second read / write interface. At this point, step S203 can be executed.

[0083] Step S203: Confirm that the data exchange between the source circuit module and the destination circuit module is correct.

[0084] As can be seen from the above, when performing data interaction detection using the solution provided in the embodiments of this application, if both the first data and the second data satisfy the timing constraints and attribute constraints, it indicates that the first data and the second data are the same data. This further indicates that the cross-connect bus can accurately perform data routing between the first read / write interface and the second read / write interface, and the source circuit module and the destination circuit module can achieve correct data interaction through the first read / write interface and the second read / write interface.

[0085] Furthermore, the execution entity of the data interaction detection scheme provided in this application obtains data at the read / write interface of the cross-connect bus without affecting the cross-connect bus itself, thus separating the data interaction detection from the data interaction process between modules. Therefore, the data interaction detection scheme provided in this application can be applied to scenarios of data interaction detection in complex chips, realizing direct binding at the code level, eliminating the need to develop complex verification scenarios, and enabling convenient, fast, and efficient data interaction detection.

[0086] The timing constraints and attribute constraints mentioned in step S202 above will be introduced below.

[0087] 1. Timing constraints

[0088] Timing constraints specify the timing of data transmitted through the read / write interface.

[0089] The timing constraints mentioned above are pre-set constraints in the detection equipment; timing refers to the chronological order of data transmission. Before setting timing constraints, users can create clock signals and reset signals, and then set the timing constraints for various data according to the clock signals and reset signals.

[0090] In one embodiment of this application, the timing constraints include the timing of at least one of the following four types of data:

[0091] Packet start flag, packet end flag, packet validity flag, and data to be transmitted in the data packet.

[0092] 1.1 Package start mark

[0093] The full name of the packet start flag is "start of packet," abbreviated as "sop." This flag is located in the packet header and indicates the beginning of a packet.

[0094] 1.2 Packet end marker

[0095] The full name of the packet end marker is "end of packet," abbreviated as "eop." This marker is located at the end of a data packet and indicates the end of the packet.

[0096] 1.3. Packaging Validity Mark

[0097] The packet validity flag, also known as the push flag, is used to identify the valid portion of data during data transmission.

[0098] 1.4 Data to be transmitted in the data packet

[0099] The data to be transmitted in a data packet can be understood as the data that actually needs to be transmitted.

[0100] See Figure 3a , Figure 3b The diagrams show the timing constraints for read and write operations, respectively. Figure 3a and Figure 3b This includes clock signals, reset signals, packet start flags, packet end flags, packet validity flags, and the timing of the data to be transmitted. Figure 3a The data to be transmitted are data 0 (DATA0) and data 1 (DATA1). Figure 3b The data to be transmitted are data 0 (DATA0), data 1 (DATA1), data 2 (DATA2), and data 3 (DATA3).

[0101] exist Figure 3a , Figure 3b When the reset signal is low, it indicates that the reset signal is valid, and the chip performs a reset operation.

[0102] In this solution, timing constraints include the timing of at least one of the following four types of data: packet start flag, packet end flag, packet validity flag, and data to be transmitted in the data packet. Users can set these according to their own needs, which can improve the user experience.

[0103] 2. Attribute Constraints

[0104] The aforementioned attribute constraints specify the attributes of the data transmitted through the first read / write interface and the second read / write interface.

[0105] Similar to timing constraints, the attribute constraints mentioned above are also pre-set constraints in the detection device. Data attributes include the ID of the first read / write interface, the ID of the second read / write interface, and so on.

[0106] In one embodiment of this application, the attributes of the data include at least one of the following:

[0107] 2.1 Read / Write Operation Types

[0108] Read and write operations include two types: read operations and write operations.

[0109] 2.2 Addresses accessed by read / write operations

[0110] The address accessed by the read / write operation is the address accessed by the source circuit module in the destination circuit module through the read / write operation.

[0111] 2.3 Data identification information.

[0112] Data identification information represents the data read or written during read / write operations, and is used to distinguish data under different read / write operations.

[0113] In this solution, data attributes include at least one of three types: read / write operation type, address accessed by the read / write operation, and data identification information. Users can set these attributes according to their needs, thus improving the user experience. Furthermore, the attribute constraints define the data attributes, which is equivalent to mathematically representing the data to be detected. Users can directly set the attribute constraints to detect the specific data they want. Different data transmissions between circuit modules enable different chip functions. Therefore, data interaction detection can also be seen as chip function detection. Adjusting the attribute constraints allows for the detection of different chip functions, enabling a comprehensive, formalized detection of chip functionality.

[0114] In another embodiment of this application, when setting attribute constraints in the detection device, attribute constraints can be set according to the definition of the data transmitted by the circuit module through cross_bar. That is, for the data to be transmitted, which attributes are defined in advance when defining the data (i.e., specifying what the data needs to carry when the circuit module interacts), can be constrained for which attributes. Furthermore, the constraints can be set by assertion, that is, given the attribute value of the data, the given attribute value is used as the real value. Subsequently, based on this, the data to be detected is checked to see if there is data that is incorrect with these given values. If so, the data interaction error is directly determined.

[0115] Each read / write interface of cross_bar logically includes two channels: a read channel and a write channel. Therefore, Figure 1 The structural diagram shown can be further refined as follows: Figure 4 The diagram shows the structural schematic. Figure 4 In the diagram, cross_bar contains the following components connected from left to right: the read / write interface connected to the source circuit module, IVQ (Input Virtual Queue), cross_bar exchange matrix, OVQ (Output Virtual Queue), and the read / write interface connected to the destination circuit module.

[0116] Each read / write interface is connected to a circuit module, and logically, each read / write interface includes both read and write channels. Each channel in the client-side read / write interface (i.e., the interface connected to the client) corresponds to a queue in the IVQ, while each channel in the target-side read / write interface (i.e., the interface connected to the target) corresponds to a queue in the OVQ. The queues in the IVQ and OVQ are typically constructed according to the FIFO (First In First Out) principle.

[0117] from Figure 4As can be seen, read / write interface 0 includes read channel 0 (XBAR_RD_0) and write channel 0 (XBAR_WR_0); read / write interface 1 includes read channel 1 (XBAR_RD_1) and write channel 1 (XBAR_WR_1); read / write interface 2 includes read channel 2 (XBAR_RD_2) and write channel 2 (XBAR_WR_2); read / write interface 3 includes read channel 3 (XBAR_RD_3) and write channel 3 (XBAR_WR_3); read / write interface 4 includes read channel 4 (XBAR_RD_4) and write channel 4 (XBAR_WR_4); read / write interface 5 includes read channel 5 (XBAR_RD_5) and write channel 5 (XBAR_WR_5); read / write interface 6 includes read channel 6 (XBAR_RD_6) and write channel 6 (XBAR_WR_6).

[0118] The following section uses the data interaction between Client_0 and Target_2 as an example to introduce the process of data interaction between the client and target through cross_bar.

[0119] 1. Client_0 writes data to Target_2

[0120] Client_0 sends a write request to cross_bar through XBAR_WR_0 in read / write interface 0. After the write request is sent, it sends the data to be written to the target to cross_bar. The write request and the data to be written are first cached in the IVQ queue corresponding to XBAR_WR_0. Then, according to the FIFO principle, they are exchanged by the cross_bar exchange matrix to, or routed to, the OVQ queue corresponding to the write channel contained in the read / write interface connected to Target_2, that is, routed to the OVQ queue corresponding to XBAR_WR_5. Then, they are transmitted to Target_2 through XBAR_WR_5. After receiving the write request, Target_2 stores the data to be written, thus completing the data writing.

[0121] 2. Client_0 reads data from Target_2

[0122] Client_0 sends a read request to cross_bar via XBAR_RD_0 in read / write interface 0. This request is first cached in the IVQ queue corresponding to XBAR_RD_0, and then, according to the FIFO principle, is routed by the cross_bar switching matrix to the OVQ queue corresponding to the read channel of the read / write interface connected to Target_2, i.e., routed to the OVQ queue corresponding to XBAR_RD_5. It is then transmitted to Target_2 via XBAR_RD_5. Target_2, upon receiving the read request, reads the corresponding data and sends the read data to cross_bar via XBAR_RD_5. Similarly, the read data is first cached in the OVQ queue corresponding to XBAR_RD_5, then routed through the cross_bar switching matrix to the IVQ queue corresponding to XBAR_RD_0, and finally transmitted to Client_0 via XBAR_RD_0, thus completing the data reading process.

[0123] In view of this, in one embodiment of this application, the first read / write interface may include a first write channel and a first read channel, the second read / write interface may include a second write channel and a second read channel, the timing constraints may include write data timing constraints and read data timing constraints, and the attribute constraints may include write data attribute constraints and read data attribute constraints.

[0124] Because the read / write interface includes both read and write channels, the data transmitted through the read / write interface also includes data transmitted through both the write and read channels. Therefore, when checking whether the first and second data satisfy timing and attribute constraints, the following two detection methods can be used:

[0125] The first detection method involves detecting whether the data transmitted through the first write channel in the first data satisfies the write data timing constraints and write data attribute constraints, and also detecting whether the data transmitted through the second write channel in the second data satisfies the write data timing constraints and write data attribute constraints.

[0126] The second type of detection: Detect whether the data transmitted through the first read channel in the first data satisfies the read data timing constraints and read data attribute constraints, and detect whether the data transmitted through the second read channel in the second data satisfies the read data timing constraints and read data attribute constraints.

[0127] For ease of description, the data transmitted through the first write channel in the first data is referred to as the first write data, the data transmitted through the second write channel in the second data is referred to as the second write data, the data transmitted through the first read channel in the first data is referred to as the first read data, and the data transmitted through the second read channel in the second data is referred to as the second read data.

[0128] For the first type of detection mentioned above, the timing of the first written data can be compared with the timing specified in the writing data timing constraint, and the attributes of the first written data can be compared with the attributes specified in the writing data attribute constraint; the timing of the second written data can be compared with the timing specified in the writing data timing constraint, and the attributes of the second written data can be compared with the attributes specified in the writing data attribute constraint.

[0129] For the second type of detection mentioned above, the timing of the first read data can be compared with the timing specified in the read data timing constraint, and the attributes of the first read data can be compared with the attributes specified in the read data attribute constraint; the timing of the second read data can be compared with the timing specified in the read data timing constraint, and the attributes of the second read data can be compared with the attributes specified in the read data attribute constraint.

[0130] If the comparison results of the above four types of data are consistent, it is determined that the first data and the second data satisfy the timing constraints and attribute constraints, and the source circuit module and the destination circuit module can correctly exchange data through the first read / write interface and the second read / write interface. Otherwise, it is determined that the data exchange between the source circuit module and the destination circuit module through the first read / write interface and the second read / write interface is incorrect.

[0131] As can be seen from the above, when using the solution provided in the embodiments of this application for data interaction detection, more refined timing constraints and attribute constraints are set for read and write operations between circuit modules. This allows for accurate detection of whether the data interaction between the source and destination circuit modules is correct. Therefore, the data interaction detection solution provided in the embodiments of this application can improve the accuracy of data interaction detection.

[0132] In one embodiment of this application, in accordance with the foregoing Figure 3a , Figure 3b During the timing constraint testing process, the testing can be performed in the following manner:

[0133] Since the circuit modules exchange data according to clock signals, the detection device can also perform detection based on clock signals. For example, detection can be performed at each rising edge of the clock signal. In addition, if a reset signal is preset, it is also necessary to detect whether the reset signal is valid, that is, to perform detection at each rising edge of the clock signal when the reset signal is invalid.

[0134] Next, the packet start flag and packet end flag can be detected. If the packet start flag is high and the packet end flag is low, it means that the data packet has started to be transmitted and has not yet ended. At this time, the preset transmission flag bit can be set to 1. Otherwise, if the packet end flag is high, it means that the data packet transmission has ended. At this time, the transmission flag bit should be cleared.

[0135] After detecting the packet start and end markers, the following two assertion checks can be performed using assertion checks:

[0136] First type of assertion detection:

[0137] First, this detection can also be performed on the rising edge of the clock signal when the reset signal is invalid. During the detection, it first checks whether the preconditions (the end-of-packet flag is high and the start-of-packet flag is low) are met. If they are met, it then checks whether the transmission flag bit is 1. If it is, the detection passes; otherwise, it reports an error.

[0138] The second type of assertion detection:

[0139] Similarly, the detection timing is the moment when the signal rises and the reset signal is invalid. During detection, the data attributes must meet the attributes specified in the attribute constraints. For example, the read / write interface on the source circuit module side must be the first read / write interface, the read / write interface on the destination circuit module side must be the second read / write interface, the read / write operation type must be the specified type, the address accessed by the read / write operation must be the specified address, and the data identification information must be the specified information.

[0140] If all attributes of the data satisfy the attributes specified in the attribute constraints, the test passes; otherwise, an error is reported directly.

[0141] Finally, if both assertion checks pass, the data is determined to satisfy the temporal and attribute constraints.

[0142] If a credit mechanism exists during data interaction between circuit modules in the chip via cross_bar, a preset data buffer exists on the destination circuit module's side to cache the data to be processed. The size of this data buffer represents the maximum amount of data the destination circuit module can process. During the interaction between the source and destination circuit modules, the destination circuit module can continuously synchronize the data buffer status with the source circuit module. This includes: when the data buffer is free, the destination circuit module notifies the source circuit module that the data buffer is free, allowing the source circuit module to send more data; when the data buffer is insufficient, the destination circuit module does not send any signal.

[0143] In view of this, in addition to detecting whether the first data and the second data meet the timing constraints and attribute constraints, the detection device can also detect whether an acknowledgment signal is transmitted in the second write channel, provided that the free space in the data buffer corresponding to the second read / write interface is not less than the preset space size.

[0144] The response signal is used to notify the source circuit module that the data buffer is available.

[0145] The above preset space size is a pre-set space size.

[0146] Specifically, the detection device can determine whether the free space in the data buffer is lower than the preset space size in the following two ways.

[0147] The first method:

[0148] The detection device can directly read the free space in the data buffer corresponding to the second read / write interface and compare it with the preset space size.

[0149] The second method:

[0150] If the cross-connect bus or destination circuit module determines that the free space in the data buffer corresponding to the second read / write interface is not less than the preset space size, it can actively send a notification to the detection device. In this way, the detection device can determine whether the free space in the data buffer is less than the preset space size based on whether it receives the notification.

[0151] If the free space in the data buffer corresponding to the second read / write interface is not less than the preset space size, the detection device can detect whether the data transmitted by the second write channel meets the following condition using an assertion detection method: the acknowledgment signal must be high (i.e., the second write channel has transmitted an acknowledgment signal). If this condition is met, it is determined that the second write channel has transmitted an acknowledgment signal.

[0152] If the detection device detects that both the first and second data satisfy the timing and attribute constraints, and detects that the second write channel has transmitted an acknowledgment signal, then it can be determined that the data interaction between the source circuit module and the destination circuit module is correct.

[0153] As can be seen from the above, when using the solution provided in the embodiments of this application for data interaction detection, the detection device not only detects whether the first data and the second data meet the timing constraints and attribute constraints, but also detects the consumption of the data buffer on the target circuit module side. This can more accurately determine whether the data interaction between the source circuit module and the target circuit module is normal. Therefore, the data interaction detection solution provided in the embodiments of this application can improve the accuracy of data interaction detection.

[0154] Based on the credit mechanism in the aforementioned interaction process, for the source circuit module, after receiving the response signal, both parties involved in the data interaction can agree in advance not to send a control response signal indicating that the response signal has been received back to the destination circuit module, or they can send back the control response signal.

[0155] Under the condition that the source circuit module is required to send a control response signal to the destination circuit module, the detection device can also detect whether the first read channel transmits a control response signal within the target time period. If the first data and the second data both meet the timing constraints and attribute constraints, the second write channel transmits a response signal, and the first read channel transmits a control response signal within the target time period, then it is determined that the data interaction between the source circuit module and the destination circuit module is correct.

[0156] The target time period is a time period with the signal feedback time as the starting time and a duration of a preset number of clock cycles. The signal feedback time is the time when the second write channel transmits the response signal. The control response signal indicates that the source circuit module has received the response signal.

[0157] The above preset quantities are pre-set quantities, such as 3, 4, etc.

[0158] In one embodiment of this application, when the timing constraint is Figure 3a , Figure 3b Under the constraints shown, if the source circuit module and the destination circuit module interact normally according to the timing constraints, the relationship between the control response signal and the timing of each data in the timing constraints should be as follows: Figure 5a , Figure 5b As shown, Figure 5a and Figure 5b In this process, the timing of the control response signal and each data in the timing constraint differs by a maximum of two clock cycles. Therefore, when determining the target time period, the preset quantity can be set to a value greater than or equal to 2.

[0159] Specifically, when the aforementioned detection device determines that the free space in the data buffer is not less than the preset space size, in addition to detecting whether an acknowledgment signal is transmitted in the second write channel on the target circuit module (or the second read / write interface) side, it can also determine the time when the second write channel transmits the acknowledgment signal after detecting that an acknowledgment signal is transmitted in the second write channel, that is, determine the signal feedback time, thereby determining the target time period based on the signal feedback time, and on the source circuit module (or the first read / write interface) side, detecting whether the first read channel transmits a control acknowledgment signal within the target time period.

[0160] If both the first and second data satisfy the timing and attribute constraints, and the destination circuit module correctly transmits the response signal to the source circuit module through the second write channel, and the source circuit module correctly transmits the control response signal to the destination circuit module through the first read channel, then the entire data interaction process is error-free, and it can be determined that the data interaction between the source circuit module and the destination circuit module is correct.

[0161] As can be seen from the above, when using the solution in the embodiments of this application for data interaction detection, the detection device detects whether the first data and the second data meet the timing constraints and attribute constraints, and also detects the consumption of the data buffer on the side of the destination circuit module, and whether the source circuit module transmits a control response signal to the destination circuit module. This can more accurately determine whether the data interaction between the source circuit module and the destination circuit module is normal. Therefore, the data interaction detection solution provided in the embodiments of this application can improve the accuracy of data interaction detection.

[0162] Corresponding to the aforementioned data interaction method, this application also provides a data interaction device.

[0163] In one embodiment of this application, see Figure 6 A schematic diagram of a data interaction detection device is provided. In this embodiment, the device includes:

[0164] The data acquisition unit 601 is used to acquire first data exchanged between the source circuit module and the destination circuit module transmitted through the first read / write interface, and to acquire second data exchanged between the source circuit module and the destination circuit module transmitted through the second read / write interface. The first read / write interface and the second read / write interface are both read / write interfaces on the cross-connect bus included in the network processor chip. The source circuit module is a circuit module on the network processor chip that is assigned the first read / write interface, and the destination circuit module is a circuit module on the network processor chip that is assigned the second read / write interface.

[0165] The constraint detection unit 602 is used to detect whether the first data satisfies the preset timing constraints and attribute constraints, and to detect whether the second data satisfies the timing constraints and attribute constraints. If both the first data and the second data satisfy the timing constraints and attribute constraints, the interaction determination unit 603 is triggered. The timing constraints specify the timing of the data exchanged between the source circuit module and the destination circuit module, and the attribute constraints specify the attributes of the data exchanged between the source circuit module and the destination circuit module.

[0166] The interaction determination unit 603 is used to determine that the data interaction between the source circuit module and the destination circuit module is correct.

[0167] As can be seen from the above, when performing data interaction detection using the solution provided in the embodiments of this application, if both the first data and the second data satisfy the timing constraints and attribute constraints, it indicates that the first data and the second data are the same data. This further indicates that the cross-connect bus can accurately perform data routing between the first read / write interface and the second read / write interface, and the source circuit module and the destination circuit module can achieve correct data interaction through the first read / write interface and the second read / write interface.

[0168] Furthermore, the execution entity of the data interaction detection scheme provided in this application obtains data at the read / write interface of the cross-connect bus without affecting the cross-connect bus itself, thus separating the data interaction detection from the data interaction process between modules. Therefore, the data interaction detection scheme provided in this application can be applied to scenarios of data interaction detection in complex chips, realizing direct binding at the code level, eliminating the need to develop complex verification scenarios, and enabling convenient, fast, and efficient data interaction detection.

[0169] In one embodiment of this application, the first read / write interface includes a first write channel and a first read channel, the second read / write interface includes a second write channel and a second read channel, the timing constraints include write data timing constraints and read data timing constraints, and the attribute constraints include write data attribute constraints and read data attribute constraints.

[0170] The constraint detection unit 602 is specifically used for:

[0171] Detect whether the data transmitted through the first write channel in the first data satisfies the write data timing constraints and write data attribute constraints, and detect whether the data transmitted through the second write channel in the second data satisfies the write data timing constraints and write data attribute constraints;

[0172] The system detects whether the data transmitted through the first read channel in the first data satisfies the read data timing constraints and read data attribute constraints, and detects whether the data transmitted through the second read channel in the second data satisfies the read data timing constraints and read data attribute constraints.

[0173] As can be seen from the above, when using the solution provided in the embodiments of this application for data interaction detection, more refined timing constraints and attribute constraints are set for read and write operations between circuit modules. This allows for accurate detection of whether the data interaction between the source and destination circuit modules is correct. Therefore, the data interaction detection solution provided in the embodiments of this application can improve the accuracy of data interaction detection.

[0174] In one embodiment of this application, the interaction determination unit 603 includes:

[0175] The first detection subunit is used to detect whether an acknowledgment signal is transmitted in the second write channel if the free space in the data buffer corresponding to the second read / write interface is not less than a preset space size. If the first data and the second data both satisfy the timing constraints and attribute constraints, and the second write channel transmits the acknowledgment signal, then the interaction determination subunit is triggered. The acknowledgment signal is used to notify the source circuit module that the data buffer is free.

[0176] The interaction determination subunit is used to determine that the data interaction between the source circuit module and the destination circuit module is correct.

[0177] As can be seen from the above, when using the solution provided in the embodiments of this application for data interaction detection, the detection device not only detects whether the first data and the second data meet the timing constraints and attribute constraints, but also detects the consumption of the data buffer on the target circuit module side. This can more accurately determine whether the data interaction between the source circuit module and the target circuit module is normal. Therefore, the data interaction detection solution provided in the embodiments of this application can improve the accuracy of data interaction detection.

[0178] In one embodiment of this application, the interactive determination subunit is specifically used for:

[0179] Detect whether the first read channel transmits a control response signal within a target time period, wherein the target time period is a time period with a signal feedback time as the start time and a duration of a preset number of clock cycles, the signal feedback time is the time when the second write channel transmits the response signal, and the control response signal indicates that the source circuit module has received the response signal;

[0180] If both the first data and the second data satisfy the timing constraints and attribute constraints, the second write channel transmits the response signal, and the first read channel transmits the control response signal within the target time period, then it is determined that the data interaction between the source circuit module and the destination circuit module is correct.

[0181] As can be seen from the above, when using the solution in the embodiments of this application for data interaction detection, the detection device detects whether the first data and the second data meet the timing constraints and attribute constraints, and also detects the consumption of the data buffer on the side of the destination circuit module, and whether the source circuit module transmits a control response signal to the destination circuit module. This can more accurately determine whether the data interaction between the source circuit module and the destination circuit module is normal. Therefore, the data interaction detection solution provided in the embodiments of this application can improve the accuracy of data interaction detection.

[0182] In one embodiment of this application, the timing constraint includes the timing of at least one of the following data:

[0183] Packet start flag, packet end flag, packet validity flag, and data to be transmitted in the data packet.

[0184] In this solution, timing constraints include the timing of at least one of the following four types of data: packet start flag, packet end flag, packet validity flag, and data to be transmitted in the data packet. Users can set these according to their own needs, which can improve the user experience.

[0185] In one embodiment of this application, the attributes of the data include at least one of the following:

[0186] Read / write operation type, address accessed by the read / write operation, and data identification information.

[0187] In this solution, data attributes include at least one of three types: read / write operation type, address accessed by the read / write operation, and data identification information. Users can set these attributes according to their needs, thus improving the user experience. Furthermore, the attribute constraints define the data attributes, which is equivalent to mathematically representing the data to be detected. Users can directly set the attribute constraints to detect the specific data they want. Different data transmissions between circuit modules enable different chip functions. Therefore, data interaction detection can also be seen as chip function detection. Adjusting the attribute constraints allows for the detection of different chip functions, enabling a comprehensive, formalized detection of chip functionality.

[0188] This invention also provides an electronic device, such as... Figure 7 As shown, it includes a processor 701, a communication interface 702, a memory 703, and a communication bus 704, wherein the processor 701, the communication interface 702, and the memory 703 communicate with each other through the communication bus 704.

[0189] Memory 703 is used to store computer programs;

[0190] When the processor 701 executes the program stored in the memory 703, it implements the steps of any of the above-described data interaction detection methods.

[0191] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0192] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0193] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0194] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0195] In another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, it implements the steps of any of the above-described data interaction detection methods.

[0196] In another embodiment of the present invention, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the data interaction detection methods described in the above embodiments.

[0197] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0198] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0199] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, computer-readable storage media, and computer program products are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0200] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A data interaction detection method, characterized in that, The method includes: The system obtains first data exchanged between the source circuit module and the destination circuit module transmitted through the first read / write interface, and obtains second data exchanged between the source circuit module and the destination circuit module transmitted through the second read / write interface. Both the first and second read / write interfaces are read / write interfaces on the cross-connect bus included in the network processor chip. The source circuit module is a circuit module on the network processor chip that is equipped with the first read / write interface, and the destination circuit module is a circuit module on the network processor chip that is equipped with the second read / write interface. The system detects whether the first data satisfies preset timing constraints and attribute constraints, and detects whether the second data satisfies the timing constraints and attribute constraints, wherein the timing constraints specify the timing of the data exchanged between the source circuit module and the destination circuit module, and the attribute constraints specify the attributes of the data exchanged between the source circuit module and the destination circuit module. If both the first data and the second data satisfy the timing constraints and attribute constraints, then the data interaction between the source circuit module and the destination circuit module is determined to be correct.

2. The method according to claim 1, characterized in that, The first read / write interface includes a first write channel and a first read channel; the second read / write interface includes a second write channel and a second read channel; the timing constraints include write data timing constraints and read data timing constraints; and the attribute constraints include write data attribute constraints and read data attribute constraints. The step of detecting whether the first data satisfies the preset time constraints and attribute constraints, and detecting whether the second data satisfies the time constraints and attribute constraints, includes: Detect whether the data transmitted through the first write channel in the first data satisfies the write data timing constraints and write data attribute constraints, and detect whether the data transmitted through the second write channel in the second data satisfies the write data timing constraints and write data attribute constraints; The system detects whether the data transmitted through the first read channel in the first data satisfies the read data timing constraints and read data attribute constraints, and detects whether the data transmitted through the second read channel in the second data satisfies the read data timing constraints and read data attribute constraints.

3. The method according to claim 2, characterized in that, If both the first data and the second data satisfy the timing constraints and attribute constraints, then determining that the data interaction between the source circuit module and the destination circuit module is correct includes: If the free space in the data buffer corresponding to the second read / write interface is not less than the preset space size, then it is detected whether an acknowledgment signal is transmitted in the second write channel, wherein the acknowledgment signal is used to notify the source circuit module that the data buffer is free; If both the first data and the second data satisfy the timing constraints and attribute constraints, and the second write channel transmits the response signal, then it is determined that the data interaction between the source circuit module and the destination circuit module is correct.

4. The method according to claim 3, characterized in that, If both the first data and the second data satisfy the timing constraints and attribute constraints, and the second write channel transmits the response signal, then determining that the data interaction between the source circuit module and the destination circuit module is correct includes: Detect whether the first read channel transmits a control response signal within a target time period, wherein the target time period is a time period with a signal feedback time as the start time and a duration of a preset number of clock cycles, the signal feedback time is the time when the second write channel transmits the response signal, and the control response signal indicates that the source circuit module has received the response signal; If both the first data and the second data satisfy the timing constraints and attribute constraints, the second write channel transmits the response signal, and the first read channel transmits the control response signal within the target time period, then it is determined that the data interaction between the source circuit module and the destination circuit module is correct.

5. The method according to any one of claims 1-4, characterized in that, The timing constraints include the timing of at least one of the following data: Packet start flag, packet end flag, packet validity flag, and data to be transmitted in the data packet.

6. The method according to any one of claims 1-4, characterized in that, The attributes of the data include at least one of the following: Read / write operation type, address accessed by the read / write operation, and data identification information.

7. A data interaction detection device, characterized in that, The device includes: A data acquisition unit is used to acquire first data exchanged between a source circuit module and a destination circuit module transmitted via a first read / write interface, and to acquire second data exchanged between the source circuit module and the destination circuit module transmitted via a second read / write interface. The first read / write interface and the second read / write interface are both read / write interfaces on a cross-connect bus included in the network processor chip. The source circuit module is a circuit module on the network processor chip that is equipped with the first read / write interface, and the destination circuit module is a circuit module on the network processor chip that is equipped with the second read / write interface. A constraint detection unit is used to detect whether the first data satisfies preset timing constraints and attribute constraints, and to detect whether the second data satisfies the timing constraints and attribute constraints. If both the first data and the second data satisfy the timing constraints and attribute constraints, an interaction determination unit is triggered. The timing constraints specify the timing of the data exchanged between the source circuit module and the destination circuit module, and the attribute constraints specify the attributes of the data exchanged between the source circuit module and the destination circuit module. The interaction determination unit is used to determine that the data interaction between the source circuit module and the destination circuit module is correct.

8. The apparatus according to claim 7, characterized in that, The first read / write interface includes a first write channel and a first read channel; the second read / write interface includes a second write channel and a second read channel; the timing constraints include write data timing constraints and read data timing constraints; and the attribute constraints include write data attribute constraints and read data attribute constraints. The constraint detection unit is specifically used for: Detect whether the data transmitted through the first write channel in the first data satisfies the write data timing constraints and write data attribute constraints, and detect whether the data transmitted through the second write channel in the second data satisfies the write data timing constraints and write data attribute constraints; The system detects whether the data transmitted through the first read channel in the first data satisfies the read data timing constraints and read data attribute constraints, and detects whether the data transmitted through the second read channel in the second data satisfies the read data timing constraints and read data attribute constraints.

9. The apparatus according to claim 8, characterized in that, The interaction determination unit includes: The first detection subunit is used to detect whether an acknowledgment signal is transmitted in the second write channel if the free space in the data buffer corresponding to the second read / write interface is not less than a preset space size. If the first data and the second data both satisfy the timing constraints and attribute constraints, and the second write channel transmits the acknowledgment signal, then the interaction determination subunit is triggered. The acknowledgment signal is used to notify the source circuit module that the data buffer is free. The interaction determination subunit is used to determine that the data interaction between the source circuit module and the destination circuit module is correct.

10. The apparatus according to claim 9, characterized in that, The interactive determination subunit is specifically used for: Detect whether the first read channel transmits a control response signal within a target time period, wherein the target time period is a time period with a signal feedback time as the start time and a duration of a preset number of clock cycles, the signal feedback time is the time when the second write channel transmits the response signal, and the control response signal indicates that the source circuit module has received the response signal; If both the first data and the second data satisfy the timing constraints and attribute constraints, the second write channel transmits the response signal, and the first read channel transmits the control response signal within the target time period, then it is determined that the data interaction between the source circuit module and the destination circuit module is correct.

11. The apparatus according to any one of claims 7-10, characterized in that, The timing constraints include the timing of at least one of the following data: Packet start flag, packet end flag, packet validity flag, and data to be transmitted in the data packet.

12. The apparatus according to any one of claims 7-10, characterized in that, The attributes of the data include at least one of the following: Read / write operation type, address accessed by the read / write operation, and data identification information.

13. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method described in any one of claims 1-6.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-6.

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