Cache folded grid FPGA acceleration system and method

Abstract

The technical scheme of the invention discloses a cache folding grid FPGA acceleration system and a cache folding grid FPGA acceleration method. According to the method, under the condition that on-chip storage resources are limited, through a data organization and access mechanism in which on-chip storage and off-chip storage are coordinated, extensible and efficient solving of the problem of minimum cut and maximum flow of a large-scale grid diagram is achieved; the method is characterized in that a label mapping cache mechanism is introduced aiming at an existing implementation mode of loading grid graph data into an on-chip memory of an FPGA (Field Programmable Gate Array) at one time; according to the method, a boundary buffer area is arranged in a boundary processor and used for temporarily storing key states related to cross-block boundaries and updating information to be submitted;

Description

Technical Field

[0001] This invention relates to an FPGA accelerator architecture and its implementation method for minimum cut maximum flow computation of large-scale lattice graphs, belonging to the field of reconfigurable computing hardware acceleration technology. Background Technology

[0002] The maximum flow minimum cut algorithm is widely used in computer vision, image processing, and other fields. However, existing implementations still suffer from performance bottlenecks, limiting its further application and promotion in these areas. This is because the algorithm has high computational complexity, strong data and control dependencies, and often requires frequent random accesses to off-chip memory during computation, resulting in long overall runtime and low computational efficiency.

[0003] On general computing platforms such as CPUs and GPUs, existing works [1-3] have optimized the maximum flow minimum cut algorithm for lattice graphs. However, due to the limitations of computation-storage architecture and off-chip memory access overhead, the end-to-end runtime of the algorithm is still difficult to significantly reduce, making it difficult to meet the latency requirements of some real-time applications. For example, in 4K image segmentation scenarios, it is often necessary to complete the solution based on maximum flow minimum cut within about 100 ms.

[0004] Compared to general-purpose computing platforms such as CPUs and GPUs, FPGAs are highly reconfigurable and can customize computing and storage architectures according to algorithm characteristics, thereby alleviating the performance bottlenecks caused by general-purpose computing architectures. In recent years, FPGA acceleration research for the maximum flow minimum cut problem [4-7] has mainly focused on parallel computing acceleration and tends to store lattice graph-related data in the FPGA's on-chip memory as much as possible to reduce the number of accesses to off-chip memory and reduce memory access overhead. However, the FPGA accelerators mentioned above usually rely on storing graph data in on-chip memory as much as possible, and the size of the lattice graphs they can process is limited by the on-chip storage capacity, and can only support lattice graphs with a maximum of about 2 million nodes.

[0005] References [1] O. Jamriska, D. Sýkora, and A. Hornung, “Cache-efficient graphcuts on structured grids,” in 2012 IEEE Conference on Computer Vision andPattern Recognition, 2012, pp. 3673–3680. [2] J. Liu and J. Sun, "Parallel graph-cuts by adaptive bottom-upmerging," 2010 IEEE Computer Society Conference on Computer Vision andPattern Recognition, San Francisco, CA, USA, 2010, pp. 2181-2188. [3] Y. Peng, L. Chen, F.-X. Ou-Yang, W. Chen, and J.-H. Yong, “JF-cut: A parallel graph cut approach for large-scale image and video,” IEEETransactions on Image Processing, vol. 24, no. 2, pp. 655–666, 2015. [4] Z. Dong, B. Zhang, Y. Jiang, Y. Yu, H. Li and S. Mai, "PEPPR-DWSon FPGA: Elevating Universal Parallelism and Precision Through Pulse-EnhancedPush-Relabel and Diffusion Wave Search," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 1, pp. 157-171,Jan. 2025 [5] G. Yan, X. Liu, F. Chen, H. Wang and Y. Ha, "Ultra-Fast FPGAImplementation of Graph Cut Algorithm With Ripple Push and EarlyTermination," in IEEE Transactions on Circuits and Systems I: Regular Papers,vol. 69, no. 4, pp. 1532-1545, April 2022. [6] G. Yan, X. Liu, H. Wang and Y. Ha, "Fast FPGA Accelerator ofGraph Cut Algorithm with Out-of-order Parallel Execution in Folding GridArchitecture," 2023 60th ACM / IEEE Design Automation Conference (DAC), SanFrancisco, CA, USA, 2023, pp. 1-6. [7] G. Yan, X. Liu, H. Wang and Y. Ha, "Fast FPGA Accelerator ofGraph Cut Algorithm With Threshold Global Relabel and Inertial Push," in IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 9, pp. 3437-3450, Sept. 2025. Summary of the Invention The technical problem to be solved by the present invention is that existing FPGA maximum flow minimum cut accelerators are limited by on-chip storage capacity, making it difficult to efficiently process large-scale lattice map data that cannot be accommodated by on-chip storage. As a result, it is difficult to meet the application scenarios that require high resolution and real-time performance, such as 4K image segmentation tasks based on maximum flow minimum cut.

[0006] To achieve the above objectives, the first aspect of the technical solution of the present invention discloses a cached folded grid FPGA acceleration system for minimum cut maximum flow computation of large-scale lattice graphs, characterized in that it includes: The data segmentation module is used to divide the grid diagram into several rectangular blocks according to a preset block size. The size of each rectangular block is an even multiple of the processor array size, so that the cache folded grid FPGA acceleration system can perform off-chip to on-chip data transfer in units of blocks. The tag mapping cache set in the FPGA accelerator establishes the correspondence between the tile labels of each rectangular tile in the off-chip grid and the on-chip cache slots. When the rectangular tile is loaded onto the chip, the on-chip cache slot number where the current rectangular tile resides is recorded, and the mapping relationship between the current rectangular tile and the corresponding on-chip cache slot number is saved in the tag mapping cache. A boundary buffer set in the boundary processor is used to solve the problem of off-chip data not being ready due to cross-tile boundary access and cache missing. The boundary buffer is used to temporarily store boundary-related status information and delayed update information. When a cache missing occurs when accessing adjacent tile data, the update record related to the current adjacent tile is written into the boundary buffer, the corresponding boundary operation is delayed and submitted, and the top-level controller is reported to load the missing tile. When the missing tile is loaded onto the chip, the data to be processed is read from the boundary buffer and sent to the processing unit located at the boundary, and the processing unit performs update calculations.

[0007] Preferably, the data segmentation module uses zero-padding to process regions that are not divisible at the boundaries of the grid diagram.

[0008] Preferably, a two-dimensional coordinate identifier (X,Y) is assigned to each rectangular block as a block label.

[0009] Preferably, the status information and delayed update information include the height label of the boundary node, excess traffic, and traffic update increments generated by cross-boundary pushes.

[0010] The second aspect of the technical solution of this invention discloses a cached folded grid FPGA acceleration method for minimum cut maximum flow in large-scale lattice graphs. Employing the aforementioned cached folded grid FPGA acceleration system, the method is characterized by comprising the following steps: Step 1: Divide the grid diagram into several rectangular blocks according to the preset block size. The size of each rectangular block is an even multiple of the processor array size. Each rectangular block is assigned a unique block coordinate as a whole unit. The arrangement of nodes within the rectangular block is consistent with the arrangement of processing units in the processor array. Identify and label all rectangular tiles containing at least one seed point as seed tiles, write the tile coordinates of the seed tiles into the tile loading queue of the top-level controller, and initialize the height label of the seed nodes in various sub-tiles to the value one. Step 2: The top-level controller reads the block coordinates of the rectangular blocks to be loaded sequentially from the block loading queue, and assigns an on-chip cache slot number to the current rectangular block through the label mapping cache to record its storage location in the on-chip cache. Then, it triggers the loading of off-chip to on-chip data for the corresponding rectangular block. After the tile data is loaded, the processing unit in the processor array writes the corresponding seed node into the initialization queue FIFO according to the identifier of the seed node in the loaded node data, which is used for subsequent height label initialization and active node initialization processing, thereby starting the minimum cut / maximum flow calculation process. At the same time, the top-level controller generates several copies of the tag mapping cache and distributes all copies to each boundary processor to form a read-only tag cache for each boundary processor; Step 3: The global height relabeling module starts the height relabeling operation, reads and processes the node identifiers in the FIFO in a loop, and updates the height labels of ordinary nodes in pairs until the current FIFO is empty; during the height labeling process, the active node numbers with updated height labels and positive excess traffic are written into the FIFO of the push streaming module for subsequent push streaming processing. Meanwhile, during the above execution process, the processing unit located at the edge of the processor array sends the tile coordinates involved in the current operation to the boundary processor, which performs tile coordinate transformation to access adjacent tile data. The boundary processor queries the read-only tag cache to see if the transformed tile coordinates are already stored on-chip. If not, the current tile coordinates are temporarily stored in the loaded tile queue and reported to the top-level controller as a cached missing tile. In the case of a missing tile, the boundary processor stores the relevant node height data corresponding to the tile currently being executed by the boundary processor in the boundary buffer according to the original tile coordinates before transformation, so as to postpone the operation that cannot be completed temporarily. Step 4: Start the streaming module, continuously read and process the active nodes in its FIFO until the current FIFO is empty, and execute the corresponding streaming operation. During the streaming process, the processing unit located at the edge of the processor array sends the tile coordinates involved in the current operation to the boundary processor, which performs the tile coordinate transformation. The boundary processor checks whether the transformed tile coordinates have been stored in the chip through the read-only tag cache. If not, the current tile coordinates are temporarily stored in the loaded tile queue, and the missing tile identifier is reported to the top-level controller. In the case of missing tiles, the boundary processor stores the relevant node height data corresponding to the tile currently being executed by the boundary processor in the boundary buffer according to the original tile coordinates before transformation, so as to postpone the operation that cannot be completed temporarily. After the streaming process is complete, the top-level controller determines the next step based on the streaming results and the queue status: If any streaming operation is performed during the streaming process, proceed to step 5 for height reset. If the push stream FIFO is empty, it is reported to the top-level controller, which then checks the tile loading queue: if the tile loading queue is not empty, the tile loading operation in step 6 is executed; if the tile loading queue is empty and there are no pending missing requests / boundary delayed updates / dirty data, the data write-back operation in step 7 is executed. Step 5: Start the height reset module to perform unified initialization processing on the height labels of the nodes currently residing in the on-chip cache: reset the height labels of ordinary nodes to value two, and set the height labels of seed nodes to value one, as the initial height reference for subsequent global height remarking operations; then, write the identifier of the seed node into the traversal FIFO of the global remarking module; after completing the above initialization, proceed to step 3 to execute the global height remarking operation. Step 6: Perform the tile loading operation. The top-level controller retrieves a batch of tile coordinates to be loaded from the tile loading queue. For each value, it first checks the label mapping cache: if a match is found, it is used directly; if not, it selects an on-chip cache slot according to the FIFO strategy and, if necessary, writes back dirty blocks. Then, it loads the target tile from off-chip to on-chip and updates the mapping relationship in the label mapping cache. After updating the copy, it redistributes it to the boundary processor to replace the original read-only label cache. After the tile is loaded, it reads the height data and push data of adjacent tiles in the boundary buffer. If the values ​​are valid, it performs the corresponding operations that were interrupted due to missing tiles. When there is any update to the node height, the node is written into the traversal FIFO of the global re-elevation module of the corresponding processing unit. After completion, proceed to step 3. Step 7: After the maximum flow and minimum cut calculations are completed, the updated tile data in the on-chip cache is written back to the off-chip memory according to the tiles, and the final calculation results are generated / output, thus ending this acceleration task.

[0011] Preferably, in step 1, when dividing the rectangular blocks, the areas at the boundary of the grid diagram that are not divisible by an integer are filled with zeros.

[0012] This invention, under conditions of limited on-chip storage resources, achieves scalable and efficient solutions to the minimum cut maximum flow problem of large-scale lattice graphs through a collaborative data organization and access mechanism between on-chip and off-chip storage. Its innovation compared to existing technologies lies in: 1. In response to the existing implementation of loading lattice graph data into the FPGA on-chip memory all at once, this invention introduces a tag mapping caching mechanism to establish a correspondence between tile tags (e.g., tile coordinates (X,Y)) and on-chip cache slots, thereby enabling on-demand loading and dynamic management of tile data. This allows for scalable solutions to the maximum flow / minimum cut problem of large-scale lattice graphs under limited on-chip storage resources.

[0013] 2. This invention sets up a boundary buffer in the boundary processor to temporarily store key states and update information to be committed (such as height labels, excess traffic, and update increments pushed across boundaries) related to cross-tile boundaries. When a cached missing operation occurs while accessing an adjacent tile, the relevant boundary operation is recorded and its commit is delayed. The operation is then merged and updated after the missing tile is loaded, thereby reducing pipeline stalls caused by waiting for off-chip memory access and improving overall computational efficiency. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a lattice diagram divided into tiles, where each dimension of the tile is twice the size of the processor array. Figure 2 This is a schematic diagram of a processor array. In the diagram, PE stands for Processing Unit, BPU stands for Boundary Processor, FIFOs stands for First In First Out Queue, RAM stands for On-Chip Memory, and AXI stands for Communication Protocol. Figure 3 This is a schematic diagram of a processor unit. In the diagram, UltraRAM is a technical term for memory in Xilinx FPGAs, and IOMUX is short for input / output multiplexer. Figure 4 This is a schematic diagram of the top-level controller; Figure 5 This is a schematic diagram of a boundary processor. Detailed Implementation

[0015] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0016] The first aspect of this invention discloses a cached folded mesh FPGA acceleration system for minimum cut maximum flow computation of large-scale lattice graphs, comprising: The data segmentation module divides the grid diagram into several rectangular blocks according to a preset block size. The size of each rectangular block is an even multiple (or 2k times) of the processor array size, enabling the cache folded grid FPGA acceleration system to perform off-chip to on-chip data transfer on a block-by-block basis. For regions located at the boundaries of the grid diagram that are not divisible, the data segmentation module uses zero-padding.

[0017] A tag mapping cache is set up in the FPGA accelerator to establish a correspondence between the tile labels of each rectangular tile in the off-chip grid and the on-chip cache slots. When a rectangular tile is loaded onto the chip, the on-chip cache slot number where the current rectangular tile resides is recorded, and the mapping relationship between the current rectangular tile and the corresponding on-chip cache slot number is stored in the tag mapping cache. In this embodiment of the invention, a two-dimensional coordinate identifier (X, Y) is assigned as the tile label for each rectangular tile.

[0018] A boundary buffer, configured within the boundary processor, addresses the issue of off-chip data insecurity caused by cross-tile boundary access and cache misses. This boundary buffer temporarily stores boundary-related status information and delayed update information, including boundary node height labels, excess traffic, and traffic update increments generated by cross-boundary pushes. When a cache miss occurs while accessing adjacent tile data, update records related to the current adjacent tile are written to the boundary buffer, the corresponding boundary operation is delayed, and the top-level controller is notified that the missing tile needs to be loaded. When the missing tile is loaded onto the chip, the data to be processed is read from the boundary buffer and sent to the processing unit located at the boundary, where update operations are performed. This centralized handling of missing tile issues reduces pipeline stalls caused by the computing array waiting for off-chip memory access.

[0019] A second aspect of this invention discloses a cached folded grid FPGA acceleration method for minimum cut maximum flow in large-scale lattice graphs, comprising the following steps: Step 1: Plot division and seed plot initialization.

[0020] Will as Figure 1 The grid diagram shown is divided into multiple rectangular blocks according to a preset block size, where the size of each rectangular block is an even multiple of the processor array size. Areas at the boundaries that are not divisible by an integer are padded with zeros. Each block is assigned a unique block label as a unit; in this embodiment, the block label is the block coordinate (X, Y). Since the arrangement of nodes within a block is consistent with the arrangement of processing units in the processor array, the two-dimensional coordinates of the processing units implicitly represent the specific coordinates of the nodes within the block. All blocks containing at least one seed point are identified and marked as seed blocks, and the block coordinates of the seed blocks are written into the block loading queue of the top-level controller. Simultaneously, the height labels of the seed nodes in various sub-blocks are initialized to 1.

[0021] Step 2: The processor array begins loading the seed tiles.

[0022] The top-level controller sequentially reads the 2D coordinates (X, Y) of the tiles to be loaded from the tile loading queue, and assigns an on-chip cache slot number (index) to the current tile through the label mapping cache to record its storage location in the on-chip cache. Then, it triggers the loading of off-chip to on-chip data for the corresponding tile. After the tile data is loaded, the processing units in the processor array write the corresponding seed nodes into the initialization queue (FIFO) based on the identifiers of the seed nodes in the loaded node data. This is used for subsequent height label initialization and active node initialization processing, thereby initiating the minimum cut / maximum flow calculation process. Simultaneously, the top-level controller generates several copies of the label mapping cache and distributes all copies to each boundary processor, forming a read-only label cache for each boundary processor.

[0023] Step 3: The global height relabeling module initiates the height relabeling operation, iteratively reading and processing the node identifiers in the FIFO, updating the height labels of paired ordinary nodes until the current FIFO is empty. During the height labeling process, the numbers of active nodes with updated height labels and positive excess traffic are written into the FIFO of the streaming module for subsequent streaming processing.

[0024] Simultaneously, during the aforementioned execution process, the processing units located at the upper and left boundaries of the processor array send the tile coordinates involved in the current operation to the boundary processor. The boundary processor then performs tile coordinate transformation to access adjacent tile data. The boundary processor... Figure 5 The read-only label cache query checks whether the transformed tile coordinates have been stored within the slice. If not, the current tile coordinates are temporarily stored in the loaded tile queue, and the top-level controller is notified that the tile is missing from the cache. In the case of a missing tile, the boundary processor stores the relevant node height data corresponding to the tile currently being executed by the boundary processor in the boundary buffer based on the original tile coordinates before transformation, in order to postpone operations that cannot be completed temporarily.

[0025] Step 4: Start the streaming module, continuously reading and processing the active nodes in its FIFO until the current FIFO is empty, then execute the corresponding streaming operation. During the streaming process, the processing units located at the upper and left boundaries of the processor array send the tile coordinates involved in the current operation to the boundary processor, which then performs the tile coordinate transformation. The boundary processor... Figure 5 The read-only tag cache query checks whether the transformed tile coordinates have been stored within the slice. If no match is found, the current tile coordinates are temporarily stored in the loaded tile queue, and the missing tile identifier is reported to the top-level controller. In the case of a missing tile as described in step 3, the boundary processor stores the relevant node traffic data corresponding to the tile currently being executed by the boundary processor in the boundary buffer based on the original tile coordinates before transformation, in order to postpone the push operation that cannot be completed temporarily.

[0026] After the streaming process is complete, the top-level controller determines the next step based on the streaming results and the queue status: (1) If any streaming operation is performed during the streaming process, proceed to step 5 for height reset operation; (2) If the push stream FIFO is empty, it is reported to the top-level controller, which checks the tile loading queue: when the tile loading queue is not empty, the tile loading operation in step 6 is executed; when the tile loading queue is empty and there are no pending missing requests / boundary delayed updates / dirty data, the data write-back operation in step 7 is executed.

[0027] Step 5: Activate the height reset module to perform unified initialization on the height labels of nodes currently residing in the on-chip cache: reset the height labels of ordinary nodes to 0, and set the height labels of seed nodes to 1, serving as the initial height reference for subsequent global height remarking operations. Then, write the identifier of the seed node into the FIFO of the global remarking module. After completing the above initialization, proceed to Step 3 to execute the global height remarking operation.

[0028] Step 6: Perform the tile loading operation. The top-level controller retrieves a batch of tile identifiers to be loaded from the tile loading queue. The batch size is N (e.g., N=128, configurable; if less than N, the actual number is used). For each tile, first check the label mapping cache: if a match is found, it is used directly; otherwise, a FIFO strategy is used to select an on-chip cache slot. After writing back dirty blocks if necessary, the target tile is loaded from off-chip to on-chip, the mapping relationship in the label mapping cache is updated, and the copy is updated before being redistributed to the boundary processor to replace the original read-only label cache. After the tile is loaded, the height data and push data of adjacent tiles in the boundary buffer are read. If the values ​​are valid, the corresponding operations interrupted due to missing tiles are performed. When any node height is updated, the node is written into the traversal FIFO of the global re-elevation module of the corresponding processing unit. After completion, proceed to step 3.

[0029] Step 7: After the maximum flow and minimum cut calculations are completed, the updated tile data in the on-chip cache is written back to the off-chip memory according to the tiles, and the final calculation results are generated / output, thus ending this acceleration task.

Claims

1. A cached folded mesh FPGA acceleration system for minimum cut and maximum flow computation of large-scale lattice graphs, characterized in that, include: The data segmentation module divides the grid diagram into several rectangular blocks according to a preset block size. The size of each rectangular block is an even multiple of the processor array size, enabling the cached folded grid FPGA acceleration system to perform off-chip to on-chip data transfer on a block-by-block basis. A tag mapping cache is set up in the FPGA accelerator to establish a correspondence between the block labels of each rectangular block in the off-chip grid diagram and the on-chip cache slots. When a rectangular block is loaded onto the chip, the on-chip cache slot number where the current rectangular block resides is recorded, and the current rectangular block is saved to the corresponding location in the tag mapping cache. The mapping relationship of on-chip cache slot numbers; the boundary buffer set in the boundary processor is used to solve the problem of off-chip data not being ready due to cross-tile boundary access and cache missing. The boundary buffer is used to temporarily store boundary-related status information and delayed update information. When a cache missing occurs when accessing adjacent tile data, the update record related to the current adjacent tile is written into the boundary buffer, the corresponding boundary operation is delayed and submitted, and the top-level controller is reported to load the missing tile. When the missing tile is loaded onto the chip, the data to be processed is read from the boundary buffer and sent to the processing unit located at the boundary. The processing unit performs update calculations.

2. The cached folded mesh FPGA acceleration system for minimum cut and maximum flow computation of large-scale lattice graphs as described in claim 1, characterized in that, For regions that are not divisible by an integer at the boundary of the lattice diagram, the data segmentation module uses zero-padding.

3. The cached folded mesh FPGA acceleration system for minimum cut and maximum flow computation of large-scale lattice graphs as described in claim 1, characterized in that, Assign a two-dimensional coordinate identifier (X,Y) to each rectangular tile as the tile label.

4. The cached folded mesh FPGA acceleration system for minimum cut and maximum flow computation of large-scale lattice graphs as described in claim 1, characterized in that, The status information and delayed update information include the height label of the boundary node, excess traffic, and traffic update increments generated by cross-boundary pushes.

5. A cached folded grid FPGA acceleration method for minimum cut maximum flow in large-scale lattice graphs, employing the cached folded grid FPGA acceleration system as described in claim 1, characterized in that, Includes the following steps: Step 1: Divide the grid map into several rectangular blocks according to a preset block size. The size of each rectangular block is an even multiple of the processor array size. Each rectangular block is assigned a unique block coordinate as a whole unit. The node arrangement within the rectangular block is consistent with the arrangement of processing units in the processor array. Identify and mark all rectangular blocks containing at least one seed point as seed blocks, and write the block coordinates of the seed blocks into the block loading queue of the top-level controller. At the same time, initialize the height label of the seed node in each sub-block to a value of one. Step 2: The top-level controller reads the block coordinates of the rectangular blocks to be loaded sequentially from the block loading queue, and assigns an on-chip cache slot number to the current rectangular block through label mapping cache to record its on-chip cache position. The storage location in the memory is then used to trigger the off-chip to on-chip data loading of the corresponding rectangular tile. After the tile data is loaded, the processing unit in the processor array writes the corresponding seed node into the initialization queue FIFO according to the identifier of the seed node in the loaded node data. This is used for subsequent height label initialization and active node initialization processing, thereby starting the minimum cut / maximum flow calculation process. At the same time, the top-level controller generates several copies of the label mapping cache and distributes all copies to each boundary processor, forming a read-only label cache for each boundary processor. Step 3: The global height relabeling module starts the height relabeling operation, cyclically reading and processing the node identifiers in the FIFO, updating the height labels of ordinary nodes in pairs, until the current FIFO is updated. The current node is empty. During the height labeling process, the active node number with updated height labels and positive excess flow is written into the FIFO of the streaming module for subsequent streaming processing. At the same time, during the above execution process, the processing unit located at the edge of the processor array sends the tile coordinates involved in the current operation to the boundary processor, which performs tile coordinate transformation to access adjacent tile data. The boundary processor queries whether the transformed tile coordinates have been stored in the chip through the read-only label cache. If not, the current tile coordinates are temporarily stored in the loaded tile queue and reported to the top-level controller as a cached missing tile. In the case of missing tiles, the boundary processor stores the relevant node height data corresponding to the tile currently being executed by the boundary processor in the boundary buffer according to the original tile coordinates before transformation, so as to postpone the operation that cannot be completed temporarily. Step 4: Start the streaming module, and read and process the active nodes in its FIFO in a loop until the current FIFO is reached. If empty, the corresponding push stream operation is executed. During the push stream process, the processing unit located at the edge of the processor array sends the tile coordinates involved in the current operation to the boundary processor, which performs the tile coordinate transformation. The boundary processor queries whether the transformed tile coordinates have been stored in the chip through the read-only tag cache. If not, the current tile coordinates are temporarily stored in the loaded tile queue, and the missing tile identifier is reported to the top-level controller.In the event of missing tiles, the boundary processor stores the relevant node height data corresponding to the currently executed tile in the boundary buffer based on the original tile coordinates before transformation, thus postponing operations that cannot be completed temporarily. After the streaming process is completed, the top-level controller determines the next operation based on the streaming result and queue status: if any streaming operation was performed during the streaming process, the height reset operation in step 5 is performed; if the streaming FIFO is empty, it is reported to the top-level controller, which checks the tile loading queue: when the tile loading queue is not empty, the tile loading operation in step 6 is performed; when the tile loading queue is empty and there are no pending missing requests / boundary delay updates / dirty data, the data write-back operation in step 7 is performed; Step 5: Start the height reset module to uniformly initialize the node height labels currently residing in the on-chip cache: reset the height labels of ordinary nodes to value two, and set the height labels of seed nodes to value one, as the subsequent full... The initial height reference for the global height recalibration operation is established. Then, the identifier of the seed node is written into the traversal FIFO of the global recalibration module. After the initialization is complete, proceed to step 3 to execute the global height recalibration operation. Step 6: Perform the tile loading operation. The top-level controller retrieves a batch of tile coordinates to be loaded from the tile loading queue. For each value, it first queries the label mapping cache: if a match is found, it is used directly; otherwise, it selects an on-chip cache slot according to the FIFO strategy and, if necessary, writes back dirty blocks. Then, it loads the target tile from off-chip to on-chip and updates the mapping relationship in the label mapping cache. After updating the copy, it redistributes it to the boundary processor to replace the original read-only label cache. After the tile is loaded, it reads the height data and push data of adjacent tiles in the boundary buffer. If the value is valid, it performs the corresponding operation interrupted due to missing tiles. When any node height is updated, the node is written into the traversal FIFO of the global height recalibration module of the corresponding processing unit. After completion, proceed to step 3. Step 7: After the maximum flow and minimum cut calculations are completed, the updated tile data in the on-chip cache is written back to the off-chip memory according to the tiles, and the final calculation results are generated / output, thus ending this acceleration task.

6. The FPGA acceleration method for cached folded grids as described in claim 5, characterized in that, In step 1, when dividing the rectangular blocks, the areas at the boundaries of the grid diagram that are not divisible by an integer are filled with zeros.

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