Heterogeneous information processing system and method based on GPU (graphics processing unit) and CPU (central processing unit)

Abstract

The invention belongs to the technical field of radar signal processing and high-performance computing, and particularly relates to a GPU + CPU-based heterogeneous information processing system and method.The GPU + CPU-based heterogeneous information processing system comprises a layered software system structure of a presentation layer, a domain layer, a persistent layer and a supporting layer, and loose coupling data interaction of components among layers and in the layers is achieved through a data management component; the presentation layer runs on a CPU main thread and is used for man-machine interaction and state monitoring; the domain layer runs on a CPU and is a core business logic layer, and the persistent layer runs on the CPU, is used for processing localized storage of data and comprises a process file storage module, an A display data storage module and a high-resolution file storage module; and the support layer runs on the CPU and provides bottom layer support service. According to the invention, deep collaboration of the CPU and the GPU is realized, and the overall efficiency, flexibility and reliability of complex radar signal processing are remarkably improved.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing and high-performance computing technology, specifically relating to a GPU+CPU heterogeneous information processing system and method. Background Technology

[0002] Modern advanced radar systems, such as synthetic aperture radar (SAR) and inverse synthetic aperture radar (ISAR), need to process massive amounts of echo data and simultaneously perform multiple complex tasks, including target detection, narrowband tracking, and wideband high-resolution imaging. Traditional processing architectures face severe challenges: Pure CPU architecture: Although general-purpose CPUs are good at complex process control and logical judgment, their serial computing mode becomes a performance bottleneck when faced with the large-scale parallel computing inherent in radar signal processing, such as matrix operations, Fast Fourier Transform (FFT) / Inverse Fourier Transform (IFFT), and it is difficult to meet the real-time processing requirements.

[0003] Dedicated hardware architectures such as FPGAs and DSPs, while capable of improving the speed of specific algorithms through hardware parallelization, suffer from long development cycles, inflexible algorithm iteration, and difficulty in adapting to dynamic switching of multiple modes such as SAR, DBS, RBM, and ISAR, resulting in poor system versatility and maintainability.

[0004] Preliminary GPU-accelerated architecture: Although GPUs are introduced for acceleration, they are usually treated as independent "computing accelerator cards" without deep collaboration with CPU control flow. The task division between CPU and GPU is crude, data transfer is frequent and costly, and the overall system architecture is not optimized for heterogeneous computing, resulting in low resource utilization and difficulty in supporting complex, dynamically configurable multi-tasking processes.

[0005] Therefore, existing technologies lack a heterogeneous information processing solution that can efficiently and tightly couple the fine-grained management and process control capabilities of the CPU with the large-scale data parallel computing capabilities of the GPU at the system architecture level, and can flexibly and dynamically adapt to various radar working modes. To this end, the present invention provides a GPU+CPU heterogeneous information processing system and method. Summary of the Invention

[0006] The purpose of this invention is to provide a GPU+CPU heterogeneous information processing system and method. Through an innovative four-layer software architecture, a centralized data management mechanism, containerized algorithm component design, and targeted heterogeneous task partitioning, it achieves deep collaboration between CPU and GPU, significantly improving the overall efficiency, flexibility, and reliability of complex radar signal processing.

[0007] The specific technical solution adopted by this invention is as follows: This invention provides a GPU+CPU heterogeneous information processing system; the system runs on a highly integrated embedded GPU platform, such as the NVIDIA Jetson AGX series, and adopts a clear layered and modular software architecture, specifically including a presentation layer, a domain layer, a persistence layer and a support layer, and uses a core data management component as the central nervous system to realize efficient and loosely coupled data interaction and collaboration between each layer and the functional components within each layer.

[0008] The presentation layer runs on the CPU's main thread and serves as the system's human-computer interaction and health status monitoring window. It specifically includes: Network status monitoring module: Displays the Ethernet connection status with the host control software in real time.

[0009] FPGA Status Monitoring Module: Displays the real-time status of the communication link with the front-end FPGA.

[0010] PCIe status monitoring module: Monitors the data packet flow, rate, and anomalies of the PCIe bus.

[0011] Log display module: centrally displays received control commands, system responses, and various network and hardware anomaly alarms.

[0012] Signal processing message counting and monitoring module: dynamically displays the running status and data throughput of each processing flow within the software.

[0013] All monitoring information in this layer is refreshed via a timer, for example, once per second, providing an intuitive view for system debugging and operation maintenance.

[0014] The domain layer runs on the CPU and is the "brain" and "execution center" that carries all core business logic. It is further refined into: Process control logic module: As the system's main scheduler, it is responsible for parsing and responding to various network messages from the display and control software, such as initialization, start, and stop commands, thereby driving the business process state transition of the entire system.

[0015] The broadband data processing logic module is specifically responsible for scheduling and managing the broadband imaging processing flow. Based on task requirements, it can invoke processing logic in different modes such as SAR, DBS, RBM, and ISAR. Its key innovation lies in its intelligent scheduling of the most computationally intensive steps to the GPU for execution, such as azimuth processing in SAR imaging.

[0016] Narrowband data processing logic module: This module is specifically responsible for executing the radar narrowband detection and tracking process. It includes a series of standard processing steps such as MTI moving target indication, SLC sidelobe cancellation, pulse compression, pulse accumulation, CFAR constant false alarm rate detection, and spot convergence.

[0017] Auxiliary logic module group: Provides support for the above core logic, including: FTP data interaction logic: responsible for downloading scenario configuration files from the remote server.

[0018] PCIe data exchange logic: manages high-speed data exchange with FPGA and data processing software.

[0019] TCP data interaction logic: handles network communication protocols with the display and control software.

[0020] Scene file parsing logic: Parse the downloaded XML scene file and extract simulation parameters.

[0021] The persistence layer runs on the CPU and provides data persistence services for debugging, backtracking, and analysis. It includes: Process file storage module: Saves intermediate result data in narrowband processing.

[0022] A-type display data storage module: Stores the final A-type display data generated after narrowband processing.

[0023] High-resolution file storage module: Stores high-resolution imaging data generated by broadband processing.

[0024] The support layer runs on the CPU and is the "cornerstone" of stable system operation, providing common underlying services: PCIe communication module: Encapsulates the underlying PCIe driver and provides standard interfaces for opening the board, reading and writing registers, direct memory access (DMA) for data upload / download, etc., to achieve high-speed and reliable data interaction with FPGA and intermediate frequency board.

[0025] TCP communication module: Implemented based on a high-performance network library such as HP-Socket, responsible for establishing a stable connection with the display and control software, and completing the reliable sending and receiving of instructions and data, packet assembly and disassembly, and protocol parsing.

[0026] Task scheduling and message queue module: Manages task scheduling, synchronization, message passing, and data sharing between processing streams in a multi-threaded environment within the system.

[0027] Model component development interface module: As one of the core innovations, it defines a unified and standardized set of algorithm component interface specifications. All signal processing algorithms, such as pulse compression, CFAR detection, and SAR imaging, must implement this interface as components. This allows algorithms to be managed in a containerized manner, decoupling the algorithms from the framework and providing fundamental support for dynamic system configuration, component reuse, and functional expansion.

[0028] The data management component is the core hub for achieving efficient collaboration and loose coupling in this invention. It runs on the CPU, employs a global management concept of "context-shared cache," and is specifically composed of the following sub-modules: The real-time update buffer management submodule manages frequently accessed and consistency-guaranteed shared data, such as scene parameters and runtime configurations. It employs mechanisms like mutexes for read / write protection.

[0029] The lock-free FIFO buffer management submodule is another core innovation. For high-throughput, low-latency streaming data, such as echo data streams and spot data streams, it employs a lock-free ring buffer design. Producers (such as PCIe receiving threads) and consumers (such as processing threads) update pointers atomically, completely avoiding the thread blocking and switching overhead of traditional locking mechanisms, greatly improving the real-time performance of data exchange.

[0030] The XML file parsing submodule is dedicated to parsing scenario XML files and converting text parameters into in-memory data structures usable by the system.

[0031] The PCIE communication component management submodule and the network data communication component management submodule: perform unified application, allocation and lifecycle management of PCIE and network communication resources.

[0032] Track file reading submodule: Reads and parses the target trajectory data file.

[0033] The narrowband data processing logic module is instantiated as a narrowband signal processing unit at runtime. This unit adopts a dual-threaded pipeline architecture to optimize CPU utilization: the first thread sequentially processes front-end algorithms such as deinterleaving, space-time adaptation, sidelobe cancellation, and pulse compression, and generates A-display data; the second thread sequentially processes back-end algorithms such as pulse accumulation, CFAR detection, and point aggregation. Data is transferred between the two threads through a lock-free FIFO in the data management unit.

[0034] The broadband data processing logic module is instantiated as a broadband signal processing component. This component adopts a deep CPU+GPU collaborative mode, and its SAR mode processing module is a typical example of heterogeneous computing: the CPU is responsible for process control, data preparation, and task submission, while computationally intensive steps such as azimuth matched filter function generation, azimuth FFT fast Fourier transform, azimuth frequency complex multiplication matched filter core, and azimuth IFFT inverse fast Fourier transform are executed in parallel on thousands of GPU computing cores through the CUDA programming model, thereby achieving orders-of-magnitude performance acceleration.

[0035] This invention also provides a heterogeneous information processing method applied to the above-mentioned system. The method is a complete, state-driven processing lifecycle, including the following steps: Step S1: System startup and integrated initialization.

[0036] The CPU executes the flow control logic. At the beginning of system startup, a shared buffer for storing parameters and states, as well as a lock-free FIFO queue connecting each processing unit, are created in the global context of the data management component. Subsequently, the main control thread is created, and the FPGA board is opened and detected sequentially through the PCIe communication module. A TCP / IP connection is established with the display and control software through the network data communication component, completing the hardware and software readiness.

[0037] Step S2: Scene-driven dynamic configuration and loading.

[0038] The system enters a waiting-for-instructions state. The CPU receives the scene file path and additional operating parameters from the display and control software and stores them in the shared cache of the data management unit. Upon receiving the "initialize" instruction, the flow control logic drives the FTP transfer unit to download the specified scene XML file; the XML parsing submodule of the data management unit then parses the file, extracting the complete set of simulation parameters, such as radar mode, waveform parameters, and processing enable flags. Subsequently, the system enters the dynamic configuration phase: Based on the parsed parameters, the narrowband / wideband processing unit dynamically loads and instantiates the required algorithm components through the model component development interface; for example, if CFAR is enabled, the CFAR detection component is loaded to form a processing pipeline customized for the current scene.

[0039] Based on the parameters, the process control logic performs precise register configuration on the FPGA through the PCIe communication component to complete hardware initialization.

[0040] Finally, the system starts dedicated PCIe data receiving and sending threads to prepare for receiving echo data.

[0041] Step S3: Execution of the heterogeneous parallel processing pipeline.

[0042] Upon receiving the "start" command, the narrowband and broadband processing pipelines are activated simultaneously, entering a concurrent heterogeneous processing state: Narrowband processing pipeline, CPU multi-threaded collaboration: The PCIe data receiving thread continuously writes the echo data packets sent by the FPGA into the "echo data lock-free FIFO" of the data management unit in a DMA manner.

[0043] The first thread (ThreadA) of the narrowband signal processing unit retrieves data from the FIFO in a non-blocking manner and processes it by calling the interfaces of each component in sequence according to the pre-assembled component chain, such as: deinterleaving → space-time adaptation → pulse compression. The intermediate results are written into the "intermediate data FIFO".

[0044] Meanwhile, the second thread (ThreadB) retrieves data from the "intermediate data FIFO" and continues to execute subsequent component chains, such as: pulse accumulation → CFAR detection → dot aggregation, ultimately generating structured dot data and A display data, and storing them in the corresponding output buffer of the data management component.

[0045] Broadband processing pipeline; CPU+GPU collaboration, taking SAR mode as an example: The broadband signal processing unit instantiates the SAR processing component based on the operating mode parameters.

[0046] The CPU (host side) organizes data blocks from a dedicated wideband echo FIFO, performs necessary preprocessing, and copies the data from host memory to GPU global memory via CUDA API (H2D).

[0047] The CPU schedules the GPU to execute a series of pre-compiled CUDA kernels: first, an azimuth FFT is performed (using the cuFFT library), then a complex multiplication with a reference function is performed in the frequency domain (matched filtering), and finally an azimuth IFFT is performed. These operations are decomposed into a massive number of threads that execute in parallel on the GPU.

[0048] After the GPU completes the calculation, the CPU copies the result data from the video memory back to the host memory (D2H) and performs post-processing such as quantization and image enhancement. Finally, the generated high-resolution SAR image data is stored in the output buffer of the data management unit.

[0049] Step S4: Unified data aggregation and intelligent distribution.

[0050] The data management unit, acting as the sole data distribution center, continuously aggregates result data from various processing pipelines, including dot data, A-scale displays, and high-resolution images. The sending thread in the network data communication unit periodically polls these output buffers; once new, valid data is available, it is immediately encapsulated into network packets according to the communication protocol and sent to the display and control software for display, recording, or further analysis. Simultaneously, dot data can also be transferred to the FPGA via DMA through the PCIe communication unit for use by subsequent data processing units.

[0051] Step S5: The orderly system process terminates.

[0052] Upon receiving a "stop" command, the flow control logic initiates an orderly shutdown process: first, PCIe data reception is stopped, cutting off the data source; then, the narrowband and broadband processing units are notified to stop operations and release threads; next, PCIe data transmission is stopped; finally, the FPGA is configured to enter a stopped state via the PCIe communication unit, and hardware resources are shut down. Throughout the process, the data management unit coordinates the state synchronization between various units to ensure no data loss or state inconsistency.

[0053] The technical effects achieved by this invention are as follows: This invention achieves true deep heterogeneous collaboration with superior performance: Designed from the top level of software architecture, it tightly integrates the complex process control, task scheduling, and I / O management capabilities of CPUs with the large-scale data parallel computing capabilities of GPUs. Through the intelligent hub of the "data management component," especially the "lock-free FIFO" mechanism, the data flow efficiency between heterogeneous units is greatly optimized, enabling the CPU control flow and GPU computing flow to mesh precisely and operate efficiently like "gears," resulting in overall processing performance far exceeding traditional CPU solutions or simple GPU acceleration solutions.

[0054] This invention boasts exceptional flexibility, configurability, and scalability: by introducing a "model component development interface," signal processing algorithms are abstracted into standard, pluggable "components." Combined with scene file XML-driven operation, the system can dynamically assemble a customized processing pipeline tailored to the current task requirements during initialization. This means that the same system software can be flexibly adapted to different radar models and mission modes, such as air-to-ground SAR, sea surface ISAR, and airborne DBS, without modifying the core framework code, as well as any new algorithms that may emerge in the future, significantly improving the system's versatility and lifespan.

[0055] This invention significantly enhances the robustness and maintainability of the system: a clear four-layer architecture and modular design ensure well-defined logical layers and low coupling. The presentation layer provides comprehensive real-time status monitoring, facilitating rapid fault location. The data management component employs a hierarchical strategy to ensure data consistency and system stability under high concurrency and real-time requirements; hierarchical strategies include lock-free FIFOs for streaming data and mutex locks for parameters. This design also greatly reduces the difficulty of subsequent code maintenance, feature upgrades, and debugging.

[0056] This invention maximizes resource utilization: narrowband processing employs a dual-thread pipeline, fully exploiting the parallel potential of multi-core CPUs; while broadband processing perfectly offloads the computational load to many-core GPUs. Both operate in parallel under a unified architecture, working collaboratively to achieve saturated utilization of computing resources on heterogeneous hardware platforms such as multi-core CPUs + many-core GPUs, resulting in high cost-effectiveness. Attached Figure Description

[0057] Figure 1 This is a four-layer architecture diagram of the signal processing software of the present invention.

[0058] Figure 2 This is a diagram showing the main functional components of the signal processing software of this invention.

[0059] Figure 3 This is a flowchart illustrating the overall execution process of the signal processing software of this invention.

[0060] Figure 4 This is a flowchart of the dual-threaded pipeline processing of the narrowband signal processing component of the present invention.

[0061] Figure 5 This is a flowchart of the multi-mode processing of the broadband signal processing component of the present invention.

[0062] Figure 6 This is a diagram showing the external interface relationships of the signal processing software of this invention.

[0063] Figure 7 This is a description table of the external interfaces of the signal processing software of this invention.

[0064] Figure 8 This is a diagram showing the internal interface relationships of the signal processing software of this invention.

[0065] Figure 9 This is a description table of the internal interfaces of the signal processing software of this invention.

[0066] Figure 10 This is a schematic diagram of the lockless FIFO and shared cache of the data management component of the present invention. Detailed Implementation

[0067] To make the objectives and advantages of this invention clearer, the invention will be specifically described below with reference to embodiments. It should be understood that the following text is merely used to describe one or more specific embodiments of the invention and does not strictly limit the scope of protection specifically claimed by the invention.

[0068] Example 1: An overall architecture and collaborative working mechanism for a GPU+CPU heterogeneous information processing system: This embodiment is built on a highly integrated embedded GPU platform, such as the NVIDIA Jetson AGX Orin. Figure 1 , Figure 2 As shown, the entire system adopts a clear four-layer software architecture and achieves efficient collaboration between layers and components through a centralized data management component.

[0069] Presentation layer implementation The presentation layer runs on the CPU main thread, is developed using a graphical user interface framework, and provides a comprehensive monitoring interface. This interface refreshes via a timer (e.g., once per second) and reads various status information from the shared parameter area of ​​the data management component. Network connection status; determined by maintaining connectivity with the display and control software via a heartbeat mechanism.

[0070] FPGA status register value.

[0071] PCIe bus packet count and transmission rate.

[0072] System log information, including received instructions, sent feedback, and various abnormal alarms.

[0073] Real-time message counting for narrowband and broadband processing flows.

[0074] All information is presented intuitively in the form of dashboards, status indicators, lists, and scrolling log windows, providing a one-stop monitoring view for system operation and debugging.

[0075] Domain layer and core processing components implementation The domain layer is the core of the system's business logic, containing multiple logical modules that are instantiated into specific functional components at runtime. Process control unit: As the system's brain, it maintains a finite state machine. When it receives instructions from the display and control software via the network data communication unit, it parses the instructions, drives system state transitions, and coordinates the work of all other components.

[0076] Narrowband signal processing unit; composed of Figure 1 Instantiation of narrowband data processing logic in the component: This component adopts a dual-threaded pipeline architecture to optimize CPU utilization, and its workflow is as follows: Figure 4 As shown.

[0077] Thread 1, Business Flow 0: In sequence, it calls algorithm components such as deinterleaving, space-time adaptation, sidelobe cancellation, angle tracking interference source, moving target display (MTI), and pulse compression. The processing results (including intermediate results of A-display data) are transmitted through the data management component.

[0078] Thread 2, Business Flow 1: In sequence, call the algorithm components such as impulse accumulation, constant false alarm rate (CFAR) detection, side lobe concealment (SLB), measurement, point clustering, and deblurring to generate the final point data.

[0079] Data exchange between the two threads is achieved through a lock-free first-in-first-out (FIFO) queue within the data management unit, which is efficient and non-blocking.

[0080] Broadband signal processing unit; composed of Figure 1Instantiation of broadband data processing logic: This component adopts a collaborative mode of CPU scheduling + GPU acceleration, supporting multiple modes such as synthetic aperture radar (SAR), Doppler beam sharpening (DBS), real-time beammap (RBM), and inverse synthetic aperture radar (ISAR); for example Figure 5 As shown. Taking SAR mode as an example: The CPU is responsible for process control, data preparation (organizing the echo data matrix), and task submission.

[0081] GPUs utilize CUDA technology to perform computationally intensive steps in parallel, such as azimuth fast Fourier transform (FFT), azimuth frequency complex multiplication (matched filter core), and azimuth inverse fast Fourier transform (IFFT).

[0082] Auxiliary components include FTP transfer components and PCIe communication components, which are responsible for auxiliary functions such as scene file download and high-speed data exchange with the FPGA, respectively.

[0083] Core implementation of data management components The data management component is key to achieving loose coupling and high performance in this invention, and its design is as follows: Figure 10 As shown, it acts as a global singleton, providing two core data management mechanisms: Shared parameter cache: A hash table protected by a read-write lock such as std::shared_mutex is used to store all scene parameters and runtime configuration parameters, such as radar operating modes and detection thresholds. This mechanism ensures high efficiency for multi-threaded reads and consistency during parameter updates.

[0084] Lock-free circular buffer, lock-free FIFO: This is an optimized design for high-throughput data streams such as echo data and point data. Its core is a pre-allocated fixed-size array, coupled with two atomic variables: a read pointer and a write pointer. Producer threads (such as PCIe receiving threads) and consumer threads (such as signal processing threads) update the pointers atomically, completely avoiding the thread suspension and switching overhead caused by traditional mutex locks, achieving extremely efficient and safe data exchange.

[0085] Key services of the support layer The support layer provides the underlying services upon which the system operates: The model component development interface module defines a unified standard for algorithm component interfaces, including methods such as "initialization," "execution," and "cleanup." Any signal processing algorithm, such as pulse compression or CFAR detection, must be encapsulated as an independent component implementing this interface. This allows algorithms to be managed and assembled in a unified manner, forming the cornerstone of the system's configurability and scalability.

[0086] The PCIE communication module and TCP communication module encapsulate underlying hardware drivers and network libraries, such as HP-Socket, to provide stable and efficient communication capabilities for the upper layers.

[0087] Example 2: Detailed Implementation of Narrowband Dual-Thread Pipeline Reference Figure 3 and Figure 4 The operational details of the narrowband processing pipeline are as follows: Thread Partitioning and Component Chains: During the initialization phase, the narrowband signal processing unit dynamically creates two processing chains based on parameters parsed from the XML scenario file. Thread A's processing chain includes: deinterleaving component -> space-time adaptive (STAP) component -> pulse compression component. Thread B's processing chain includes: pulse accumulation component -> constant false alarm rate (CFAR) detection component -> point aggregation component. The two processing chains are connected via an intermediate data lock-free FIFO within the data management unit.

[0088] Data flow process: An independent PCIe data receiving thread continuously pushes echo data packets received from the FPGA into the global "echo data lock-free FIFO".

[0089] Thread A, within a loop, retrieves data from the "echo data unlocked FIFO" in a non-blocking manner. If successfully retrieved, it sequentially calls each component in its processing chain to execute the algorithm. After processing, the generated intermediate data is pushed into the "intermediate data unlocked FIFO". This thread primarily performs front-end processing such as "filtering and pulse compression".

[0090] In another loop, thread B retrieves data from the "intermediate data lock-free FIFO" and sequentially calls components in its processing chain to complete backend processing such as "detection, measurement, and aggregation". The final generated point data is written to the "point data output buffer" of the data management component for network transmission and PCIe download, while display data is written to the "display data buffer".

[0091] Dynamic control mechanism: During initialization, all algorithm components of the CFAR detection module read their own unique parameters, such as false alarm probability and number of reference cells, from the shared parameter buffer through the data management component's interface. During system operation, the display and control software can dynamically issue new parameters through the "simulation working parameter interface." The data management component updates the shared parameter buffer, and the relevant components can immediately apply the new parameters when processing the next frame of data, achieving real-time dynamic adjustment and intervention of the processing flow.

[0092] Example 3: GPU-accelerated implementation of broadband SAR imaging Reference Figure 5Wideband SAR imaging is a prime example of deep collaboration between CPU and GPU. The implementation of the SAR mode processing component includes host-side (CPU) code and device-side (GPU) code.

[0093] Host-side (CPU) preparation: When the execution interface of this component is called, the input is a two-dimensional complex data matrix from the "wideband echo data unlocked FIFO", in range × azimuth direction. The CPU first calculates the reference function, a complex sequence, required to generate the azimuth matched filtering in the host memory.

[0094] GPU memory allocation and data transfer: The CPU calls the CUDA interface to allocate three blocks of memory in the GPU's global video memory, which are used to store echo data, reference functions, and result data, respectively.

[0095] The cudaMemcpy function is used to copy the echo data matrix and reference function from the host memory to the GPU memory.

[0096] GPU parallel computing, kernel scheduling: Step 1: Azimuth-oriented FFT. Use the CUDA Math Library (cuFFT) to create and execute a batch one-dimensional FFT schedule to transform the data from the azimuth domain to the time domain and then to the frequency domain.

[0097] Step 2: Frequency Domain Matched Filtering. Start a custom CUDA kernel function. Within this kernel, hundreds or thousands of GPU threads are organized, each responsible for calculating a complex multiplication of a distance cell at a specific azimuth frequency point—that is, the data is multiplied by the conjugate of the reference function, achieving highly parallel matched filtering.

[0098] Step 3: Azimuth IFFT. The cuFFT library is used again to perform a batch one-dimensional inverse FFT, transforming the filtered data from the frequency domain back to the azimuth time domain, completing the core imaging processing.

[0099] Results retrieval and post-processing: After the GPU completes the calculation, the CPU copies the result data from the GPU memory back to the host memory. Subsequently, the CPU performs post-processing operations such as amplitude detection calculation of complex numbers and data quantization, such as converting floating-point numbers to 8-bit grayscale values. Finally, the generated high-resolution SAR image data is written to the "high-resolution image output buffer" of the data management unit.

[0100] Example 4: Unified Interface and Communication Mechanism Based on Data Management Component like Figure 8 , Figure 9 As shown, the internal interface design of this system is extremely simple and efficient. All communication between components is transformed into operations on specific buffers in the data management component, achieving complete loose coupling.

[0101] Asynchronous transmission of control commands: After receiving a "start" command, the network data communication component verifies and parses it. Instead of directly invoking the flow control component, it encapsulates the command information into a message and writes it to the data management component's "control command lock-free FIFO." The flow control component's main loop continuously reads and executes commands from this FIFO. This approach decouples network reception from flow control logic, allowing them to run independently and asynchronously, thus improving system responsiveness and stability.

[0102] High-efficiency transmission of large data streams: The DMA upload module of the PCIe communication component directly writes the received echo data packets into the "echo data lock-free FIFO". Narrowband and broadband processing components, acting as consumers, each read the data they need from it. This unidirectional producer-consumer model, perfectly supported by the lock-free FIFO, completely avoids complex synchronization callbacks or direct function calls, resulting in a clear data flow and extremely high efficiency.

[0103] Centralized parameter access: When any component in the system needs parameters, it only needs to call the unified interface provided by the data management component, such as getParameter(“parameter name”). This interface internally reads and returns the value from the shared parameter cache. Components do not need to care whether the parameters come from parsing the initial scene file or from dynamic network updates at runtime, thus achieving centralized and transparent parameter management.

[0104] In summary, this invention establishes a clear logical foundation through a four-layer architecture, achieves efficient collaboration and loose coupling through a data management component and its lock-free FIFO mechanism, endows the system with the "superpower" of dynamic reconfiguration through model component interfaces, and ensures ultimate processing performance through deep collaboration between CPU and GPU. This solution successfully transforms the potential of heterogeneous computing platforms into powerful comprehensive capabilities for complex radar signal processing tasks, demonstrating significant innovation, practicality, and scalability.

[0105] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained in this invention are implemented according to conventional methods in the art unless otherwise specified or limited.

Claims

1. A GPU+CPU heterogeneous information processing system, running on a highly integrated embedded GPU platform, characterized in that: The heterogeneous information processing system adopts a layered software architecture including a presentation layer, a domain layer, a persistence layer, and a support layer, and realizes loosely coupled data interaction between and within each layer through a data management component. The presentation layer runs on the CPU main thread and is used for human-computer interaction and status monitoring. It includes at least a network status monitoring module, an FPGA status monitoring module, a PCIE status monitoring module, a log display module, and a signal processing message counting monitoring module, and refreshes data periodically by timer triggering. The domain layer runs on the CPU and is the core business logic layer, including at least: The process control logic module is used to respond to external control commands and control system business processes; The broadband data processing logic module is used to schedule and manage the signal processing flow in Synthetic Aperture Radar (SAR), Doppler Beam Sharpening (DBS), Real-time Beammap (RBM), and Inverse Synthetic Aperture Radar (ISAR) modes. The narrowband data processing logic module is used to execute narrowband signal processing procedures, including moving target indication (MTI), sidelobe cancellation (SLC), pulse compression, pulse accumulation, constant false alarm rate (CFAR) detection, and spot aggregation. The auxiliary logic module includes FTP data interaction logic, PCIE data interaction logic, TCP data interaction logic, and scenario file parsing logic; The persistent layer runs on the CPU and is used to process localized data storage, including a process file storage module, an A display data storage module, and a high-resolution file storage module. The support layer runs on the CPU and provides underlying support services, including at least: The PCIe communication module is used to interact with the FPGA and intermediate frequency board via the PCIe bus. The TCP communication module is used to exchange network commands and data with the display and control software via Ethernet. The task scheduling and message queue module is used for internal task flow control and data sharing within the system. The model component development interface module provides a unified interface for the development, management, and invocation of various signal processing algorithm model components; The data management component, acting as the system data hub, runs on the CPU and employs a context-shared cache mechanism, and includes at least: The real-time update buffer management submodule is used to manage shared configuration parameters and status data; The lock-free FIFO buffer management submodule is used to manage high real-time streaming data; The XML file parsing submodule is used to parse scenario XML files. The narrowband data processing logic module is instantiated as a narrowband signal processing component, which adopts a dual-threaded pipeline architecture. The broadband data processing logic module is instantiated as a broadband signal processing component. This component adopts a collaborative processing mode of CPU scheduling and GPU acceleration. The SAR mode processing module uses CUDA technology to execute azimuth matched filter function generation, azimuth FFT processing, azimuth frequency complex multiplication and azimuth IFFT processing in parallel on the GPU.

2. The GPU+CPU heterogeneous information processing system according to claim 1, characterized in that: The dual-threaded pipeline architecture of the narrowband signal processing unit specifically includes: The first processing thread is configured to sequentially call the deinterleaving module, the space-time adaptive module, the sidelobe cancellation module, the angle tracking interference source module, the MTI processing module, and the pulse compression module, and generate intermediate A-display data results; The second processing thread is configured to sequentially call the pulse accumulation module, CFAR detection module, sidelobe concealment module, measurement module, dot clustering module, and deblurring module, and generate the final dot data. The first processing thread and the second processing thread exchange data through the lock-free FIFO buffer in the data management component.

3. The GPU+CPU heterogeneous information processing system according to claim 2, characterized in that: The broadband signal processing component includes at least a SAR mode processing module, an RBM mode processing module, and a DBS mode processing module. The RBM mode processing module is configured to perform non-coherent accumulation and quantization processing on the echoes within each coherent processing interval CPI. The DBS mode processing module is configured to perform coherent accumulation and quantization processing on the echoes within each CPI. Each processing module inherits from the basic interface defined by the model component development interface module, and is dynamically called by the main process according to the working mode parameters.

4. The GPU+CPU heterogeneous information processing system according to claim 3, characterized in that: The data management component also includes: The PCIE communication component management submodule is used for unified resource application, allocation and destruction of PCIE communication functions; The network data communication component management submodule is used for unified resource application, allocation, and destruction of network communication functions; The trajectory file reading submodule is used to read trajectory file data in a predetermined format and store it in a buffer. The real-time update buffer management submodule uses a mutex lock mechanism to protect shared parameters from being read and written; the lock-free FIFO buffer management submodule uses a circular buffer and atomic operations to implement a lock-free producer-consumer data exchange model.

5. The GPU+CPU heterogeneous information processing system according to claim 3, characterized in that: The system also includes the following functional components that are specifically instantiated by the domain layer and the support layer logic: The process control unit is used to specifically control the FPGA's opening, initialization, startup, stop, and shutdown operations according to external instructions, as well as the initialization, startup, and stop processes of the broadband and narrowband processing units; The PCIE communication component includes a PCIE basic operation module, an FPGA initialization module, an FPGA start / stop module, a DMA data upload / download module, and an FPGA status query module, which are used to perform specific execution of FPGA register configuration and high-speed data transfer; The FTP transfer component includes a server connection and login module, a directory file index acquisition module, and a file traversal and download module, which are used to download scene files from a remote FTP server. The network data communication component includes a network connection module, a network receiving module, and a network sending module. It uses the HP-Socket library to implement data packet transmission, reception, parsing, and verification with the display and control software.

6. The GPU+CPU heterogeneous information processing system according to claim 5, characterized in that: The DMA data upload module of the PCIE communication component is configured to: after starting DMA upload, if a timeout occurs, determine whether partial data has been received; if received, resume data transmission; if not received, exit; if no timeout occurs but the data packet is incomplete, continue starting DMA transmission until a complete data packet is received.

7. A heterogeneous information processing method applied to the GPU+CPU heterogeneous information processing system according to any one of claims 1 to 6, characterized in that: The method includes the following steps: S1. System Startup and Resource Preparation: The CPU executes the flow control logic, creates a shared data cache and a data communication FIFO between components in the context of the data management component; creates the main thread, opens the PCIe card, and establishes a network connection with the display control software; S2. Scene Loading and Dynamic Configuration: The CPU receives the scene file path and running configuration parameters from the display and control software and stores them in the shared cache; according to the initialization instructions, it downloads and parses the scene XML file through the FTP transfer component to obtain simulation parameters; based on the simulation parameters and running configuration parameters, it completes the process initialization of the broadband and narrowband processing components and the FPGA initialization; and it starts the PCIE data receiving and sending threads. S3. Heterogeneous parallel processing execution: The CPU receives the start command and simultaneously executes the narrowband processing flow and the broadband processing flow; S31. Narrowband processing flow: The CPU sequentially calls each algorithm model component dynamically assembled according to scene parameters through the dual-thread pipeline of the narrowband signal processing unit to process the echo data and generate point data and A display data. S32. Wideband processing flow: The CPU calls the corresponding module of the wideband signal processing component according to the working mode parameters; for SAR mode, the CPU organizes and moves the echo data to the GPU memory, schedules the GPU to execute the computationally intensive tasks related to azimuth matched filtering in parallel, the CPU collects the results and performs post-processing to generate high-resolution imaging data; for RBM or DBS mode, the corresponding accumulation and quantization processing is performed. S4. Unified data management and distribution: The data management component centrally caches and manages the dot data, A-display data and high-resolution imaging data generated by each processing flow, and distributes them to the display control software or FPGA by the network data communication component and / or PCIE communication component; S5. Process Termination: The CPU receives a stop command and sequentially stops the PCIe data receiving thread, narrowband and wideband processing flow, and PCIe data sending thread, and controls the FPGA to stop.

8. The heterogeneous information processing method according to claim 7, characterized in that: The sequential invocation of each algorithm model component dynamically assembled based on scene parameters in step S31 specifically includes: During initialization, the narrowband signal processing component loads and instantiates the corresponding algorithm components for uninterruption, pulse compression, pulse accumulation, CFAR detection, and spot aggregation based on the enable parameters parsed from the scene XML file through the model component development interface module, forming an executable component processing chain. During runtime, the first and second processing threads call the component interfaces in the processing chain to execute the algorithm in a predetermined order.

9. The heterogeneous information processing method according to claim 7, characterized in that: The specific steps in step S32, which involve scheduling the GPU to perform computationally intensive tasks related to azimuth matched filtering in parallel, include: The CPU prepares the SAR echo data matrix and matched filter function in the host memory; Data is copied from host memory to GPU global memory via CUDA API; On the GPU, CUDA kernels are launched sequentially to perform azimuth FFT, azimuth frequency complex multiplication, and azimuth IFFT, and matrix operations are completed in parallel by multiple computing cores of the GPU. After the calculation is complete, the result data is copied from the GPU memory back to the host memory.

10. The heterogeneous information processing method according to claim 7, characterized in that, When performing data management, the data management component uses a lock-free FIFO mechanism to buffer high real-time data streams, and the producer thread and consumer thread update the read and write pointers through atomic operations to achieve conflict-free access; access to shared configuration parameters is protected by a mutex lock mechanism.

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