Storage module wrapper determination method, electronic equipment and storage medium
By employing a layered design and modular configuration approach to the packager, the fragmentation and compatibility issues of memory modules in SoC chips are resolved, improving the reusability and design efficiency of the packager while reducing physical area and development costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-04-07
AI Technical Summary
Existing memory wrapper technology is difficult to adapt to the fragmented and complex requirements of storage modules in SoC chips, resulting in poor reusability of the wrapper, high development costs, and hindering the improvement of SoC chip design efficiency.
By adopting a layered design and adding functional modules at different levels as needed, the layered structure and modular design achieve highly modular and dynamically configurable wrappers, adapting to fragmented needs, improving the reusability of wrappers, and shortening the development cycle.
It improves the reusability of the package, reduces the physical area of the memory array, alleviates the wiring congestion problem, improves the efficiency of back-end physical design and chip area utilization, and shortens the development cycle.
Smart Images
Figure CN121809360A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the chip technical field, and particularly relates to a memory module wrapper determination method, an electronic device and a storage medium. BACKGROUND
[0002] In the design process of a contemporary system on chip (SoC), a memory module is a key infrastructure supporting the implementation of a chip core function. Due to differences in the process of different memory modules and significant differences in chip testing, power consumption control, back-end integration and other aspects, when different memory modules are directly integrated into an SoC, a series of problems such as interface incompatibility and low integration efficiency are often encountered, which seriously restricts the design cycle and development efficiency of the SoC. A memory module wrapper can build a standardized shell for different memory modules, and through standardized encapsulation processing, the interfaces of different memory modules are unified. In actual application, although about 2% to 4% of the chip area and power consumption cost is required for adopting the Memory wrapper technology, the design cycle of the SoC can be effectively shortened and the development efficiency can be improved.
[0003] However, the existing Memory wrapper technology still has obvious technical bottlenecks in actual popularization and application, and the core problem lies in the high fragmentation of the demand. With the continuous improvement of the integration degree of the SoC, the demand for memory modules presents the characteristics of diversification and complication, and the existing Memory wrapper technology is difficult to adapt to the above fragmented and complex functional requirements, and often needs to develop a customized wrapper for a specific memory module or a specific application scenario, resulting in poor reusability of the wrapper, high development cost, and unable to fully play the value of the wrapper in the large-scale integration of the SoC chip design, which restricts the further improvement of the design efficiency of the SoC chip. SUMMARY
[0004] The present application discloses a memory module wrapper determination method, an electronic device and a storage medium, which realizes a highly modularized and on-demand dynamic configuration design by hierarchical design and adding functional modules on demand at different levels, which is conducive to better adapting to the fragmented demand of the wrapper and improving the reusability of the wrapper and shortening the development cycle of the wrapper.
[0005] In a first aspect, an embodiment of the present application provides a memory module wrapper determination method, which can be applied to an electronic device or a device (such as a chip or a processor, etc. placed in the electronic device) matched with the electronic device. Wherein, the wrapper adopts a hierarchical structure, the third level module of the wrapper includes the second level module, the second level module includes the first level module, and the first level module includes a first simulation model of the memory module. The method comprises: obtaining configuration parameters, the configuration parameters at least including a type of the storage module, a depth of the storage module, a data bit width, and a required function identifier of the wrapper; wherein the required function identifier is used to indicate whether a first function module is configured in the first-level module and whether a second function module is configured in the third-level module; if the required function identifier indicates that the first function module is configured in the first-level module, instantiating the first function module in the first-level module; determining a first simulation model through the first-level module, and instantiating the first-level module; wherein the first simulation model is determined based on the type of the storage module; determining a construction manner of the plurality of storage units through the second-level module, so that the depth and the data bit width of a storage array constructed according to the construction manner match the depth and the data bit width of the storage module respectively, and a target construction manner corresponding to a storage array with the smallest occupied area is taken as the construction manner of the storage module; instantiating the second-level module based on the target construction manner; if the required function identifier indicates that the second function module is configured in the third-level module, instantiating the second function module in the third-level module.
[0006] In the technical solution, the hierarchical design and the on-demand addition of the function modules in different levels are implemented, so that the design of high modularity and on-demand dynamic configuration is achieved, which is conducive to better adapting to the fragmentation needs of the wrapper and improving the reusability of the wrapper and shortening the development cycle of the wrapper. In addition, the automatic selection of the storage array construction scheme that meets the needs and has the smallest occupied area can significantly reduce the physical area of the storage array, alleviate the problem of winding congestion caused by irregular shape, and improve the efficiency of the back-end physical design and the chip area utilization.
[0007] In a possible implementation manner, the first simulation model is compiled by a first compiler based on a first process library; the method further includes: if the compiler used is changed from the first compiler to a second compiler, replacing the first simulation model with a second simulation model; wherein the second simulation model is compiled by the second compiler; and / or, if the process library of the first compiler is changed from the first process library to a second process library, replacing the first simulation model with a third simulation model; wherein the third simulation model is compiled by the first compiler based on the second process library.
[0008] In the technical solution, the simulation model can be replaced as the compiler or the process library changes, that is, only the underlying simulation model file needs to be replaced, and the RTL design code of the wrapper top layer (i.e., the third layer) does not need to be changed, because the external interface of the wrapper does not change when the compiler or the process library is replaced.
[0009] In one possible implementation, the storage array constructed based on the target construction method has the smallest physical aspect ratio.
[0010] In this technical solution, the aspect ratio of the memory array directly affects wiring resources and routing difficulty in chip physical design. Minimizing the physical aspect ratio of the memory array through a targeted construction method can make the memory array shape more regular, reduce wiring congestion and routing length, improve the efficiency and success rate of back-end physical design, and avoid the extra area waste caused by irregular shapes.
[0011] In one possible implementation, the storage array constructed based on the target construction method has N storage cells in the first direction and M storage cells in the second direction; wherein the sum of the data bit widths of the N storage cells is greater than or equal to the data bit width of the storage module, the sum of the depths of the M storage cells is equal to the depth of the storage module, and M and N are both positive integers.
[0012] In one possible implementation, the configuration parameters also include M and N.
[0013] In one possible implementation, multiple storage units are of the same type, but different types of storage units have different physical lengths and / or physical widths.
[0014] In one possible implementation, the third-level module further includes an FPGA model; the method further includes: receiving a selection operation for a target model, the target model being a first simulation model or an FPGA model; in response to the selection operation, selecting the target model through the third-level module to perform corresponding verification; wherein the first simulation model is used to perform chip design front-end verification, and the simulation model is used to perform FPGA verification.
[0015] In this technical solution, the package can include both an FPGA model and a first simulation model of the storage module. Electronic devices (such as the electronic devices corresponding to the chip design verification platform) can dynamically switch verification models according to user selection, realizing flexible switching between front-end verification and FPGA verification. This can meet both FPGA verification scenarios and Electronic Design Automation (EDA) verification scenarios without redevelopment, thus adapting to a wider range of scenarios.
[0016] In one possible implementation, the first functional module includes one or more of the following: an input data insertion module, an output data insertion module, and an integrated clock gating unit module; the second functional module includes an error correction code module and / or an error injection module.
[0017] Secondly, embodiments of this application provide a packager determination apparatus for a storage module, the packager determination apparatus for a storage module including a unit for implementing the method described in the first aspect.
[0018] Thirdly, embodiments of this application provide an electronic device including at least one processor; the at least one processor is configured to run a computer program or instructions to perform the method described in the first aspect.
[0019] In one possible implementation, the electronic device may further include a memory connected to the at least one processor; the memory is used to store computer programs or instructions; the at least one processor is specifically used to retrieve the computer programs or instructions from the memory and run the computer programs or instructions to perform the method described in the first aspect.
[0020] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program or computer instructions, which, when executed, cause an electronic device to perform the method described in the first aspect.
[0021] Fifthly, embodiments of this application provide a computer program product including a computer program or instructions, which, when executed on an electronic device, causes the electronic device to perform the method described in the first aspect. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of the structure of a memory module package provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a method for determining the packager of a storage module according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a storage module package determining device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0023] The terms "first," "second," etc., used in the embodiments of this application are used to distinguish different objects, not to describe a specific order. "At least one" in the embodiments of this application refers to one or more, and "multiple" refers to two or more. "And / or" in the embodiments of this application describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. Here, A and B can be singular or plural.
[0024] In the embodiments of this application, "at least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent the following seven cases: a, b, c, a and b, a and c, b and c, a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.
[0025] The following describes the method for determining the packager of a storage module proposed in the embodiments of this application. This method can be executed by an electronic device or by a device that matches the electronic device (such as a chip or processor placed inside the electronic device). The embodiments of this application illustrate the method for determining the packager of a storage module by an electronic device.
[0026] The embodiments of this application do not limit the form of the electronic device. For example, the electronic device may include, but is not limited to, terminal devices, servers, devices in clusters or distributed systems.
[0027] In this embodiment, the encapsulator adopts a layered structure. The third-level module of the encapsulator includes an instantiated second-level module, the second-level module includes an instantiated first-level module, and the first-level module includes a first simulation model of the storage module. In other words, the encapsulator can be divided into three layers, which, in order from top to bottom or from outside to inside, are: third layer, second layer, and first layer. The third layer is the topmost or outermost layer. A schematic diagram of the layered structure of the encapsulator can be shown below. Figure 1 As shown. The simulation model of the storage module (such as the first simulation model, the second simulation model mentioned later, etc.) is a software model that simulates the function, performance, timing and other characteristics of the real storage module in a computer simulation environment. The purpose is to verify the working logic of the storage module and its compatibility with other systems without building real hardware.
[0028] Please see Figure 2 , Figure 2 This is a flowchart illustrating a method for determining the packager of a storage module according to an embodiment of this application. The method for determining the packager of a storage module may include, but is not limited to, the following steps. S201: Obtain configuration parameters. The configuration parameters include at least the type of storage module, the depth of the storage module, the data bit width, and the required function identifier of the wrapper. The required function identifier is used to indicate whether to configure the first function module in the first-level module and whether to configure the second function module in the third-level module.
[0029] Electronic devices can obtain configuration parameters by reading configuration files, or they can obtain configuration parameters input by the user from the parameter configuration interface. This application embodiment does not limit the method by which electronic devices obtain configuration parameters.
[0030] This application does not limit the type of storage module, which may include, but is not limited to, volatile storage modules and non-volatile storage modules. Volatile storage modules may include, but are not limited to, Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Non-volatile storage modules may include, but are not limited to, Flash Memory and Read-Only Memory (ROM).
[0031] The data bit width of a storage module refers to the amount of data that can be read and written from the storage module at one time, while the storage depth refers to the total number of data sets that the storage module can store. The total capacity of a storage module is the product of its data bit width and storage depth. The unit for data bit width can be bits, and the unit for storage depth can be units. For example, a RAM with a depth of 1K and a data bit width of 8 bits has a total capacity of 1K × 8 bits = 8Kbits.
[0032] The required functional identifiers of the wrapper can be used to indicate whether to configure corresponding optional functional modules in the first-level and third-level modules. The first and second functional modules are both optional; in other words, users can choose to configure corresponding optional functional modules in the first-level and third-level modules based on their actual needs, or choose not to configure them. By adding functional modules at different levels as needed, a highly modular and dynamically configurable design is achieved. This facilitates better adaptation to the fragmented needs of the wrapper, improves its reusability, and shortens its development cycle.
[0033] In one possible implementation, the first functional module may include one or more of the following: an input data pipe (IPIPE) functional module, an output data pipe (OPIPE) functional module, and an integrated clock gating cell (ICG) functional module. The second functional module may include an error correcting code (ECC) functional module and / or an error inject module (EIM) functional module. For example, the required function identifier of the package can be a 5-bit binary number, with one bit corresponding to one functional module. Assume the first three bits correspond to the IPIPE, OPIE, and ICG functional modules respectively, and the last two bits correspond to the ECC and EIM functional modules respectively. Assume a binary value of 1 indicates that the corresponding functional module needs to be configured in the package, and a binary value of 0 indicates that the corresponding functional module does not need to be configured in the package. If the required function identifier of the packager is 11011, it means that: the IPIPE function module and the OPIPE function module need to be configured in the first-level module of the packager, the ECC function module and the EIM function module need to be configured in the third-level module of the packager, and the ICG function module does not need to be configured in the first-level module of the packager.
[0034] In one possible implementation, where the required function identifier of the wrapper indicates that the IPIPE function module and the OPIPE function module are configured in the first-level module, the configuration parameters may also include: the number of IPIPE cycles and the number of OPIPE cycles.
[0035] Input data interpolation refers to the process where raw external input data is sampled and stored in registers one or more times according to the system clock cycle before entering the storage module. This essentially delays the input data by several clock cycles before it is transmitted to the storage module. The core function of this operation is to eliminate glitches and interference from the input signal, resolving the issue of asynchronous operation between the external signal and the chip's internal clock.
[0036] Output data timing refers to the process where data in the storage module is delayed by registering according to clock cycles before being output to external devices (such as displays or other chips). In other words, the output data first "remains in the register for one or more clock cycles" before being sent to the external interface. The core function of this operation is to match the receiving timing of external devices and avoid instability in the output signal caused by circuit delays.
[0037] The number of clock cycles of delay is called the "number of clock cycles". The number of IPIPE clock cycles is the number of clock cycles of input data delay, and the number of OPIPE clock cycles is the number of clock cycles of output data delay. One clock cycle is when the data stays in the register for one clock cycle.
[0038] An integrated clock gating unit is a hardware module that integrates gating logic (such as AND gates, OR gates, and latches) and control circuitry into a single standard unit. It receives the original clock signal (Clock, CLK) and a gating enable signal (Enable, EN). It only transmits the original clock signal to downstream circuits when the enable signal is valid; when the enable signal is invalid, it cuts off the downstream clock path, stopping the clock from toggling for the corresponding module. In other words, an integrated clock gating unit is a type of integrated sequential logic unit in chip design, specifically designed for precise "on / off" control of the clock signal. It supplies the clock to downstream circuits only when they need to operate (when the enable signal is valid); when the circuit is idle, it turns off the clock to avoid unnecessary power consumption.
[0039] Error-correcting codes are a type of encoding technology that has the ability to detect and correct errors. By adding a certain amount of redundant check bits to the original data, the encoded data is formed. When errors such as bit flipping occur during data storage or transmission, the receiving end or reading end can locate the error position and automatically correct it through logical operations of the check bits.
[0040] The error injection module is a test module used to verify the fault tolerance capability of a system. It can actively inject preset types of errors (such as single-bit flips, multi-bit errors, burst errors, etc.) into the storage module, thereby verifying whether error correction mechanisms such as ECC can effectively detect and repair errors, and evaluating the stability and fault tolerance boundary of the system when errors occur.
[0041] S202: If the required function identifier indicates that the first function module is configured in the first-level module, then the first function module is instantiated in the first-level module.
[0042] Electronic devices can select a template for the first functional module from a pre-built functional module template library and instantiate it. The functional module template library contains pre-stored templates for IPIPE, OPIPE, ICG, ECC, and EIM functional modules. The templates in the functional module template library are pre-developed standard functional templates.
[0043] Instantiation is the process of creating a concrete, runnable "module entity" based on an abstract "module template." In hardware RTL (Register Transfer Level) design, a functional module template only describes the module's interface and internal logic; it is merely a "design description" and does not actively function. Instantiation, on the other hand, replicates a concrete, operational module instance within a higher-level module (the first-level module) according to this template. This instance consumes actual logic resources (registers, combinational logic) and connects to external signals through port mapping, becoming part of the overall circuit.
[0044] RTL is a code-based description of the hierarchy of data transfer and logic processing between registers in a digital circuit under clock control. It is the core of chip front-end design and can be functionally verified and integrated independently of specific processes and toolchains.
[0045] S202 enables modular reuse of functions. The first-level module can integrate multiple functional modules (such as instantiating the IPIPE, OPIPE and ICG functional modules at the same time), which reduces the complexity of the overall design and improves the maintainability and reusability of the code.
[0046] S203: Determine the first simulation model through the first-level module and instantiate the first-level module; wherein, the first simulation model is determined based on the type of the storage module.
[0047] After matching a suitable simulation model (i.e., the first simulation model) to the storage module in the first-level module and instantiating the first functional module in the first-level module, the electronic device actually generates the corresponding hardware structure code or logical entity in the first-level module, making the first-level module a module that can participate in subsequent level integration. The electronic device can improve code development efficiency by executing scripts that automatically generate code based on configuration parameters.
[0048] The first simulation model can be different depending on the type of storage module.
[0049] In one possible implementation, the first-level module can be further divided into two layers: one layer includes the first simulation model, and the other layer includes the first functional module. These two layers can be powered independently. Through independent power supply control, the functional module can be dynamically started and stopped according to actual needs. This flexible, fine-grained power domain management adapts to the power consumption requirements of different operating modes (such as high-performance mode and low-power mode). For example, when the first functional module is not needed, its power supply can be turned off, leaving only the first simulation model powered on. The first functional module contains additional logic circuitry; its static leakage current can be eliminated after power failure, significantly reducing the overall static power consumption of the system.
[0050] S204: The construction method of multiple storage units is determined by the second-level module so that the depth and data width of the constructed storage array match the depth and data width of the storage module, and the target construction method corresponding to the storage array with the smallest area is taken as the construction method of the storage module.
[0051] Based on the depth and data bit width of the storage modules, multiple possible "storage cell combination schemes" (i.e., construction methods) can be designed. Each construction method results in a storage array whose depth and data bit width meet the requirements of the storage modules, thus avoiding insufficient capacity or data bit width, or redundancy. Among all the satisfactory construction methods, the chip area (e.g., silicon wafer area) occupied by the storage array for each method is calculated, and the scheme with the smallest occupied area is selected as the target construction method. By automatically selecting the storage array construction scheme that meets the requirements and has the smallest occupied area, the physical area of the storage array can be significantly reduced, alleviating the wiring congestion problem caused by irregular shapes, and improving the efficiency of back-end physical design and chip area utilization.
[0052] A storage cell is the smallest functional module that makes up a storage array, typically referring to an independent storage block with a fixed data width and a fixed depth. Different types of storage cells can have data widths of 8 bits, 16 bits, 32 bits, etc.; and different types of storage cells can have depths of 1024, 2048, etc. For example, to achieve a 64-bit width, eight 8-bit storage cells can be joined together, or four 16-bit storage cells can be joined together, or two 32-bit storage cells can be joined together.
[0053] In one possible implementation, the memory array constructed based on the target construction method has the smallest physical aspect ratio. The physical aspect ratio of a memory array refers to the ratio of its horizontal length to its vertical length in the chip's physical layout. For example, if the horizontal length is 100μm and the vertical length is 50μm, the aspect ratio is 2:1; if the horizontal length is 80μm and the vertical length is 80μm, the aspect ratio is 1:1.
[0054] In chip physical design, the aspect ratio of the memory array directly affects routing resources and winding difficulty. Minimizing the physical aspect ratio of the memory array through targeted construction methods can make the memory array shape more regular, reduce routing congestion and winding length, improve the efficiency and success rate of back-end physical design, and avoid the extra area waste caused by irregular shapes.
[0055] In one possible implementation, the storage array constructed based on the target construction method has N storage cells in the first direction and M storage cells in the second direction; wherein the sum of the data bit widths of the N storage cells is greater than or equal to the data bit width of the storage module, the sum of the depths of the M storage cells is equal to the depth of the storage module, and M and N are both positive integers.
[0056] The storage array arranges N storage cells along the first direction, and these N storage cells are concatenated along the data bit width dimension. Each type of storage cell has a fixed data bit width (e.g., 32 bits). The sum of the data bit widths of the N storage cells (i.e., the product of the data bit width of a single storage cell and N) is greater than or equal to the data bit width of the storage module, ensuring that the data bit width of the storage array meets the requirements. The first direction is the horizontal direction.
[0057] The storage array arranges M storage cells along the second direction, with the M cells joined together along the storage depth dimension. Each type of storage cell has a fixed depth, and the sum of the depths of the M cells (i.e., the product of the depth of a single storage cell and M) equals the depth of the storage module, ensuring that the capacity of the storage array meets the requirements. The second direction is the vertical direction.
[0058] In one possible implementation, the configuration parameters may also include M and N. In other words, the number of storage units spliced in the first direction and the number of storage units spliced in the second direction can be set by the user based on their needs. Alternatively, as mentioned above, M and N can also be determined by the electronic device, that is, the electronic device determines the target construction method by comparing different construction methods, and then determines the number of storage units spliced in the first direction (i.e., N) and the number of storage units spliced in the second direction (i.e., M) corresponding to the target construction method.
[0059] In one possible implementation, the aforementioned multiple storage units are all of the same type, but the physical length and / or physical width of different types of storage units are different.
[0060] For example, the physical length and / or physical width of different types of storage cells are shown in Table 1.
[0061] Table 1
[0062] S205: Instantiate the second-level module based on the target construction method.
[0063] After determining the target configuration of the storage array, the electronic device generates the corresponding hardware structure code or logical entity in the second-level module based on the specific parameters of the target configuration (such as N, M, and the type of storage unit). This makes the second-level module a module that can participate in subsequent level integration. The electronic device can execute scripts to automatically generate code based on the target configuration, thus improving code development efficiency.
[0064] S206: If the required function identifier indicates that the second function module is configured in the third-level module, then the second function module is instantiated in the third-level module.
[0065] Electronic devices can select a template for a second functional module from a pre-built functional module template library and instantiate it. S206 realizes functional modular reuse, and the third-level module can integrate multiple functional modules (such as simultaneously instantiating the ECC functional module and the EIM functional module), which reduces the complexity of the overall design and improves the maintainability and reusability of the code.
[0066] The third-level module is the top-level module that is exposed to the outside world. Its interfaces include standard interfaces, through which wrappers can be called. With standardized interfaces across different wrappers, the SoC top-level design only needs to connect using a unified interface, eliminating the need to adapt different interfaces for each storage module, significantly reducing integration time. Furthermore, with standardized wrapper interfaces, verification platforms, test scripts, and environments can be reused, reducing redundant development and improving verification efficiency and coverage.
[0067] Optionally, the standard interface may include built-in interfaces for the second functional module (such as the EIM interface and ECC interface), allowing users to access EIM and ECC functions by calling the standard interface. Alternatively, the interface for the third-level module may also include interfaces for the second functional module (such as the EIM interface and ECC interface), meaning the standard interface and the interfaces for the second functional module are set up separately. Users can access EIM functions by calling the EIM interface and access ECC functions by calling the ECC interface.
[0068] This application does not limit the type of standard interface. For example, the standard interface can be a TCM (Tightly-coupled memory) interface or other interfaces. The TCM interface is a dedicated direct interconnect interface between the processor core and ITCM (Instruction Tightly-coupled Memory) and DTCM (Data Tightly-coupled Memory). It does not go through the system bus matrix and cache, and provides the processor with a low-latency, highly deterministic access path.
[0069] In one possible implementation, the third-level module may also include a Field Programmable Gate Array (FPGA) model, such as... Figure 1 As shown by the dashed line in the image, Figure 1 The modules or models shown by the dashed lines are optional content, meaning that these optional content can be configured or not in the wrapper based on actual needs.
[0070] The electronic device can receive a selection operation for a target model. In response to this selection operation, it selects the target model through a third-level module to perform corresponding verification. The target model can be either a first simulation model or an FPGA model. The first simulation model is used to perform front-end verification of the chip design, while the simulation model is used to perform FPGA verification. In this way, the package can simultaneously include both an FPGA model and a first simulation model of the storage module. The electronic device (such as the electronic device corresponding to a chip design verification platform) can dynamically switch verification models according to user selection, achieving flexible switching between front-end verification and FPGA verification. This allows it to meet both FPGA verification scenarios and Electronic Design Automation (EDA) verification scenarios without requiring redevelopment, thus adapting to a wider range of applications.
[0071] Front-end verification is a core step in the chip design front-end flow (after RTL coding and before back-end placement and routing). Through techniques such as logic simulation and formal verification, based on the RTL code of a hardware description language, it comprehensively verifies the functional correctness, logical consistency, and timing rationality of digital circuits, identifying and fixing logic flaws in advance to prevent errors from flowing into the back-end physical implementation stage. Front-end verification can be run in EDA tools, focusing on verifying the correctness of logical functions.
[0072] FPGA verification is a hardware prototyping technology for FPGAs in chip design. It maps the RTL code of the package to FPGA hardware resources, builds a hardware prototype with the same function as the package, and verifies the functional integrity, real-time performance, stability and interface compatibility of the package in a scenario close to real application through actual data interaction and external device docking. It is a key intermediate verification link connecting front-end logic verification and chip mass production.
[0073] Users (such as chip design engineers) can proactively initiate the selection operation for the target model based on verification needs (such as selecting front-end verification or FPGA verification through the GUI interface, or entering command line parameters).
[0074] The third-level module acts as an isolation layer between the FPGA model and the first simulation model. If front-end verification is selected, the third-level module enables the interface and logic of the first simulation model, inputs the test stimuli into the first simulation model, captures its output, and compares it with the expected results. If FPGA verification is selected, the third-level module switches to the interface and logic of the FPGA model, sends the test stimuli to the FPGA prototype platform, collects the hardware response, and verifies it.
[0075] The first simulation model is compiled by a first compiler based on a first process library. In this embodiment, the process library is a database describing the physical rules of transistors, interconnections, etc., in a certain generation of chip manufacturing process. The compiler converts the design code of the memory module into a model that can be simulated under that process.
[0076] In one possible implementation, if the compiler used changes from a first compiler to a second compiler, the electronic device can replace the first simulation model with the second simulation model; wherein the second simulation model is compiled by the second compiler; and / or, if the process library of the first compiler changes from a first process library to a second process library, the electronic device can replace the first simulation model with a third simulation model; wherein the third simulation model is compiled by the first compiler based on the second process library. In this way, the simulation model can be replaced as the compiler or process library changes; that is, only the underlying simulation model file needs to be replaced, without changing the RTL design code of the top-level (i.e., third-level) wrapper. This is because when the compiler or process library changes, the external interface of the wrapper remains unchanged, so the RTL design code of the top-level (i.e., third-level) wrapper does not need to be modified.
[0077] In one possible implementation, after the electronic device replaces the first simulation model with the second or third simulation model, it can re-instantiate the first-level module.
[0078] In this embodiment, a highly modular and dynamically configurable design is achieved through layered design and the addition of functional modules at different levels as needed. This facilitates better adaptation to the fragmented needs of the packager, improves its reusability, and shortens its development cycle. Furthermore, automatically selecting the storage array construction scheme that meets the requirements and occupies the smallest area can significantly reduce the physical area of the storage array, alleviate wiring congestion caused by irregular shapes, and improve the efficiency of backend physical design and chip area utilization.
[0079] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a storage module package determining device provided in an embodiment of this application. Figure 3As shown, the storage module package determination device 30 includes an acquisition unit 301 and a processing unit 302. Optionally, the storage module package determination device 30 may further include a receiving unit 303. The storage module package determination device 30 can perform the relevant steps of the electronic device in the foregoing method embodiments.
[0080] The acquisition unit is used to acquire configuration parameters, which include at least the type of storage module, the depth of the storage module, the data bit width, and the required function identifier of the wrapper; wherein, the required function identifier is used to indicate whether to configure the first function module in the first-level module and whether to configure the second function module in the third-level module. The processing unit is configured to instantiate the first functional module in the first-level module if the required functional identifier indicates that the first functional module is configured in the first-level module. The processing unit is further configured to determine a first simulation model through a first-level module and instantiate the first-level module; wherein the first simulation model is determined based on the type of the storage module; The processing unit is also used to determine the construction method of multiple storage units through the second-level module, so that the depth and data bit width of the constructed storage array match the depth and data bit width of the storage module, and the target construction method corresponding to the storage array with the smallest area is taken as the construction method of the storage module. The processing unit is also used to instantiate second-level modules based on the target construction method; The processing unit is also configured to instantiate the second functional module in the third-level module if the required functional identifier indicates that the second functional module is configured in the third-level module.
[0081] In one possible implementation, the third-level module also includes an FPGA model. A receiving unit receives a selection operation for a target model, which can be either a first simulation model or an FPGA model. A processing unit, in response to the selection operation, selects the target model through the third-level module to perform corresponding verification. The first simulation model is used to perform chip design front-end verification, and the simulation model is used to perform FPGA verification.
[0082] Specifically, in this case, the operations performed by the acquisition unit, processing unit, and receiving unit can be referred to the description of the electronic device in the method embodiment, and will not be repeated here.
[0083] Please see Figure 4 , Figure 4This is a schematic diagram of the structure of an electronic device 40 provided in an embodiment of this application, which can be used to implement the functions of the electronic device in the above method embodiments. The electronic device 40 may include at least one processor 401. Optionally, the electronic device 40 may also include one or more of a communication interface 402 and a memory 403. Figure 4 The components shown by the dashed lines are optional components, meaning that electronic device 40 may not include them. Figure 4 The component shown by the dashed line.
[0084] At least one processor, communication interface, memory, and display screen can be connected via bus 404 or other means. The bus is in... Figure 4 The connections between other components are shown in bold lines only and are not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.
[0085] The coupling in this application embodiment is an indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information interaction between devices, units, or modules. This application embodiment does not limit the specific connection medium between the at least one processor, communication interface, memory, and display screen mentioned above.
[0086] The memory may include read-only memory and random access memory, and provides instructions and data to at least one processor. A portion of the memory may also include non-volatile random access memory.
[0087] At least one processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, optionally, and at least one processor can also be any conventional processor.
[0088] In one example, when the electronic device adopts Figure 4 When in the form shown, At least one processor in the device can execute the method executed by the electronic device in any of the above method embodiments.
[0089] In one possible implementation, a memory is provided for storing computer programs or instructions; at least one processor is provided for calling the computer programs or instructions stored in the memory to perform the steps performed by the electronic device in the method embodiment.
[0090] In the embodiments of this application, the methods provided in the embodiments of this application can be implemented by running a computer program (including program code) capable of performing the steps involved in the above-described methods on a general-purpose computing device, such as a computer, which includes processing elements and storage elements such as a CPU, random access memory (RAM), and read-only memory (ROM). The computer program can be recorded on, for example, a computer-readable recording medium, loaded into an electronic device through the computer-readable recording medium, and run therein.
[0091] Based on the same inventive concept, the principles and beneficial effects of the devices and electronic equipment provided in the embodiments of this application in solving the problem are similar to those of the electronic equipment in the method embodiments of this application in solving the problem. Please refer to the principles and beneficial effects of the method embodiments. For the sake of brevity, they will not be repeated here.
[0092] This application also provides a computer-readable storage medium storing a computer program or computer instructions, which is adapted to be loaded by an electronic device and execute the method provided in the above-described method embodiments.
[0093] This application also provides a computer program product containing a computer program or instructions, which, when run on an electronic device, causes the electronic device to perform the method provided in the above-described method embodiments.
[0094] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The implementation is achieved through a software program that runs on a processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into electronic devices, each of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the electronic device. Alternatively, at least some modules / units can be implemented using a software program that runs on a processor integrated within the electronic device, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.
[0095] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.
[0096] In the above embodiments, the descriptions of each embodiment have their own emphasis, and any multiple embodiments can be used in combination. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0097] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.
[0098] The modules in the device of this application embodiment can be merged, divided, and deleted according to actual needs.
[0099] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by program instructions and related hardware. The program instructions can be stored in a computer-readable storage medium, which may include: flash drive, ROM, RAM, disk or optical disk, etc.
[0100] The above-disclosed embodiments are merely one example of this application and only a part of the embodiments of this application. They should not be construed as limiting the scope of this application.
Claims
1. A method for determining the packager of a storage module, characterized in that, The encapsulator adopts a layered structure. The third-level module of the encapsulator includes an instantiated second-level module, the second-level module includes an instantiated first-level module, and the first-level module includes a first simulation model of the storage module. The method includes: Obtain configuration parameters, which include at least the type of the storage module, the depth of the storage module, the data bit width, and the required function identifier of the wrapper; wherein, the required function identifier is used to indicate whether to configure a first function module in the first-level module and whether to configure a second function module in the third-level module. If the required function identifier indicates that a first function module is configured in the first-level module, then the first function module is instantiated in the first-level module. The first simulation model is determined by the first-level module, and the first-level module is instantiated; wherein, the first simulation model is determined based on the type of the storage module; The second-level module determines the construction method of multiple storage units so that the depth and data width of the constructed storage array match the depth and data width of the storage module, and the target construction method corresponding to the storage array with the smallest area is taken as the construction method of the storage module. Instantiate the second-level module based on the target construction method; If the required function identifier indicates that a second function module is configured in the third-level module, then the second function module is instantiated in the third-level module.
2. The method according to claim 1, characterized in that, The first simulation model is compiled by a first compiler based on a first process library; the method further includes: If the compiler used changes from the first compiler to the second compiler, then the first simulation model is replaced with the second simulation model; wherein the second simulation model is compiled by the second compiler; and / or, If the process library of the first compiler changes from the first process library to the second process library, then the first simulation model is replaced with the third simulation model; wherein the third simulation model is compiled by the first compiler based on the second process library.
3. The method according to claim 1, characterized in that, The storage array constructed based on the aforementioned target construction method has the smallest physical aspect ratio.
4. The method according to any one of claims 1-3, characterized in that, The storage array constructed based on the target construction method has N storage cells in the first direction and M storage cells in the second direction; wherein the sum of the data bit widths of the N storage cells is greater than or equal to the data bit width of the storage module, the sum of the depths of the M storage cells is equal to the depth of the storage module, and M and N are both positive integers.
5. The method according to claim 4, characterized in that, The configuration parameters also include M and N.
6. The method according to any one of claims 1-3, characterized in that, The multiple storage units are all of the same type, but the physical length and / or physical width of the different types of storage units are different.
7. The method according to any one of claims 1-3, characterized in that, The third-level module also includes an FPGA model; the method further includes: Receive a selection operation for a target model, wherein the target model is the first simulation model or the FPGA model; In response to the selection operation, the target model is selected through the third-level module to perform the corresponding verification; wherein, the first simulation model is used to perform chip design front-end verification, and the simulation model is used to perform FPGA verification.
8. The method according to any one of claims 1-3, characterized in that, The first functional module includes one or more of the following: an input data insertion module, an output data insertion module, and an integrated clock gating unit module. The second functional module includes an error correction code functional module and / or an error injection functional module.
9. An electronic device, characterized in that, include: A processor and a memory connected to the processor; wherein, The memory is used to store computer programs or instructions, and the processor is used to execute the computer programs or instructions in the memory. When the computer programs or instructions are executed by the processor, the electronic device performs the method as described in any one of claims 1-8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or computer instructions that, when executed by a processor, cause the method described in any one of claims 1-8 to be performed.